High-speed high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving

Abstract

The invention discloses a high-speed and high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving. The high-speed and high-precision hybrid architecture analog-to-digital converter comprises a clock circuit, a Flash ADC, a fully differential gain bootstrap amplifier, a two-stage multi-channel Piped SAR ADC, a register delay alignment circuit and a digital correction circuit. A time domain interleaving technology is adopted in the two-stage multi-channel Pipelled SAR ADC, so that post-stage local interleaving is realized, and the speed of the Pipelled SAR ADC is increased; time domain interleaving is not adopted in the front-stage Flash ADC, so that sampling clock skew errors are avoided; according to the invention, higher energy efficiency can be realized, the precision and the speed of the analog-to-digital converter are remarkably improved and the power consumption and the area of the analog-to-digital converter are reduced through a time domain interleaving technology and an operational amplifier sharing technology in a post-stage two-stage multi-channel Pipeled SAR ADC (Synthetic Aperture Radar Analog-to-Digital Converter).

Description

Technical Field

[0001] This invention belongs to the field of CMOS analog integrated circuit technology, specifically relating to a high-speed, high-precision hybrid architecture analog-to-digital converter based on back-stage local interleaving. Background Technology

[0002] With the rapid development of electronic technology, especially in fields such as communications, radar, and medical equipment, increasingly higher demands are being placed on the speed and accuracy of signal processing. As a key component in signal processing systems, the analog-to-digital converter (ADC) plays a crucial role. Traditional ADC structures, such as successive approximation (SAR) ADCs and pipelined ADCs, have a certain trade-off between speed and accuracy. SAR ADCs offer high accuracy and low power consumption, but their speed is relatively slow; while pipelined ADCs, although offering high speed, have limitations in terms of accuracy and power consumption.

[0003] In recent years, with the advancement of process technology, especially the continuous development of CMOS technology, higher demands have been placed on the speed and accuracy of ADCs. To meet this demand, researchers have begun to explore a new structure that combines SAR ADCs and Pipelined ADCs, namely Pipelined SAR ADCs. This structure aims to combine the high accuracy of SAR ADCs with the high speed of Pipelined ADCs, thereby achieving high-speed and high-precision ADC design.

[0004] However, existing pipelined SAR ADCs still have some problems in practical applications. Maintaining high accuracy while pursuing high speed is a significant challenge; high-speed ADCs are usually accompanied by high power consumption, and reducing power consumption while ensuring speed and accuracy is an issue that needs to be addressed. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving, comprising:

[0007] Clock circuit, Flash ADC, fully differential gain bootstrap amplifier, two-stage multi-channel pipelined SAR ADC, register delay alignment circuit, and digital correction circuit; among which,

[0008] The clock circuit is used to control the working status of the other modules;

[0009] The Flash ADC is used to quantize the input signal under the control of the clock circuit to obtain binary code D<1:N0> and the first residual voltage Vres1;

[0010] The fully differential gain bootstrap amplifier is used to amplify the first residual voltage Vres1 under the control of the clock circuit and output the first amplified signal.

[0011] The two-stage multi-channel Pipelined SAR ADC employs time-domain interleaving technology. The first stage, under the control of the clock circuit, sequentially quantizes the first amplified signal corresponding to each channel of its own channel, outputting the corresponding first-stage quantization result D<1:N1> and inter-stage residual voltage Vres2. The inter-stage residual voltage Vres2 is amplified using a fully differential ring amplifier between the two stages, outputting a second amplified signal. The second stage, also under the control of the clock circuit, sequentially quantizes the second amplified signal corresponding to each channel of its own channel, outputting the second-stage quantization result D<1:N2>.

[0012] The register delay alignment circuit is used to reconstruct the binary code D<1:N0>, the first-level quantization result D<1:N1>, and the second-level quantization result D<1:N2> in the time dimension under the control of the clock circuit, store the reconstructed binary data, and send its stored binary data to the digital correction circuit after receiving the second-level quantization result D<1:N2>.

[0013] The digital correction circuit is used to correct the received binary data under the control of the clock circuit, eliminate inter-stage gain error and capacitor mismatch error, and output the corrected analog-to-digital conversion result.

[0014] In one embodiment of the present invention, the Flash ADC includes:

[0015] The sample-and-hold circuit (S / H), comparator, capacitor array, switch array, and encoder are included; among them,

[0016] The input terminal of the sample-and-hold circuit S / H is connected to the input signal, and the output terminal is connected to the first input terminal of the capacitor array.

[0017] The output terminal of the capacitor array is connected to the positive input terminal of the comparator;

[0018] The negative input terminal of the comparator is connected to the reference voltage Vref, and the output terminal is connected to the input terminal of the encoder.

[0019] The input terminal of the switch array is connected to the output terminal of the encoder, and the output terminal is connected to the second input terminal of the capacitor array.

[0020] In one embodiment of the present invention, the Flash ADC quantizes the input signal to obtain binary code D<1:N0> and a first residual voltage Vres1, including:

[0021] The sample-and-hold circuit S / H samples the input signal and holds the sampled signal on the lower-level board of the capacitor array.

[0022] By switching the switch array, the signal on the lower-level board of the capacitor array is transmitted to the upper-level board of the capacitor array.

[0023] The comparator compares the voltage on the upper board of the capacitor array with the reference voltage Vref to obtain the thermometer code;

[0024] The encoder processes the thermometer code to obtain the binary code D<1:N0>;

[0025] The switch array switches according to the binary code D<1:N0>, thereby changing the voltage on the upper board of the capacitor array to obtain the first residual voltage Vres1; where the thermometer code is 2. N0 -1 bit, binary code is N0 bits.

[0026] In one embodiment of the present invention, the fully differential gain bootstrap amplifier is a folded cascode amplifier, comprising:

[0027] MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M5, MOSFET M6, MOSFET M7, MOSFET M8, MOSFET M9, MOSFET M 10 MOSFET M 11 Auxiliary amplifier A, auxiliary amplifier B, and the first common-mode feedback circuit; among which,

[0028] The source of the MOS transistor M1 is connected to the drain of the MOS transistor M3, the gate serves as the negative input terminal of the fully differential gain bootstrap amplifier, and the drain is connected to the drain of the MOS transistor M4.

[0029] The source of MOS transistor M2 is connected to the source of MOS transistor M1, the gate serves as the positive input terminal of the fully differential gain bootstrap amplifier, and the drain is connected to the drain of MOS transistor M5.

[0030] The source of the MOSFET M3 is connected to the power supply voltage VDD, and the gate is connected to the bias voltage Vbp.

[0031] The source of the MOS transistor M4 is connected to the source of the MOS transistor M5, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M5, and the drain of the MOS transistor M4 is connected to the positive input terminal of the auxiliary amplifier B.

[0032] The source of the MOS transistor M5 is grounded, the gate is connected to a bias voltage Vbn1, and the drain is connected to the negative input terminal of the auxiliary amplifier B.

[0033] The source of the MOS transistor M6 is connected to the positive input terminal of the auxiliary amplifier B, the gate is connected to the negative output terminal of the auxiliary amplifier B, and the drain is connected to the drain of the MOS transistor M8, serving as the output port VOUTP1 of the fully differential gain bootstrap amplifier.

[0034] The source of the MOS transistor M7 is connected to the negative input terminal of the auxiliary amplifier B, the gate is connected to the positive output terminal of the auxiliary amplifier B, and the drain is connected to the drain of the MOS transistor M9, serving as the output port VOUTN1 of the fully differential gain bootstrap amplifier.

[0035] The source of the MOS transistor M8 is connected to the positive input terminal of the auxiliary amplifier A, the gate is connected to the negative output terminal of the auxiliary amplifier A, and the drain is connected to the drain of the MOS transistor M6.

[0036] The source of the MOS transistor M9 is connected to the negative input terminal of the auxiliary amplifier A, the gate is connected to the positive output terminal of the auxiliary amplifier A, and the drain is connected to the drain of the MOS transistor M7.

[0037] The MOS transistor M 10 The source is connected to the power supply voltage VDD, and the gate is connected to the MOS transistor M. 11 The gate is connected, and the drain is connected to the positive input terminal of the auxiliary amplifier A;

[0038] The MOS transistor M 11 The source is connected to the power supply voltage VDD, the gate is connected to the bias voltage Vbp1, and the drain is connected to the negative input terminal of the auxiliary amplifier A.

[0039] The input terminal of the first common-mode feedback circuit is connected to the common-mode feedback voltage Vcmfb1, the first output terminal is connected to the output port VOUTP1 of the fully differential gain bootstrap amplifier, and the second output terminal is connected to the output port VOUTN1 of the fully differential gain bootstrap amplifier.

[0040] In one embodiment of the present invention, both the first and second stages of the two-stage multi-channel pipelined SAR ADC employ multi-channel pipelined successive approximation analog-to-digital converters; each sub-channel pipelined successive approximation analog-to-digital converter includes a sampling switch, a sampling capacitor, a comparator, SAR dynamic logic, a switch array, and a register array; wherein,

[0041] The first terminal of the sampling switch serves as the input terminal of a multi-channel pipelined successive approximation analog-to-digital converter, and the second terminal is connected to the first terminal of the sampling capacitor.

[0042] The first end of the sampling capacitor is connected to the output of the switch array, and the second end is connected to the input of the comparator.

[0043] The positive input terminal of the comparator is connected to the positive input signal on the sampling capacitor, the negative input terminal is connected to the negative input signal on the sampling capacitor, and the output terminal is connected to the input terminal of the SAR dynamic logic.

[0044] The output of the SAR dynamic logic is connected to the input of the switch array;

[0045] The input of the register array is connected to the output of the SAR dynamic logic, and the output serves as the output of a multi-channel pipelined successive approximation analog-to-digital converter.

[0046] In one embodiment of the present invention, in the two-stage multi-channel pipelined SAR ADC, the quantization bits of each sub-channel pipelined successive approximation analog-to-digital converter are 10-14 bits.

[0047] In one embodiment of the present invention, in the two-stage multi-channel Pipelined SAR ADC, the sampling capacitor of the first stage is sampled by the lower stage board, and the sampling capacitor of the second stage is sampled by the upper stage board.

[0048] In one embodiment of the present invention, the two-stage multi-channel pipelined SAR ADC employs time-domain interleaving technology. Under the control of the clock circuit, each channel sequentially quantizes the amplified signal corresponding to that channel, including:

[0049] In the two-stage multi-channel Pipelined SAR ADC, the sampling switches of each stage are turned on sequentially under the control of the non-overlapping clock output by the clock circuit, thereby quantizing the amplified signal received by the channel corresponding to the sampling switch.

[0050] In one embodiment of the present invention, the fully differential ring amplifier includes a three-stage inverter and a second common-mode feedback circuit.

[0051] In one embodiment of the present invention, in the three-stage inverter,

[0052] The first stage includes: an inverting amplification MOSFET group, a bias MOSFET group, and a local common-mode feedback circuit; among which...

[0053] The first input terminal of the reverse amplifying MOS transistor group serves as the positive input terminal of the first stage, the second input terminal serves as the negative input terminal of the first stage, the positive output terminal serves as the positive output terminal of the first stage, and the negative output terminal serves as the negative output terminal of the first stage.

[0054] The first bias output terminal of the bias transistor group is connected to the first bias terminal of the inverting amplifying MOS transistor group, and the second bias output terminal is connected to the second bias terminal of the inverting amplifying MOS transistor group.

[0055] The first terminal of the local common-mode feedback circuit is connected to the positive output terminal of the inverting MOS transistor group, and the second terminal is connected to the negative output terminal of the inverting MOS transistor group.

[0056] The positive input of the second stage is connected to the positive output of the first stage, the negative input is connected to the negative output of the first stage, the positive output is connected to the positive input of the third stage, and the negative output is connected to the positive input of the third stage.

[0057] The positive output terminal of the third stage is connected to the positive output terminal of the second common-mode feedback circuit, serving as the positive output terminal of the fully differential ring amplifier. The negative output terminal is connected to the negative output terminal of the second common-mode feedback circuit, serving as the negative output terminal of the fully differential ring amplifier.

[0058] The beneficial effects of this invention are:

[0059] In the solution provided by this invention, the two-stage multi-channel Pipelined SAR ADC in the high-speed, high-precision hybrid architecture analog-to-digital converter based on rear-stage local interleaving employs time-domain interleaving technology to achieve rear-stage local interleaving, thereby improving the speed of the Pipelined SAR ADC. Simultaneously, the front-stage Flash ADC does not employ time-domain interleaving, thus avoiding sampling clock skew errors. Compared to traditional Pipelined ADCs, the architecture of this invention achieves higher energy efficiency. In the rear-stage two-stage multi-channel Pipelined SAR ADC, time-domain interleaving and operational amplifier sharing technologies significantly improve the accuracy and speed of the analog-to-digital converter while reducing its power consumption and area. Attached Figure Description

[0060] Figure 1 This is a schematic diagram of a high-speed, high-precision hybrid architecture analog-to-digital converter based on a post-stage local interleaving, provided in an embodiment of the present invention.

[0061] Figure 2 This is a schematic diagram of the structure of a Flash ADC in a high-speed, high-precision hybrid architecture analog-to-digital converter based on a post-stage local interleaving, provided in an embodiment of the present invention.

[0062] Figure 3 This is a schematic diagram of the structure of a fully differential gain bootstrap amplifier in a high-speed, high-precision hybrid architecture analog-to-digital converter based on a post-stage local interleaving, provided in an embodiment of the present invention.

[0063] Figure 4 This is a schematic diagram of the structure of a two-stage multi-channel Pipelined SAR ADC in a high-speed, high-precision hybrid architecture analog-to-digital converter based on a post-stage local interleaving, provided in an embodiment of the present invention.

[0064] Figure 5 This is a schematic diagram of the structure of a fully differential ring amplifier in a high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving, provided as an embodiment of the present invention. Detailed Implementation

[0065] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0066] This invention provides a high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving, such as... Figure 1 As shown, it may include:

[0067] Clock circuit, Flash ADC, fully differential gain bootstrap amplifier, two-stage multi-channel pipelined SAR ADC, fully differential ring amplifier, register delay alignment circuit, and digital correction circuit; among which,

[0068] The clock circuit is used to control the operating status of the other modules.

[0069] The Flash ADC is used to quantize the input signal under the control of the clock circuit to obtain the binary code D<1:N0> and the first residual voltage Vres1.

[0070] A fully differential gain bootstrap amplifier is used to amplify the first residual voltage Vres1 under the control of a clock circuit and output the first amplified signal.

[0071] The two-stage multi-channel pipelined SAR ADC employs time-domain interleaving technology. In the first stage, under the control of a clock circuit, each channel sequentially quantizes the first amplified signal corresponding to that channel, outputting the first-stage quantization result D<1:N1> and the inter-stage residual voltage Vres2. The inter-stage residual voltage Vres2 is amplified using a fully differential ring amplifier between the two stages, outputting the second amplified signal. In the second stage, under the control of a clock circuit, each channel sequentially quantizes the second amplified signal corresponding to that channel, outputting the second-stage quantization result D<1:N2>.

[0072] The register delay alignment circuit is used to reconstruct the binary code D<1:N0>, the first-level quantization result D<1:N1>, and the second-level quantization result D<1:N2> in the time dimension under the control of the clock circuit. The reconstructed data is stored, and after receiving the second-level quantization result D<1:N2>, the stored data is sent to the digital correction circuit.

[0073] The digital correction circuit, under the control of the clock circuit, corrects the interstage gain error and capacitor mismatch error in the data it receives, and outputs the corrected analog-to-digital conversion result.

[0074] The two-stage multi-channel Pipelined SAR ADC in the high-speed, high-precision hybrid architecture analog-to-digital converter based on rear-stage local interleaving proposed in this embodiment of the invention employs time-domain interleaving technology to achieve rear-stage local interleaving, thereby improving the speed of the Pipelined SAR ADC. Simultaneously, the front-stage Flash ADC does not employ time-domain interleaving, thus avoiding sampling clock skew errors. Compared with traditional Pipelined ADCs, the architecture of this invention achieves higher energy efficiency. In the rear-stage two-stage multi-channel Pipelined SAR ADC, time-domain interleaving and operational amplifier sharing technologies significantly improve the accuracy and speed of the analog-to-digital converter while reducing its power consumption and area.

[0075] For ease of understanding, the following describes each module of the high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving proposed in the embodiments of the present invention.

[0076] Flash ADC, such as Figure 2 As shown, it may include:

[0077] The sample-and-hold circuit (S / H), comparator, capacitor array, switch array, and encoder are included; among them,

[0078] The input terminal of the sample-and-hold circuit S / H is connected to the input signal, and the output terminal is connected to the first input terminal of the capacitor array;

[0079] The output of the capacitor array is connected to the positive input of the comparator.

[0080] The negative input terminal of the comparator is connected to the reference voltage Vref, and the output terminal is connected to the input terminal of the encoder;

[0081] The input terminal of the switch array is connected to the output terminal of the encoder, and the output terminal is connected to the second input terminal of the capacitor array.

[0082] The Flash ADC quantizes the input signal to obtain binary code D<1:N0> and the first residual voltage Vres1, which may include:

[0083] The sample-and-hold circuit S / H samples the input signal and holds the sampled signal on the lower-level board of the capacitor array;

[0084] By switching the switch array, the signal on the lower-level board of the capacitor array is transmitted to the upper-level board of the capacitor array.

[0085] The comparator compares the voltage on the upper board of the capacitor array with the reference voltage Vref to obtain the thermometer code;

[0086] The encoder processes the thermometer code to obtain the binary code D<1:N0>;

[0087] The switch array switches according to the binary code D<1:N0>, thereby changing the voltage on the upper board of the capacitor array to obtain the first residual voltage Vres1; where the thermometer code is 2. N0 -1 bit, binary code is N0 bits.

[0088] Understandably, a Flash ADC can have a sampling rate of 125 MSPs and a quantization bit depth of 4-6 bits, including 2... N0 One resistor, 2 N0 -1 comparator, N0 is the number of quantization bits. When N0 = 4, its structure diagram of the Flash ADC based on the high-speed, high-precision hybrid architecture analog-to-digital converter with subsequent local interleaving is shown in the figure. Figure 2 As shown. The binary code output by the Flash ADC is N0 bits, and the encoder will convert 2 bits... N0 -1 bit thermometer code is converted to N0 bit binary code.

[0089] In this embodiment of the invention, during sampling, the input signal Vin first passes through the sample-and-hold circuit S / H to hold the sampled signal on the lower-level board of the capacitor array Cs0; during the signal holding phase, the signal from the lower-level board of the capacitor array is transmitted to the upper-level board of the capacitor array through the switching of the switch array; the upper-level board of the capacitor array is connected to the negative terminals of comparators Com1, Com2, Com3, Com4, Com5, Com6, Com7, Com8, Com9, Com10, Com11, Com12, Com13, Com14, and Com15;

[0090] Optionally, the Flash ADC may include 16 resistors, namely R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, and R16. Among them, resistors R1 and R16 are of equal value, and resistors R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, and R15 are of equal value. Resistor R2 is equal to twice the value of R1. Resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, and R16 are connected end to end in sequence. The bottom end of resistor R1 is connected to the ground wire, and the top end of resistor R16 is connected to the reference voltage Vref.

[0091] The positive terminals of comparators Com1, Com2, Com3, Com4, Com5, Com6, Com7, Com8, Com9, Com10, Com11, Com12, Com13, Com14, and Com15 are connected to the upper terminals of resistors R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, and R15, respectively. These 15 comparators operate simultaneously, comparing the voltage of the upper-level board of the capacitor array with the voltage across the 16 resistors to obtain a 15-bit thermometer code. This 15-bit thermometer code is then converted into a 4-bit binary code value by an encoder. Finally, the 4-bit binary code value is transmitted to the switch array, which switches according to the binary code value, thereby changing the voltage of the upper-level board of the capacitor array. This quantization of the voltage signal yields the first residual voltage Vres1, which is used as Vout_F.

[0092] The front-end Flash ADC operates with only one channel and does not employ time-domain interleaving technology, thus avoiding sampling clock skew errors and improving the accuracy of the analog-to-digital converter.

[0093] The fully differential gain bootstrap amplifier is a folded cascode amplifier, such as... Figure 3 As shown, it may include:

[0094] MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M5, MOSFET M6, MOSFET M7, MOSFET M8, MOSFET M9, MOSFET M 10 MOSFET M 11 Auxiliary amplifier A, auxiliary amplifier B, and the first common-mode feedback circuit; among which,

[0095] The source of MOSFET M1 is connected to the drain of MOSFET M3, and its gate serves as the negative input terminal of the fully differential gain bootstrap amplifier. Its drain is connected to the drain of MOSFET M4.

[0096] The source of MOSFET M2 is connected to the source of MOSFET M1, the gate serves as the positive input of the fully differential gain bootstrap amplifier, and the drain is connected to the drain of MOSFET M5.

[0097] The source of MOSFET M3 is connected to the power supply voltage VDD, and the gate is connected to the bias voltage Vbp.

[0098] The source of MOSFET M4 is connected to the source of MOSFET M5, the gate of MOSFET M5 is connected to the gate of MOSFET M5, and the drain of MOSFET M4 is connected to the positive input terminal of auxiliary amplifier B.

[0099] The source of MOSFET M5 is grounded, the gate is connected to a bias voltage Vbn1, and the drain is connected to the negative input terminal of auxiliary amplifier B.

[0100] The source of MOSFET M6 is connected to the positive input terminal of auxiliary amplifier B, the gate is connected to the negative output terminal of auxiliary amplifier B, and the drain is connected to the drain of MOSFET M8, serving as the output port VOUTP1 of the fully differential gain bootstrap amplifier.

[0101] The source of MOSFET M7 is connected to the negative input terminal of auxiliary amplifier B, the gate is connected to the positive output terminal of auxiliary amplifier B, and the drain is connected to the drain of MOSFET M9, serving as the output port VOUTN1 of the fully differential gain bootstrap amplifier.

[0102] The source of MOSFET M8 is connected to the positive input terminal of auxiliary amplifier A, the gate is connected to the negative output terminal of auxiliary amplifier A, and the drain is connected to the drain of MOSFET M6.

[0103] The source of MOSFET M9 is connected to the negative input terminal of auxiliary amplifier A, the gate is connected to the positive output terminal of auxiliary amplifier A, and the drain is connected to the drain of MOSFET M7.

[0104] MOSFET M 10 The source is connected to the power supply voltage VDD, and the gate is connected to the MOSFET M. 11 The gate is connected, and the drain is connected to the positive input terminal of the auxiliary amplifier A;

[0105] MOSFET M 11 The source is connected to the power supply voltage VDD, the gate is connected to the bias voltage Vbp1, and the drain is connected to the negative input terminal of the auxiliary amplifier A.

[0106] The input terminal of the first common-mode feedback circuit is connected to the common-mode feedback voltage Vcmfb1, the first output terminal is connected to the output port VOUTP1 of the fully differential gain bootstrap amplifier, and the second output terminal is connected to the output port VOUTN1 of the fully differential gain bootstrap amplifier.

[0107] The aforementioned fully differential gain bootstrap amplifier is a folded cascode amplifier. Its two auxiliary amplifiers, A and B, are also folded cascode amplifier circuits, defined as Class A and Class B, respectively. When the current stage Flash ADC is sampling, the fully differential gain bootstrap amplifier is grounded to reduce its power consumption. Its first common-mode feedback circuit is used to stabilize the output common-mode voltage.

[0108] like Figure 3 As shown, in a fully differential gain bootstrap amplifier, the first stage's input transistors are MOSFETs M1 and M2, and the current bias transistor is MOSFET M3. The second stage's input transistors are MOSFETs M6, M7, M8, and M9, and the current bias transistors are MOSFETs M4, M5, and M6. 10 and MOSFET M 11The first common-mode feedback circuit of the fully differential gain bootstrap amplifier may include: switches φ11, φ12, φ13, φ14, φ21, φ22, φ23, φ24, capacitors C11, C12, C21, and C22; wherein, the first terminal of switch φ11 is connected to the bias voltage Vcm, and the second terminal is connected to the first terminal of capacitor C11; the first terminal of switch φ12 is connected to the bias voltage Vcm, and the second terminal is connected to the first terminal of capacitor C12; the first terminal of switch φ13 is connected to the bias voltage Vbias1, and the second terminal is connected to the second terminal of capacitor C11; the first terminal of switch φ14 is connected to the bias voltage Vbias1, and the second terminal is connected to the second terminal of capacitor C12; The first end of φ21 is connected to the first end of capacitor C11, and the second end is connected to the first end of capacitor C21; the first end of switch φ22 is connected to the first end of capacitor C12, and the second end is connected to the first end of capacitor C22; the first end of switch φ23 is connected to the second end of capacitor C11, and the second end is connected to the second end of capacitor C21; the first end of switch φ24 is connected to the second end of capacitor C12, and the second end is connected to the second end of capacitor C22; the first end of capacitor C21 is connected to the output port VOUTP1 of the fully differential gain bootstrap amplifier, and the first end of capacitor C22 is connected to the output port VOUTN1 of the fully differential gain bootstrap amplifier; the second ends of capacitors C21 and C22 are both connected to the common-mode feedback voltage Vcmfb1.

[0109] Capacitors C11 and C12 have the same capacitance, and capacitors C21 and C22 have the same capacitance, but capacitor C21 has a smaller capacitance than capacitor C11. With switches φ11, φ12, φ13, and φ14 closed, bias voltages Vcm and Vbias1 are connected. The two ends of capacitor C11 are connected to the amplifier's output terminal VOUTN1 and the common-mode feedback voltage Vcmfb1, respectively. The two ends of capacitor C12 are connected to the amplifier's output terminal VOUTP1 and the common-mode feedback voltage Vcmfb1, respectively. With switches φ21, φ22, φ23, and φ24 closed, capacitors C11 and C21 are connected in parallel, and capacitors C12 and C22 are connected in parallel.

[0110] The first residual voltage Vres1 of the Flash ADC output is amplified by using a fully differential gain bootstrap amplifier for processing by the subsequent two-stage multi-channel Pipelined SAR ADC.

[0111] A schematic diagram of the structure of a two-stage, multi-channel pipelined SAR ADC, as shown below. Figure 4 As shown, Figure 4 Here is an example image with 4 sub-channels. Figure 4As can be seen, both the first and second stages of the two-stage multi-channel pipelined SAR ADC employ multi-channel pipelined successive approximation analog-to-digital converters; each sub-channel pipelined successive approximation analog-to-digital converter includes a sampling switch, sampling capacitor, comparator, SAR dynamic logic, switch array, and register array; among which,

[0112] The first terminal of the sampling switch serves as the input terminal of a multi-channel pipelined successive approximation analog-to-digital converter, and the second terminal is connected to the first terminal of the sampling capacitor.

[0113] The first end of the sampling capacitor is connected to the output of the switch array, and the second end is connected to the input of the comparator.

[0114] The positive input terminal of the comparator is connected to the positive input signal on the sampling capacitor, the negative input terminal is connected to the negative input signal on the sampling capacitor, and the output terminal is connected to the input terminal of the SAR dynamic logic.

[0115] The output of the SAR dynamic logic is connected to the input of the switch array;

[0116] The input of the register array is connected to the output of the SAR dynamic logic, and the output serves as the output of a multi-channel pipelined successive approximation analog-to-digital converter.

[0117] The sampling rate of the two-stage multi-channel pipelined SAR ADC can reach 31.25 MSPs. In this ADC, each sub-channel pipelined successive approximation analog-to-digital converter shares a fully differential ring amplifier, and the quantization bit depth of each sub-channel pipelined successive approximation analog-to-digital converter is 10-14 bits. In the two-stage multi-channel pipelined SAR ADC, the sampling capacitors of the first stage are sampled by the lower-stage board, and the sampling capacitors of the second stage are sampled by the upper-stage board. Each sub-channel includes one sampling capacitor. For the first stage, the sampling capacitors are Cs1, Cs2, Cs3, and Cs4. Under the control of the clock signal, each sampling capacitor is sequentially connected to the output ports VOUTP1 and VOUTN1 of the fully differential gain bootstrap amplifier to sample the amplified first signal, which is then sampled onto the capacitor arrays Cs1, Cs2, Cs3, and Cs4.

[0118] In a two-stage, multi-channel pipelined SAR ADC (analog-to-digital converter), sampling switches φs1, φs2, φs3, and φs4 are sequentially activated under the control of four non-overlapping clock phases. Under the control of these switches, the amplified residual voltage is connected to the lower-level boards of the capacitor arrays Cs1, Cs2, Cs3, and Cs4 for the four channels, respectively. When the amplified residual voltage is sampled onto capacitor array Cs1, channel T1 begins quantization. The quantization process involves sampling capacitors, comparators, SAR dynamic logic, switch arrays, and register arrays. Simultaneously, the comparator compares the voltage at the positive and negative input terminals of the capacitor array, which serves as the sampling capacitor, and transmits the comparison result to the SAR logic dynamic circuit. The SAR logic dynamic circuit generates the corresponding logic result based on the comparison result and feeds it back to the switch array, comparator, and register array. At this point, the switch array switches accordingly based on the feedback result, thereby changing the voltage on the capacitor array. The register array stores the feedback result and outputs the first-stage quantization result D<1:N1> to the register delay alignment circuit. For the first-stage quantization result D<1:N1>, N1 is the number of quantization bits in the first stage of the two-stage multi-channel Pipelined SAR ADC. The operation of the remaining channels T2, T3, and T4 in the first stage is the same as that of channel T1.

[0119] After the first-stage quantization of the two-stage multi-channel pipelined SAR ADC is completed, the fully differential ring amplifier amplifies the residual voltage on the first-stage array as the inter-stage residual voltage Vres2, which is then passed to the second-stage capacitor array to begin the second-stage quantization process. Specifically, the inter-stage residual voltage Vres2 is controlled by four switches φss1, φss2, φss3, and φss4, which are connected to the upper-level board of the capacitor arrays Css1, Css2, Css3, and Css4 of the four sub-channels, respectively. Switches φss1, φss2, φss3, and φss4 are sequentially opened under the control of four non-overlapping clock phases. When the amplified signal is sampled onto capacitor array Cps1, channel T1 begins quantization. The quantization process is completed jointly by the sampling capacitors, comparators, SAR dynamic logic, and the switch array. The comparator compares the voltage at the positive input terminal and the voltage at the negative input terminal of the capacitor array, which serves as the sampling capacitor. The comparison result is passed to the SAR dynamic logic. The SAR dynamic logic generates a corresponding logic result based on the comparison result and feeds it back to the switch array, comparator, and register array. At this point, the switch array switches accordingly based on the feedback result, thereby changing the voltage on the capacitor array. The register array stores the feedback result and sends the second-stage quantization result D<1:N2> to the register delay alignment circuit. For the second-stage quantization result D<1:N2>, N2 is the number of quantization bits in the second stage of the two-stage multi-channel Pipelined SAR ADC. The operation of the remaining channels T2, T3, and T4 in the second stage is the same as that of channel T1.

[0120] The two-stage, multi-channel pipelined SAR ADC employs time-domain interleaving technology. Under the control of a clock circuit, each channel sequentially quantizes the amplified signal corresponding to that channel, which may include:

[0121] In a two-stage multi-channel pipelined SAR ADC, the sampling switches of each stage are turned on sequentially under the control of the non-overlapping clock output by the clock circuit, thereby quantizing the amplified signal received by the channel corresponding to the sampling switch.

[0122] Specifically, the implementation of the subsequent local interleaving technology is as follows: time-domain interleaving technology is adopted in the subsequent two-stage multi-channel Pipelined SAR ADC. The speed of the Pipelined SAR ADC is improved by time-domain interleaving technology. Compared with the traditional Pipelined SAR ADC, the two-stage multi-channel Pipelined SAR ADC proposed in this embodiment can achieve a higher speed. In the subsequent two-stage multi-channel Pipelined SAR ADC, the accuracy and speed of the analog-to-digital converter are significantly improved by using time-domain interleaving technology and operational amplifier sharing technology, while reducing the power consumption and area of ​​the analog-to-digital converter.

[0123] Fully differential ring amplifier, such as Figure 5 As shown, it may include a three-stage inverter and a second common-mode feedback circuit.

[0124] In a three-stage inverter

[0125] The first stage may include: an inverting amplifying MOS transistor group, a bias transistor group, and a local common-mode feedback circuit; wherein...

[0126] The first input terminal of the inverting MOSFET group serves as the positive input terminal of the first stage, the second input terminal serves as the negative input terminal of the first stage, the positive output terminal serves as the positive output terminal of the first stage, and the negative output terminal serves as the negative output terminal of the first stage.

[0127] The first bias output terminal of the bias transistor group is connected to the first bias terminal of the inverting MOSFET group, and the second bias output terminal is connected to the second bias terminal of the inverting MOSFET group.

[0128] The first terminal of the local common-mode feedback circuit is connected to the positive output terminal of the inverting MOSFET group, and the second terminal is connected to the negative output terminal of the inverting MOSFET group.

[0129] The inverting amplifier MOSFET group may include: MOSFET NM1, MOSFET NM2, MOSFET PM3, and MOSFET PM4; the bias transistor group includes MOSFET NM... 01 MOSFET NM 02 MOSFET NM 03The source of MOSFET PM0 is used as the second bias terminal, and the gate of MOSFET NM1 is used as the positive input terminal of the first stage of the three-stage inverter. The drain of MOSFET PM3 is connected to the drain of MOSFET PM4, serving as the negative output terminal OUTN1 of the first stage. The source of MOSFET NM2 is connected to the source of MOSFET NM1, and the gate of MOSFET NM2 is used as the negative input terminal of the first stage of the three-stage inverter. The drain of MOSFET PM4 is connected to the drain of MOSFET PM0, serving as the positive output terminal OUTP1 of the first stage. The source of MOSFET PM3 is connected to the drain of MOSFET PM0, and the gate of MOSFET NM1 is connected to the gate of MOSFET NM2. The source of MOSFET PM3 is connected to the drain of MOSFET PM0 and serves as the first bias terminal, while the gate of MOSFET PM3 is connected to the gate of MOSFET NM1. The source of MOSFET PM4 is connected to the drain of MOSFET PM0, and the gate of MOSFET PM4 is connected to the gate of MOSFET NM2. The source of MOSFET PM0 is connected to the power supply voltage VDD, the gate is connected to the bias voltage Vbp2, and the drain serves as the first bias output terminal. 01 The source of the MOSFET is grounded, the gate is connected to a bias voltage VFB1, and the drain is used as the second bias output terminal; MOSFET NM 02 The source and NM of the MOS transistor 01 The source is connected, the gate is biased by voltage VFB1, and the drain is connected to the MOSFET NM. 01 Drain connection; MOSFET NM 03 The source and NM of the MOS transistor 02 The source is connected, the gate is connected to the common-mode feedback voltage Vcmfb2 of the fully differential ring amplifier, and the drain is connected to the MOSFET NM. 02 The drain connection. Understandably, the MOSFET NM... 01 MOSFET NM 02 and MOSFET NM 03 These are MOSFETs of the same specifications.

[0130] The aforementioned local common-mode feedback circuit connects the output terminals OUTN1 and OUTP1 through two resistors R of equal value. 11 and R 22 The connection is established, and the bias voltage VFB1 is passed to the gate of the MOSFET NM1. By changing the value of VFB1, the current of the first stage can be controlled, thereby adjusting the value of the output common-mode voltage of the first stage and stabilizing the output common-mode voltage of the first stage.

[0131] The positive input of the second stage is connected to the positive output of the first stage, the negative input is connected to the negative output of the first stage, the positive output is connected to the positive input of the third stage, and the negative output is connected to the positive input of the third stage.

[0132] The second stage may include MOSFETs NM5, NM6, PM7, and PM8, and the dead zone resistor R.33 and R 44 The second stage of the fully differential ring amplifier is an inverting amplifier circuit, which is connected through the dead-time resistor R. 33 and R 44 A dead-time voltage VDZ is provided to the third stage, causing the MOSFET in the third stage to quickly enter the cutoff region from the saturation region, thereby achieving rapid amplification. The source of MOSFET NM5 is grounded, its gate is connected to the negative output terminal OUTN1 of the first stage, and its drain is connected to resistor R. 33 The second terminal is connected; the source of MOSFET PM7 is connected to the power supply voltage VDD, the gate is connected to the gate of MOSFET NM5, and the drain is connected to resistor R. 33 The first terminal is connected; the source of MOSFET NM6 is grounded, the gate is connected to the positive output terminal OUTP1 of the first stage, and the drain is connected to resistor R. 44 The second terminal is connected; the source of MOSFET PM8 is connected to the power supply voltage VDD, the gate is connected to the gate of MOSFET NM6, and the drain is connected to resistor R. 44 The first end is connected.

[0133] The positive output terminal of the third stage is connected to the positive output terminal of the second common-mode feedback circuit, serving as the positive output terminal of the fully differential ring amplifier. The negative output terminal is connected to the negative output terminal of the second common-mode feedback circuit, serving as the negative output terminal of the fully differential ring amplifier.

[0134] The third stage can include: MOSFET NM9, MOSFET NM 10 MOSFET PM 11 MOSFET PM 12 The second common-mode feedback circuit; wherein, the source of MOSFET NM9 is grounded, and the gate and resistor R 33 The second terminal is connected, and the drain terminal is connected to the MOSFET PM. 11 The drain terminal is connected as the negative output terminal OUTN3 of the third stage; MOSFET PM 11 The source is connected to the power supply voltage VDD, and the gate is connected to the resistor R. 33 The first terminal is connected; MOSFET NM 10 The source is grounded, the gate and resistor R 44 The second terminal is connected, and the drain terminal is connected to the MOSFET PM. 12 The drain terminal is connected as the positive output terminal OUTP3 of the third stage; MOSFET PM 12 The source is connected to the power supply voltage VDD, and the gate is connected to the resistor R. 33 The first end is connected.

[0135] The structure of the second common-mode feedback circuit described above is similar to that of the first common-mode feedback circuit, and may include: switches φ31, φ32, φ33, φ34, φ41, φ42, φ43, and φ44; capacitors C31, C32, C41, and C42. When switches φ31, φ32, φ33, and φ34 are closed, bias voltages Vcm and Vbias2 are connected to the circuit. When switches φ41, φ42, φ43, and φ44 are closed, capacitors C31 and C41 are connected in parallel, and capacitors C32 and C42 are connected in parallel.

[0136] The register delay alignment circuit reconstructs the binary code D<1:N0>, the first-level quantization result D<1:N1>, and the second-level quantization result D<1:N2> in the time dimension, stores the reconstructed data, and sends its stored data to the digital correction circuit after receiving the second-level quantization result D<1:N2>.

[0137] The digital correction circuit, under the control of the clock circuit, corrects the received binary data, eliminates inter-stage gain error and capacitor mismatch error, and outputs the corrected analog-to-digital conversion result to solve the timing deviation problem.

[0138] The two-stage multi-channel Pipelined SAR ADC in the high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving provided in this embodiment of the invention employs time-domain interleaving technology to achieve post-stage local interleaving, thereby improving the speed of the Pipelined SAR ADC. Simultaneously, the front-stage Flash ADC does not employ time-domain interleaving, thus avoiding sampling clock skew errors. Compared to traditional Pipelined ADCs, the architecture of this invention achieves higher energy efficiency. In the post-stage two-stage multi-channel Pipelined SAR ADC, time-domain interleaving and operational amplifier sharing technologies significantly improve the accuracy and speed of the analog-to-digital converter while reducing its power consumption and area.

[0139] It should be noted that, in the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0140] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving, characterized in that, include: Clock circuit, Flash ADC, fully differential gain bootstrap amplifier, two-stage multi-channel pipelined SAR ADC, register delay alignment circuit, and digital correction circuit; among which, The clock circuit is used to control the working status of the other modules; The Flash ADC is used to quantize the input signal under the control of the clock circuit to obtain binary code D<1:N0> and the first residual voltage Vres1; The fully differential gain bootstrap amplifier is used to amplify the first residual voltage Vres1 under the control of the clock circuit and output the first amplified signal. The two-stage multi-channel Pipelined SAR ADC employs time-domain interleaving technology. The first stage, under the control of the clock circuit, sequentially quantizes the first amplified signal corresponding to each channel of its own channel, outputting the corresponding first-stage quantization result D<1:N1> and inter-stage residual voltage Vres2. The inter-stage residual voltage Vres2 is amplified using a fully differential ring amplifier between the two stages, outputting a second amplified signal. The second stage, also under the control of the clock circuit, sequentially quantizes the second amplified signal corresponding to each channel of its own channel, outputting the second-stage quantization result D<1:N2>. The register delay alignment circuit is used to reconstruct the binary code D<1:N0>, the first-level quantization result D<1:N1>, and the second-level quantization result D<1:N2> in the time dimension under the control of the clock circuit, store the reconstructed binary data, and send its stored binary data to the digital correction circuit after receiving the second-level quantization result D<1:N2>. The digital correction circuit is used to correct the received binary data under the control of the clock circuit, eliminate inter-stage gain error and capacitor mismatch error, and output the corrected analog-to-digital conversion result.

2. The high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving according to claim 1, characterized in that, The Flash ADC includes: The sample-and-hold circuit (S / H), comparator, capacitor array, switch array, and encoder are included; among them, The input terminal of the sample-and-hold circuit S / H is connected to the input signal, and the output terminal is connected to the first input terminal of the capacitor array. The output terminal of the capacitor array is connected to the positive input terminal of the comparator; The negative input terminal of the comparator is connected to the reference voltage Vref, and the output terminal is connected to the input terminal of the encoder. The input terminal of the switch array is connected to the output terminal of the encoder, and the output terminal is connected to the second input terminal of the capacitor array.

3. The high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving according to claim 2, characterized in that, The Flash ADC quantizes the input signal to obtain binary code D<1:N0> and a first residual voltage Vres1, including: The sample-and-hold circuit S / H samples the input signal and holds the sampled signal on the lower-level board of the capacitor array. By switching the switch array, the signal on the lower-level board of the capacitor array is transmitted to the upper-level board of the capacitor array. The comparator compares the voltage on the upper board of the capacitor array with the reference voltage Vref to obtain the thermometer code; The encoder processes the thermometer code to obtain the binary code D<1:N0>; The switch array switches according to the binary code D<1:N0>, thereby changing the voltage on the upper board of the capacitor array to obtain the first residual voltage Vres1; where the thermometer code is 2. N0 -1 bit, binary code is N0 bits.

4. The high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving according to claim 1, characterized in that, The fully differential gain bootstrap amplifier is a folded cascode amplifier, comprising: MOSFET M1, MOSFET M2, MOSFET M3, MOSFET M4, MOSFET M5, MOSFET M6, MOSFET M7, MOSFET M8, MOSFET M9, MOSFET M 10 MOSFET M 11 Auxiliary amplifier A, auxiliary amplifier B, and the first common-mode feedback circuit; among which, The source of the MOS transistor M1 is connected to the drain of the MOS transistor M3, the gate serves as the negative input terminal of the fully differential gain bootstrap amplifier, and the drain is connected to the drain of the MOS transistor M4. The source of MOS transistor M2 is connected to the source of MOS transistor M1, the gate serves as the positive input terminal of the fully differential gain bootstrap amplifier, and the drain is connected to the drain of MOS transistor M5. The source of the MOSFET M3 is connected to the power supply voltage VDD, and the gate is connected to the bias voltage Vbp. The source of the MOS transistor M4 is connected to the source of the MOS transistor M5, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M5, and the drain of the MOS transistor M4 is connected to the positive input terminal of the auxiliary amplifier B. The source of the MOS transistor M5 is grounded, the gate is connected to a bias voltage Vbn1, and the drain is connected to the negative input terminal of the auxiliary amplifier B. The source of the MOS transistor M6 is connected to the positive input terminal of the auxiliary amplifier B, the gate is connected to the negative output terminal of the auxiliary amplifier B, and the drain is connected to the drain of the MOS transistor M8, serving as the output port VOUTP1 of the fully differential gain bootstrap amplifier. The source of the MOS transistor M7 is connected to the negative input terminal of the auxiliary amplifier B, the gate is connected to the positive output terminal of the auxiliary amplifier B, and the drain is connected to the drain of the MOS transistor M9, serving as the output port VOUTN1 of the fully differential gain bootstrap amplifier. The source of the MOS transistor M8 is connected to the positive input terminal of the auxiliary amplifier A, the gate is connected to the negative output terminal of the auxiliary amplifier A, and the drain is connected to the drain of the MOS transistor M6. The source of the MOS transistor M9 is connected to the negative input terminal of the auxiliary amplifier A, the gate is connected to the positive output terminal of the auxiliary amplifier A, and the drain is connected to the drain of the MOS transistor M7. The MOS transistor M 10 The source is connected to the power supply voltage VDD, and the gate is connected to the MOS transistor M. 11 The gate is connected, and the drain is connected to the positive input terminal of the auxiliary amplifier A; The MOS transistor M 11 The source is connected to the power supply voltage VDD, the gate is connected to the bias voltage Vbp1, and the drain is connected to the negative input terminal of the auxiliary amplifier A. The input terminal of the first common-mode feedback circuit is connected to the common-mode feedback voltage Vcmfb1, the first output terminal is connected to the output port VOUTP1 of the fully differential gain bootstrap amplifier, and the second output terminal is connected to the output port VOUTN1 of the fully differential gain bootstrap amplifier.

5. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving as described in claim 1, characterized in that, The first and second stages of the two-stage multi-channel pipelined SAR ADC both employ multi-channel pipelined successive approximation analog-to-digital converters (ADCs). Each sub-channel pipelined successive approximation ADC includes a sampling switch, a sampling capacitor, a comparator, SAR dynamic logic, a switch array, and a register array. The first terminal of the sampling switch serves as the input terminal of a multi-channel pipelined successive approximation analog-to-digital converter, and the second terminal is connected to the first terminal of the sampling capacitor. The first end of the sampling capacitor is connected to the output of the switch array, and the second end is connected to the input of the comparator. The positive input terminal of the comparator is connected to the positive input signal on the sampling capacitor, the negative input terminal is connected to the negative input signal on the sampling capacitor, and the output terminal is connected to the input terminal of the SAR dynamic logic. The output of the SAR dynamic logic is connected to the input of the switch array; The input of the register array is connected to the output of the SAR dynamic logic, and the output serves as the output of a multi-channel pipelined successive approximation analog-to-digital converter.

6. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving as described in claim 5, characterized in that, In the two-stage multi-channel pipelined SAR ADC, the quantization bits of each sub-channel pipelined successive approximation analog-to-digital converter are 10-14 bits.

7. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving as described in claim 5, characterized in that, In the two-stage multi-channel Pipelined SAR ADC, the sampling capacitor of the first stage is sampled by the lower stage board, and the sampling capacitor of the second stage is sampled by the upper stage board.

8. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving as described in claim 5, characterized in that, The two-stage multi-channel pipelined SAR ADC employs time-domain interleaving technology. Under the control of the clock circuit, each channel sequentially quantizes the amplified signal corresponding to that channel, including: In the two-stage multi-channel Pipelined SAR ADC, the sampling switches of each stage are turned on sequentially under the control of the non-overlapping clock output by the clock circuit, thereby quantizing the amplified signal received by the channel corresponding to the sampling switch.

9. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving according to claim 1, characterized in that, The fully differential ring amplifier includes a three-stage inverter and a second common-mode feedback circuit.

10. A high-speed, high-precision hybrid architecture analog-to-digital converter based on post-stage local interleaving as described in claim 9, characterized in that, In the three-stage inverter, The first stage includes: an inverting amplification MOSFET group, a bias MOSFET group, and a local common-mode feedback circuit; among which... The first input terminal of the reverse amplifying MOS transistor group serves as the positive input terminal of the first stage, the second input terminal serves as the negative input terminal of the first stage, the positive output terminal serves as the positive output terminal of the first stage, and the negative output terminal serves as the negative output terminal of the first stage. The first bias output terminal of the bias transistor group is connected to the first bias terminal of the inverting amplifying MOS transistor group, and the second bias output terminal is connected to the second bias terminal of the inverting amplifying MOS transistor group. The first terminal of the local common-mode feedback circuit is connected to the positive output terminal of the inverting MOS transistor group, and the second terminal is connected to the negative output terminal of the inverting MOS transistor group. The positive input of the second stage is connected to the positive output of the first stage, the negative input is connected to the negative output of the first stage, the positive output is connected to the positive input of the third stage, and the negative output is connected to the positive input of the third stage. The positive output terminal of the third stage is connected to the positive output terminal of the second common-mode feedback circuit, serving as the positive output terminal of the fully differential ring amplifier. The negative output terminal is connected to the negative output terminal of the second common-mode feedback circuit, serving as the negative output terminal of the fully differential ring amplifier.

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