Optical data signal receiver

Abstract

The invention relates to an optical data signal receiver. An assembly for an electronic component for receiving data by using an optical fiber, where the data is received in burst form, and where the assembly comprises: a photodiode; a transimpedance amplifier coupled to the photodiode, wherein a gain of the transimpedance amplifier is adjusted based on a level of a gain control signal; a receive input signal sensor configured to sense a receive input signal level and provide the gain control signal, the gain control signal varying according to the receive input signal level, and wherein the receive input signal level is sensed via a sampling circuit arrangement; and a regulator for adjusting the low frequency behavior and the high frequency behavior of the comparator such that the detection of positive and negative data symbol level shifts in the received signal has the same behavior within acceptance engineering tolerances.

Description

Technical Field

[0001] Some embodiments relate to systems and methods for receiving optical signals. Background Technology

[0002] This invention relates to the operation of an optical line terminal (OLT) unit used as a hub device in a passive optical network (PON) for data communication between a central hub device and multiple client optical network units (ONUs).

[0003] In such a system, data to be sent from each ONU to the OLT is typically transmitted in time-division multiplexing as short data bursts. Due to differences in optical path length to each ONU and other factors, the optical signal strength of each received burst can vary significantly between different data bursts.

[0004] The problem to be solved is how the OLT receiver handles data bursts from different ONUs, separated by short time intervals and with varying signal strengths. For each data burst, the receiver electronics must set amplification levels and other system parameters so that the information can be successfully recovered in subsequent electronics. The receiver path electronics should preferably adapt its characteristics to the signal strength of each input burst within a very short time interval, typically with a very short training signal available during the preamble period before the data payload. This adaptation should also preferably be performed within a settling time that remains consistent with the wide range of signal levels and different data rates expected for each burst. Furthermore, this adaptation should preferably adjust the settling time based on the presence of the training preamble or the payload data to provide optimized control over the system gain in both cases. The adaptive device configured to control amplification and stabilization in response to each individual data burst should also preferably be insensitive to errors and defects in the included electronics, or, to take these errors and defects into account, be easily adjustable.

[0005] The purpose of this invention is to provide an apparatus for calibrating a clock system that controls the sampling of the TIA output of a TIA AGC system, thereby minimizing both low-frequency and high-frequency defects in the sampling clock generation circuit. Summary of the Invention

[0006] According to one aspect of the present invention, a system is provided comprising: an assembly of electronic components for receiving data using an optical fiber, wherein the data is received in burst form, and wherein the assembly comprises: a photodiode; a transimpedance amplifier coupled to the photodiode, wherein the gain of the transimpedance amplifier is adjusted based on the level of a gain control signal, and wherein the transimpedance amplifier comprises: a first amplifier; a network of electronic components presenting impedance between two terminals, wherein one terminal of the network of electronic components presenting impedance is coupled to an output of the first amplifier, and the other terminal of the network of electronic components presenting impedance is coupled to an input of the first amplifier; and a receiving input signal sensor configured to sense a received input signal level, wherein the receiving input signal sensor is configured to provide a first control signal, the first control signal being based on the received input signal level. The received input signal sensor further includes: an integrator or filter for smoothing the first control signal, the output of which is the gain control signal; a sampler for sampling the received input signal at sampling times depending on the occurrence of data symbol level transitions in the received input signal; a comparator configured to detect data symbol level transitions in the received input signal, wherein the sampling time of the sampler is derived from the output of the comparator; and a regulator for adjusting the low-frequency and high-frequency behavior of the comparator such that the detection of both positive and negative data symbol level transitions in the received signal has the same behavior within acceptable engineering tolerances, and wherein the regulator further includes: a calibration controller; a low-frequency calibration arrangement; and a high-frequency calibration arrangement.

[0007] The comparator may have differential inputs and complementary logic outputs, wherein the logic high values ​​of each of the complementary outputs are the same within the acceptable engineering limit, and wherein the logic low values ​​of each of the complementary outputs are the same within the acceptable engineering limit.

[0008] At least one input of the comparator can be connected to the received signal via at least one capacitor.

[0009] The comparator can be configured to disconnect from the received signal and to receive a low-frequency ramp calibration input with a defined level.

[0010] The low-frequency calibration setup can be configured to analyze the decisions generated by the comparator in response to a low-frequency ramp calibration input with a defined level.

[0011] The low-frequency calibration arrangement can be configured, under the control of the low-frequency controller, to reduce any loss of symmetry between the positive and negative decision levels of the comparator to a negligible level through adjustments made by the regulator.

[0012] The high-frequency calibration arrangement may include a passive low-pass filter connected to each of the complementary outputs of the comparators, wherein the cutoff frequency of the passive low-pass filter is significantly lower than the lowest frequency component expected in the received signal when the components of the electronics are configured to receive the signal.

[0013] The input from the photodiode can be disconnected, and a high-frequency test signal is applied to the input of the transimpedance amplifier.

[0014] The high-frequency calibration setup may also include a high-frequency signal source, wherein the high-frequency signal source provides the high-frequency test signal having a frequency equivalent to the frequency of the preamble pattern appearing in the data burst, and wherein the high-frequency test signal has a magnitude equivalent to the magnitude of the signal received from the photodiode, and wherein the high-frequency test signal has a basic square wave waveform having a mark-space ratio equal within acceptable engineering tolerances.

[0015] The outputs of the passive low-pass filters can be compared, and the difference between the DC levels present at the outputs of each passive low-pass filter is transmitted to the calibration controller. The high-frequency calibration arrangement is configured to reduce the difference between the DC levels of the outputs of the low-pass filters to a negligible value through adjustment of the regulator under the control of the calibration controller.

[0016] According to a second aspect of the invention, a method for receiving data using an optical fiber is provided, wherein the data is received in burst form, and wherein the method comprises: setting a photodiode; setting a transimpedance amplifier coupled to the photodiode, wherein the gain of the transimpedance amplifier is adjusted based on the level of a gain control signal, and wherein the transimpedance amplifier comprises: a first amplifier; a network of electronic components presenting impedance between two terminals, wherein one terminal of the network of electronic components presenting impedance is coupled to an output of the first amplifier, and the other terminal of the network of electronic components presenting impedance is coupled to an input segment of the first amplifier; setting a receive input signal sensor configured to sense a receive input signal level, wherein the receive input signal sensor is configured to provide a first control signal, the first control signal varying according to the receive input signal level. The received input signal sensor further includes: an integrator or filter for smoothing the first control signal, the output of which is the gain control signal; a sampler for sampling the received input signal, wherein the sampler samples the received input signal at sampling times depending on the occurrence of data symbol level transitions in the received input signal; a comparator configured to detect data symbol level transitions in the received input signal, wherein the sampling time of the sampler is derived from the output of the comparator; and a regulator for adjusting the low-frequency and high-frequency behavior of the comparator such that the detection of both positive and negative data symbol level transitions in the received signal has the same behavior within acceptance engineering tolerances, and wherein the regulator further includes: a calibration controller; a low-frequency calibration arrangement; and a high-frequency calibration arrangement.

[0017] The comparator may have differential inputs and complementary logic outputs, wherein the logic high values ​​of each of the complementary outputs are the same within the acceptable engineering limit, and wherein the logic low values ​​of each of the complementary outputs are the same within the acceptable engineering limit.

[0018] At least one input of the comparator can be connected to the received signal via at least one capacitor.

[0019] The comparator set in the method can be configured to be disconnected from the received signal and configured to receive a low-frequency ramp calibration input with a defined level.

[0020] The low-frequency calibration arrangement set in the method can be configured to analyze the decisions generated by the comparator in response to the low-frequency ramp calibration input having a defined level.

[0021] The low-frequency calibration arrangement set in the method can be configured, under the control of the calibration controller, to reduce any loss of symmetry between the positive and negative decision levels of the comparator to a negligible level through the adjustment of the regulator.

[0022] The high-frequency calibration arrangement set in the method may include a passive low-pass filter connected to each of the complementary outputs of the comparators, wherein when the components of the electronics are configured to receive the signal, the cutoff frequency of the passive low-pass filter is significantly lower than the lowest frequency component expected in the received signal.

[0023] In the method, the input from the photodiode can be disconnected, and a high-frequency test signal is applied to the input of the transimpedance amplifier.

[0024] The high-frequency calibration arrangement set in the method may further include a high-frequency signal source, wherein the high-frequency signal source provides the high-frequency test signal having a frequency equivalent to the frequency of the preamble pattern appearing in the data burst, and wherein the high-frequency test signal has a magnitude equivalent to the magnitude of the signal received from the photodiode, and wherein the high-frequency test signal has a basic square wave waveform having a mark-space ratio equal within acceptable engineering tolerances.

[0025] The outputs of the passive low-pass filters configured in the method can be compared, and the difference between the DC levels present at the outputs of each passive low-pass filter is transmitted to the calibration controller. The high-frequency calibration arrangement is further configured to reduce the difference between the DC levels of the outputs of the low-pass filters to a negligible small value under the control of the calibration controller and through the adjustment of the regulator. Attached Figure Description

[0026] The invention will now be described by way of example only and with reference to the accompanying drawings, wherein:

[0027] Figure 1 This illustrates a typical arrangement of a passive optical network system based on existing technology, showing bursts of different amplitudes and extinction ratios that occur during system operation.

[0028] Figure 2 The performance and timing specification parameters of a typical data burst used in a passive optical network according to the prior art are shown.

[0029] Figure 3 This represents a typical arrangement of the input circuitry in a PON receiver according to the prior art, where there are separate time constants for DC removal and automatic gain control.

[0030] Figure 4 The diagram illustrates the expected behavior in a PON receiver according to the prior art, where the AGC response has a slow, fixed time constant.

[0031] Figure 5 The diagram illustrates the expected behavior in a PON receiver according to the prior art, where the AGC response has a fast fixed time constant.

[0032] Figure 6 This describes the arrangement of a PON receiver according to one aspect of the invention, wherein the AGC time constant varies according to the data conversion density in a burst.

[0033] Figure 7 The form of the expected behavior in a PON receiver according to one aspect of the invention is shown, wherein the time constant of the AGC response changes from fast to slow before the end of the preamble of the data burst.

[0034] Figure 8 This illustrates the arrangement of a PON receiver according to one aspect of the invention, wherein the AGC is controlled by a circuit including a signal path for a switched capacitor, and wherein sampling of the switched capacitor is controlled by a conversion in the input data.

[0035] Figure 9 This invention illustrates the derivation of a sampling control signal from an input signal, wherein transitions on the edges of the input data can be used to provide a sampling control signal for a switched capacitor circuit used in AGC control (data waveform samples obtained at predictable times).

[0036] Figure 10 This illustrates an arrangement of a PON receiver according to one aspect of the invention, wherein the AGC is controlled by a circuit including a switched capacitor signal path, and wherein sampling of the switched capacitor is controlled by a circuit including a frequency divider controlled by a conversion in the input data.

[0037] Figure 11 This invention illustrates the derivation of a sampling control signal from an input signal preamble, wherein transitions on the edges of the input data can be used to control an odd-number divider to provide a sampling control signal for a switched-capacitor circuit used in AGC control (data waveform samples obtained at predictable times).

[0038] Figure 12 This invention illustrates deriving a sampling control signal from an input signal during data payload, wherein transitions on the edges of the input data can be used to control an odd-number divider to provide a sampling control signal for a switched-capacitor circuit used in AGC control (acquiring data waveform samples at predictable times).

[0039] Figure 13 This illustrates the arrangement of a PON receiver according to one aspect of the invention, wherein a comparator AC used to provide a sampling signal for a switched capacitor circuit in an AGC system is coupled to the signal path.

[0040] Figure 14 The ideal behavior of a comparator with hysteresis is shown, which can be used to provide a sampling signal for a switched capacitor circuit in an AGC system.

[0041] Figure 15 This describes the arrangement of a PON receiver according to one aspect of the invention, wherein means are provided for calibrating the DC and AC performance of the comparator used to provide sampling signals for the switched capacitor circuit in the AGC system.

[0042] Figure 16 A method according to one aspect of the invention is shown for calibrating the DC and AC performance of a comparator used to provide a sampling signal for a switched capacitor circuit in an AGC system.

[0043] Figure 17 This describes an arrangement of a PON receiver according to one aspect of the invention, wherein the time constant in the AGC circuit can be changed from fast to slow by altering the resistance generated in the input signal path, and wherein the change in the signal path resistance is controlled by a timing circuit that determines the duration or end of the preamble.

[0044] Figure 18 This describes the arrangement of a PON receiver according to one aspect of the invention, wherein the time constant in the AGC circuit can be changed from fast to slow by connecting an additional capacitor, and wherein the connection of said capacitor is controlled by a timing circuit that determines the duration or end of the preamble.

[0045] Figure 19 This describes an arrangement according to one aspect of the invention for detecting the end of a preamble in a burst-mode PON receiver, wherein a detection threshold level is set during the preamble.

[0046] Figure 20 This describes an arrangement for detecting the end of a preamble in a burst-mode PON receiver according to one aspect of the invention, wherein a ramp signal controlled by data conversion does not cross a previously set detection threshold level during the preamble.

[0047] Figure 21 This describes an arrangement according to one aspect of the invention for detecting the end of a preamble in a burst-mode PON receiver, wherein a ramp signal controlled by data transitions crosses a previously set detection threshold level during the data payload and generates a signal indicating that the preamble has ended.

[0048] Figure 22 This describes an arrangement according to one aspect of the invention for detecting the end of a preamble in a burst-mode PON receiver, wherein a ramp signal controlled by a data transition is used, and the crossing of the detection threshold level by the ramp signal is detected by a comparator triggered by a clock at a subsequent data transition moment before the ramp is reset.

[0049] Figure 23 The behavior of an arrangement for detecting the end of a preamble in a burst-mode PON receiver according to one aspect of the invention is illustrated, wherein a ramp signal controlled by a data transition is used, wherein the crossing of the detection threshold level by the ramp signal is detected by a comparator triggered by a clock at a subsequent data transition moment before the ramp is reset, and provides a signal indicating that the preamble has ended. Detailed Implementation

[0050] Although the invention has been described with reference to specific examples and possible embodiments thereof, these descriptions should not be construed as limiting the scope of the invention in any way. It should be understood that many other possible embodiments, modifications, and improvements may be incorporated into or used in conjunction with the invention without departing from the scope and spirit of the invention as set forth in the claims.

[0051] Figure 1 This illustrates a typical arrangement of transceivers suitable for an optical communication system. Within an optical line terminal (OLT) 101, a transmitter 102 transmits data in the form of an optical signal 106, which is effectively connected in parallel to multiple individual optical fibers 103, which transmit the data signal to several individual optical network units (ONUs) 105.

[0052] Each of the input fiber 103 and output fiber 104 of each ONU 105 may have different lengths; therefore, the intensity of the optical signal received by each ONU may differ from the intensity of the signal received at some other ONUs. This variation is not a major problem for the ONU receiving path because the signal to be received is virtually constant for each consecutive data burst, exhibiting only slow variations due to environmental changes. Therefore, the gain control settings of the ONU 105 receiving circuit can be determined in some initial transmission protocol and thus remain relatively fixed for the duration of any activity.

[0053] The situation is slightly more complex for signal 107 transmitted back from ONU 105 to OLT 101. Even if the magnitude of the transmitted optical signal is the same for each ONU, the magnitude of signal 107 received by OLT receiver 108 may differ for each consecutive burst due to variations in fiber path length 104. Therefore, the gain setting of the OLT receiver 108 circuitry must be reset for each burst and optimized for the strength of each specific burst. Furthermore, this gain setting optimization process must be performed quickly and efficiently within the preamble period of the burst. Additionally, the information provided at the system level to guide this gain setting process is limited.

[0054] Figure 2 This illustrates a typical timing specification for data bursts. A specified protection time of 201T exists between the end of one burst and the start of another. G uard, the protection time is 201T G The minimum value of uard is typically on the order of 100 nanoseconds. Within this protection time and at the end of the burst, there is a pre-defined time period 202Tx. D isable, this time period 202Tx D isable is used to disable the transmission path and laser driver in a specific ONU or OLT. A pre-defined time period of 203Tx is reserved at the end of the protection interval and during the protection interval. E nable, the time period 203Tx E The preamble is used to activate the transmission path and laser driver in a specific ONU or OLT. At the start of a new data burst, there is an initial time period during which a defined preamble signal pattern 204 is transmitted for the purpose of providing a known signal. This preamble is typically a continuously balanced pattern, such as a "1010" pattern, to allow the target receiver to adjust its gain and, possibly, other parameters to optimize the reception of the burst. The preamble may have a defined minimum duration to allow the receiver to successfully adjust the circuit parameters.

[0055] Following the preamble, some form of delimiter pattern 205 indicates that the data payload 206 is about to begin. As the signal transitions from the preamble to the data payload, the data pattern typically changes from a "1010" pattern with high transition density to a more random pattern with no transitions and potentially longer intervals. The input signal may remain in "1" or "0" for several unit time intervals at the current data rate. This latter factor influences the choice of the setup time constant, which can be used in the AGC of the receiver signal path. A fast setup time, preferably selected during the preamble, tends to degrade the quality of the signal remaining in "1" or "0" states for multiple unit intervals and leads to deviations from optimal levels.

[0056] Figure 3 The diagram illustrates a typical arrangement of a transimpedance amplifier (TIA) 300 that can be used in the input circuitry of a PON receiver according to existing technology. The amplifier 301 has a feedback path 302, which can be purely resistive or include a combination of resistive and reactive components. This arrangement draws signal current from a photodiode 310 and converts it into a signal voltage, thereby facilitating subsequent signal processing circuitry.

[0057] In this TIA arrangement, it is common practice to have two separate automatic control loops within the TIA. First, there may be a control loop whose purpose is to set the gain of the amplifier system so that the amplifier output remains at a substantially constant level even if the amplitude of the input optical signal varies greatly; this is often referred to as an automatic gain control (AGC) system. Generally, the resistance (or impedance) of the feedback network 302 is adjusted in response to the detected magnitude of the signal present at the output of the TIA 303. In many cases, the TIA output signal 303 is AC-coupled to the signal detection function 304. The output of the signal detection function is passed through an integrator 305 or a low-pass filter to provide a smooth control signal 311, thereby adjusting the resistance (or impedance) of the feedback network 302.

[0058] In addition to the AGC function, a second loop is typically used to remove the DC component of the photodiode current. This is desirable because the average DC value present in the photodiode current varies depending on the intensity of the light signal (and other factors such as temperature). This DC component of the photodiode signal can be amplified by the TIA 300, and, in extreme cases, cause the amplifier response to saturate, limiting its output to one or another maximum output value, thus blocking any signal from passing through.

[0059] To mitigate the risk of TIA 300 saturation, the DC voltage level 306 at the TIA output can be applied to a differential amplifier 307, which compares the TIA output with a suitable reference level 308. The resulting error signal can then be used to drive an integrator or a low-pass filter 309. The integrated (or filtered) DC error signal can then be used to control a variable current source 310, which can be used to remove the DC component of the photodiode 310 current from the input of the TIA 300. In this way, the TIA output 303 is effectively only the AC component of the photodiode signal, thus representing the received data signal.

[0060] While using separate AGC and DC removal / recovery functions is convenient in TIAs receiving continuous signals or repetitive bursts with nearly identical amplitudes, problems remain when signal levels can fluctuate significantly between consecutive data bursts. In the latter case, two separate control loops must stabilize to optimal values ​​within the time allocated to the burst preamble. It will be clear to those skilled in the art that, in addition to being a very difficult task, the presence of two separate integration or filtering functions in a TIA arrangement introduces a significant risk of instability.

[0061] To simplify stability issues, the TIA can be designed to handle variations in the DC component of the photodiode current within the desired optical input range. Therefore, significant variations in the common-mode level at the TIA's output must be compatible with subsequent signal conditioning and processing circuitry.

[0062] Although the absence of a photodiode DC control loop in the TIA helps avoid any instability within the TIA, it still leaves questions related to the choice of the time constant used in the AGC.

[0063] Figure 4 The typical behavior of an AGC system with a relatively long time constant is shown. When a burst arrives with the system following a reset state 401 (which would be the case for an OLT receiving bursts from various ONUs), it can be seen that the AGC control 311 is not fully stable before the end of the preamble mode 204, and the TIA output 303 is not optimally conditioned when the system needs to recover data from the signal during the data payload period 206. Furthermore, the AGC system typically sets the gain to its maximum at the start of a burst, so if the optical input signal is strong, the TIA output 303 may remain saturated after the preamble ends. Clearly, slow AGC stabilization during the data payload period 206 may have some advantages because it does not respond quickly to the effects of mode density changes caused by the data itself, but slower stabilization during the payload period is disadvantageous if the AGC is not sufficiently stable during the preamble period.

[0064] Figure 5This indicates that AGC stability is configured to reflect the behavior of a relatively fast system. In this case, even if the system is reset 401 before the data burst arrives, the AGC control signal 311 may remain stable for the duration of the preamble. However, the fast response of the AGC system makes its stable level sensitive to the data pattern during the payload. It will be apparent to those skilled in the art that if a long sequence of consecutive "1" or "0" data values ​​is received, the AGC responds to a short-term average level of the TIA output 303, which may be higher or lower than the ideal common-mode level. Therefore, in order to recover the data value from the TIA output signal 303 through subsequent signal conditioning and processing circuitry, the AGC level 311 does not remain at an optimal level.

[0065] Figure 6 An arrangement of a TIA system according to one aspect of the invention to solve the aforementioned problems is shown. An AGC control loop including an integrator 601 is provided, the input of which is obtained from the output 303 of the TIA 300 via a resistor 602. The output 603 of the integrator is used to control the gain of the TIA 300, either by changing the resistance (or impedance) of the feedback path 302 or by changing the gain of the amplifier core 301 within the TIA configuration 300. A means 604 for resetting the integrator 601 between data bursts is also provided, a process that can be activated by an externally configured system-level signal.

[0066] To achieve improved stabilization of the AGC level within the preamble 204, while reducing sensitivity to data pattern density during the payload 206, the stabilization time of the integrator 601 controlling the AGC level is made variable, for example, by controlling the resistor 602 of the AGC system used to sense the output 303 of the TIA 300.

[0067] To control the stable speed of AGC at any given moment, a system is set up to detect the occurrence and density of data transitions. Figure 6 In the illustrated arrangement, this functionality is provided by using comparator 605 to detect data transitions and, based on these decisions, generating pulses 606 of equal duration and amplitude at each data transition. These pulses are smoothed using a low-pass filter 607, providing a signal 608 proportional to the data transition density. Therefore, when the data transition density is high, as in preamble 204, the AGC settling time is adjusted for a faster response. When the data density decreases, as expected during payload 206, the AGC settling time is adjusted to be slower, resulting in reduced sensitivity to consecutive identical symbol sequences.

[0068] Figure 7 Give a behavioral representation of the TIA system, where such as Figure 6As shown, the AGC settling time is adjusted according to the detected data conversion density. It can be seen that when the data conversion density is high, the AGC control level 311 stabilizes to optimal conditions during the duration of the preamble 204. During the data payload interval 206, the stabilization of the AGC control level 311 slows down, and the response to any consecutive sequences of the same data symbols decreases to a minimum.

[0069] It is clear to those skilled in the art that, despite Figure 6 The arrangement shown proposes a possible solution that considers data transformation density to ensure stable AGC behavior. Figure 6 The fact that the data transition detection arrangement itself has a stable time constant still presents a potential problem. While this is unlikely to cause instability throughout the TIA system, it does impose a limitation on how quickly the AGC settling time can respond to changes in data transition density. On the one hand, it is desirable for the smoothing of data transition information to be fast, but this could inject noise into the AGC control loop via variable elements in the AGC integrator (or filter). On the other hand, if the smoothing time constant of the data transition information is slow, the AGC settling time constant may not respond fast enough to reduce sensitivity to consecutive identical data symbols after the preamble ends.

[0070] Figure 8 This illustrates another arrangement of a TIA system according to one aspect of the invention, wherein the AGC settling time depends on the data conversion density. An integrator function 601 is provided to generate an AGC control signal 603 to set the overall gain of the TIA 300. The output of the integrator is used to control the gain of the TIA 300 either by changing the resistance (or impedance) of the feedback path 302 or by changing the gain of the amplifier core 301 within the TIA configuration. A means 604 is also provided for resetting the integrator 601 between data bursts, a process that can be activated by an externally configured system-level signal or by some timing system 804 within the TIA system itself.

[0071] Instead of using a conventional resistive input for the integrator, an input is provided for sampling the TIA output via a switched capacitor circuit arrangement 801. The sampling clocks 802 and 803 required by the switched capacitor circuit 801 are provided by a sampling clock generation and timing function 804, which in turn receives timing information from a comparator 805 that detects transitions in the data waveform present at the output 303 of the TIA 300. Preferably, to prevent erroneous responses under low-signal conditions at the TIA output, the comparator employs a degree of hysteresis during its operation.

[0072] By using a switched capacitor input to the integrator, it is clear that since the input charge (equivalent to smoothing current) supplied to the integrator 601 per unit time is directly related to each sampling period of the switched capacitor arrangement 801, the settling time of the AGC becomes directly related to the data conversion density. In this way, it avoids... Figure 6 This addresses any issues related to latency or smoothness in the data density detection scheme shown, and provides a more ideal AGC stabilization time mechanism.

[0073] Note that in order to sample the TIA output signal 303 in a symmetrical manner without introducing an inherent offset into the integrator 601 input, it is preferable to derive the sampling clock information from both the rising and falling edges of the comparator output 806.

[0074] Figure 9 Possible sampling schemes are illustrated, where both the rising and falling edges seen at the output 806 of comparator 805 derive the sampling clocks 802 and 803. Comparator 805 provides a sliced ​​version of the amplified data waveform. The sampling clocks can be generated using a pulse generator or other means, such that each edge creates a complete cycle for each sampling clock. Figure 9 In the diagram, the sampling process is shown to occur during preamble 204, where it is assumed that the data pattern is a balanced "1010" and the data rate allows the sampling circuitry to operate conflict-free at the symbol rate. It can be seen that sampling occurs during both "1" and "0" symbol periods, although not necessarily at the precise peaks or valleys of the data waveform at output 303 of TIA 300. The exact timing of the sampling process depends on any time delay in the sampling clock generation system 804; however, as long as the sampling is time-symmetric with respect to the data transition time, the sampling provides an input equivalent to the average common-mode value of the data waveform, which is expected for the correct operation of the AGC system.

[0075] In cases where the data symbol rate is so high that it is not convenient to directly derive the sampling clock from the data conversion, it may become necessary to create a sampling clock with a rate lower than the symbol rate, while still satisfying the requirement of sampling equally from data "1" and data "0" values.

[0076] Figure 10This section describes another arrangement of the TIA system according to one aspect of the invention, which addresses the clock requirement of the switched capacitor circuit 801. A frequency divider 1001 is configured to effectively divide the sliced ​​data waveform 806 by a factor of N+1 / 2, where N is an integer. One practical way to achieve this is to use both the rising and falling edges of the data conversion from the sliced ​​signal 806 from the TIA output 303 to provide the clock for the odd-numbered frequency divider. The sampling clocks 802 and 803 are then generated from the output 1002 of said frequency divider 1001. In a practical example, a divide-by-5 ​​counter can be used, thus giving an apparent division ratio of 21 / 2.

[0077] Figure 11 This illustrates how such odd-number division can be used to allow symmetrical sampling of the data signal waveform at the output 303 of the TIA 300, even when the data stream symbol rate is faster than the rate at which simple switched-capacitor sampling can be reliably clock-triggered. A preferred timing scheme is also shown, where the falling edge of the switched-capacitor sampling clocks 802, 803 is directly derived from the slice data conversion 806, while the rising edge of the switched-capacitor sampling clock is generated by a time delay element. This derivation of the sampling clock is preferred because the falling edge of sampling clock 802 defines the moment when the TIA output signal 303 is sampled (assuming a logic "1" state in sampling clock φ1 802 or φ2 803 is taken as setting the corresponding switch to the "closed" state) and therefore its timing is critical. The timing of the rising edge of the switched-capacitor clock is less critical, provided that conventional non-overlapping clock rules are followed, and can therefore be conveniently derived from a time delay element, where the delay is defined with respect to the falling edge of the sampling clock. During the balanced preamble 204 (such as “1010” mode), the sampling of the TIA output signal 303 is considered to be performed uniformly over the positive and negative offsets of the data signal waveform, thereby providing the AGC integrator 601 with an input representing the average common-mode level at the TIA output 303.

[0078] Figure 12 The diagram further illustrates how the odd-division function 1001 can be used to provide switched-capacitor sampling clocks 802 and 803, which can be used to sample the data signal waveform 303 at the output of the TIA 300 during the data payload 206. Although the sampling clocks are no longer generated at a fixed repetition rate, but rather at moments that fluctuate in time depending on the presence of data stream transitions, it can be seen that the switched-capacitor sampling function 801 is still able to provide an equal number of signal samples from the "1" and "0" states present in the data waveform.

[0079] It will be clear to those skilled in the art that the reference Figures 8-12The successful operation of the described switched capacitor sampling arrangement 801 depends to a large extent on a clock signal derived from the data stream of the TIA output signal 303, wherein such derived clock signal has well-defined timing properties.

[0080] Figure 13 This arrangement, according to one aspect of the invention, includes a differential comparator 1301 that functions to provide a precise slice signal 1302 from the data signal 303 present at the output of the TIA 300. (As...) Figure 13 As shown, the output of the TIA core amplifier 301 can be in single-ended form, and in this case, a single-ended to differential signal conversion function 1303 is typically used to provide suitable input for subsequent functions (such as the limiting amplifier 1304). Figure 13 In the illustrative arrangement shown, the common-mode level of the differential signal 1305 generated by the single-ended to differential signal conversion function 1303 is not set to any fixed level, but is allowed to vary within an acceptable range as a result of the DC component variation of the current in the photodiode 310 due to different light signal intensities. This differential signal 1305 may have a significant DC offset before being passed to comparator 1301 via coupling capacitor 1306, such that comparator input 1307 is effectively a symmetrical differential version of the data signal 303 at the output of TIA 300. The purpose of comparator 1301 is to generate a sliced ​​square waveform 1302 representing the intersection of the two complementary portions of the AC-coupled differential signal 1307, which is equivalent to the average level of the data signal waveform.

[0081] To avoid misjudgments in comparator 1301 due to noise at low signal levels, a certain degree of hysteresis is preferably added to the comparator response. This naturally means a small delay in the output waveform used to drive the switched capacitor sampling clock generation system 804. However, as long as the decision level and associated hysteresis level of comparator 1301 are symmetrical about the levels when the two inputs of the comparator are at the same potential, the sampling timing will operate correctly to ensure symmetrical sampling of the TIA output signal 303.

[0082] Figure 14 The desired behavior of the fast differential comparator 1301 used to create sampling clocks 802, 803 is illustrated. With an ideal ramp signal 1401 applied to one input and a fixed reference level 1402 set to the other input, for example at the common-mode level of the ramp input, the two complementary outputs 1403, 1404 will have symmetrically occurring transitions at the points where the positive and negative ramp signals 1401 cross the reference level 1402. Through this behavior, the signal 1302 used to drive the sampling clock circuit 804 provides symmetrical transitions around the crossover points of the differential input signals.

[0083] To ensure that the fast differential comparator 1301 provides the required precision symmetry reflected in its complementary output signal 1302 between its decisions made for both positive and negative inputs, it is prudent to provide mechanisms to adjust or fine-tune the comparator's behavior to accommodate performance variations caused by manufacturing defects or environmental influences. In providing suitable adjustment or fine-tuning capabilities, it is important to note that when processing slowly changing inputs, the comparator's performance in terms of its decision level and any hysteresis in its response may differ compared to processing signals with very high frequency components (potentially in the gigahertz range). This difference can be caused by many factors such as variations in transistor threshold voltage, resistance, transistor gain factor, parasitic capacitance, etc. Therefore, to account for these diverse factors, it is preferable to arrange the system to allow for adjustment or fine-tuning operations to optimize performance for both slowly and rapidly changing input signals.

[0084] Figure 15 This illustrates an arrangement according to one aspect of the invention, wherein means are provided for adjusting and fine-tuning the behavior of the sampling clock generation comparator 1301 under both low-frequency (i.e., quasi-static) and high-frequency (i.e., dynamic) conditions.

[0085] The adjustment or fine-tuning of the fast differential comparator 1301 used to generate the sampling clock can be conveniently started from low-frequency or quasi-static performance. When there is no optical input signal present in the TIA path and therefore at the TIA output 303, a slowly varying precision calibration signal 1501 can be applied to one or both of the comparator input terminals. Such as Figure 14 As illustrated, the calibration signal can conveniently be in the form of a ramp signal 1401. The common-mode level 1502 of the comparator input can be conveniently set to the normal operating level. Since the calibration signal is inherently slowly changing, its source can be constructed with the same high precision. At the outputs (1403, 1404) of comparator 1301, the conversion is detected and transmitted to the calibration and offset correction controller 1504.

[0086] The calibration controller 1504 can then adjust known circuit parameters 1505 within the comparator 1301 that affect low-frequency behavior, for example, by adjusting the transistor threshold via the body bias level, by digitally selecting the fine-tuning resistor value, or by other methods known to those skilled in the art. Calibration of the low-frequency behavior is considered complete when the transitions at the comparator outputs 1403, 1404 are found to be symmetrical about the crossover point of the comparator input levels, and any hysteresis level corresponding to the desired value is observed.

[0087] The fine-tuning input 1505 required to achieve the desired low-frequency behavior is then stored in the calibration controller 1504, and the TIA system is reconfigured to perform the second part of the calibration to obtain the desired performance under rapidly changing inputs. For these operations, two simple passive low-pass filter circuits 1506, 1507 are connected to the complementary outputs 1403, 1404 of the comparator 1301. Because they are inherently passive, these low-pass filters themselves do not introduce any DC offset to any measurement. The outputs of the two filter circuits 1506, 1507 can be combined in a subtraction arrangement 1510, which can be a discrete subtractor, or connected as a differential input to an analog-to-digital converter (ADC), or connected to other configurations capable of detecting differences between low-frequency levels present at the outputs of the filters. The result of the subtraction operation is communicated to the calibration controller 1504. The subtraction function (or ADC, etc.) 1501 only needs to operate at low frequencies, and therefore can be easily constructed to have fairly high accuracy.

[0088] A high-frequency calibration source 1511 is also provided, which can be connected to the input of the TIA 300. This can be connected via a suitable resistor 1512 to replicate the input current signal level expected from the photodiode 310. The calibration signal source 1511 is configured to operate at frequencies substantially within the same frequency range expected in the preamble mode 204 during normal operation. The calibration signal source 1511 is also configured to provide a basic square wave waveform with a precise 1:1 mark-to-space ratio. This can be conveniently achieved, for example, by a suitable phase-locked loop with a digital divider at its output to ensure a waveform that is symmetrical in the time domain.

[0089] The signal at the TIA input is amplified and passed through a single-ended to differential converter 1303, via an AC coupling network 1306, to comparator 1301 to remove any DC offset between the two input signal branches. Ideally, the outputs 1403, 1404 of comparator 1301 should then have complementary square wave signals, each with a 1:1 mark-to-space ratio. Therefore, the DC levels at the outputs of the two passive low-pass filters should be identical. Any difference between the DC levels 1508, 1509 at the outputs of the two passive low-pass filters 1506, 1507 obtained through a suitable subtraction function 1510 can be detected in calibration controller 1504. Calibration controller 1504 can then adjust circuit parameters 1513 within the comparator that affect dynamic performance, such as fine-tuning the bias current, the parasitic capacitance value which can be fine-tuned via digital selection, or other methods well known to those skilled in the art.

[0090] The calibration of the comparator's high-frequency performance is considered complete when the DC levels 1508 and 1509 at the outputs of the two passive low-pass filters 1506 and 1507 are sufficiently close to be consistent so that the calibration process cannot improve them further. The fine-tuning input 1513, determined during the calibration and fine-tuning operations required to achieve the desired high-frequency behavior, is then stored in the calibration controller 1504, and the system returns to its normal operating configuration.

[0091] Figure 16 A flowchart illustrating an exemplary method of the calibration and fine-tuning process described above according to one aspect of the present invention is provided. It should be understood that many modifications of this method and other different methods are possible in order to achieve the objectives of the present invention.

[0092] Therefore, there exists a first operation 1601 that disables the data correlation signals through the TIA and the single-ended to differential conversion circuit.

[0093] Then, in operation 1602, the common-mode level at the input of the differential comparator is fixed at the normal operating level.

[0094] Then, in operation 1603, a varying input ramp can be applied, or alternatively, the comparator's DC offset parameter can be changed.

[0095] Then, in operation 1604, the DC offset of the comparator is adjusted by fine-tuning parameters such as threshold voltage and resistance value.

[0096] Then, in operation 1605, if hysteresis is used in the comparator design, the DC offset is adjusted to achieve a symmetrical threshold.

[0097] Then, in operation 1606, the static DC offset fine-tuning value is stored.

[0098] Then, in operation 1607, a high-frequency test signal is connected to the input of the TIA, and the size of the test source is set to be on the same order of magnitude as the normal signal from the photodiode, which is sufficient to overcome any hysteresis in the comparator 1301.

[0099] Then, in operation 1608, the test signal is configured with symmetrical rise and fall times with a precise mark-to-space ratio of 1:1.

[0100] Then, in operation 1609, the dynamic offset behavior of the comparator is adjusted by fine-tuning the capacitor, transconductance, etc.

[0101] Then, in operation 1610, the dynamic offset of the comparator is adjusted until the output levels of the low-pass filters coupled to the output of the comparator are substantially equal.

[0102] Then, in operation 1611, the static DC and high-frequency dynamic trimming values ​​are stored, and the circuit is reconfigured for normal operation.

[0103] Figure 17 Another arrangement of the TIA system according to one aspect of the invention is provided, wherein means are provided to allow for a large discrete variation of the settling time of the AGC system. In this arrangement, when a fast settling time constant is desired, for example during the preamble period 204 of a data burst, the output 303 of the TIA 300 is connected via a first resistor 1701 to an integrator 601 that controls the AGC function. When a change from a fast AGC settling time constant to a slow AGC settling time constant is desired, the input path from the TIA output 303 to the AGC integrator 601 becomes a connection via a larger value resistor 1702. Those skilled in the art will appreciate that the effective resistance variation between the integrator's input and the TIA's output can also be achieved through many other possible switching arrangements, including series connections, parallel connections, or combinations thereof.

[0104] The change from the fast AGC settling time constant to the slow AGC settling time constant can be initiated by a detection function 1703, which determines that the preamble 204 is about to end and the reception of the data payload 206 is about to begin. The detection function 1703 receives a sliced ​​version 1705 of the signal 303 present at the output of the TIA 300, the sliced ​​signal 1705 being provided by a limiting amplifier or a self-reference comparator 1704 or other comparable device.

[0105] Figure 18 This section presents another arrangement of a TIA system according to one aspect of the invention, wherein alternative means are provided to allow for larger discrete variations in the settling time of the AGC system. In this arrangement, the AGC integrator 601 is connected to the output 303 of the TIA 300 via a single resistor 1801, but in this arrangement, the AGC integrator 601 includes two feedback capacitors 1802, 1803. In cases where a fast AGC settling time is desired, for example during the preamble period 204 of a data burst, only the first capacitor of the capacitors 1802 is connected from the input to the output of the integrator 601 to accumulate the charge supplied by the AGC integrator amplifier.

[0106] When AGC needs to transition to a slow settling time, for example, at the end of the preamble and the start of the data payload 206, then the second capacitor 1803 can be connected between the input and output of the AGC integrator 601. Figure 18As shown, a convenient method for this switching process is to fix one terminal of the second capacitor 1803 to the output terminal 603 of the AGC integrator 601, switch the other terminal of the second capacitor 1803 from the reference potential 1804 used to set the virtual ground level of the AGC integrator, and then connect that terminal of the second capacitor 1803 to the input terminal of the AGC integrator 601. In this way, the second capacitor 1803 always has the correct stored charge value regardless of whether it is connected to the input terminal of the AGC integrator 601, thereby avoiding transients in the control loop when the AGC settling time changes.

[0107] The change from the fast AGC settling time constant to the slow AGC settling time constant can be initiated by the detection function 1703 as previously described, for example, the detection function 1703 determines that the preamble 204 is about to end and the reception of the data payload 206 is about to begin.

[0108] As per reference Figure 17 and Figure 18 In the case of a facility that is desired to change the AGC settling time constant at the end of the data burst preamble 204, in order to be able to send a suitable timing signal to make such a change, by selecting different feedback capacitors 1802, 1803 or different input resistors 1701, 1702 in the arrangement of integrator 601, or by some other means, it is obvious that it is necessary to be able to determine when the preamble ends and when the reception of the data payload begins.

[0109] A possible method for detecting the end of a preamble is to detect when a repeating “1010” pattern of input data, starting from a burst, stops, and when a more random data pattern begins, which contains multiple consecutive occurrences of the same data symbol.

[0110] Figure 19 This describes the arrangement of a portion of a TIA system for burst mode reception, in which means are provided to detect the end of a preamble sequence by detecting, for example, two or more data sequences with the same symbols. A problem to be solved in such a detection system is defining the accuracy of the required timing function while taking into account factors such as manufacturing tolerances, power supply, and environmental influences.

[0111] The arrangement uses a simple ramp integrator, wherein, for example, a programmable or adjustable current source 1901 charges a capacitor 1902, and wherein a switch 1903 is provided to allow the integration process to be reset. The charging process is initiated, for example, on the falling edge of the output 1910 of a comparator or limiting amplifier that detects the value of a data symbol (corresponding to the start of a "0" data symbol), and is reset on the rising edge of the output 1910 of the comparator (corresponding to the start of a "1" data symbol).

[0112] The ramp voltage 1904 generated by the integrator is compared with the reference voltage 1905 in comparator 1906, and an output signal 1907 is generated to indicate whether the reference level has been crossed. If the data symbols in the preamble are a repeating "1010" pattern, the ramp voltage 1904 may not reach the reference level 1905 before it is reset by switch 1903, and therefore no comparison output signal corresponding to such a crossing event is generated. If the data stream contains a sequence of multiple identical symbols, the integrator ramp 1904 will not be reset after one symbol cycle, and the ramp voltage will rise to a higher level before being reset by switch 1903, creating the possibility that the ramp voltage 1904 will cross the reference level 1905, thus causing the output 1907 of the detection comparator 1906 to signal a crossing event.

[0113] It is explicitly required to be able to set circuit parameters such that the ramp voltage 1904 does not exceed the reference level 1905 within one symbol period, while ensuring that the ramp voltage will exceed the reference level if a larger defined number of identical symbols exist in the data sequence. These requirements can be met by adjusting the reference level. Alternatively, the rise rate of ramp 1904 can be set such that it does not exceed the reference level 1905 within one symbol period, while ensuring that the ramp voltage will exceed the reference level if a larger defined number of identical symbols exist in the data sequence.

[0114] To meet the above requirements, Figure 19 The arrangement is configured to perform a calibration process at the start of each burst 204, and the illustrative waveform indicating the internal signal level is intended to represent the calibration process. Assuming the burst has an appropriate minimum number of symbols in a preamble sequence containing, for example, a "1010" pattern, calibration can be performed before the end of the preamble and is ready to detect the start of the data payload 206.

[0115] exist Figure 19In this configuration, the reference level 1905 connected to the negative input of the comparator 1906 is set to a convenient value consistent with the correct operation of the comparator, and a sufficient range, for example, 70% of the power supply range, is allowed for the integrator ramp output 1904. At the start of a data burst, the current source 1901 is configured to deliver a suitable low initial current value, and the integrator is reset via switch 1903. During the time when the data symbol value is "0", the ramp voltage 1904 rises linearly. If the ramp voltage does not reach a level exceeding the reference level 1905 before the end of the symbol period and the integrator is reset via switch 1903, the comparator output 1907 will indicate that the reference level has not been crossed, and the current value supplied by the current source 1901 will increase under the control of the calibration system 1908. This process is repeated in subsequent data symbol periods until the integrator ramp output 1904 rises fast enough to exceed the reference level 1905 for the duration of a single symbol period.

[0116] The calibration system 1908 thus determines the necessary settings for the current source 1901 so that the detection comparator 1906 signals that the rising ramp signal 1904 has crossed the reference level 1905 within the duration of one data symbol period.

[0117] Before the start of the next integration cycle, the output of current source 1901 is reduced to a certain proportion of the current required to cause integrator ramp 1904 to cross reference level 1905 within one data symbol cycle. For example, it may be advantageous to set current source 1901 to 70% of the previous value set when detection occurs. Note that if it is desired to be able to detect when at least two consecutive identical symbols exist, the new current value should preferably be no less than 50% of the previous value.

[0118] Figure 20 The diagram illustrates the operation of the detection system after the calibration process is completed and during the remaining period of the data burst preamble 204. The output of the detection comparator 1906 is combined in logic function 2001 with status information from the calibration system 1908, indicating that the calibration process has ended and the system is actively monitoring signal conditions indicating the start of the data payload 206. The output of logic function 2001 is signal 2002 indicating whether the preamble 204 has ended.

[0119] The integrator ramp 1904 is activated after each "1" to "0" transition of the input slice signal 1910 and is reset by switch 1903 during the next "0" to "1" transition. In this state, it can now be determined that the integrator ramp output 1904 cannot rise to a value greater than the reference level 1905 within a single symbol period. During the remainder of the preamble 204, the dominant "1010" mode ensures that the integrator ramp 1904 is reset by switch 1903 after a single symbol period, and the detection comparator 1906 does not generate the preamble end detection signal 1907, and therefore it is not generated by the logic function 2001 that determines that the preamble has ended and the data payload has begun.

[0120] Figure 21 This illustrates the operation of the detection system when preamble 204 ends and data payload 206 begins. Integrator ramp 1904 still starts after each "1" to "0" transition of the input slice signal 1910 and is reset by switch 1903 on the next "0" to "1" transition. Now, it is likely that two or more consecutive sequences of the same symbols will appear in the data stream. In this case, integrator ramp 1904 has a longer rise time before being reset by switch 1903. For example, if two or more consecutive "0" symbols exist in the data stream, the setting of current source 1901, determined by calibration function 1908, provides sufficient current for integrator ramp 1904 to exceed reference level 1905 for the duration of two or more data symbol cycles. The output 1907 of detection comparator 1906 is then acquired and combined in logic function 2001, whose output 2002 then indicates that preamble 204 has ended and data payload 206 is being received. The end of the preamble signal 2002 can then be communicated to the AGC system to trigger any desired change in the AGC settling time constant, for example, from a fast value to a significantly slower value.

[0121] Note that the values ​​of each increment of the current from the current source 1901 used during the calibration process should be selected such that there is sufficient distinction between the levels at which the detection condition occurs or does not occur, and that the calibration function can reliably set an appropriate reduction current for the preamble end detection. However, the current increments should not be too small, otherwise the calibration process may not be able to be reliably completed within a number of symbol periods significantly less than the total number of symbol periods allocated for the entire preamble.

[0122] for Figure 19 , Figure 20 and Figure 21The actual implementation of the arrangement shown may have advantageous modifications and alternative arrangements. At particularly high data rates, in order to provide a sufficiently large ramp 1904 that can be reliably detected by a suitable detection comparator, the associated extremely short symbol period may require excessive current and insufficient capacitance in the integrator.

[0123] Assuming careful selection of the programmable current source 1901 increments and a sufficiently long preamble used in the system under discussion, it may be advantageous to employ a digital frequency divider 1911, such that... Figure 19 As shown, reducing the switching frequency of the slice signal input 1910 used for resetting the integrator 1903 extends the integration period before each reset. A simple division by 2 at the input of the integrator reset switch 1903 results in a minimum integration period of 2 symbol periods. Since any consecutive identical symbol sequence will extend the integration period by the same duration, the use of... Figure 19 , Figure 20 and Figure 21 The arrangement described in the text still allows for preamble end detection.

[0124] In the preceding section Figure 19 , Figure 20 and Figure 21 In this description, it should be understood that the preamble 204 pattern is assumed to be a balanced data symbol sequence of the form "1010", and the detection of the end of the preamble is indicated by a change to a longer sequence of the same symbols. The description of the calibration and detection process assumes that the reference timing is determined relative to a single data symbol period, and the detection of the start of the data payload can be considered as the detection of two or more identical data symbols. It will be apparent to those skilled in the art that the arrangement proposed and described with reference to the detection of the end of the preamble can be readily configured to identify other data patterns in the preamble 204 and payload 206 without departing from the scope of the invention.

[0125] In addition, refer to Figure 19 , Figure 20 and Figure 21 The described arrangement is configured to initiate a ramp charging process 1904 in response to a "1" to "0" transition in the input slice signal 1910, and to stop and reset the ramp charging process in response to a "0" to "1" transition. Those skilled in the art will recognize that this simple strategy limits the detection of identical data symbol sequences to a pattern of "0" data symbols. This limitation can be easily overcome by employing a second end of a preamble detection system, where the initiation and termination of the ramp are controlled by data value transitions of opposite meanings, and where signals from both detection systems are combined to indicate a continuous sequence of "1" or "0" data symbols.

[0126] exist Figure 22 An alternative arrangement for detecting the end of a preamble is presented. In this arrangement, the simple ideal asynchronous detection comparator 1906 is replaced by a clock-controlled regenerative comparator 2201. Designing an asynchronous comparator capable of making accurate decisions at GHz rates is a challenging task, typically requiring significant power consumption to ensure fast operation. In contrast, clock-controlled comparators with positive feedback generally require much less operating current to achieve very high-speed operation; however, this introduces limitations such as the circuit needing to be periodically reset and making a decision only when the clock or enable signal initiates the decision process. This clock-controlled regenerative comparator can be readily integrated into arrangements designed to detect the end of a preamble in a data burst, simplifying the design and reducing power consumption.

[0127] exist Figure 22 In this circuit, a delay element 2202 is incorporated into the clock input 2203 of the integrator reset switch 1903. This delay element 2202 is designed to produce a delay significantly shorter than a single symbol period, and its purpose is to ensure that the clock-controlled regenerative comparator 2201 is activated shortly before the integrator is reset by switch 1903. The output 2204 of the comparator 2201 is combined in logic function 2001 with status information from calibration function 1908, which indicates that the calibration process has ended and the system is actively monitoring the start of the data payload 206. The output of logic function 2001 is a signal 2002 indicating whether the preamble has ended.

[0128] Figure 23 yes Figure 22 A schematic diagram of the timing waveforms within the arrangement shown.

[0129] Input clock 1910 is received from a slice comparator or limiting amplifier that detects the "1" and "0" states in the received data stream. The falling edge of this signal 1910 initiates the integration process by turning on reset switch 1903, and the integrator output 1904 will rise with a linear ramp. If the system has passed the previous reference... Figure 19 , Figure 20 and Figure 21 The calibration process described is similar to the calibration process described above, and with the integrating current source 1901 set, if the preamble 204 is present, then before the end of the symbol period, when the regenerative clock control detection comparator 2201 is activated, the integrator ramp 1904 will not cross the reference level 1905, and the detection comparator will not generate an output signal 2204 indicating that a crossing event has occurred. Immediately after the regenerative clock control detection comparator 2201 makes its decision, the integrator is reset by switch 1903.

[0130] If there is a sequence of more than one consecutive identical symbols after the start of the integration period, and assuming the integrating current source 1901 has been properly configured, the integrator output ramp 1904 will cross the reference level 1905 at some point during the integration process. Since the regenerative clock control detection comparator 2201 only needs to determine whether a crossing of the reference level 1905 has occurred, and the exact timing of any crossing is not important, it is not important whether the integrator ramp 1904 saturates at its maximum level. The detection comparator output 2204 is combined in logic function 2001 with a signal from calibration function 1908 indicating that the calibration process is complete, thereby generating a signal 2002 indicating that the preamble 204 has ended and the data payload 206 is being received. This signal 2002 indicating the end of the preamble can then be conveyed to the AGC system to allow any desired variation in the settling time.

[0131] Note that in the preceding description, the accompanying drawings suggest that a signal indicating the end of the preamble condition is emitted after the detection of a defined sequence (e.g., more than two consecutive "0" symbols). It will be clear to those skilled in the art that in... Figure 19 , Figure 20 , Figure 21 and Figure 22 The proposed arrangement can be easily adjusted to detect sequences of consecutive "1" symbols to indicate the end of the preamble and that the data payload is being received. For more accurate detection, reference... Figures 19-22 The described arrangement of the sequence for detecting "0" symbols can be combined with a similar arrangement for detecting "1" symbols. However, given the DC balancing requirements within the data stream, in practice only one or the other of the proposed arrangements may be needed.

[0132] Although the invention has been described with reference to specific examples and possible embodiments thereof, these descriptions should not be construed as limiting the scope of the invention in any way. It should be understood that many other possible embodiments, modifications, and improvements may be incorporated into or combined with the invention without departing from the scope and spirit of the invention as set forth in the claims.

Claims

1. An assembly for receiving data using an electronic component via optical fiber, wherein the data is received in burst form, and wherein said assembly comprises: Photodiode; A transimpedance amplifier coupled to the photodiode, wherein the gain of the transimpedance amplifier is adjusted based on the level of a gain control signal; A receiving input signal sensor configured to sense the level of a received input signal and provide a gain control signal that varies according to the level of the received input signal; Furthermore, the received input signal level is sensed via a sampling circuit arrangement, wherein the sampling circuit arrangement samples depending on the time at which the data symbol conversion occurs; Furthermore, the response speed of the received input signal sensor to changes in the level of the received input signal is configured to depend on the frequency of symbol level transitions in the received signal; Furthermore, the timing of the sampling is defined as being symmetrical in time with respect to both positive and negative data symbol level transitions; A comparator configured to detect data symbol level shifts in the received input signal, wherein the output of the comparator is configured to control the sampling timing of the sampling circuit arrangement; as well as A regulator for adjusting the low-frequency and high-frequency behavior of the comparator such that the detection of both positive and negative data symbol level transitions in the received signal behaves identically within acceptable engineering tolerances, and wherein the regulator further comprises: Low-frequency calibration setup; High-frequency calibration setup; A calibration controller configured to control the comparator's configuration to different desired modes, said modes including: Normal operating mode for signal reception; Low-frequency calibration mode, wherein the comparator's deficiencies in response to rapidly changing inputs are analyzed and corrected by the calibration controller; In a high-frequency calibration mode, the comparator's response to slowly changing inputs is imperfect and is analyzed and corrected by the calibration controller.

2. The assembly of the electronic components for receiving data using optical fiber according to claim 1, wherein the comparator has differential inputs, and wherein the comparator has complementary logic outputs, wherein the logic high values ​​of each of the complementary outputs are the same within acceptance engineering limits, and wherein the logic low values ​​of each of the complementary outputs are the same within acceptance engineering limits.

3. The assembly of electronic components for receiving data using optical fiber according to claim 1, wherein at least one input of the comparator is connected to the received signal via at least one capacitor.

4. The assembly of electronic components for receiving data using optical fiber according to claim 1, wherein at least one input of the comparator is configured to be disconnected from the received signal and configured to receive a low-frequency ramp calibration input having a defined level.

5. The assembly of electronic components for receiving data using optical fiber according to claim 1, wherein the low-frequency calibration arrangement is configured to analyze a decision generated by the comparator in response to the low-frequency ramp calibration input.

6. The assembly of electronic components for receiving data using optical fiber according to claim 5, wherein the low-frequency calibration arrangement is configured to, under the control of the calibration controller, reduce any loss of symmetry between the positive and negative decision levels of the comparator to a negligible level through adjustment by the regulator.

7. The assembly of the electronic components for receiving data using optical fiber according to claim 2, wherein the high-frequency calibration arrangement further comprises a passive low-pass filter connected to each of the complementary outputs of the comparators, and wherein, when the assembly of the electronic components is configured to receive the signal, the cutoff frequency of the passive low-pass filter is significantly lower than the lowest frequency component expected in the received signal.

8. The assembly of the electronic components for receiving data using optical fiber according to claim 2, wherein the input from the photodiode is disconnected and a high-frequency test signal is applied to the input of the transimpedance amplifier.

9. The assembly of claim 8 for receiving data using an electronic component via an optical fiber, wherein the high-frequency calibration arrangement further comprises a high-frequency signal source, and wherein the high-frequency signal source provides the high-frequency test signal having a frequency equivalent to the frequency of the preamble pattern appearing in the data burst, and wherein the high-frequency test signal has a magnitude equivalent to the magnitude of the signal received from the photodiode, and wherein the high-frequency test signal has a basic square wave waveform having a mark-space ratio equal within acceptance engineering tolerances.

10. The assembly of claim 7 for receiving data using an electronic component via optical fiber, wherein the outputs of the passive low-pass filters are compared and the difference between the DC levels present at the outputs of each passive low-pass filter is transmitted to the calibration controller, the high-frequency calibration arrangement being configured to reduce the difference between the DC levels of the outputs of the low-pass filters to a negligible small value under the control of the calibration controller and by adjustment of the regulator.

11. A method for receiving data using optical fiber, wherein the data is received in burst form, and wherein the method comprises: An electronic component for receiving data using optical fiber, wherein the data is received in burst form, and wherein said component includes: Set up a photodiode; A transimpedance amplifier coupled to the photodiode is provided, wherein the gain of the transimpedance amplifier is adjusted based on the level of a gain control signal; A receiving input signal sensor is configured to sense the level of a received input signal and provide a gain control signal, the gain control signal varying according to the level of the received input signal. Furthermore, the received input signal level is sensed via a sampling circuit arrangement, wherein the sampling circuit arrangement samples depending on the time at which the data symbol conversion occurs; Furthermore, the response speed of the sensor to changes in the level of the received input signal therefore depends on the frequency of symbol level transitions in the received signal; Furthermore, the timing of the sampling is configured such that the sampling is defined as being symmetrical in time with respect to both positive data symbol level transitions and negative data symbol level transitions; A comparator is configured to detect data symbol level transitions in the received input signal, and the output of the comparator is configured to control the sampling timing of the sampling circuit arrangement; and A regulator is configured to adjust the low-frequency and high-frequency behavior of the comparator such that the detection of positive and negative data symbol level transitions in the received signal exhibits identical behavior within acceptable engineering tolerances, and wherein the regulator further comprises: Low-frequency calibration setup; High-frequency calibration setup; A calibration controller configured to control the comparator's configuration to different desired modes, said modes including: Normal operating mode for signal reception; Low-frequency calibration mode, wherein the comparator's deficiencies in response to rapidly changing inputs are analyzed and corrected by the calibration controller; In a high-frequency calibration mode, the comparator's response to slowly changing inputs is imperfect and is analyzed and corrected by the calibration controller.

12. The method of claim 11, wherein the comparator has differential inputs, and wherein the comparator has complementary logic outputs, wherein the logic high values ​​of each of the complementary outputs are the same within an acceptance engineering limit, and wherein the logic low values ​​of each of the complementary outputs are the same within an acceptance engineering limit.

13. The method of claim 11, wherein at least one input of the comparator is connected to the received signal via at least one capacitor.

14. The method of claim 11, wherein at least one input of the comparator is configured to be disconnected from the received signal and configured to receive a low-frequency ramp calibration input having a defined level.

15. The method of claim 14, wherein the low-frequency calibration arrangement is configured to analyze the decision generated by the comparator in response to the low-frequency ramp calibration input.

16. The method of claim 15, wherein the low-frequency calibration arrangement is further configured to, under the control of the calibration controller, reduce any loss of symmetry between the positive and negative decision levels of the comparator to a negligible level through adjustment of the regulator.

17. The method of claim 12, wherein the high-frequency calibration arrangement includes a passive low-pass filter connected to each of the complementary outputs of the comparators, and wherein, when the components of the electronic component are configured to receive the signal, the cutoff frequency of the passive low-pass filter is significantly lower than the lowest frequency component expected in the received signal.

18. The method of claim 17, wherein the input from the photodiode is disconnected, and a high-frequency test signal is applied to the input of the transimpedance amplifier.

19. The method of claim 18, wherein the high-frequency calibration arrangement further comprises a high-frequency signal source, wherein the high-frequency signal source provides the high-frequency test signal having a frequency equivalent to the frequency of the preamble pattern appearing in the data burst, and wherein the high-frequency test signal has a magnitude equivalent to the magnitude of the signal received from the photodiode, and wherein the high-frequency test signal has a basic square wave waveform having a mark-space ratio equal within acceptable engineering tolerances.

20. The method of claim 18, wherein the outputs of the passive low-pass filters are compared, and the difference between the DC levels present at the outputs of each passive low-pass filter is transmitted to the calibration controller, the high-frequency calibration arrangement being further configured to reduce the difference between the DC levels of the outputs of the low-pass filters to a negligible small value by means of adjustment of the regulator under the control of the calibration controller.

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