A calibration method with hardware assistance

Abstract

The application provides a hardware-assisted calibration method, and belongs to the technical field of wireless communication.The application integrates a hardware adjustable structure in a chip, including a voltage-controlled current source circuit and a voltage adjustment module, so that in the mass production test stage, the key parameters can be dynamically adjusted by the hardware mode, the chips originally at the performance edge are compensated in real time, and thus the chips can reach the established function and performance requirements.The application can effectively improve the consistency and overall yield of the chip, and avoid the resource waste caused by the limitations of software calibration.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and specifically relates to a calibration method combined with hardware assistance. Background Technology

[0002] In wireless communication systems, radio frequency transceiver chips typically employ a "zero intermediate frequency" (Zero-IF) scheme. This is a direct conversion architecture that directly down-converts the radio frequency signal to baseband, meaning the center frequency is zero. Due to the unique nature of this architecture, it often faces IQ imbalance issues, including amplitude mismatch and phase mismatch, leading to image interference.

[0003] There are two main approaches to solving IQ mismatch: one is to optimize the internal analog circuit design of the chip, and the other is to process IQ mismatch through the baseband DSP algorithm.

[0004] In the mass production of RFIC (Radio Frequency Integrated Circuit) chips, the physical differences introduced by this manufacturing process are typically modeled as different process corners, such as SS, TT, and FF. These process corner variations directly affect the image rejection of the RFIC chip. In actual products, to ensure stability under various worst-case scenarios, the chip usually needs to implement a software-level self-calibration mechanism during the mass production testing phase to dynamically adapt to the actual manufacturing results. However, traditional software calibration (such as...) Figure 1 As shown, when faced with deep hardware deviations caused by differences in process physics, the adjustment range and accuracy are limited, making it difficult to effectively compensate for all mismatch paths. Especially in the boundary performance region, it often leads to chips that could have been used being misclassified as defective or downgraded products, thereby affecting the overall yield and cost-effectiveness.

[0005] Therefore, there is an urgent need for an improved solution that can finely adjust chip characteristics directly at the hardware level to compensate for performance losses caused by process angles and manufacturing deviations, thereby achieving more robust classification and higher shipment rates. Summary of the Invention

[0006] To address the problems existing in the prior art, this invention discloses a hardware-assisted calibration method, which can effectively improve chip consistency and overall yield, and avoid resource waste caused by the limitations of software calibration.

[0007] To achieve the above objectives, the technical solution of the present invention is as follows:

[0008] This invention provides a hardware-assisted calibration method based on an integrated hardware adjustable structure within a chip. The hardware adjustable structure includes a voltage-controlled current source circuit and a voltage regulation module. The voltage-controlled current source circuit is connected to a mixer; the voltage regulation module is connected to an IQ generator. The method includes the following steps:

[0009] Step 1: Determine if the mixer operating current is within the reference current range. If not, proceed to Step 2; otherwise, end the process.

[0010] Step 2: Simultaneously scan the static bias current and common-mode resistor value of the voltage-controlled current source circuit, then proceed to Step 3; the scan refers to simultaneously adjusting two sets of control word parameters, namely the static bias current and the common-mode resistor value. Each set of control word parameters has 3 bits, resulting in a total of 64 adjustment combinations.

[0011] Step 3: Read the mirror suppression value (IRR).

[0012] Step 4: Determine if the mirror rejection ratio (IRR) meets the requirements. If not, proceed to Step 5; otherwise, end the process.

[0013] Step 5: Determine whether the mirror suppression value IRR has reached the adjustment limit. If not, proceed to step 2; otherwise, proceed to step 6.

[0014] Step 6: Increase the IQ generator voltage through the voltage regulation module and read the image rejection value IRR; determine whether the image rejection value IRR meets the requirements. If not, proceed to step 7; otherwise, end.

[0015] Step 7: Determine whether the mirror suppression value IRR has reached the adjustment limit. If not, proceed to step 6; otherwise, end the process.

[0016] Furthermore, in step 2, during the scan, the combination of static bias current and common-mode resistor values ​​that have already been taken will not be taken again.

[0017] The present invention also provides a hardware-assisted calibration method, comprising the following steps:

[0018] Step 1: Initialize parameters;

[0019] Step two: Perform IQ calibration using software;

[0020] Step 3: If the software IQ calibration effect does not meet the requirements, use the above-mentioned calibration method combined with hardware assistance to perform calibration, and then jump to step 2; if the software IQ calibration effect meets the requirements, the process ends.

[0021] The beneficial effects of this invention are as follows:

[0022] This invention integrates adjustable hardware structures within the chip, such as voltage-controlled current source circuits and IQ generator voltage regulation modules. This allows for dynamic adjustment of key parameters via hardware during mass production testing, enabling real-time compensation for chips that are initially at the performance edge, thereby bringing them up to the intended functional and performance requirements. Applying this invention can effectively improve chip consistency and overall yield, avoiding resource waste caused by limitations in software calibration. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the process of a pure software calibration method in the prior art.

[0024] Figure 2 A schematic diagram of the process after incorporating the hardware calibration method provided by this invention.

[0025] Figure 3 This is a schematic diagram of the hardware calibration method for the radio frequency chip provided by the present invention.

[0026] Figure 4 A schematic diagram of the internal hardware connections of the chip used to increase the voltage-controlled current source circuit of the mixer.

[0027] Figure 5 To change the value of BIAS<2:0> and the corresponding output port's spectrum.

[0028] Figure 6 To change the value of DGEN<2:0> and the corresponding output port's spectrum.

[0029] Figure 7 The spectrum of the output signal IRR obtained by changing the AVDD_TXFE voltage.

[0030] Figure 8 A schematic diagram showing the distribution of the number of chips produced in each process corner. Detailed Implementation

[0031] The technical solutions provided by the present invention will be described in detail below with reference to specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention.

[0032] This invention integrates an adjustable hardware structure within the chip, namely a mixer voltage-controlled current source circuit (TX_GM) and a voltage regulation module (AVDD_TXFE). The voltage-controlled current source circuit is connected to the mixer, and the voltage regulation module is connected to the IQ generator. This allows for dynamic adjustment of key parameters via hardware during mass production testing, enabling real-time compensation for chips that are initially at the performance edge, thereby achieving the intended functional and performance requirements. A schematic diagram of the internal hardware connections of the chip with the added mixer voltage-controlled current source circuit is shown below. Figure 4 As shown, the voltage-controlled current source circuit is used to control the current using a voltage signal. It converts the voltage signal of TXBB into a current signal for processing by the mixer and PA circuits. The voltage regulation module adjusts the IQ generator voltage by detecting the current magnitude of the mixer.

[0033] Through experiments, we found significant differences in image rejection caused by process corners SS and FF. Among numerous hardware parameters, we discovered that the mixer's static bias and the module's common-mode resistance have a significant impact on IQ image rejection; the voltage of the IQ generator also greatly affects the phase and amplitude of IQ. Therefore, we propose a hardware-assisted calibration method to address these issues. The specific calibration procedure is as follows: Figure 3 As shown, it includes the following steps:

[0034] Step 1: Determine if the mixer's operating current is within the reference current range. If not, proceed to Step 2; otherwise, end the process. The reference current value is preset.

[0035] Step 2: Simultaneously scan the static bias current of the voltage-controlled current source circuit and the common-mode resistor value, then proceed to Step 3. Scanning refers to simultaneously adjusting two sets of control word parameters: the static bias current and the common-mode resistor value. Each set of control parameters has a corresponding adjustable value or adjustable range. Combinations of static bias current and common-mode resistor values ​​that have already been selected will not be repeated.

[0036] Step 3: Read the mirror suppression value (IRR).

[0037] Step 4: Determine whether the image suppression value IRR meets the requirements (the required value should be preset). If not, proceed to step 5; otherwise, end the process.

[0038] Step 5: Determine whether the image rejection value IRR has reached the adjustment limit. If not, proceed to step 2; otherwise, proceed to step 6. The adjustment limit value of IRR is the limit value obtained by trying various combinations of control words for different static bias current values ​​and common mode resistance values ​​in advance, based on the hardware environment for implementing this method.

[0039] Step 6: Increase the IQ generator voltage through the voltage regulation module and read the image rejection value IRR; determine whether the image rejection value IRR meets the requirements. If not, proceed to step 7; otherwise, end.

[0040] Step 7: Determine whether the mirror suppression value IRR has reached the adjustment limit. If not, proceed to step 6; otherwise, end the process.

[0041] Simulation experiments were conducted on the circuit without using the above calibration method, and the simulation results are shown in Table 1 below:

[0042] Table 1

[0043]

[0044] As can be seen from the simulation results summarized in Table 1 above, at the same temperature, the image suppression energy of the SS process angle and FF process angle differs from that of the TT process angle by about 7 dB.

[0045] Since the mixer voltage-controlled current source circuit (TX_GM) and voltage regulation module (AVDD_TXFE) are two relatively independent circuits, adjusting AVDD_TXFE alone will not interfere with the control effect of the two sets of control words BIAS / DGEN<2:0> of the voltage-controlled current source circuit. Therefore, the three sets of control words are divided into two groups: BIAS / DGEN<2:0> and AVDD_TXFE.

[0046] To compensate for the IRR loss caused by changes in the process corner, SS27 was selected as the target process corner. A hardware-assisted calibration mechanism was used to adjust the two sets of control words, BIAS / DGEN<2:0>, of the mixer voltage-controlled current source circuit (TX_GM), i.e., the bias current / common-mode resistance value, to improve its IRR. The corresponding IRR values ​​are shown in Tables 2 and 3 below.

[0047] Table 2

[0048]

[0049] Table 3

[0050]

[0051] The simulation conditions are as follows: input signal frequency fif = 10 MHz, input signal power pif = -50 dBm; local oscillator signal frequency frf = 780 MHz, local oscillator signal power pref = 10 dBm.

[0052] Figure 5 To keep DGEN<2:0> constant, change the value of BIAS<2:0> and the corresponding output port's spectrum. Figure 5 It can be seen that BIAS<2:0> decreases from the default value of 111 (maximum value) to 001 (minimum value). The difference between the minimum and maximum IRR values ​​of the bias current is 10.29dB. That is, as the bias current decreases, the IRR value of the output port increases. This indicates that at the process corner SS27, a larger current bias will cause the transistor in TX_GM to enter the linear region, resulting in a decrease in gain, a decrease in bandwidth, and an increase in noise.

[0053] Figure 6 This involves changing only the value of DGEN<2:0> and the corresponding output port's spectrum. Figure 6 It can be seen that the IRR value corresponding to the minimum value of DGEN<2:0> (38.73dB) and the IRR value corresponding to the maximum value (36.21dB) differ by 2.52dB. This means that as the value of DGEN<2:0> decreases, the IRR value of the output port decreases (corresponding to an increase in the common-mode resistance). This indicates that at the SS27 process corner, the IRR value can be optimized by increasing the value of DGEN<2:0>.

[0054] The two sets of control words BIAS / DGEN<2:0> belong to the mixer voltage-controlled current source circuit (TX_GM). They are not independent of each other. When calibrating IRR, the two sets of control words can be adjusted simultaneously. Each set of control words has 3 bits, with a total of 64 combinations. The best value that can be achieved by combining the two is taken as the limit value of adjustment, and then the next calibration is performed based on this.

[0055] Additionally, at SS27 process angle, maintaining BIAS<2:0>=111 and DGEN<2:0>=110, adjusting AVDD_TXFE separately yields IRR data as follows: Figure 7 And as shown in Table 4 below:

[0056] Table 4

[0057]

[0058] Adjusting the voltage AVDD_TXFE of IQ_GENERATOR reveals an IRR of 35.66dB under normal power supply conditions (AVDD_TXFE = 1.2V). By increasing AVDD_TXFE through the voltage regulation module, the IRR reaches 37.78dB at AVDD_TXFE = 1.44V. This demonstrates that during chip manufacturing, chips that fall into edge process corners can have their IRR recovered by increasing AVDD_TXFE.

[0059] In chip manufacturing, the vast majority of chips are manufactured in the "TT process corner," while SS and FF are minority cases. Their distribution depends on the manufacturing process and is usually similar to a Gaussian distribution, such as... Figure 8 As shown. According to statistics, the yield of the chip is improved by approximately 1.5% after calibration using the method of this invention.

[0060] It should be noted that the above content merely illustrates the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. For those skilled in the art, various improvements and modifications can be made without departing from the principle of the present invention, and all such improvements and modifications fall within the scope of protection of the claims of the present invention.

Claims

1. A method of combining hardware-assisted calibration, characterized by, Based on the realization of the hardware adjustable structure integrated inside the chip, the hardware adjustable structure includes: a voltage-controlled current source circuit and a voltage adjustment module, the voltage-controlled current source circuit is connected with a mixer; the voltage adjustment module is connected with an IQ generator; including the following steps: Step 1, judge whether the mixer working current is in the reference current range, if not, go to step 2, if yes, end; Step 2, scan the static bias current of the voltage-controlled current source circuit and the common-mode resistance value at the same time, go to step 3; the scanning means adjusting the static bias current and the common-mode resistance value two groups of control word parameters at the same time, each group of control word parameters has 3 bits, and there are 64 kinds of adjustment combinations; Step 3, read the image rejection value IRR size; Step 4, judge whether the image rejection value IRR meets the requirements, if not, go to step 5, if yes, end; Step 5, judge whether the image rejection value IRR has reached the adjustment limit, if not, go to step 2, if yes, go to step 6; Step 6, increase the IQ generator voltage through the voltage adjustment module, read the image rejection value IRR size; judge whether the image rejection value IRR meets the requirements, if not, go to step 7, if yes, end; Step 7, judge whether the image rejection value IRR has reached the adjustment limit, if not, go to step 6, if yes, end.

2. The method of claim 1, wherein, In the step 2, when scanning, the static bias current and the common-mode resistance value combination that has been taken will not be repeated.

3. A method of combining hardware-assisted calibration, the method comprising: Including the following steps: Step one, initialize parameters; Step two, calibrate IQ through software; Step three, when the software IQ calibration effect does not meet the demand, calibrate by the calibration method combined with hardware assistance in any one of claims 1-2, and jump to step two; if the software IQ calibration effect meets the demand, end.

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