Semiconductor structure and preparation method thereof, storage system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of how to improve the production yield of the semiconductor structure. The semiconductor structure includes a plurality of conductive pillars, a first insulating layer, and a first conductive layer. The plurality of conductive columns are arranged in multiple rows and multiple columns. The first insulating layer is arranged at one end of the extension direction of the plurality of conductive columns and is connected with the plurality of conductive columns. The first conductive layer surrounds the periphery of the conductive column. The first conductive layer penetrates through the first insulating layer between any two adjacent rows and two columns of conductive columns and extends to the side, away from the conductive columns, of the first insulating layer. The semiconductor structure is used for realizing data reading and writing operations.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and its fabrication method, a storage system, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) consists of multiple memory cells, each typically consisting of a capacitor controlled by a first transistor; that is, DRAM is a memory cell with one first transistor and one capacitor (1T1C). Improving the production yield of DRAM is a problem that needs to be solved. Summary of the Invention

[0003] On one hand, a semiconductor structure is provided. The semiconductor structure includes a plurality of conductive pillars, a first insulating layer, a third insulating layer, and a first conductive layer. The plurality of conductive pillars are arranged in multiple rows and columns. The first insulating layer is disposed at one end of the plurality of conductive pillars in their extending direction and is connected to the plurality of conductive pillars. The first conductive layer surrounds the periphery of the conductive pillars. The first conductive layer penetrates the first insulating layer between any two adjacent rows and two columns of four conductive pillars, and extends to the side of the first insulating layer away from the plurality of conductive pillars.

[0004] In some embodiments, the semiconductor structure further includes a second insulating layer disposed between and connected to the plurality of conductive pillars. Between any two adjacent conductive pillars in the row and / or column directions of the plurality of conductive pillars, the first conductive layer is located on opposite sides of the second insulating layer. Furthermore, between any two adjacent rows and two columns of four conductive pillars, the first conductive layer penetrates the second insulating layer.

[0005] In some embodiments, the conductive post includes a first sub-post and a second conductive layer. The first sub-post includes opposing first and second end faces. The first insulating layer contacts the first end face. The second conductive layer covers the periphery of the first sub-post and the second end face. Furthermore, along the extending direction of the conductive post, the second conductive layer extends to the side of the first end face away from the second end face.

[0006] In some embodiments, the first insulating layer includes a first sublayer and a plurality of first protrusions. The first sublayer covers one end of the second conductive layer. The plurality of first protrusions are located between the second conductive layers and are in contact with the first end face.

[0007] In some embodiments, the semiconductor structure further includes a third insulating layer surrounding the periphery of the conductive pillars and located between the conductive pillars and the first conductive layer. The third insulating layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars and extends to the side of the first insulating layer away from the plurality of conductive pillars.

[0008] In some embodiments, between two adjacent conductive pillars, the third insulating layer further covers the surface of the first insulating layer near the plurality of conductive pillars, and the first conductive layer further covers the surface of the third insulating layer away from the first insulating layer.

[0009] In some embodiments, the semiconductor structure further includes a first filling layer disposed on the side of the first conductive layer away from the third insulating layer. The first filling layer is located between the plurality of conductive pillars and penetrates the first insulating layer between any two adjacent rows and two columns of four conductive pillars, extending to the side of the first insulating layer away from the plurality of conductive pillars.

[0010] In some embodiments, the semiconductor structure further includes a plurality of first transistors disposed on the side of the plurality of conductive pillars away from the first insulating layer. Each first transistor includes a first electrode, a second electrode, and a gate, with the second electrode of one first transistor connected to one of the conductive pillars.

[0011] In some embodiments, the semiconductor structure further includes a first interlayer insulating layer and a first connection pad. The first interlayer insulating layer is disposed on the side of the plurality of first transistors adjacent to the plurality of conductive pillars; between two adjacent conductive pillars, a third insulating layer further covers the surface of the first interlayer insulating layer adjacent to the first insulating layer, and the first conductive layer further covers the surface of the third insulating layer away from the first interlayer insulating layer. The first connection pad is disposed between the plurality of first transistors and the plurality of conductive pillars. The conductive pillars penetrate at least a portion of the first interlayer insulating layer and connect to the first connection pad, and the first connection pad is connected to a second electrode of the first transistor.

[0012] On the other hand, a storage system is provided. The storage system includes a controller and a memory, the memory comprising a semiconductor structure as described in some of the embodiments above, and the controller is coupled to the memory to control the memory to store data.

[0013] In another aspect, an electronic device is provided. The electronic device includes a storage system and a processor as described in the above embodiments, the storage system and the processor being connected.

[0014] In another aspect, a method for fabricating a semiconductor structure is provided. The method for fabricating the semiconductor structure includes:

[0015] A first intermediate semiconductor structure is formed. The first intermediate semiconductor structure includes a plurality of conductive pillars and a first insulating layer. The plurality of conductive pillars are arranged in multiple rows and columns. The first insulating layer is disposed at one end of the plurality of conductive pillars in the extending direction and is connected to the plurality of conductive pillars.

[0016] A first conductive layer is formed. The first conductive layer surrounds the periphery of the conductive pillars. The first conductive layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars, and extends to the side of the first insulating layer away from the plurality of conductive pillars.

[0017] In some embodiments, forming the first intermediate semiconductor structure includes: forming a stacked structure. The stacked structure includes a first sacrificial layer and a second sacrificial layer stacked sequentially. A first via is formed through the stacked structure. A conductive pillar is formed within the first via. The conductive pillar includes a first sub-pillar and a second conductive layer. The first sub-pillar includes opposing first and second end faces, with the first end face close to the second sacrificial layer. The second conductive layer covers the periphery of the first sub-pillar and the second end face. Along the extension direction of the conductive pillar, the second conductive layer extends to the side of the first end face away from the second end face.

[0018] In some embodiments, forming the first intermediate semiconductor structure further includes forming a first insulating layer. The first insulating layer includes a first sublayer and a plurality of first protrusions, the first sublayer covering one end of the second conductive layer. The first protrusions are located between the second conductive layers and contact the first end face. The first insulating layer has a plurality of second vias, with one second via disposed between any two adjacent rows and two columns of four conductive pillars. The second sacrificial layer and the first sacrificial layer are sequentially removed via the second vias.

[0019] In some embodiments, during the formation of the stacked structure, a second insulating layer and a third sacrificial layer are also formed. The second insulating layer is disposed between the third sacrificial layer and the first sacrificial layer. After the second sacrificial layer and the first sacrificial layer are sequentially removed via the second via, the formation of the first intermediate semiconductor structure further includes:

[0020] A third via is formed on the second insulating layer. One of the third vias is provided between any two adjacent rows and two columns of the four conductive pillars. The third sacrificial layer is removed through the third via.

[0021] In some embodiments, forming a conductive post within the first via includes:

[0022] A second conductive film is formed. The second conductive film covers the bottom and sidewalls of the first via and the upper surface of the second sacrificial layer. A second fill layer is formed. The second fill layer fills the first via and covers the upper surface of the second conductive film.

[0023] The second filler layer and the second conductive film are etched such that portions of the second filler layer and the second conductive film located above the second sacrificial layer are removed, and the upper surfaces of the second filler layer and the second conductive film are located between the upper surfaces of the first sacrificial layer and the second sacrificial layer. The second filler layer is etched such that the upper surface of the second filler layer is lower than the upper surface of the second conductive film.

[0024] In some embodiments, during the etching of the second filler layer, the second sacrificial layer is also etched. The second sacrificial layer includes a second sublayer and a plurality of second protrusions, the upper surface of the second sublayer being flush with the upper surface of the second conductive film. The second protrusions are disposed on the side of the second sublayer away from the first sacrificial layer and are located between the four conductive pillars arranged in two adjacent rows and two columns.

[0025] In some embodiments, forming the first insulating layer includes: forming a first insulating film. The first insulating film fills the first via and covers the upper surface of the second sacrificial layer. A portion of the first insulating film located on the side of the second protrusion away from the first sacrificial layer is removed.

[0026] In some embodiments, prior to forming the stacked structure, forming the first intermediate semiconductor structure further includes forming a first connection pad and a first interlayer insulating layer. The first interlayer insulating layer is disposed on the side of the first sacrificial layer away from the second sacrificial layer and covers the first connection pad. During the formation of the first via through the stacked structure, the first via also penetrates at least a portion of the first interlayer insulating layer, thereby exposing the first connection pad.

[0027] In some embodiments, prior to forming the first conductive layer, the fabrication method further includes forming a third insulating layer. The third insulating layer surrounds the periphery of the conductive pillars and is located between the conductive pillars and the first conductive layer. The third insulating layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars and extends to the side of the first insulating layer away from the plurality of conductive pillars.

[0028] In some embodiments, after forming the first conductive layer, the fabrication method further includes forming a first filling layer. The first filling layer is disposed on the side of the first conductive layer away from the third insulating layer. The first filling layer is located between the plurality of conductive pillars and penetrates the first insulating layer between any two adjacent rows and two columns of four conductive pillars, extending to the side of the first insulating layer away from the plurality of conductive pillars.

[0029] In some embodiments, prior to forming the first intermediate semiconductor structure, the fabrication method further includes forming a second intermediate semiconductor structure. The first intermediate semiconductor structure is located on one side of the second intermediate semiconductor structure along the extending direction of the conductive post. Furthermore, the second intermediate semiconductor structure includes a plurality of first transistors, each first transistor including a first electrode, a second electrode, and a gate, with the second electrode of one first transistor connected to one of the conductive posts. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0031] Figure 1 A three-dimensional structural diagram of a memory according to some embodiments;

[0032] Figure 2 A cross-sectional view of a memory according to some embodiments;

[0033] Figure 3 for Figure 1 A structural diagram of a storage unit in China;

[0034] Figure 4 for Figure 3 The equivalent circuit diagram of the storage cell shown;

[0035] Figure 5 This is a top view of a semiconductor structure according to some embodiments;

[0036] Figure 6 This is a top view of another semiconductor structure according to some embodiments;

[0037] Figure 7 for Figure 6 A sectional view along section line AA;

[0038] Figure 8 for Figure 6 Another sectional view along section line AA;

[0039] Figures 9-14 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0040] Figures 15-47 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0041] Figure 48 This is a block diagram of a storage system according to some embodiments;

[0042] Figure 49 A block diagram of a storage system according to some other embodiments;

[0043] Figure 50 This is a block diagram of an electronic device according to some embodiments. Detailed Implementation

[0044] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0045] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0047] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0048] In describing some embodiments, the terms "connection" and "coupling," and their derivative expressions, may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The term "coupling" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0049] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0050] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0051] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0052] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0053] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0054] The term “overlapping” or “overlapping” means that the first object may be above or below the second object or to the side of the second object, and vice versa. Additionally, the term “overlapping” may include layering, stacking, facing or oriented, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0055] The term "relative" means that the first element can be directly or indirectly relative to the second element. In the case where the third element is between the first and second elements, although they are still relative to each other, the first and second elements can be understood as being indirectly relative to each other.

[0056] In this disclosure, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be structurally symmetrical, they can be structurally indistinguishable. That is to say, the first electrode and the second electrode of the transistor in this disclosure can be structurally indistinguishable.

[0057] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0058] Figure 1 This is a three-dimensional structural diagram of a memory according to some embodiments. Figure 2 This is a cross-sectional view of a memory according to some embodiments. Figure 3 for Figure 1 A structural diagram of a storage cell. Figure 4 for Figure 3 The equivalent circuit diagram of the storage cell is shown.

[0059] See Figure 1 and Figure 2 Some embodiments of this disclosure provide a memory 10, including a semiconductor device 100 and peripheral devices 200. The peripheral devices 200 may be disposed on one side of the semiconductor device 100.

[0060] like Figure 2 As shown, the semiconductor device 100 may include a memory cell array 110 and a common layer GD. Peripheral devices 200 may, for example, be disposed on the side of the memory cell array 110 away from the common layer GD.

[0061] See Figure 2 and Figure 3The common layer GD can be connected to a first reference voltage, which can be ground voltage or other voltages. The material of the common layer GD can be a conductive material, such as at least one selected from tungsten, cobalt, copper, aluminum, and metal silicides. Of course, other suitable materials can also be used, and this disclosure does not specifically limit the choice of materials.

[0062] See Figure 1 and Figure 2 The storage cell array 110 includes multiple storage cells 111 arranged in an array. Among them, combined with... Figure 3 and Figure 4 The memory cell 111 includes a first transistor T1 and a capacitor C. The first electrode of the first transistor T1 can be connected to a bit line BL, for example, and the second electrode of the first transistor T1 can be connected to one plate of the capacitor C, for example, and the other plate of the capacitor C can be connected to a common layer GD, for example. The gate of the first transistor T1 can be, for example, part of a gate layer 20. In this way, a voltage can be applied to the gate layer 20 to control the first transistor T1 to be turned on or off, and when the first transistor T1 is turned on, the bit line BL performs read or write operations on the first transistor T1.

[0063] A first interlayer insulating layer 112 and a first connecting pad 113 may be provided between the first transistor T1 and the capacitor C. The first interlayer insulating layer 112 can serve as an insulating protection layer, and the first connecting pad 113 is connected to the second electrode of the first transistor T1 and one plate of the capacitor C to reduce contact resistance.

[0064] The material of the first interlayer insulation layer 112 can be an insulating material, such as at least one of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0065] The material of the first connecting pad 113 can be a conductive material, such as at least one of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0066] In some embodiments, as Figure 2 As shown, the semiconductor device 100 may further include a shielding layer 30, which is disposed between two adjacent first transistors T1 to reduce electromagnetic interference generated between adjacent first transistors T1.

[0067] See Figure 2The shielding layer 30 can be connected to a second reference voltage, which can be, for example, ground voltage, a negative voltage, or other voltages. The material of the shielding layer 30 includes a conductive material, which can include, for example, titanium nitride, but can also be other suitable materials; this disclosure does not specifically limit the specific materials used.

[0068] In some embodiments, see Figure 2 The semiconductor device 100 may also include an array interconnect layer 120, which can be connected to the memory cell 111 to enable the transmission of electrical signals between the memory cell 111 and external circuits (such as the peripheral circuits mentioned below).

[0069] For example, such as Figure 2 As shown, the array interconnect layer 120 may include an array interconnect conductor layer 121, a second interlayer insulating layer 122, and a plurality of array connection posts 123. The array interconnect conductor layer 121 may be configured to have interconnect traces on the same layer. The gate layer 20, the shielding layer 30, and the bit line BL may be led out of the array interconnect conductor layer 121 through the array connection posts 123, and different array interconnect conductor layers 121 may be connected to each other through the array connection posts 123.

[0070] The array interconnect conductor layer 121 and the array connection post 123 can be made of conductive materials, such as at least one of tungsten, cobalt, copper, aluminum, and metal silicides, or other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0071] The material of the second interlayer insulation layer 122 can be an insulating material, such as at least one of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0072] like Figure 2As shown, peripheral device 200 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., first transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0073] In some embodiments, as Figure 2 As shown, the peripheral device 200 may include a substrate 210, a second transistor T2 disposed on the substrate 210, and a peripheral interconnect layer 220 disposed on the substrate 210. The aforementioned peripheral circuit may include the second transistor T2.

[0074] The substrate 210 can be made of monocrystalline silicon or other suitable materials, such as silicon-germanium, germanium, or silicon-on-insulator thin film. The peripheral interconnect layer 220 is connected to the second transistor T2 to enable the transmission of electrical signals between the second transistor T2 and the peripheral interconnect layer 220.

[0075] For example, such as Figure 2 As shown, the peripheral interconnect layer 220 may include a peripheral interconnect conductor layer 221, a third interlayer insulation layer 222, and a plurality of peripheral connection posts 223. The peripheral interconnect conductor layer 221 may be configured to have interconnect traces on the same layer, and different peripheral interconnect conductor layers 221 may be connected to each other via the peripheral connection posts 223.

[0076] The materials of the peripheral interconnect conductor layer 221 and the peripheral connecting post 223 can be conductive materials, such as at least one of tungsten, cobalt, copper, aluminum, and metal silicides, and may also include other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0077] The material of the third interlayer insulation layer 222 is an insulating material, which may include at least one of silicon oxide, silicon nitride, and high dielectric constant insulating materials, and may also include other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0078] In some embodiments, as Figure 2As shown, the peripheral interconnect layer 220 can be connected to the array interconnect layer 120, thereby connecting the semiconductor device 100 and the peripheral device 200. Since the peripheral interconnect layer 220 is connected to the array interconnect layer 120, the peripheral circuits in the peripheral device 200 can be connected to the memory cells 111 in the semiconductor device 100 to realize the transmission of electrical signals between the peripheral circuits and the memory cells 111.

[0079] In some possible implementations, such as Figure 2 As shown, the peripheral interconnect layer 220 and the array interconnect layer 120 are bonded together, so that the peripheral interconnect conductor layer 221 in the peripheral interconnect layer 220 and the corresponding array interconnect conductor layer 121 in the array interconnect layer 120 are in contact, thereby enabling the peripheral circuit in the peripheral device 200 to be connected to the memory cell 111 in the semiconductor device 100.

[0080] In related technologies, multiple capacitors are divided into multiple capacitor groups. A capacitor group includes four adjacent capacitors and a support structure. The four capacitors are arranged in two rows and two columns, and the support structure is located between the four capacitors in the two rows and two columns to improve structural stability.

[0081] However, since there is no supporting structure between four adjacent capacitors belonging to different capacitor banks, the forces on the capacitors near and away from the supporting structure are uneven during the fabrication process. Within the same capacitor bank, adjacent capacitors are at higher risk of bending and deforming towards each other. Furthermore, fabricating the supporting structure requires the introduction of a new mask, which is costly to manufacture, resulting in higher overall process costs.

[0082] Based on this, see Figure 2 Some embodiments of this disclosure provide a semiconductor structure 300, which may include a semiconductor device 100 and peripheral devices 200. The semiconductor structure 300 may also be part of a memory 10, for example, the semiconductor structure 300 may be the semiconductor device 100 in the memory 10; or, for another example, the semiconductor structure 300 may be a plurality of capacitors C arranged in an array in the memory 10. The embodiments of this disclosure do not specifically limit this.

[0083] Figure 6 It can be understood as Figure 7 or Figure 8 The plane containing the top end of the conductive post 40 along the middle ( Figure 7 and Figure 8 A cross-sectional view of the plane at point A'-A'. For example, as shown... Figure 5 and Figure 6 The semiconductor structure 300 includes a plurality of conductive pillars 40, a first insulating layer 50, a third insulating layer 60, and a first conductive layer 70.

[0084] like Figure 5 and Figure 6 As shown, multiple conductive posts 40 are arranged in multiple rows and columns. Each row may include at least two conductive posts 40 arranged along a first direction X, and each column may include at least two conductive posts 40 arranged along a second direction Y.

[0085] Wherein, the first direction X is the row direction in which the plurality of conductive posts 40 are arranged, and the second direction Y is the column direction in which the plurality of conductive posts 40 are arranged. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular. In addition, the conductive posts 40 may extend along a third direction Z, for example, and both the first direction X and the second direction Y are perpendicular to the third direction Z.

[0086] It should be noted that the orthographic projection of the conductive post 40 onto the first insulating layer 50 can be any of the following shapes: circle, ellipse, polygon, or other irregular shapes. For example, Figure 5 and Figure 6 As shown, the orthographic projection of the conductive post 40 onto the first insulating layer 50 is a circle.

[0087] like Figure 7 and Figure 8 As shown, a first insulating layer 50 is disposed at one end of the extension direction of the plurality of conductive posts 40 and is connected to the plurality of conductive posts 40. The first insulating layer 50 connects all the conductive posts 40, providing support and fixation, thereby reducing the risk of the conductive posts 40 tipping over and improving structural stability.

[0088] The material of the first insulating layer 50 can be, for example, an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon carbon nitride, and high dielectric constant insulating materials, and may also include other suitable materials. This disclosure does not specifically limit the materials used in this embodiment.

[0089] like Figure 7 and Figure 8 As shown, the third insulating layer 60 surrounds the periphery of the conductive pillar 40 and is located between the conductive pillar 40 and the first conductive layer 70. The third insulating layer 60 penetrates the first insulating layer 50 between any two adjacent rows and columns of four conductive pillars 40, and extends to the side of the first insulating layer 50 away from the conductive pillars 40. For example, the third insulating layer 60 extends to the side of the first insulating layer 50 away from the conductive pillars 40 and covers the first insulating layer 50.

[0090] The material of the third insulating layer 60 can be, for example, an insulating material, which may include at least one of silicon oxide, silicon nitride, silicon carbon nitride, and high dielectric constant insulating materials, and may also include other suitable materials, which are not specifically limited in this embodiment.

[0091] like Figure 7 and Figure 8 As shown, the first conductive layer 70 surrounds the periphery of the conductive posts 40 and is disposed on the side of the third insulating layer 60 away from the surrounding conductive posts 40. The first conductive layer 70 penetrates the first insulating layer 50 between any two adjacent rows and two columns of four conductive posts 40 and extends to the side of the first insulating layer 50 away from the plurality of conductive posts 40. For example, the first conductive layer 70 extends to the side of the first insulating layer 50 away from the plurality of conductive posts 40 and covers the third insulating layer 60.

[0092] The material of the first conductive layer 70 can be a conductive material, which may include at least one of metal compounds such as tungsten, cobalt, copper, aluminum, and titanium nitride. Of course, it may also include other suitable materials, but this disclosure does not specifically limit the materials used.

[0093] At this time, the first conductive layer 70 and the surrounding conductive pillar 40 form a capacitor C. The first conductive layer 70 and the surrounding conductive pillar 40 are the two plates of the capacitor C, and the conductive pillar 40 can be connected to the second electrode of the first transistor T1, for example, and the first conductive layer 70 can be connected to the common layer GD, for example.

[0094] In this case, the semiconductor structure 300 can utilize the first insulating layer 50 to remove the sacrificial layer through a self-aligned process and form the third insulating layer 60 and the first conductive layer 70, avoiding the introduction of a new mask and reducing the fabrication cost.

[0095] Furthermore, since the third insulating layer 60 and the first conductive layer 70 penetrate the first insulating layer 50 between each pair of four conductive pillars 40 arranged in two rows and two columns, it can be seen that during the process of removing the sacrificial layer and forming the third insulating layer 60 and the first conductive layer 70, there are etching channels and deposition channels on the periphery of each conductive pillar 40. This can improve the uneven stress on the periphery of the conductive pillar 40, reduce the risk of bending deformation of the conductive pillar 40, and thus reduce the risk of bending deformation of the formed capacitor C.

[0096] It should be noted that the specific method for fabricating the semiconductor structure 300 can be found in the following text, and will not be repeated here in the embodiments disclosed herein.

[0097] In some embodiments, such as Figure 8 As shown, the semiconductor structure 300 also includes a second insulating layer 80, which is disposed between and connected to the plurality of conductive pillars 40.

[0098] In the row and / or column directions of the arrangement of multiple conductive posts 40, between any two adjacent conductive posts 40, the first conductive layer 70 and the third insulating layer 60 may, for example, be located on opposite sides of the second insulating layer 80, the third insulating layer 60 may cover the two opposite surfaces of the second insulating layer 80, and the first conductive layer 70 may be located on the side of the adjacent third insulating layer 60 away from the second insulating layer 80. Furthermore, between any two adjacent rows and two columns of four conductive posts 40, the first conductive layer 70 and the third insulating layer 60 may, for example, penetrate the second insulating layer 80.

[0099] At this time, the second insulating layer 80 can also connect all the conductive posts 40 to support and fix the conductive posts 40, thereby further reducing the risk of the conductive posts 40 tipping over and improving structural stability.

[0100] In some embodiments, as Figure 7 and Figure 8 As shown, the conductive pillar 40 includes a first sub-pillar 41 and a second conductive layer 42.

[0101] like Figure 7 and Figure 8 As shown, the first sub-pillar 41 includes a first end face 41A and a second end face 41B facing each other. The first insulating layer 50 is in contact with the first end face 41A. The first sub-pillar 41 provides mechanical support, reducing the risk of collapse of the semiconductor structure 300 and improving structural stability.

[0102] The material of the first sub-pillar 41 can be, for example, an insulating material. The insulating material may include at least one of silicon oxide, silicon nitride, polycrystalline silicon, silicon carbon nitride, and high dielectric constant insulating materials, and may also include other suitable materials, which are not specifically limited in this embodiment.

[0103] like Figure 7 and Figure 8 As shown, the second conductive layer 42 covers the periphery of the first sub-pillar 41 and the second end face 41B. Furthermore, along the third direction Z, the second conductive layer 42 extends to the side of the first end face 41A away from the second end face 41B. The second conductive layer 42 can be connected to the first transistor T1 (see...). Figure 2 The second pole connection.

[0104] The material of the second conductive layer 42 can be a conductive material, such as at least one of metal compounds such as tungsten, cobalt, copper, aluminum, and titanium nitride. Of course, it can also include other suitable materials, but this embodiment does not specifically limit it.

[0105] Based on this, such as Figure 7 and Figure 8As shown, the first insulating layer 50 includes a first sub-layer 51 and a plurality of first protrusions 52, the plurality of first protrusions 52 being disposed on the side of the first sub-layer 51 near the plurality of conductive pillars 40.

[0106] Along the third direction Z, the two opposing surfaces of the first sub-layer 51 are parallel to the reference plane, and the first sub-layer 51 covers one end of the second conductive layer 42. A first protrusion 52 is located between the portions of the second conductive layer 42 extending to the side of the first end face 41A away from the second end face 41B, and contacts the first end face 41A and the second conductive layer 42. The reference plane can be a plane defined by the first direction X and the second direction Y.

[0107] In this way, the contact area between the first insulating layer 50 and the conductive post 40 is large, which can improve the connection effect between the first insulating layer 50 and the conductive post 40; and, in the direction parallel to the reference plane, the first insulating layer 50 can play a better limiting role for the conductive post 40, which can provide better support and fixation for the conductive post 40, thereby further reducing the risk of the conductive post 40 tipping over and improving structural stability.

[0108] In some embodiments, as Figure 7 and Figure 8 As shown, between two adjacent conductive pillars 40, the third insulating layer 60 also covers the surface of the first insulating layer 50 near the plurality of conductive pillars 40, and the first conductive layer 70 also covers the surface of the third insulating layer 60 away from the first insulating layer 50.

[0109] In this configuration, the first conductive layer 70 and the third insulating layer 60 can be directly formed by a thin-film deposition process, which is simple and low-cost. It should be noted that the specific preparation methods for the first conductive layer 70 and the third insulating layer 60 are detailed below, and will not be repeated here in the embodiments disclosed herein.

[0110] In some embodiments, as Figure 7 and Figure 8 As shown, the semiconductor structure 300 also includes a first filling layer 90, which is disposed on the side of the first conductive layer away from the third insulating layer 60.

[0111] The first filling layer 90 is located between the plurality of conductive pillars 40, and penetrates the first insulating layer 50 between any two adjacent rows and two columns of four conductive pillars 40, extending to the side of the first insulating layer 50 away from the plurality of conductive pillars 40. The first filling layer 90 can provide mechanical support, reduce the risk of collapse of the semiconductor structure 300, and improve structural stability.

[0112] The material of the first filler layer 90 can be, for example, an insulating material. The insulating material may include at least one of silicon oxide, silicon nitride, polycrystalline silicon, silicon carbon nitride, and high dielectric constant insulating materials, and may also include other suitable materials, which are not specifically limited in this embodiment.

[0113] In some embodiments, as Figure 2 , Figure 5 and Figure 8 As shown, the semiconductor structure 300 also includes a plurality of first transistors T1, which are disposed on the side of the plurality of conductive pillars 40 away from the first insulating layer 50, and the second electrode of the first transistor T1 is connected to one of the conductive pillars 40.

[0114] In this embodiment, the gate of the first transistor T1 may surround the channel; the gate of the first transistor T1 may be located on three sides of the channel; the gate of the first transistor T1 may also be located on two opposite sides of the channel; the gate of the first transistor T1 may also be located on one side of the channel, and the gates of adjacent first transistors T1 are mirror-symmetrical. This embodiment does not specifically limit this. Figure 2 and Figure 5 The example shown is that the gate of the first transistor T1 is located on one side of the channel, and the gates of adjacent first transistors T1 are mirror-symmetrical.

[0115] Based on this, such as Figure 2 , Figure 7 and Figure 8 As shown, the semiconductor structure 300 also includes a first interlayer insulating layer 112 and a first connection pad 113. The first interlayer insulating layer 112 is disposed on the side of the plurality of first transistors T1 near the plurality of conductive pillars 40, and the first connection pad 113 is disposed between the plurality of first transistors T1 and the plurality of conductive pillars 40.

[0116] In this process, between two adjacent conductive pillars 40, the third insulating layer 60 also covers the surface of the first interlayer insulating layer 112 near the first insulating layer 50, and the first conductive layer 70 also covers the surface of the third insulating layer 60 away from the first interlayer insulating layer 112. In this way, the first conductive layer 70 and the third insulating layer 60 can be directly formed by thin film deposition process, which is simple and low cost.

[0117] In addition, such as Figure 7 and Figure 8 As shown, the conductive post 40 may penetrate at least part of the first interlayer insulating layer 112 and connect to the first connecting pad 113, and the first connecting pad 113 is connected to the second electrode of the first transistor T1 to reduce contact resistance and reduce power consumption.

[0118] Based on this, the area of ​​the first connecting pad 113 can be larger than the area of ​​the second electrode of the first transistor T1, so that the conductive post 40 can be aligned and connected with the first connecting pad 113, reducing the difficulty of the alignment process and improving the production yield.

[0119] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, and the aforementioned semiconductor structure 300 can be fabricated using this method, for example. Figure 9 As shown, the preparation method includes steps S100 to S200.

[0120] S100: See Figure 45 , Figure 46 and Figure 47 This forms the first intermediate semiconductor structure 310.

[0121] In the above steps, the first intermediate semiconductor structure 310 includes a plurality of conductive pillars 40 and a first insulating layer 50. The plurality of conductive pillars 40 are arranged in multiple rows and columns, with each row including at least two conductive pillars 40 arranged along a first direction X, and each column including at least two conductive pillars 40 arranged along a second direction Y. Along a third direction Z, the first insulating layer 50 is disposed at one end of the plurality of conductive pillars 40.

[0122] It should be noted that the first direction X, the second direction Y, and the third direction Z can be referred to above, and will not be repeated here.

[0123] In some embodiments, see Figure 10 S100 includes S110 to S130.

[0124] Figure 15 , Figure 16 and Figure 17 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 16 for Figure 15 A sectional view along section line BB. Figure 17 for Figure 15 A cross-sectional view along section line CC.

[0125] S110: See also Figure 15 , Figure 16 and Figure 17 This forms a stacked structure 320.

[0126] In the above steps, the stacked structure 320 includes a first sacrificial layer 321 and a second sacrificial layer 322 stacked sequentially. The first sacrificial layer 321 and the second sacrificial layer 322 are made of different materials. For example, the first sacrificial layer 321 is made of tetraethyl orthosilicate and / or borosilicate glass, and the second sacrificial layer 322 is made of silicon nitride and / or silicon oxide.

[0127] Furthermore, the first sacrificial layer 321 and the second sacrificial layer 322 can be formed sequentially using thin film deposition processes, for example. Thin film deposition processes include any one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0128] In some embodiments, as Figure 16 and Figure 17 As shown, during process S110, a second insulating layer 80 and a third sacrificial layer 323 are also formed. The second insulating layer 80 and the third sacrificial layer 323 can also be formed separately by thin film deposition process. That is, the stacked structure 320 also includes a second insulating layer 80 and a third sacrificial layer 323, with the second insulating layer 80 disposed between the third sacrificial layer 323 and the first sacrificial layer 321.

[0129] The second insulating layer 80 is made of a different material than the first sacrificial layer 321, and also differs from the material of the third sacrificial layer 323. For example, the first sacrificial layer 321 may be made of tetraethyl orthosilicate and / or borosilicate glass, the second insulating layer 80 may be made of silicon nitride and / or silicon oxide, and the third sacrificial layer 323 may be made of tetraethyl orthosilicate and / or borosilicate glass.

[0130] S120: See Figure 15 , Figure 16 and Figure 17 This forms the first through-hole 330 that penetrates the stacked structure 320.

[0131] In the above steps, the first via 330 extends from the upper side of the stacked structure 320, sequentially penetrating the first sacrificial layer 321 and the second sacrificial layer 322. The first via 330 can be formed using dry etching and / or wet etching processes. For example, a wet etching process can be used to form the first via 330 penetrating the stacked structure 320.

[0132] In addition, such as Figure 16 and Figure 17 As shown, when the stacked structure 320 also includes a second insulating layer 80 and a third sacrificial layer 323, during the process of S120, the first via 330 also penetrates the second insulating layer 80 and the third sacrificial layer 323.

[0133] S130: See also Figure 7 and Figure 9 Conductive pillar 40 is formed within the first via 330.

[0134] In the above steps, the conductive pillar 40 includes a first sub-pillar 41 and a second conductive layer 42. The first sub-pillar 41 includes a first end face 41A and a second end face 41B facing each other, with the first end face 41A close to the second sacrificial layer 322. The second conductive layer 42 covers the periphery of the first sub-pillar 41 and the second end face 41B. Furthermore, along the third direction Z, the second conductive layer 42 extends to the side of the first end face 41A away from the second end face 41B.

[0135] In some embodiments, see Figure 11 S130 includes S131 to S134.

[0136] Figure 18 , Figure 19 and Figure 20 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 19 for Figure 18 A cross-sectional view along section line DD. Figure 20 for Figure 18 A cross-sectional view along section line EE.

[0137] S131: See also Figure 18 , Figure 19 and Figure 20 A second conductive film 421 is formed.

[0138] In the above steps, the second conductive film 421 covers the bottom wall and sidewalls of the first via 330 and the upper surface of the second sacrificial layer 322, and the second conductive film 421 does not completely fill the first via 330, leaving gaps inside the first via 330. The second conductive film 421 can be formed using a thin-film deposition process.

[0139] Figure 21 , Figure 22 and Figure 23 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 21 It can be understood as Figure 22 or Figure 22 A cross-sectional view along the plane containing the second sacrificial layer 322. Figure 22 for Figure 21 A sectional view along section line FF. Figure 23 for Figure 21 A cross-sectional view along section line GG.

[0140] S132: See also Figure 21 , Figure 22 and Figure 23 This forms the second filling layer 411.

[0141] In the above steps, the second filling layer 411 fills the first via 330 and covers the upper surface of the second conductive film 421. The second filling layer 411 leaves gaps within the first via 330, and the second filling layer 411 can be formed using a thin-film deposition process.

[0142] Figure 24 , Figure 25 and Figure 26 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 24 It can be understood as Figure 25 or Figure 26 Top view, Figure 25 for Figure 24 A cross-sectional view along section line HH. Figure 26 for Figure 24 Sectional view along section line II.

[0143] S133: See also Figure 24 , Figure 25 and Figure 26 Etch the second filling layer 411 and the second conductive film 421.

[0144] In the above steps, the second filling layer 411 and the second conductive film 421 are etched, such that the portions of the second filling layer 411 and the second conductive film 421 located above the second sacrificial layer 322 are removed, and the upper surfaces of the second filling layer 411 and the second conductive film 421 are located between the upper surfaces of the first sacrificial layer 321 and the second sacrificial layer 322. At this time, the remaining portion of the second conductive film 421 forms the second conductive layer 42.

[0145] The second filling layer 411 and the second conductive film 421 can be formed by dry etching and / or wet etching processes. For example, a wet etching process can be used to simultaneously etch the second filling layer 411 and the second conductive film 421.

[0146] Figure 27 , Figure 28 and Figure 29 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 27 It can be understood as Figure 28 or Figure 29 Top view, Figure 28 for Figure 27 A sectional view along section line JJ. Figure 29 for Figure 27 A cross-sectional view along section line KK.

[0147] S134: See also Figure 27 , Figure 28 and Figure 29 , etch the second filling layer 411.

[0148] In the above steps, the second filling layer 411 is etched separately, so that the upper surface of the second filling layer 411 is lower than the upper surface of the second conductive film 421. At this time, the retained portion of the second filling layer 411 forms the first sub-pillar 41, and the first sub-pillar 41 and the second conductive layer 42 form the conductive pillar 40.

[0149] In addition, such as Figure 27 , Figure 28 and Figure 29 As shown, during process S134, the second sacrificial layer 322 is also etched. S134 can employ a wet etching process, where the second sacrificial layer 322, located above the second conductive layer 42, can be etched away along the first direction X and the second direction Y. Based on this, since the distance between the two diagonally opposite conductive pillars 40 in the four adjacent conductive pillars 40 is relatively large, and due to the isotropic nature of the etching, a portion of the second sacrificial layer 322 located above the second conductive layer 42 will be retained between the four adjacent conductive pillars 40.

[0150] In other words, the second sacrificial layer 322 includes a second sublayer 3221 and a plurality of second protrusions 3222. Along the third direction Z, the two opposing surfaces of the second sublayer 3221 are parallel to the reference plane, and the upper surface of the second sublayer 3221 is flush with the upper surface of the second conductive film 421. The second protrusions 3222 are disposed on the side of the second sublayer 3221 away from the first sacrificial layer 321, and are located between four conductive pillars 40 arranged in two adjacent rows and two columns to facilitate the subsequent formation of the first insulating layer 50.

[0151] In some embodiments, see Figure 10 S100 includes S140 to S150.

[0152] Figure 33 , Figure 34 and Figure 35 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 34 for Figure 33 A cross-sectional view along section line NN. Figure 35 for Figure 33 A sectional view along section line OO.

[0153] S140: See also Figure 33 , Figure 34 and Figure 35 , forming the first insulating layer 50.

[0154] In the above steps, the first insulating layer 50 includes a first sub-layer 51 and a plurality of first protrusions 52. Along the third direction Z, two opposing surfaces of the first sub-layer 51 are parallel to the reference plane, and the first sub-layer 51 covers one end of the second conductive layer 42. The plurality of first protrusions 52 are disposed on the side of the first sub-layer 51 near the plurality of conductive pillars 40. Furthermore, the first protrusions 52 are located between portions of the second conductive layer 42 extending to the side of the first end face 41A away from the second end face 41B, and are in contact with the first end face 41A and the second conductive layer 42.

[0155] In addition, the first insulating layer 50 is provided with a plurality of second vias 501, and a second via 501 is provided between any two adjacent rows and two columns of four conductive posts 40.

[0156] In the case where the second sacrificial layer 322 includes a second sublayer 3221 and a plurality of second protrusions 3222, see [reference]. Figure 12 S140 may include S141 to S142.

[0157] Figure 30 , Figure 31 and Figure 32 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 30 It can be understood as Figure 31 or Figure 32 The plane containing the top edge of the second conductive layer 42 ( Figure 31 and Figure 32 A sectional view of the plane at point B'-B'. Figure 31 for Figure 30 A sectional view along section line LL. Figure 32 for Figure 30 A cross-sectional view along section line MM.

[0158] S141: See also Figure 30 , Figure 31 and Figure 32 The first insulating film 510 is formed.

[0159] In the above steps, the first insulating film 510 fills the first via 330 and covers the upper surface of the second sacrificial layer 322. The first insulating film 510 can be formed using a thin film deposition process.

[0160] Figure 33 , Figure 34 and Figure 35 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 33 It can be understood as Figure 34 or Figure 35 Top view, Figure 34 for Figure 33 A cross-sectional view along section line NN. Figure 35 for Figure 33 A sectional view along section line OO.

[0161] S142: See also Figure 33 , Figure 34 and Figure 35 Remove the portion of the first insulating film 510 located on the side of the second protrusion 3222 away from the first sacrificial layer 321.

[0162] In the above steps, the portion of the first insulating film 510 located on the side of the second protrusion 3222 away from the first sacrificial layer 321 can be removed by any of the following processes: dry etching, wet etching, or planarization. For example, a chemical mechanical polishing process can be used to polish the surface of the first insulating film 510 away from the first sacrificial layer 321 until the second protrusion 3222 is exposed.

[0163] S150: Combined Figures 33-41 The second sacrificial layer 322 and the first sacrificial layer 321 are removed sequentially through the second via 501.

[0164] Figure 36 , Figure 37 and Figure 38 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 36 It can be understood as Figure 37 or Figure 38 Top view, Figure 37 for Figure 36 A cross-sectional view along section line PP. Figure 38 for Figure 37 A sectional view along section line QQ.

[0165] like Figure 36 , Figure 37 and Figure 38 As shown, the second sacrificial layer 322 is removed via the second via 501 (see...). Figure 34 and Figure 35 The second sacrificial layer 322 can be removed using dry etching and / or wet etching processes. For example, the second sacrificial layer 322 can be removed using a wet etching process.

[0166] Figure 39 , Figure 40 and Figure 41 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 39 It can be understood as Figure 40 or Figure 41 Top view, Figure 40 for Figure 39 A sectional view along section line RR. Figure 41 for Figure 39 A sectional view along section line SS.

[0167] like Figure 39 , Figure 40 and Figure 41 As shown, the first sacrificial layer 321 is removed via the second via 501 (see...). Figure 37 and Figure 38 The first sacrificial layer 321 can be removed using dry etching and / or wet etching processes. For example, the first sacrificial layer 321 can be removed using a wet etching process.

[0168] It should be noted that, Figures 33-41 The middle section uses a stacked structure of 320 (see...) Figure 16 The following is an illustration, including the second insulating layer 80 and the third sacrificial layer 323.

[0169] In the case where a second insulating layer 80 and a third sacrificial layer 323 are also formed during process S110, see [reference needed]. Figure 13 After S150, S100 also includes S160 to S170.

[0170] Figure 42 , Figure 43 and Figure 44 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 42 It can be understood as Figure 43 or Figure 44 Top view, Figure 43 for Figure 42 A cross-sectional view along section line TT. Figure 44 for Figure 42 A cross-sectional view along section line UU.

[0171] S160: See also Figure 42 , Figure 43 and Figure 44 A third via 801 is formed on the second insulating layer 80.

[0172] In the above steps, a third via 801 is provided between any two adjacent rows and two columns of four conductive pillars 40. The third via 801 can be removed using dry etching and / or wet etching processes. For example, the third via 801 is formed using a dry etching process.

[0173] Figure 45 , Figure 46 and Figure 47 This diagram illustrates the fabrication steps of a semiconductor structure fabrication method according to some embodiments. Wherein, Figure 45 It can be understood as Figure 46 or Figure 47 Top view, Figure 46 for Figure 45 A cross-sectional view along section line VV. Figure 47 for Figure 45 A sectional view along section line WW.

[0174] S170: See also Figure 45 , Figure 46 and Figure 47 The third sacrificial layer 323 is removed via the third via 801.

[0175] In the above steps, the third sacrificial layer 323 can be removed using dry etching and / or wet etching processes. For example, the third sacrificial layer 323 is formed using a wet etching process.

[0176] In some embodiments, as Figure 13 As shown, before S110, S100 also includes S180.

[0177] S180: See also Figure 15 , Figure 16 and Figure 17 This forms the first connecting pad 113 and the first interlayer insulating layer 112.

[0178] In the above steps, the first interlayer insulating layer 112 is disposed on the side of the first sacrificial layer 321 away from the second sacrificial layer 322, and covers the first connecting pad 113. When the stacked structure 320 includes a third sacrificial layer 323, the first interlayer insulating layer 112 is located on the side of the third sacrificial layer 323 away from the first sacrificial layer 321.

[0179] The first connecting pad 113 can be formed directly using a thin-film deposition process with a photomask, or it can be formed by first using a thin-film deposition process and then patterning it using an etching process. The first interlayer insulating layer 112 can be formed directly using a thin-film deposition process.

[0180] Furthermore, during process S120, the first via 330 also penetrates at least part of the first interlayer insulating layer 112, exposing the first connecting pad 113 so that the conductive post 40 formed in S130 can be connected to the first connecting pad 113.

[0181] S200: See also Figure 7 and Figure 8 The first conductive layer 70 is formed.

[0182] In the above steps, the first conductive layer 70 surrounds the periphery of the conductive pillar 40 and is disposed on the side of the third insulating layer 60 away from the surrounding conductive pillar 40. The first conductive layer 70 penetrates the first insulating layer 50 between any two adjacent rows and two columns of four conductive pillars 40 and extends to the side of the first insulating layer 50 away from the multiple conductive pillars 40.

[0183] The first conductive layer 70 can be formed by depositing conductive material between the plurality of conductive pillars 40 through a thin-film deposition process via a second via 501 on the first insulating layer 50. Furthermore, if the first intermediate semiconductor structure 310 also includes a second insulating layer 80, the first conductive layer 70 can be formed by depositing conductive material between the plurality of conductive pillars 40 through a thin-film deposition process via a second via 501 on the first insulating layer 50 and a third via 801 on the second insulating layer 80.

[0184] In some embodiments, see Figure 9 Before S200, the above preparation method also includes S300.

[0185] S300: See reference Figure 7 and Figure 8 , forming a third insulating layer 60.

[0186] In the above steps, the third insulating layer 60 surrounds the periphery of the conductive post 40 and is located between the conductive post 40 and the first conductive layer 70. The third insulating layer 60 penetrates the first insulating layer 50 between any two adjacent rows and two columns of four conductive posts 40 and extends to the side of the first insulating layer 50 away from the multiple conductive posts 40.

[0187] The third insulating layer 60 can be formed by depositing insulating material between the plurality of conductive pillars 40 through a thin-film deposition process via a second via 501 on the first insulating layer 50. Furthermore, if the first intermediate semiconductor structure 310 also includes a second insulating layer 80, the third insulating layer 60 can be formed by depositing insulating material between the plurality of conductive pillars 40 through a thin-film deposition process via a second via 501 on the first insulating layer 50 and a third via 801 on the second insulating layer 80.

[0188] In some embodiments, see Figure 5 Following S300, the above preparation method also includes S400.

[0189] S400; see also Figure 7 and Figure 8 This forms the first filling layer 90.

[0190] In the above steps, the first filling layer 90 is disposed on the side of the first conductive layer 70 away from the third insulating layer 60. The first filling layer 90 is located between the plurality of conductive pillars 40, and penetrates the first insulating layer 50 between any two adjacent rows and two columns of four conductive pillars 40, extending to the side of the first insulating layer 50 away from the plurality of conductive pillars 40, so as to provide mechanical support, reduce the risk of collapse of the semiconductor structure 300, and improve structural stability.

[0191] The first filling layer 90 can be formed by depositing insulating material between the plurality of conductive pillars 40 through a thin film deposition process via a second via 501 on the first insulating layer 50. Furthermore, if the first intermediate semiconductor structure 310 also includes a second insulating layer 80, the first filling layer 90 can be formed by depositing insulating material between the plurality of conductive pillars 40 through a thin film deposition process via a second via 501 on the first insulating layer 50 and a third via 801 on the second insulating layer 80.

[0192] In some embodiments, see Figure 14 Before S100, the above preparation method may also include S500.

[0193] S500: See Figure 2 This forms a second intermediate semiconductor structure 340.

[0194] In the above steps, combined Figure 2 , Figure 46 and Figure 47 Along the third direction Z, the first intermediate semiconductor structure 310 is located on one side of the second intermediate semiconductor structure 340. Furthermore, the second intermediate semiconductor structure 340 includes a plurality of first transistors T1, each first transistor T1 including a first electrode, a second electrode, and a gate. The second electrode of one first transistor T1 is connected to a conductive post 40. The second electrode of the first transistor T1 can be connected to the conductive post 40 via a first connecting pad 113.

[0195] Based on the above, the method for fabricating the semiconductor structure 300 can utilize the second via 501 on the first insulating layer 50 and the third via 801 on the second insulating layer 80 to remove the first sacrificial layer 321, the second sacrificial layer 322, and the third sacrificial layer 323 through a self-aligned process, avoiding the introduction of a new mask and reducing fabrication costs. Simultaneously, the method for fabricating the semiconductor structure 300 can also directly form the third insulating layer 60 and the first conductive layer 70 surrounding the conductive pillar 40 through a deposition process via the second via 501 on the first insulating layer 50 and the third via 801 on the second insulating layer 80, which is simple and has low fabrication costs.

[0196] Furthermore, during the etching or deposition process, the second via 501 on the first insulating layer 50 and the third via 801 on the second insulating layer 80 are uniformly distributed on the periphery of each conductive post 40. Each conductive post 40 has etching channels and deposition channels on its periphery, which can improve the uneven stress on the periphery of the conductive post 40, reduce the risk of bending deformation of the conductive post 40, and thus reduce the risk of bending deformation of the formed capacitor C.

[0197] Figure 48 This is a block diagram of a storage system according to some embodiments; Figure 49This is a block diagram of a storage system according to some other embodiments.

[0198] Please see Figure 48 and Figure 49 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 400 and a memory 10, the memory 10 including a semiconductor structure 300 as described in some of the above embodiments, and the controller 400 coupled to the memory 10 to control the memory 10 to store data.

[0199] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0200] In some embodiments, see Figure 48 The storage system 1000 includes a controller 400 and a memory 10, and the storage system 1000 can be integrated into a memory card.

[0201] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0202] In other embodiments, see Figure 49 The storage system 1000 includes a controller 400 and multiple storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0203] In some embodiments of the storage system 1000, the controller 400 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0204] In other embodiments, the controller 400 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0205] In some embodiments, the controller 400 may be configured to manage data stored in the memory 10 and communicate with external devices (e.g., a host).

[0206] In some embodiments, the controller 400 may also be configured to control the operation of the memory 10, such as read, erase and program operations.

[0207] In some embodiments, the controller 400 may also be configured to manage various functions relating to data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling.

[0208] In some embodiments, the controller 400 is also configured to process error correction codes for data read from or written to the memory 10.

[0209] Of course, the controller 400 can also perform any other suitable function, such as formatting the memory 10; for example, the controller 400 can communicate with an external device (e.g., a host) through at least one of a variety of interface protocols.

[0210] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0211] Figure 50 This is a block diagram of an electronic device according to some embodiments.

[0212] See Figure 50Some embodiments of this disclosure also provide an electronic device 2000. The electronic device 2000 can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0213] The electronic device 2000 may include, for example, the storage system 1000 and the processor 1100 described above. The storage system 1000 and the processor 1100 are connected, and the processor 1100 is used to control the storage system 1000. The processor 1100 may be, for example, a central processing unit (CPU). In addition, the electronic device 2000 may also include a cache, etc., which are not specifically limited in this embodiment.

[0214] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: Multiple conductive pillars are arranged in multiple rows and columns; A first insulating layer is disposed at one end of the extension direction of the plurality of conductive pillars and is connected to the plurality of conductive pillars; A first conductive layer surrounds the periphery of the conductive pillars; the first conductive layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars, and extends to the side of the first insulating layer away from the plurality of conductive pillars.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A second insulating layer is disposed between the plurality of conductive pillars and connected to the plurality of conductive pillars; In the row and / or column directions of the plurality of conductive pillars, between any two adjacent conductive pillars, the first conductive layer is located on opposite sides of the second insulating layer; and, between any two adjacent rows and two columns of four conductive pillars, the first conductive layer also penetrates the second insulating layer.

3. The semiconductor structure according to claim 1, characterized in that, The conductive pillar includes: The first sub-post includes a first end face and a second end face that are opposite to each other; the first insulating layer is in contact with the first end face. A second conductive layer covers the periphery of the first sub-pillar and the second end face; and along the extending direction of the conductive pillar, the second conductive layer extends to the side of the first end face away from the second end face.

4. The semiconductor structure according to claim 3, characterized in that, The first insulating layer includes: The first sublayer covers one end of the second conductive layer; Multiple first protrusions are located between the second conductive layers and are in contact with the first end face.

5. The semiconductor structure according to claim 1, characterized in that, Also includes: A third insulating layer surrounds the periphery of the conductive post and is located between the conductive post and the first conductive layer; The third insulating layer penetrates the first insulating layer between any two rows and two columns of the four conductive pillars arranged in any two adjacent rows and two columns, and extends to the side of the first insulating layer away from the plurality of conductive pillars.

6. The semiconductor structure according to claim 5, characterized in that, Between two adjacent conductive pillars, the third insulating layer also covers the surface of the first insulating layer near the plurality of conductive pillars, and the first conductive layer also covers the surface of the third insulating layer away from the first insulating layer.

7. The semiconductor structure according to claim 5, characterized in that, Also includes: A first filling layer is disposed on the side of the first conductive layer away from the third insulating layer; the first filling layer is located between the plurality of conductive pillars, and penetrates the first insulating layer between any two rows and two columns of four conductive pillars arranged in any adjacent arrangement, extending to the side of the first insulating layer away from the plurality of conductive pillars.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, Also includes: A plurality of first transistors are disposed on the side of the plurality of conductive pillars away from the first insulating layer; The first transistor includes a first electrode, a second electrode, and a gate, wherein the second electrode of the first transistor is connected to one of the conductive posts.

9. The semiconductor structure according to claim 8, characterized in that, Also includes: A first interlayer insulating layer is disposed on the side of the plurality of first transistors near the plurality of conductive pillars; between two adjacent conductive pillars, a third insulating layer further covers the surface of the first interlayer insulating layer near the first insulating layer, and the first conductive layer further covers the surface of the third insulating layer away from the first interlayer insulating layer. A first connection pad is disposed between the plurality of first transistors and the plurality of conductive pillars; the conductive pillars penetrate at least a portion of the first interlayer insulating layer and are connected to the first connection pad, and the first connection pad is connected to the second electrode of the first transistor.

10. A storage system, characterized in that, include: The memory includes the semiconductor structure as described in any one of claims 1 to 9; A controller, coupled to the memory, controls the memory to store data.

11. An electronic device, characterized in that, include: The storage system as described in claim 10; The processor is connected to the storage system.

12. A method for fabricating a semiconductor structure, characterized in that, include: Forming the first intermediate semiconductor structure; The first intermediate semiconductor structure includes a plurality of conductive pillars and a first insulating layer. The plurality of conductive pillars are arranged in multiple rows and columns. The first insulating layer is disposed at one end of the extension direction of the plurality of conductive pillars and is connected to the plurality of conductive pillars. A first conductive layer is formed; the first conductive layer surrounds the periphery of the conductive pillars; the first conductive layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars, and extends to the side of the first insulating layer away from the plurality of conductive pillars.

13. The preparation method according to claim 12, characterized in that, The formation of the first intermediate semiconductor structure includes: A stacked structure is formed; the stacked structure includes a first sacrificial layer and a second sacrificial layer stacked sequentially. A first through-hole is formed through the stacked structure; A conductive pillar is formed within the first via; the conductive pillar includes a first sub-pillar and a second conductive layer, the first sub-pillar includes a first end face and a second end face opposite to each other, the first end face being close to the second sacrificial layer; the second conductive layer covers the periphery of the first sub-pillar and the second end face; and along the extension direction of the conductive pillar, the second conductive layer extends to the side of the first end face away from the second end face.

14. The preparation method according to claim 13, characterized in that, The formation of the first intermediate semiconductor structure further includes: A first insulating layer is formed; the first insulating layer includes a first sub-layer and a plurality of first protrusions, the first sub-layer covering one end of the second conductive layer; the first protrusions are located between the second conductive layers and are in contact with the first end face; the first insulating layer is provided with a plurality of second vias, and a second via is provided between any two adjacent rows and two columns of four conductive pillars; The second sacrificial layer and the first sacrificial layer are removed sequentially through the second via.

15. The preparation method according to claim 14, characterized in that, During the process of forming the stacked structure, a second insulating layer and a third sacrificial layer are also formed; the second insulating layer is disposed between the third sacrificial layer and the first sacrificial layer; After sequentially removing the second sacrificial layer and the first sacrificial layer via the second via, the formation of the first intermediate semiconductor structure further includes: A third via is formed on the second insulating layer; a third via is provided between any two adjacent rows and columns of four conductive pillars; The third sacrificial layer is removed via the third via.

16. The preparation method according to claim 13, characterized in that, The formation of a conductive pillar within the first via includes: A second conductive film is formed; the second conductive film covers the bottom wall and sidewalls of the first via and the upper surface of the second sacrificial layer; A second filling layer is formed; the second filling layer fills the first via and covers the upper surface of the second conductive film; The second filling layer and the second conductive film are etched such that the portions of the second filling layer and the second conductive film located above the second sacrificial layer are removed, and the upper surfaces of the second filling layer and the second conductive film are located between the upper surfaces of the first sacrificial layer and the upper surfaces of the second sacrificial layer. The second filling layer is etched so that the upper surface of the second filling layer is lower than the upper surface of the second conductive film.

17. The preparation method according to claim 16, characterized in that, During the etching of the second filling layer, the second sacrificial layer is also etched; the second sacrificial layer includes a second sub-layer and a plurality of second protrusions, the upper surface of the second sub-layer is flush with the upper surface of the second conductive film; the second protrusions are disposed on the side of the second sub-layer away from the first sacrificial layer and are located between the four conductive pillars arranged in two adjacent rows and two columns.

18. The preparation method according to claim 17, characterized in that, The formation of the first insulating layer includes: A first insulating film is formed; the first insulating film fills the first via and covers the upper surface of the second sacrificial layer; Remove the portion of the first insulating film located on the side of the second protrusion away from the first sacrificial layer.

19. The preparation method according to claim 13, characterized in that, Prior to forming the stacked structure, forming the first intermediate semiconductor structure further includes: A first connecting pad and a first interlayer insulation layer are formed; the first interlayer insulation layer is disposed on the side of the first sacrificial layer away from the second sacrificial layer and covers the first connecting pad; During the formation of the first via through the stacked structure, the first via also penetrates at least a portion of the first interlayer insulation layer, thereby exposing the first connection pad.

20. The preparation method according to claim 12, characterized in that, Prior to forming the first conductive layer, the preparation method further includes: A third insulating layer is formed; the third insulating layer surrounds the periphery of the conductive pillar and is located between the conductive pillar and the first conductive layer; the third insulating layer penetrates the first insulating layer between any two adjacent rows and two columns of the four conductive pillars and extends to the side of the first insulating layer away from the plurality of conductive pillars.

21. The preparation method according to claim 20, characterized in that, After forming the first conductive layer, the preparation method further includes: A first filling layer is formed; the first filling layer is disposed on the side of the first conductive layer away from the third insulating layer; the first filling layer is located between the plurality of conductive pillars, and penetrates the first insulating layer between any two rows and two columns of four conductive pillars arranged in any adjacent arrangement, extending to the side of the first insulating layer away from the plurality of conductive pillars.

22. The preparation method according to any one of claims 12 to 21, characterized in that, Prior to forming the first intermediate semiconductor structure, the fabrication method further includes: A second intermediate semiconductor structure is formed; along the extension direction of the conductive post, the first intermediate semiconductor structure is located on one side of the second intermediate semiconductor structure; and the second intermediate semiconductor structure includes a plurality of first transistors, each first transistor including a first electrode, a second electrode and a gate, wherein the second electrode of one first transistor is connected to one of the conductive posts.

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