Semiconductor device, manufacturing method thereof and memory system

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method thereof and a memory system, the semiconductor device comprises a first semiconductor structure, and the first semiconductor structure comprises a transistor which comprises a semiconductor layer extending at least along a first direction and a gate layer extending along a second direction; the gate layer is located between the two adjacent semiconductor layers in the third direction; the third direction intersects with the second direction, and a plane formed by the third direction and the second direction intersects with the first direction; the semiconductor layer is provided with a first end and a second end which are oppositely arranged along the first direction; wherein the first end comprises a convex structure, and the convex structure comprises a main body and a first part which extend along the first direction; and a second portion extending along the third direction, the second portion being located between the main body and the first portion.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device, a method for manufacturing the same, and a memory system. Background Technology

[0002] Some semiconductor devices, such as Dynamic Random Access Memory (DRAM), may include a memory array and peripheral circuitry. The peripheral circuitry controls the memory array, performing read, write, or refresh operations. There is considerable room for improvement in both memory devices and their fabrication methods to enhance their performance. Summary of the Invention

[0003] According to some aspects of embodiments of this disclosure, a semiconductor device is provided, including a first semiconductor structure, the first semiconductor structure including: a transistor including at least a semiconductor layer extending along a first direction and a gate layer extending along a second direction; the gate layer is located between two semiconductor layers adjacent in a third direction; the third direction intersects the second direction, and a plane formed by the third direction and the second direction intersects the first direction; the semiconductor layer has a first end and a second end disposed opposite to each other along the first direction; wherein the first end includes a protrusion structure, the protrusion structure including: a body extending along the first direction and a first portion; and a second portion extending along the third direction, the second portion being located between the body and the first portion.

[0004] In some embodiments, the first end further includes a protrusion located on the side of the first portion away from the body, the protrusion extending in a direction away from the first portion.

[0005] In some embodiments, the first semiconductor structure further includes: a capacitor structure including a first electrode extending along the first direction, the first electrode being coupled to the first end; the first end extending into the first electrode, the first end being surrounded by the first electrode.

[0006] In some embodiments, the first electrode includes a conductive post and a first conductive layer surrounding the conductive post; the first end covers and contacts one side surface of the conductive post in the first direction, and the first end is surrounded by the first conductive layer.

[0007] In some embodiments, the first semiconductor structure further includes: a contact portion located between the first end and the first electrode; one side of the contact portion is coupled to the first electrode, and the other side is coupled to the first end; the first end extends into the contact portion, and the first end is surrounded by the contact portion.

[0008] In some embodiments, the contact portion includes: a conductive block and a second conductive layer surrounding the conductive block; the first end covers and contacts one side surface of the conductive block in the first direction, and the first end is surrounded by the second conductive layer.

[0009] In some embodiments, the first semiconductor structure further includes: a wall structure extending along the second direction; the semiconductor layer is located at least on two opposing sides of the wall structure in the third direction.

[0010] In some embodiments, the size of the semiconductor layer in the first direction is smaller than the size of the wall structure in the first direction.

[0011] In some embodiments, the wall structure includes: a first dielectric layer, a third conductive layer, and a second dielectric layer stacked in the first direction; the first semiconductor structure further includes a third dielectric layer located between the semiconductor layer and the wall structure.

[0012] In some embodiments, the semiconductor layer surrounds two sides of the wall structure disposed opposite each other along the third direction, and surrounds one side surface of the wall structure along the first direction; the semiconductor layer includes two first ends, the first ends exposing the other side surface of the wall structure along the first direction.

[0013] In some embodiments, the constituent material of the semiconductor layer includes indium gallium zinc oxide (IGZO).

[0014] In some embodiments, the gate layer is located on two sides of the wall structure disposed opposite to each other in the third direction; the first semiconductor structure further includes: a gate dielectric layer located between the semiconductor layer and the gate layer.

[0015] In some embodiments, a portion of the gate dielectric layer extends toward and is surrounded by the protrusion structure.

[0016] In some embodiments, the capacitor structure further includes: a fourth dielectric layer and a second electrode, the fourth dielectric layer being located between the first electrode and the second electrode; a portion of the fourth dielectric layer extending along the first direction, and a portion of the second electrode extending along the first direction being located between two adjacent first electrodes; and a plurality of the capacitor structures being coupled through the second electrode.

[0017] In some embodiments, the first semiconductor structure further includes: a bit line located on the side of the semiconductor layer near the second end and coupled to the second end; the bit line extends along the third direction.

[0018] In some embodiments, the semiconductor device further includes: a second semiconductor structure located on the side of the bit line away from the semiconductor layer; the second semiconductor structure includes peripheral circuitry and is bonded to the first semiconductor structure.

[0019] According to some aspects of embodiments of this disclosure, a method for fabricating a semiconductor device is provided, comprising forming a first semiconductor structure. The method for forming the first semiconductor structure includes: forming at least a first electrode of a capacitor structure, the first electrode extending along a first direction; forming a wall structure on one side of the first electrode along the first direction, the wall structure extending along a second direction; forming an opening in an exposed area between two adjacent wall structures; forming a semiconductor layer on two opposing sides of the wall structure along a third direction and on the inner wall of the opening; the semiconductor layer having a first end and a second end opposing to each other in the first direction; wherein the first end includes a protrusion structure located in the opening, the opening of the protrusion structure facing the second end; the second direction intersects the third direction, and a plane formed by the second direction and the third direction intersects the first direction.

[0020] In some embodiments, the region between two adjacent wall structures exposes the first electrode; the method of forming the semiconductor layer includes: removing a portion of the first electrode near one end of the wall structure to form a first opening facing the second end; the inner wall of the first opening is formed by the first electrode; the semiconductor layer is formed on two sides of the wall structure disposed opposite each other along the third direction and on the inner wall of the first opening; the protrusion structure is located in the first opening and coupled to the first electrode.

[0021] In some embodiments, the first electrode includes a conductive post and a first conductive layer surrounding the conductive post; the method of forming the first opening includes: removing a portion of the conductive post near one end of the wall structure; wherein the sidewall of the first opening exposes the first conductive layer, and the bottom of the first opening exposes the conductive post.

[0022] In some embodiments, the method of forming the first semiconductor structure further includes: forming a contact portion between two adjacent wall structures, the contact portion being coupled to the first electrode; the method of forming the semiconductor layer includes: removing a portion of the contact portion away from the first electrode to form a second opening with the opening direction facing the second end; the inner wall of the second opening being formed by the contact portion; forming the semiconductor layer on two sides of the wall structure disposed opposite to each other along the third direction and on the inner wall of the second opening; the protrusion structure being located in the second opening and coupled to the contact portion.

[0023] In some embodiments, the contact portion includes a conductive block and a second conductive layer surrounding the conductive block; the method of forming the second opening includes: removing a portion of the conductive block near one end of the wall structure; wherein the sidewall of the second opening exposes the second conductive layer, and the bottom of the second opening exposes the conductive block.

[0024] In some embodiments, the method of forming the wall structure includes: forming a first dielectric layer, a third conductive layer, and a second dielectric layer stacked along the first direction on one side of the first electrode; forming a first trench that penetrates the first dielectric layer, the third conductive layer, and the second dielectric layer and extends along the second direction; and forming the opening using the first trench; the method of forming the first semiconductor structure further includes: forming a third dielectric layer between the semiconductor layer and the wall structure.

[0025] In some embodiments, the method of forming the semiconductor layer includes: forming a semiconductor material layer on the inner wall of the first trench and the inner wall of the opening; the semiconductor material layer covering the side surface of the wall structure away from the first electrode along the first direction; the semiconductor material layer penetrating the bottom of the first trench along the first direction, and retaining the semiconductor material layer in the opening, to form the semiconductor layer.

[0026] In some embodiments, the method of forming the semiconductor layer includes: forming a protrusion in a residual portion of the semiconductor material layer as it penetrates the semiconductor material layer; wherein the protrusion structure includes: a body and a first portion on two sidewalls disposed opposite each other in the third direction of the opening, and a second portion at the bottom of the opening; the body is close to the wall structure, and the protrusion is located outside the opening and extends in a direction away from the first portion.

[0027] In some embodiments, the method of forming the first semiconductor structure further includes: forming a gate dielectric layer and a gate layer on two sides of the wall structure along the third direction, the gate dielectric layer being located between the semiconductor layer and the gate layer; the gate layer extending along the second direction, the gate layer being located between two adjacent semiconductor layers in the third direction.

[0028] In some embodiments, a portion of the gate dielectric layer extends into the opening and is surrounded by the protrusion structure on the inner wall of the opening.

[0029] In some embodiments, the method of forming the first semiconductor structure further includes: forming a bit line extending in a third direction on the side of the semiconductor layer near the second end, the bit line being coupled to the second end.

[0030] In some embodiments, the method of fabricating the semiconductor device further includes bonding a second semiconductor structure on the side of the bit line away from the semiconductor layer, the second semiconductor structure including peripheral circuitry.

[0031] In some embodiments, the method of forming the capacitor structure further includes: forming a second electrode, forming a fourth dielectric layer between the second electrode and a first electrode, a portion of the fourth dielectric layer extending along the first direction, and a portion of the second electrode extending along the first direction located between two adjacent first electrodes; and multiple capacitor structures being coupled through the second electrode.

[0032] According to some aspects of embodiments of the present disclosure, a memory system is provided, including: the semiconductor device; and a memory controller coupled to and controlling the semiconductor device.

[0033] This disclosure provides a semiconductor device including a first semiconductor structure including a transistor. The transistor includes a semiconductor layer extending along a first direction and a gate layer extending along a second direction. The semiconductor layer has a first end and a second end disposed opposite to each other along the first direction. The first end includes a protrusion structure with an opening facing the second end. The protrusion structure increases the coupling area with devices such as capacitor structures, reduces contact resistance, reduces contact surface voids, and improves device stability. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a storage array according to an exemplary embodiment;

[0035] Figure 2 This is a schematic diagram of a semiconductor device according to an exemplary embodiment;

[0036] Figures 3 to 7 This is a schematic diagram of an exemplary semiconductor device shown according to embodiments of the present disclosure;

[0037] Figure 8 This is a schematic diagram of a semiconductor device fabrication method according to an embodiment of the present disclosure;

[0038] Figures 9 to 20 This is a schematic diagram illustrating a semiconductor device fabrication method according to an embodiment of the present disclosure;

[0039] Figure 21 and Figure 22 This is a schematic diagram of an exemplary system according to an embodiment of the present disclosure. Detailed Implementation

[0040] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0041] It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as a second element, component, area, layer, or part. And the discussion of a second element, component, area, layer, or part does not imply that the first element, component, area, layer, or part necessarily exists in this disclosure.

[0042] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0044] It should be understood that the phrases "some embodiments" or "an embodiment" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "some embodiments" or "an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure.

[0045] The semiconductor device in this disclosure can be DRAM, or at least a portion of the memory device within DRAM. It is applicable to Double Data Rate Synchronous Dynamic Random Access Memory (DRAM) using DDR4 or DDR5 memory specifications, and Low Power Double Data Rate DRAM using LPDDR5 memory specifications. It should be noted that this disclosure is not limited to DRAM; however, for clarity, DRAM will be used as an example in the following description.

[0046] In DRAM, memory arrays can be arranged in rows and columns, allowing memory cells to be addressed by specifying their rows and columns. A memory array includes multiple word lines and multiple bit lines. Word lines and bit lines intersect; selecting a memory cell at the intersection of a word line and a bit line selects it for read, write, or refresh operations. Figure 1 As exemplified, the memory array may include multiple word lines WLn, WLn+1, WLn-1, and WLn-2, ​​and multiple bit lines BLn, BLn+1, BLn-1, and BLn-2, ​​with word lines and bit lines intersecting. Memory cells within the memory array may include capacitors and transistors; a memory cell may include one transistor and one capacitor. Word lines may also be conductive structures such as gate layers, serving as the gate of a transistor. One controlled terminal (source) of the transistor is coupled to one electrode of the capacitor, and the other controlled terminal (drain) of the transistor is coupled to the bit line. The other electrode of the capacitor may be grounded or have another voltage (such as Vdd / 2) applied to it. Figure 1As shown, the storage cell array is arranged in an x-row, y-column configuration. The rows and columns can be perpendicular or not. The x-direction can be the third direction mentioned in the embodiments of this disclosure, and the y-direction can be the second direction mentioned in the embodiments of this disclosure. The extension direction of the bit line can be parallel to the x-direction or at an angle to the x-direction. The extension direction of the word line can be parallel to the y-direction or at an angle to the y-direction. The orthogonal projection of the word line on the xoy plane is perpendicular to the orthogonal projection of the bit line on the xoy plane, or it is not perpendicular but at a certain angle. This disclosure does not limit this. The z-direction in the examples shown below can be the first direction. The z-direction can be perpendicular to the xoy plane, or it can intersect the xoy plane but not perpendicular to it.

[0047] During read or write operations, the corresponding word line can be selected using a word line selection signal, and the corresponding bit line can be selected using a column selection signal. Simultaneous selection of the word line and bit line allows location of the selected memory cell. At this time, the transistor of the selected memory cell is turned on due to the operating voltage applied to the word line, thereby enabling read, write, or refresh operations on the selected memory cell. In some embodiments, the capacitor can be replaced with other memory structures, including but not limited to: phase-change memory structures, resistive switching memory structures, or magnetic switching memory structures.

[0048] In some embodiments, a capacitor represents a logical 1 or 0 by the amount of charge stored within it, or by the voltage difference across its terminals. A voltage signal on the word line is applied to the gate to control the transistor's on or off state, thus selecting or deselecting the capacitor. This allows data stored in the capacitor to be read via the bit line, or data to be written to the capacitor for storage via the bit line.

[0049] According to some aspects of embodiments of this disclosure, Figure 2 A semiconductor device is provided, including a first semiconductor structure 101. The first semiconductor structure 101 includes a transistor 110, including a semiconductor layer 111 extending at least along the z-direction and a gate layer 112 extending along the y-direction. The gate layer 112 is located between two adjacent semiconductor layers 111 in the x-direction. The two adjacent semiconductor layers 111 may include a first semiconductor layer 1111 and a second semiconductor layer 1112. The x-direction intersects the y-direction, and the plane formed by the x-direction and the y-direction intersects the z-direction. The semiconductor layer 111 has a first end and a second end disposed opposite to each other along the z-direction. The first end can be used for coupling with a capacitor structure 140, and the second end can be used for coupling with a bit line 114. The first end may have a protrusion 1114 extending away from the semiconductor layer 111 along the x-direction. The protrusion 1114 can increase the coupling area with the capacitor structure 140 and provide a flat contact surface, thereby reducing contact resistance.

[0050] Transistor 110 may include a semiconductor layer 111, and a gate dielectric layer 113 and a gate layer 112 located on the semiconductor layer 111. The gate layer 112 serves as the control gate or word line of transistor 110, and the semiconductor layer 111 serves as the channel of transistor 110. The transistor 110 can be turned on or off by applying a voltage to the gate layer 112, specifically controlling the on / off state of the corresponding semiconductor layer 111. At least a portion of the semiconductor layer 111 may extend in a planar yoz plane. The two ends of the semiconductor layer 111 disposed opposite each other in the z-direction are respectively designated as a first end and a second end. The region between the first end and the second end is an intermediate region. The first end and the second end may have the same type of doping and can serve as the active region (drain or source, the source and drain can be interchanged) of transistor 110. The intermediate region between the first end and the second end may have doping of the opposite type to that of the first end, serving as the channel of transistor 110. The gate layer 112 covers the intermediate region between the first end and the second end in the x-direction. The first end, the second end, and the intermediate region in this embodiment are different locations of the semiconductor layer 111, which are only useful for explaining the scheme of this embodiment. In the actual physical structure, there may not be a clear dividing line. The first end can be the end in the negative z-direction of the figure, which can be the lower end of the semiconductor layer 111, and can be used to couple with the capacitor structure 140; the second end can be the end in the positive z-direction of the figure, which can be the upper end of the semiconductor layer 111, and can be used to couple with the bit line 114.

[0051] For example, the constituent materials of semiconductor layer 111 may include any semiconductor material within the art, including but not limited to: elemental semiconductor materials (e.g., silicon, germanium), III-V compound semiconductor materials, II-VI compound semiconductor materials, organic semiconductor materials, or other semiconductor materials known in the art; for example, single-crystal silicon, polycrystalline silicon, germanium, silicon carbide, indium gallium zinc oxide (IGZO), etc. The constituent materials of gate layer 112 include but are not limited to: conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, or aluminum. Gate dielectric layer 113 includes but is not limited to: insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, or aluminum oxide.

[0052] Figure 2As shown, semiconductor layer 111 may be located on two opposite sides of wall structure 120 in the x direction, wall structure 120 extends in the y direction, semiconductor layer 111 and gate layer 112 are located between two adjacent wall structures 120, wall structure 120 provides an attachment surface for semiconductor layer 111; first semiconductor layer 1111 may be located on the right side of wall structure 120, second semiconductor layer 1112 may be located on the left side of wall structure 120; first gate layer 1121 may be located on the right side of wall structure 120, second gate layer 1122 may be located on the left side of wall structure 120. The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 can be a continuous structure. One semiconductor layer 111 can cover one side surface of the wall structure 120 in the z direction and two surfaces opposite to each other in the x direction. One semiconductor layer 111 can include a first semiconductor layer 1111 and a second semiconductor layer 1112. The second ends of the first semiconductor layer 1111 and the second semiconductor layer 1112 are partially connected by a semiconductor layer 111 extending in the x direction. The first semiconductor layer 1111 and the second semiconductor layer 1112 correspond to two transistors 110 respectively. Alternatively, the cross-sectional shape of the semiconductor layer 111 in the xoz plane can be U-shaped (or inverted U-shaped), including two first ends and a second end covering the top surface of the wall structure 120. The two first ends form an opening to expose the wall structure 120. One semiconductor layer 111 corresponds to two transistors 110, and the first semiconductor layer 1111 and the second semiconductor layer 1112 extend in the z direction respectively. For example, the first transistor 110 may include a first semiconductor layer 1111 located on the right side of a wall structure 120, a first gate layer 1121 located on the first semiconductor layer 1111, specifically the portion of the first gate layer 1121 that overlaps with the first semiconductor layer 1111 in the x direction, and a gate dielectric layer 113 located between the first semiconductor layer 1111 and the first gate layer 1121.

[0053] In some embodiments, Figure 2 The U-shaped semiconductor layer 111 shown in the diagram covers the film layer of the wall structure 120 along the z direction. The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 are not connected by the semiconductor layer 111. Figure 2 The U-shaped semiconductor layer 111 shown covers a portion of the wall structure 120 along the z-direction, providing a larger area and a flatter contact surface for the bit line 114 to reduce the contact gap between the bit line 114 and the semiconductor layer 111, improve device stability, and save the process steps of removing the semiconductor layer 111 to expose the wall structure 120, thereby reducing manufacturing costs.

[0054] In some embodiments, reference Figure 2As shown, the semiconductor layer 111 may be located on one side of the capacitor structure 140. The capacitor structure 140 may include a first electrode 141 extending along the z-direction, a second electrode 143, and a fourth dielectric layer 142 located between the two electrodes for electrical isolation. A first end of the semiconductor layer 111 may be coupled to the first electrode 141, such as a protrusion 1114 extending away from the semiconductor layer 111 along the x-direction at the first end being coupled to the first electrode 141, with one surface of the protrusion 1114 in the z-direction coupled to the first electrode 141. According to some aspects of embodiments of this disclosure, a semiconductor device is provided in which the first end of the semiconductor layer 111 has a protrusion structure 1113 with an opening facing the second end. Both sides of the protrusion structure 1113 in the x-direction and one surface in the z-direction may be coupled to the first electrode 141, further increasing the coupling area, improving the contact adhesion of the components, reducing contact resistance, and improving device stability.

[0055] According to some aspects of embodiments of this disclosure, Figure 3 and Figure 4 A semiconductor device is provided, including a first semiconductor structure 101. The first semiconductor structure 101 includes a transistor 110, including a semiconductor layer 111 extending at least along a first direction (z-direction) and a gate layer 112 extending along a second direction (y-direction). The gate layer 112 is located between two adjacent semiconductor layers 111 in a third direction (x-direction). The third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction. The semiconductor layer 111 has a first end and a second end disposed opposite to each other along the first direction. The first end includes a protrusion structure 1113, which includes a body 1115 extending along the z-direction and a first portion 1116. The protrusion structure 1113 includes a second portion 1117 extending along the x-direction, which is located between the body 1115 and the first portion 1116. The first semiconductor structure 101 also includes a wall structure 120 extending along the y-direction. A semiconductor layer 111 is disposed on two opposite sides of the wall structure 120 in the x-direction. The semiconductor layer 111 can cover one side surface of the wall structure 120 in the z-direction while exposing the other side surface of the wall structure 120 in the z-direction. The wall structure 120 provides an attachment surface for the semiconductor layer 111 and supports the semiconductor layer 111. The semiconductor layer 111 and the gate layer 112 are located between two adjacent wall structures 120.

[0056] Reference Figure 3 As shown, the first end located in the negative z direction and at the bottom of the semiconductor layer 111 has a protrusion structure 1113. The protrusion structure 1113 extends away from the second end in the z direction, or protrudes from the wall structure 120 away from the second end in the z direction; at least a portion of the protrusion structure 1113 protrudes downward from the wall structure 120 in the z direction. Figure 2The first end of the semiconductor layer 111 shown may be flush with the bottom of the wall structure 120. The cross-sectional shape of the protrusion structure 1113 in the xoz plane may be a closed shape formed by three straight lines or approximately straight lines, or curves, including but not limited to a U-shape, or a similar U-shape, with the opening of the U-shape facing the second end, and the U-shaped opening being filled by other material layers (e.g., gate dielectric layer 113). The portion protruding downward along the z-direction from the wall structure 120 may have a U-shaped cross-sectional shape in the xoz plane, with the opening of the U-shape facing upward along the z-direction towards the second end of the top of the semiconductor layer 111. The protrusion structure 1113 includes at least two sidewalls extending along the z-direction and a bottom extending along the x-direction. Both the sidewalls and the bottom can be used for electrical coupling, for example, extending into the interior of the capacitor structure 140 or other conductive components for coupling, increasing the electrical connection area and reducing contact resistance.

[0057] In some embodiments, for ease of explanation, the specific shape of the first end of the semiconductor layer 111 is described. Figure 3 A partial magnification of the first end is shown below. Figure 3 As shown, the protrusion structure 1113 includes: a main body 1115 and a first portion 1116 extending along the z-direction; and a second portion 1117 extending along the x-direction, the second portion 1117 being located between the main body 1115 and the first portion 1116. The intermediate region between the first end and the second end, at least a portion of which can be covered by the gate layer 112 along the x-direction, is also included. The main body 1115 may be a portion of the protrusion structure 1113 connected to the intermediate region, or a sidewall of the protrusion structure 1113 extending along the z-direction closer to the wall structure 120 in the partial schematic diagram. The first portion 1116 is a sidewall opposite to the main body 1115 in the x-direction, and the second portion 1117 is the bottom of the protrusion structure 1113 located between the main body 1115 and the first portion 1116, extending along the x-direction. The main body 1115, the first portion 1116, and the second portion 1117 are different locations of the protrusion structure 1113, used only for illustrative purposes, and may not actually have clear physical boundaries.

[0058] In some embodiments, reference Figure 3As shown, the first end further includes a protrusion 1114 located on the side of the first portion 1116 away from the body 1115, extending away from the first portion 1116. The protrusion 1114 is located on the first portion 1116 and extends away from the body 1115 along the x-direction. The film height of the protrusion 1114 in the z-direction is different from the film height of the second portion 1117, for example, the film height of the protrusion 1114 may be higher than the film height of the second portion 1117. The protrusion 1114 is a remnant from the etching that breaks the semiconductor material between adjacent wall structures 120 in the z-direction during the formation of the semiconductor layer 111, and is used to increase the coupling area and reduce the contact resistance. In some embodiments, the protrusion 1114 may not exist, or the size of the protrusion 1114 in the x-direction may be small and not clearly visible.

[0059] In some embodiments, reference Figure 4 As shown, the first semiconductor structure 101 further includes a capacitor structure 140, including a first electrode 141 extending along the z-direction, the first electrode 141 being coupled to a first end; the first end extends into the first electrode 141 and is surrounded by the first electrode 141. The capacitor structure 140 includes two conductive electrodes and a dielectric layer (e.g., a fourth dielectric layer 142) located between the two conductive electrodes and electrically isolated. One electrode of the capacitor structure 140 is directly contacted and coupled to the first end of the semiconductor layer 111, or coupled through a conductive structure. The specific structure of the capacitor structure 140 is not limited in this embodiment, and at least one electrode of the capacitor structure 140 may extend along the z-direction.

[0060] Reference Figure 4 As shown, the end of the first electrode 141 that contacts the first end of the semiconductor layer 111 has a groove. The first end of the semiconductor layer 111 extends into the groove of the first electrode 141 along the z-direction, such that at least a portion of the protrusion structure 1113 at the first end is surrounded by the first electrode 141. The sidewalls of the protrusion structure 1113 extending along the z-direction and the bottom extending along the x-direction are in contact with and coupled to the first electrode 141, thereby increasing the contact area between the semiconductor layer 111 and the first electrode 141, reducing the contact resistance, and improving the adhesion between the semiconductor layer 111 and the first electrode 141. Specifically, in conjunction with... Figure 3 As shown, the protruding structure 1113 extends into the first electrode 141 and is surrounded by the first electrode 141. The main body 1115, the first part 1116 and the second part 1117 can be contacted and coupled to the first electrode 141.

[0061] In some embodiments, reference Figure 4As shown, the capacitor structure 140 further includes a fourth dielectric layer 142 and a second electrode 143. The fourth dielectric layer 142 is located between the first electrode 141 and the second electrode 143. A portion of the fourth dielectric layer 142 extends along the z-direction, and a portion of the second electrode 143 extending along the z-direction is located between two adjacent first electrodes 141. The multiple capacitor structures 140 are coupled through the second electrode 143.

[0062] The first electrode 141 extends along the z-direction and is directly coupled to the first end of the semiconductor layer 111 or coupled through a connection portion (or, contact portion 150). The first electrode 141 and / or the second electrode 142 may include an air gap 144 to reduce stress concentration and thus reduce device deformation. The fourth dielectric layer 142 may surround the sidewall of the first electrode 141 and the end of the first electrode 141 not coupled to the first end. The second electrode 143 may surround the fourth dielectric layer 142. A portion of the fourth dielectric layer 142 may extend along the z-direction, a portion of the second electrode 143 may extend along the z-direction and be located between two adjacent first electrodes 141, and another portion of the second electrode 143 may extend along the x-direction and cover the fourth dielectric layer 142 along the z-direction. The cross-sectional shape of the portion of the second electrode 143 extending in the z-direction in the xoz plane can be dumbbell-shaped. A third and fourth end are positioned opposite each other in the z-direction, and a strip connects the third and fourth ends. The dimensions of the third and fourth ends in the x-direction are larger than the dimensions of the strip in the x-direction. The third and fourth ends include an air gap 144. The third end, the strip, and the fourth end are different regions of the second electrode 143, presented only as illustrative examples; in reality, they are a single unit and may not have clear physical boundaries. Multiple capacitor structures 140 can be coupled through the portion of the second electrode 143 extending in the x-direction. Multiple capacitor structures 140 are connected in series in the portion of the second electrode 143 extending in the x-direction. The portion of the second electrode 143 extending in the x-direction can be used for grounding or for applying other voltages (such as Vdd / 2).

[0063] In some embodiments, reference Figure 4 The first electrode 141 shown includes a conductive post 1411 and a first conductive layer 1412 surrounding the conductive post 1411; the first end covers and contacts one side surface of the conductive post 1411 in the z direction along the z direction, and the first end is surrounded by the first conductive layer 1412.

[0064] The first electrode 141 may include a single-layer structure or a multi-layer structure. For example, the first electrode 141 may only include a conductive post 1411 extending along the z-direction, or the first electrode 141 may include a conductive post 1411 extending along the z-direction and a first conductive layer 1412 surrounding the sidewalls and bottom of the conductive post 1411. The first conductive layer 1412 may serve as a connecting layer to increase the adhesion between the conductive post 1411 and the fourth dielectric layer 142. For example, the conductive post 1411 may include tungsten, and the first conductive layer 1412 may include titanium nitride. The sidewalls of the protrusion structure 1113 extending along the z-direction are surrounded by the first conductive layer 1412 and are in contact with each other; the bottom of the protrusion structure 1113 along the x-direction covers the conductive post 1411 along the z-direction and is in contact with each other. In the z-direction, the film height of the contact interface between the protrusion structure and the conductive post 1411 is different from the film height of the first conductive layer 1412, such that the film height of the contact interface is lower than the film height of the first conductive layer 1412.

[0065] For example, the materials used to compose the first electrode 141 and the second electrode 143 may include, but are not limited to, conductive materials such as tungsten, gold, silver, platinum, copper, aluminum, titanium, nickel, or titanium nitride. The materials used to compose the fourth dielectric layer 142 may include, but are not limited to, insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide.

[0066] In some embodiments, reference Figure 5 As shown, the first semiconductor structure 101 further includes: a contact portion 150 located between the first end and the first electrode 141; one side of the contact portion 150 is coupled to the first electrode 141, and the other side is coupled to the first end; the first end extends into the contact portion 150 and is surrounded by the contact portion 150. The contact portion 150 can improve the adhesion between the semiconductor layer 111 and the first electrode 141 and can reduce the contact resistance. Figure 5 A partially enlarged schematic diagram of the contact portion 150 coupled to the semiconductor layer 111 and the first electrode 141 is also shown. The end of the contact portion 150 that contacts the first end of the semiconductor layer 111 has a groove. The first end of the semiconductor layer 111 extends into the groove of the contact portion 150 along the z-direction, such that at least a portion of the protrusion structure 1113 at the first end is surrounded by the contact portion 150. The sidewalls of the protrusion structure 1113 extending along the z-direction and the bottom extending along the x-direction are coupled to the contact portion 150, thereby increasing the contact area between the semiconductor layer 111 and the contact portion 150, reducing contact resistance, and improving the adhesion between the semiconductor layer 111 and the contact portion 150. Specifically, in conjunction with... Figure 3As shown, the protruding structure 1113 extends into and is surrounded by the contact portion 150. The main body 1115, the first portion 1116, and the second portion 1117 can be coupled to the contact portion 150. The contact portion 150 and the first electrode 141 may be offset or misaligned in the x-direction and not perfectly aligned in the z-direction, thereby improving the manufacturing process window.

[0067] In some embodiments, reference Figure 5 As shown, the contact portion 150 includes: a conductive block 151 and a second conductive layer 152 surrounding the conductive block 151; a first end covers and contacts one side surface of the conductive block 151 along the z-direction, and the first end is surrounded by the second conductive layer 152. The contact portion 150 may include, but is not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, titanium nitride, or metal silicides. The contact portion 150 may include a single-layer conductive structure or a multi-layer conductive structure, such as including the conductive block 151 and the second conductive layer 152. The second conductive layer 152 is located between the conductive block 151 and the semiconductor layer 111. The second conductive layer 152 can serve as a connecting layer to increase the adhesion between the conductive block 151 and the semiconductor layer 111, thereby reducing contact resistance. The conductive block 151 may include tungsten, and the second conductive layer 152 may include metal silicides or titanium nitride. The sidewalls of the protruding structure 1113 extending along the z-direction are surrounded by the second conductive layer 152 and are coupled to each other; the bottom of the protruding structure 1113 along the x-direction covers the conductive block 151 along the z-direction and is coupled to each other. In the z-direction, the film height of the contact interface between the protruding structure and the conductive block 151 is different from the film height of the second conductive layer 152, such that the film height of the contact interface is lower than the film height of the second conductive layer 152.

[0068] In some embodiments, reference Figures 3 to 5 The first semiconductor structure 101 shown further includes: a wall structure 120 extending along the y direction; and a semiconductor layer 111 located at least on two sides of the wall structure 120 that are disposed opposite each other in the x direction.

[0069] The wall structure 120 extending along the y-direction provides an attachment plane for the semiconductor layer 111 and can provide support for the semiconductor layer 111. The semiconductor layer 111 covers two opposite sides of the wall structure 120 along the x-direction. The semiconductor layer 111 can also cover one surface of the wall structure 120 along the z-direction. The cross-sectional shape of the semiconductor layer 111 in the xoz plane is U-shaped. The second ends of the first semiconductor layer 1111 and the second ends of the second semiconductor layer 1112 located on both sides of the same wall structure 120 are connected. Alternatively, the semiconductor layer 111 can cover only two sides of the wall structure 120, with the second ends of the first semiconductor layer 1111 and the second ends of the second semiconductor layer 1112 not connected.

[0070] In some embodiments, reference Figure 3 and Figure 4 As shown, the dimension of the semiconductor layer 111 in the z-direction is larger than the dimension of the wall structure 120 in the z-direction. (Refer to...) Figure 5 As shown, the side surface of the contact portion 150 near the first electrode 141 in the z direction is at the same film height as the side surface of the contact portion 150 near the first electrode 141. The first end of the semiconductor layer 111 extends into the contact portion 150. The size of the semiconductor layer 111 in the z direction is smaller than the size of the wall structure 120 in the z direction.

[0071] In some embodiments, reference Figures 2 to 5 As shown, the wall structure 120 includes a first dielectric layer 121, a third conductive layer 122, and a second dielectric layer 123 stacked in the z-direction; the first semiconductor structure 101 also includes a third dielectric layer 131 located between the semiconductor layer 111 and the wall structure 120.

[0072] The wall structure 120 may include an insulating material, which provides an attachment surface for the semiconductor layer 111 and serves as mechanical support. Alternatively, the wall structure 120 may include a conductive material as a back gate, which is connected to a low potential, such as ground or a negative voltage, to improve the coupling effect between adjacent transistors 110, reduce the parasitic capacitance between adjacent first semiconductor layer 1111 and second semiconductor layer 1112, and improve device stability. For example, the wall structure 120 includes a first dielectric layer 121, a third conductive layer 122, and a second dielectric layer 123 stacked sequentially. The third conductive layer 122 serves as a back gate ground or negative voltage. A third dielectric layer 131 is disposed between the side of the wall structure 120 and the semiconductor layer 111 to electrically isolate the third conductive layer 122 from the semiconductor layer 111. The second dielectric layer 123 electrically isolates the semiconductor layer 111 and the third conductive layer 122 on both sides of its z-direction. The first dielectric layer 121 electrically isolates the third conductive layer 122 on both sides of its z-direction from other conductive devices, such as electrically isolating the third conductive layer 122 from the electrodes of the capacitor structure 140. The materials of the first dielectric layer 121, the second dielectric layer 123, and the third dielectric layer 131 may be the same or different, including but not limited to insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or aluminum oxide. For example, the third conductive layer 122 may include, but is not limited to, conductive materials such as tungsten, gold, silver, copper, chromium, nickel, titanium, aluminum, and titanium nitride.

[0073] In some embodiments, reference Figures 2 to 5 As shown, the semiconductor layer 111 surrounds two opposite sides of the wall structure 120 along the x-direction and surrounds one side surface of the wall structure 120 along the z-direction; the semiconductor layer 111 includes two first ends, the first ends of which expose the other side surface of the wall structure 120 along the z-direction.

[0074] The second end of the first semiconductor layer 1111 and the second end of the second semiconductor layer 1112 can be a continuous structure. One semiconductor layer 111 can cover one side surface of the wall structure 120 in the z direction and two surfaces opposite to each other in the x direction. One semiconductor layer 111 can include a first semiconductor layer 1111 and a second semiconductor layer 1112. The second ends of the first semiconductor layer 1111 and the second semiconductor layer 1112 are partially connected by a semiconductor layer 111 extending in the x direction. The first semiconductor layer 1111 and the second semiconductor layer 1112 correspond to two transistors 110 respectively. Alternatively, the cross-sectional shape of the semiconductor layer 111 in the xoz plane can be U-shaped (or inverted U-shaped), including two first ends and a second end covering the top surface of the wall structure 120. The two first ends form an opening to expose the wall structure 120. One semiconductor layer 111 corresponds to two transistors 110, and the first semiconductor layer 1111 and the second semiconductor layer 1112 extend in the z direction respectively. The semiconductor layer 111 covers a portion of the wall structure 120 along the z-direction, providing a larger and flatter contact surface for the bit line 114 to reduce the contact gap between the bit line 114 and the semiconductor layer 111, improve device stability, and save the process steps of removing the semiconductor layer 111 to expose the wall structure 120, thereby reducing manufacturing costs.

[0075] In some embodiments, the semiconductor layer 111 is composed of indium gallium zinc oxide (IGZO). IGZO material may be composed of oxides of elements such as indium, gallium, and zinc, exhibiting superior semiconductor properties. The addition of indium and gallium improves the electron mobility of the semiconductor material, achieving lower operating voltage and lower power consumption compared to traditional semiconductor materials such as silicon; the introduction of zinc helps improve the stability of the semiconductor material. IGZO material can be used to deposit and fabricate the semiconductor layer 111. By controlling the deposition process parameters, the film thickness, crystal form, and film morphology of the semiconductor layer 111 can be controlled, improving the fabrication yield of the semiconductor layer 111 while simplifying the fabrication process. IGZO material allows the semiconductor layer 111 to directly contact and couple with metal components such as the first electrode 141 and the contact portion 150, reducing contact resistance.

[0076] In some embodiments, reference Figures 2 to 5As shown, the first semiconductor structure 101 further includes: a gate layer 112 located on two opposite sides of the wall structure 120 in a third direction; and a gate dielectric layer 113 located between the semiconductor layer 111 and the gate layer 112. The semiconductor layer 111 and the gate layer 112 are located between two adjacent wall structures 120. The first semiconductor layer 1111 may be located on the right side of the wall structure 120, and the second semiconductor layer 1112 may be located on the left side of the wall structure 120. The first gate layer 1121 may be located on the right side of the wall structure 120, and the second gate layer 1122 may be located on the left side of the wall structure 120. The gate layer 112 may include a conductive single-layer structure, such as tungsten; the gate layer 112 may also include a conductive multilayer structure, such as a first sub-gate layer and a second sub-gate layer. The first sub-gate layer is located between the gate dielectric layer and the second sub-gate layer. The dimension of the first sub-gate layer in the x-direction is smaller than the thickness of the second sub-gate layer. The first sub-gate layer is used to increase the adhesion between the gate dielectric layer and the second sub-gate layer. For example, the first sub-gate layer may include titanium nitride, and the second sub-gate layer may include tungsten.

[0077] In some embodiments, a filler layer is provided between adjacent wall structures 120 to electrically isolate adjacent gates and semiconductor layers 111. The filler layer and gate dielectric layer 113 may be made of the same material, and in this case, the filler layer and gate dielectric layer 113 may not have a clear physical boundary.

[0078] In some embodiments, reference Figures 3 to 5 As shown, a portion of the gate dielectric layer 113 extends toward and is surrounded by the protrusion structure 1113. Specifically, as... Figure 5 As shown, a portion of the gate dielectric layer 113 relative to the first electrode 141 may extend into the opening of the protrusion structure 1113, filling the opening of the protrusion structure 1113 to reduce voids.

[0079] In some embodiments, reference Figure 6 As shown, the first semiconductor structure 101 further includes: a bit line 114 located on the side of the semiconductor layer 111 near the second end and coupled to the second end; the bit line 114 extends along the x direction.

[0080] For example, the second electrode 143 is connected to a common voltage. A voltage is applied through a bit line 114 and a gate layer 112 to select the semiconductor layer 111 at the intersection of the bit line 114 and the gate layer 112. A conduction voltage is applied to the gate layer 112 to turn on the semiconductor layer 111 and provide voltage to the first electrode 141. At this time, a capacitor structure 140 is selected to perform read, write, or update operations. An interconnect layer is provided on the side of the bit line 114 away from the capacitor structure 140 to supply power to the bit line 114 or to the gate layer 112 and other structures, so as to realize the supply of power to the first semiconductor structure 101 or the output of electrical signals.

[0081] In some embodiments, reference Figure 7 As shown, the semiconductor device 100 further includes: a second semiconductor structure 102 located on the side of the bit line 114 away from the semiconductor layer 111; the second semiconductor structure 102 includes peripheral circuitry 160, and the second semiconductor structure 102 is bonded to the first semiconductor structure 101; the bonding may include hybrid bonding.

[0082] Before bonding, the bonding surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 respectively have a first bonding contact and a second bonding contact, which respectively lead the electrical signals of the semiconductor structure to the bonding surface. The bonding contacts may include structures such as pads and conductive plugs. The bonding surfaces of the first semiconductor structure 101 and the second semiconductor structure 102 are then bonded together, and the interface between the two bonding surfaces is called the bonding interface. The first bonding contact and the second bonding contact contact and bond at the bonding interface, realizing the electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. After bonding, the first bonding contact and the second bonding contact may not have a physical boundary and can be considered as... Figure 7 A bonding contact 115 is provided, which penetrates the bonding interface. The portion of the bonding contact 115 located in the first semiconductor is the first bonding contact before bonding, and the portion of the bonding contact 115 located in the second semiconductor is the second bonding contact before bonding. Taking the gate layer 112, bit line 114, and second electrode 143 as an example, the gate layer 112, bit line 114, and second electrode 143 can respectively lead electrical signals out to the bonding contact 115 and couple them with the peripheral circuit 160 through contact structures. An interconnect layer can be provided between the bit line 114 and the bonding contact 115 to interconnect the signals of the first semiconductor structure 101 with the electrical signals of the peripheral circuit 160.

[0083] For example, peripheral circuitry 160 may include, but is not limited to, a sensing amplifier circuit, a row decoding circuit, a column decoding circuit, and a voltage generation circuit. The sensing amplifier circuit is coupled to bit line 114 and can be configured to capture weak voltage fluctuations on bit line 114 and locally reconstruct the capacitor voltage of the memory cell based on the voltage fluctuations. The sensing amplifier circuit may include a latch to latch the reconstructed capacitor voltage value, thereby transferring the information stored in the memory cell from the capacitor to the amplifier circuit. The sensing amplifier circuit may include a differential sensing amplifier circuit coupled to two bit lines 114, operating using a selected bit line 114 and a complementary bit line 114 used as a reference line to detect and amplify the voltage difference on a pair of bit lines 114. The row decoding circuit is configured to perform row addressing of the memory array and apply an operating voltage to the word line. The column decoding circuit is configured to perform column addressing of the memory array and apply or receive the bit line 114 voltage. The voltage generation circuit generates the required high and low voltages for each device.

[0084] In some embodiments, the second semiconductor structure 102 and the first semiconductor structure 101 are not fixed by bonding, and bonding contacts 115 may not be provided between the first semiconductor structure 101 and the second semiconductor structure 102.

[0085] According to some aspects of embodiments of the present disclosure, a method for fabricating a semiconductor device is provided, forming a first semiconductor structure 101, with reference to... Figure 8 As shown, a method for forming a first semiconductor structure 101 includes: forming at least a first electrode of a capacitor structure, the first electrode extending along a first direction; forming a wall structure on one side of the first electrode along the first direction, the wall structure extending along a second direction; forming an opening in an exposed area between two adjacent wall structures; forming a semiconductor layer on two opposing sides of the wall structure along a third direction and on the inner wall of the opening; the semiconductor layer having a first end and a second end opposingly disposed in the first direction; wherein the first end includes a protrusion structure located in the opening, the opening of the protrusion structure facing the second end; the second direction intersects the third direction, and the plane formed by the second direction and the third direction intersects the first direction. The opening may include a first opening 13 formed by etching the first electrode 141 mentioned later, the protrusion structure 1113 may be formed based on the inner wall of the first opening 13; the opening may include a second opening 14 formed by etching the contact portion 150, the protrusion structure 1113 may be formed based on the inner wall of the second opening 14. In this embodiment, the capacitor structure 140 may be fabricated before the semiconductor layer 111, gate layer 112, etc., or the first electrode 141 of the capacitor structure 140 may be fabricated before the semiconductor layer 111, gate layer 112, etc.

[0086] In some embodiments, the method of forming the wall structure 120 includes: forming a first dielectric layer 121, a third conductive layer 122, and a second dielectric layer 123 stacked along the z-direction on one side of the first electrode 141; forming a first trench 12 that penetrates the first dielectric layer 121, the third conductive layer 122, and the second dielectric layer 123 and extends along the y-direction; and forming an opening using the first trench 12. The method of forming the first semiconductor structure 101 further includes: forming a third dielectric layer 131 between the semiconductor layer 111 and the wall structure 120.

[0087] Reference Figure 9 As shown, a first dielectric layer 121, a third conductive layer 122, and a second dielectric layer 123 are sequentially formed on one side of the first electrode 141 along the z-direction. The formation process may include, but is not limited to, deposition processes, including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD). (Refer to...) Figure 10 As shown, a first trench 12 extending along the y-direction is etched and formed, exposing a first electrode 141 at the bottom of the first trench 12. The remaining first dielectric layer 121, third conductive layer 122, and second dielectric layer 123 form a wall structure 120. A third dielectric layer 131 is formed on the two opposite sides of the first trench 12, which are also the wall structure 120, along the x-direction. The etching process may include, but is not limited to, dry etching, wet etching, or any combination thereof.

[0088] In some embodiments, reference Figure 11 As shown, the region between two adjacent wall structures 120 exposes the first electrode 141; the method of forming the semiconductor layer 111 includes: referring to Figure 11 As shown, a portion of the first electrode 141 near the wall structure 120 is removed to form a first opening 13 facing the second end; the inner wall of the first opening 13 is formed by the first electrode 141; see reference. Figure 12 and Figure 13 As shown, a semiconductor layer 111 is formed on two sides of the wall structure 120 that are arranged opposite each other along the x-direction and on the inner wall of the first opening 13; the protrusion structure 1113 is located in the first opening 13 and is coupled to the first electrode 141.

[0089] In some embodiments, reference Figure 11As shown, the first electrode 141 includes a conductive post 1411 and a first conductive layer 1412 surrounding the conductive post 1411. The first conductive layer 1412 does not cover the top of the conductive post 1411, and the first conductive layer 1412 may surround the sidewalls and bottom of the conductive post 1411. The method of forming the first opening 13 includes: referring to... Figure 11 The diagram shows the removal of a portion of the conductive post 1411 near the wall structure 120; wherein, the sidewall of the first opening 13 exposes the first conductive layer 1412, and the bottom of the first opening 13 exposes the conductive post 1411. The sidewall of the first opening 13 in the x-direction is composed of the first conductive layer 1412.

[0090] The conductive pillar 1411 may include tungsten, and the first conductive layer 1412 may include titanium nitride. The first conductive layer 1412 can increase the adhesion between the conductive pillar 1411 and materials such as the dielectric layer. The conductive pillar 1411 may include tungsten, and the first conductive layer 1412 may include titanium nitride. The sidewalls of the protruding structure 1113 extending along the z-direction are surrounded by the first conductive layer 1412 and are in contact with each other; the bottom of the protruding structure 1113 along the x-direction covers the conductive pillar 1411 along the z-direction and is in contact with each other. In the z-direction, the film height at the contact interface between the protruding structure and the conductive pillar 1411 is different from the film height of the first conductive layer 1412, for example, the film height at the contact interface is lower than the film height of the first conductive layer 1412.

[0091] In some embodiments, the method of forming the semiconductor layer 111 includes: referring to Figure 12 As shown, a semiconductor material layer 1101 is formed on the inner wall of the first trench 12 and the inner wall of the opening (first opening 13); the semiconductor material layer 1101 can cover the side surface of the wall structure 120 away from the first electrode 141 along the z-direction; refer to Figure 13 As shown, a semiconductor material layer 1101 extends through the bottom of the first trench 12 along the z-direction, and a semiconductor material layer 1101 is retained in the opening to form a semiconductor layer 111.

[0092] In some embodiments, the method of forming the semiconductor layer 111 includes: referring to Figure 13 As shown, when penetrating the semiconductor material layer 1101, the residual portion of the semiconductor material layer 1101 forms a protrusion 1114; wherein, the protrusion structure 1113 includes: a main body 1115 and a first portion 1116 disposed opposite to each other on two sidewalls of the opening (first opening 13) in the x direction, and a second portion 1117 at the bottom of the opening (first opening 13); the main body 1115 is close to the wall structure 120, and the protrusion 1114 is located outside the opening (first opening 13) and extends in a direction away from the first portion 1116.

[0093] The portion of the semiconductor layer 111 covering the second dielectric material layer along the z-direction can be retained to provide a larger area and a flatter contact surface for the subsequent bit line 114, reducing the contact gap between the bit line 114 and the semiconductor layer 111, improving device stability, and saving the process step of removing the semiconductor layer 111 to expose the wall structure 120, thus reducing manufacturing costs. When the semiconductor material layer 1101 penetrates the bottom of the first trench 12 along the z-direction, the remaining semiconductor material layer 1101 forms a protrusion 1114. The protrusion 1114 extends away from the first dielectric layer 121 along the x-direction. The protrusion 1114 can be coupled with the capacitor structure 140, increasing the contact area between the first end and the capacitor structure 140 and providing a flat contact surface, thereby improving coupling stability.

[0094] In some embodiments, a portion of the semiconductor layer 111 covering the second dielectric material layer along the z-direction can be removed, reducing electron migration between the semiconductor layers 111 on opposite sides of the same wall structure 120 in the x-direction and improving device stability. Exemplarily, the removal process may include etching and chemical mechanical polishing.

[0095] In some embodiments, reference Figure 14 As shown, the method for forming the first semiconductor structure 101 further includes: forming a gate dielectric layer 113 and a gate layer 112 on two sides of the wall structure 120 along the x-direction, wherein the gate dielectric layer 113 is located between the semiconductor layer 111 and the gate layer 112; the gate layer 112 extends along the y-direction and is located between two adjacent semiconductor layers 111 in the x-direction. (Refer to...) Figure 14 ,exist Figure 13 A gate dielectric layer 113 and a gate layer 112 are formed on the semiconductor layer 111 of the two sidewalls of the first trench 12 shown; the remaining space of the first trench 12 is filled with an insulating material to electrically isolate the adjacent gate layer 112 and the adjacent semiconductor layer 111, and to provide support.

[0096] In some embodiments, reference Figure 14 As shown, a portion of the gate dielectric layer 113 extends into the opening (first opening 13) and is surrounded by a protrusion structure 1113 on the inner wall of the opening (first opening 13). When the gate dielectric layer 113 is formed, a portion of the gate dielectric layer 113 relatively close to the first electrode 141 can fill the opening space of the protrusion structure 1113 to reduce voids.

[0097] The protrusion structure 1113 of the semiconductor layer 111 is formed based on the first opening 13 of the first electrode 141, and the protrusion structure 1113 may be formed based on the second opening 14 of the contact portion 150 between the first electrode 141 and the semiconductor layer 111.

[0098] In some embodiments, the method of forming the first semiconductor structure 101 further includes: referring to Figure 15 As shown, a contact portion 150 is formed between the two wall structures 120, and the contact portion 150 is coupled to the first electrode 141; the method for forming the semiconductor layer 111 includes: referring to Figure 15 As shown, a portion of the contact portion 150 away from the first electrode 141 is removed to form a second opening 14 with its opening direction facing the second end; the inner wall of the second opening 14 is formed by the contact portion 150; in reference Figure 16 As shown, a semiconductor layer 111 is formed on two sides of the wall structure 120 that are arranged opposite each other along a third direction, and on the inner wall of the second opening 14; the protrusion structure 1113 is located in the second opening 14 and is coupled to the contact portion 150. Figure 15 In this process, the third dielectric layer 131 may be formed on the sidewall of the first trench 12 after the contact portion 150 is formed.

[0099] In some embodiments, reference Figure 15 As shown, the contact portion 150 includes a conductive block 151 and a second conductive layer 152 surrounding the conductive block 151. The method of forming the second opening 14 includes removing a portion of the conductive block 151 near the end of the wall structure 120; wherein the sidewall of the second opening 14 exposes the second conductive layer 152, and the bottom of the second opening 14 exposes the conductive block 151. The contact portion 150 may include a single-layer conductive structure or a multi-layer conductive structure, such as including the conductive block 151 and the second conductive layer 152. The second conductive layer 152 is located between the conductive block 151 and the semiconductor layer 111, and can serve as a connecting layer to increase the adhesion between the conductive block 151 and the semiconductor layer 111, thereby reducing contact resistance. The conductive block 151 may include tungsten, and the second conductive layer 152 may include metal silicide or titanium nitride. (Refer to...) Figure 16 As shown, the sidewalls of the protruding structure 1113 extending along the z-direction are surrounded by the second conductive layer 152 and are coupled to each other; the bottom of the protruding structure 1113 along the x-direction is covered by the conductive block 151 along the z-direction and is coupled to each other. In the z-direction, the film height of the contact interface between the protruding structure and the conductive block 151 is different from the film height of the second conductive layer 152, such that the film height of the contact interface is lower than the film height of the second conductive layer 152.

[0100] In some embodiments, reference Figure 17 As shown, in Figure 16 A gate dielectric layer 113 and a gate layer 112 are formed on the semiconductor layers 111 on the two sidewalls of the first trench 12; the remaining space of the first trench 12 is filled with an insulating material to electrically isolate adjacent gates and adjacent semiconductor layers 111 and to provide support.

[0101] In some embodiments, reference Figure 18As shown, the method of forming the first semiconductor structure 101 further includes: forming a bit line 114 extending in the x direction on the side of the semiconductor layer 111 near the second end, the bit line 114 being coupled to the second end.

[0102] In some embodiments, reference Figure 18 As shown, the method for fabricating a semiconductor device further includes: bonding a second semiconductor structure 102 to the side of bit line 114 away from semiconductor layer 111, the second semiconductor structure 102 including peripheral circuitry 160. One bit line 114 is coupled to the second ends of multiple semiconductor layers 111. After forming the bit line 114, the second semiconductor structure 102 is bonded to the first semiconductor structure 101, and the second semiconductor structure 102 is used as a support to thin the surface of the first semiconductor structure 101 on the side away from semiconductor layer 111. After thinning, it can be... Figure 19 The first electrode 141 is exposed as shown. The thinning process may include, but is not limited to, etching, wheel grinding, chemical mechanical polishing, or any combination thereof.

[0103] Before bonding, the surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 each have a first bonding contact 115 and a second bonding contact 115, respectively, which respectively lead the electrical signals of the semiconductor structure to the surfaces to be bonded. The bonding contact 115 may include structures such as pads and conductive plugs. The surfaces to be bonded of the first semiconductor structure 101 and the second semiconductor structure 102 are bonded together, and the interface between the two surfaces is called the bonding interface. The first bonding contact and the second bonding contact contact and bond at the bonding interface to realize the electrical signal interconnection between the first semiconductor structure 101 and the second semiconductor structure 102. After bonding, the first bonding contact and the second bonding contact may not have a physical boundary and can be regarded as the bonding contact 115 in the figure. The bonding contact 115 penetrates the bonding interface. Taking the gate layer 112, bit line 114 and second electrode 143 as an example, the gate layer 112, bit line 114 and second electrode 143 can respectively lead out electrical signals to the bonding contact 115 and couple them with the peripheral circuit 160 through the contact structure.

[0104] In some embodiments, the method of forming a capacitor structure 140 further includes: forming a second electrode 143, forming a fourth dielectric layer 142 between the second electrode 143 and the first electrode 141, a portion of the fourth dielectric layer 142 extending along a first direction, and a portion of the second electrode 143 extending along the z-direction located between two adjacent first electrodes 141; and multiple capacitor structures 140 being coupled through the second electrode 143.

[0105] based on Figure 19 The structure shown has an opening formed between adjacent first electrodes 141, and a fourth dielectric layer 142 and a second electrode 143 formed within the opening. (Refer to...) Figure 7As shown, the first electrode 141 extends along the z-direction. The first electrode 141 and the second electrode 143 may include an air gap 144 to reduce stress concentration and thus reduce device deformation. A fourth dielectric layer 142 may surround the sidewall of the first electrode 141 and the end of the first electrode 141 not coupled to the first end. The second electrode 143 may surround the fourth dielectric layer 142. A portion of the fourth dielectric layer 142 may extend along the z-direction, a portion of the second electrode 143 extends along the z-direction and is located between two adjacent first electrodes 141, and another portion of the second electrode 143 extends along the x-direction and covers the fourth dielectric layer 142 along the z-direction. Multiple capacitor structures 140 may be coupled through the portion of the second electrode 143 extending along the x-direction. The portion of the second electrode 143 extending along the x-direction connects multiple capacitor structures 140 in series. The portion of the second electrode 143 extending along the x-direction may be used for grounding or to be subjected to other voltages (such as Vdd / 2). In some other embodiments, based on... Figure 19 The structure shown allows for the formation of an opening in the fourth dielectric layer 142 and the second electrode 143, which can be formed in the x-direction every two first electrodes 141. The resulting semiconductor device 100 can be configured as follows: Figure 20 As shown, there are two first electrodes 141 between two adjacent portions of the second electrode 143 extending along the z direction. A fourth dielectric layer 142 with an air gap can be disposed between the two first electrodes 141 to support the capacitor structure 140.

[0106] According to some aspects of embodiments of the present disclosure, a memory system is provided, including: a semiconductor device; and a memory controller coupled to and controlling the semiconductor device.

[0107] The semiconductor device described in this disclosure can be as follows: Figures 2 to 7 as well as Figure 20 As shown, the semiconductor device can be used as DRAM, or at least as a part of DRAM. Alternatively, refer to... Figure 21 As shown, this disclosure provides a memory system 202, including a memory device 204, including the aforementioned semiconductor device; and a memory controller 206, which is coupled to the memory device 204 and controls the memory device 204.

[0108] Reference Figure 21 As shown, this disclosure provides a system 200 including a host 208. The system 200 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 21As shown, system 200 may include host 208 and memory system 202, the memory system 202 having one or more memory devices 204 and memory controller 206. Host 208 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 208 may be configured to send data to or receive data from memory device 204.

[0109] According to some implementations, a memory controller 206 is coupled to a memory device 204 and a host 208, and is configured to control the memory device 204 to perform read, write, or refresh operations. The memory controller 206 can manage data stored in the memory device 204 and communicate with the host 208. The memory device 204 includes DRAM, or a package structure formed by stacking multiple DRAMs, such as an HBM or HMC package structure. The memory system 202 can serve as memory for the host 208 in system 200 or as a cache for system 200. In some specific examples, the memory system 202 can be used in conjunction with a solid-state drive (SSD) to improve read and write speeds. Currently, high-end SSD products often embed DRAM to improve product performance and random read / write speeds. For example, during file writing, especially small file writing, small files are processed by DRAM before being stored in flash memory, making SSD storage more efficient and faster. Flash memory includes non-volatile memory, including but not limited to 2D NAND memory or 3D NAND memory.

[0110] In other embodiments, reference is made to Figure 22 As shown, system 200 may consist only of host 208 and memory device 204 coupled thereto. The controller for controlling memory device 204 may be located inside host 208, such as a memory controller integrated in a central processing unit (CPU), or a southbridge or northbridge chip integrated on the motherboard of system 200. Memory device 204 may include, but is not limited to: DDR4 memory, DDR5 memory (double data rate synchronous dynamic random access memory), and low-power LPDDR5 memory (double data rate synchronous dynamic random access memory).

[0111] In some embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. Furthermore, the components shown or discussed may be directly or indirectly coupled to each other. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0112] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized in that, Includes a first semiconductor structure, the first semiconductor structure comprising: A transistor includes at least a semiconductor layer extending along a first direction and a gate layer extending along a second direction; the gate layer is located between two adjacent semiconductor layers in a third direction; the third direction intersects the second direction, and the plane formed by the third direction and the second direction intersects the first direction; The semiconductor layer has a first end and a second end disposed opposite to each other along the first direction; wherein the first end includes a protrusion structure, the protrusion structure comprising: A main body and a first portion extending along the first direction; and a second portion extending along the third direction, the second portion being located between the main body and the first portion.

2. The semiconductor device according to claim 1, characterized in that, The first end also includes: A protrusion is located on the side of the first portion away from the body, and the protrusion extends in a direction away from the first portion.

3. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A capacitor structure includes a first electrode extending along the first direction, the first electrode being coupled to the first end; The first end extends into the first electrode, and the first end is surrounded by the first electrode.

4. The semiconductor device according to claim 3, characterized in that, The first electrode includes a conductive post and a first conductive layer surrounding the conductive post; the first end covers and contacts the surface of the conductive post on one side of the conductive post in the first direction, and the first end is surrounded by the first conductive layer.

5. The semiconductor device according to claim 3, characterized in that, The first semiconductor structure further includes: A contact portion is located between the first end and the first electrode; one side of the contact portion is coupled to the first electrode, and the other side is coupled to the first end; the first end extends into the contact portion, and the first end is surrounded by the contact portion.

6. The semiconductor device according to claim 5, characterized in that, The contact portion includes: A conductive block and a second conductive layer surrounding the conductive block; the first end covers and contacts one side surface of the conductive block in the first direction, and the first end is surrounded by the second conductive layer.

7. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: A wall structure extending along the second direction; the semiconductor layer is located at least on two opposing sides of the wall structure in the third direction.

8. The semiconductor device according to claim 7, characterized in that, The size of the semiconductor layer in the first direction is smaller than the size of the wall structure in the first direction.

9. The semiconductor device according to claim 7, characterized in that, The wall structure includes: A first dielectric layer, a third conductive layer, and a second dielectric layer are stacked in the first direction; The first semiconductor structure further includes a third dielectric layer located between the semiconductor layer and the wall structure.

10. The semiconductor device according to claim 7, characterized in that, The semiconductor layer surrounds two opposing sides of the wall structure along the third direction and surrounds one side surface of the wall structure along the first direction; the semiconductor layer includes two first ends, the first ends exposing the other side surface of the wall structure along the first direction.

11. The semiconductor device according to claim 1, characterized in that, The semiconductor layer is composed of indium gallium zinc oxide (IGZO).

12. The semiconductor device according to claim 7, characterized in that, The gate layer is located on two opposite sides of the wall structure in the third direction; The first semiconductor structure further includes: A gate dielectric layer is located between the semiconductor layer and the gate layer.

13. The semiconductor device according to claim 12, characterized in that, A portion of the gate dielectric layer extends toward and is surrounded by the protrusion structure.

14. The semiconductor device according to claim 3, characterized in that, The capacitor structure also includes: A fourth dielectric layer and a second electrode, the fourth dielectric layer being located between the first electrode and the second electrode; a portion of the fourth dielectric layer extending along the first direction, and a portion of the second electrode extending along the first direction being located between two adjacent first electrodes; a plurality of the capacitor structures being coupled through the second electrode.

15. The semiconductor device according to claim 1, characterized in that, The first semiconductor structure further includes: Bit lines are located on the side of the semiconductor layer near the second end and are coupled to the second end; the bit lines extend along the third direction.

16. The semiconductor device according to claim 15, characterized in that, The semiconductor device further includes: A second semiconductor structure is located on the side of the bit line away from the semiconductor layer; the second semiconductor structure includes peripheral circuitry and is bonded to the first semiconductor structure.

17. A method for fabricating a semiconductor device, characterized in that, The method for forming the first semiconductor structure includes: At least a first electrode forming a capacitor structure, the first electrode extending along a first direction; A wall structure is formed on one side of the first electrode along the first direction, and the wall structure extends along the second direction; An opening is formed in the exposed area between two adjacent wall structures; A semiconductor layer is formed on two opposing sides of the wall structure along a third direction and on the inner wall of the opening; the semiconductor layer has a first end and a second end opposite to each other in a first direction; wherein the first end includes a protrusion structure located in the opening, the opening of the protrusion structure facing the second end; the second direction intersects the third direction, and the plane formed by the second direction and the third direction intersects the first direction.

18. The manufacturing method according to claim 17, characterized in that, The first electrode is exposed in the area between two adjacent wall structures; The method of forming the semiconductor layer includes: Remove a portion of the first electrode near one end of the wall structure to form a first opening facing the second end; The inner wall of the first opening is formed by the first electrode; The semiconductor layer is formed on two opposing sides of the wall structure along the third direction and on the inner wall of the first opening; the protrusion structure is located in the first opening and coupled to the first electrode.

19. The manufacturing method according to claim 18, characterized in that, The first electrode includes a conductive post and a first conductive layer surrounding the conductive post; The method for forming the first opening includes: Remove a portion of the conductive post near one end of the wall structure; wherein the first conductive layer is exposed on the sidewall of the first opening, and the conductive post is exposed at the bottom of the first opening.

20. The manufacturing method according to claim 17, characterized in that, The method for forming the first semiconductor structure further includes: A contact portion is formed between two adjacent wall structures, and the contact portion is coupled to the first electrode; The method of forming the semiconductor layer includes: A portion of the contact portion away from the first electrode is removed to form a second opening facing the second end; the inner wall of the second opening is formed by the contact portion. The semiconductor layer is formed on two opposing sides of the wall structure along the third direction and on the inner wall of the second opening; the protrusion structure is located in the second opening and coupled to the contact portion.

21. The manufacturing method according to claim 20, characterized in that, The contact portion includes a conductive block and a second conductive layer surrounding the conductive block; The method of forming the second opening includes: Remove a portion of the conductive block near one end of the wall structure; wherein the sidewall of the second opening exposes the second conductive layer, and the bottom of the second opening exposes the conductive block.

22. The manufacturing method according to claim 17, characterized in that, The method of forming the wall structure includes: A first dielectric layer, a third conductive layer, and a second dielectric layer are formed on one side of the first electrode and stacked along the first direction. A first trench is formed that penetrates the first dielectric layer, the third conductive layer, and the second dielectric layer and extends along the second direction; the opening is formed using the first trench. The method for forming the first semiconductor structure further includes: A third dielectric layer is formed between the semiconductor layer and the wall structure.

23. The manufacturing method according to claim 22, characterized in that, The method of forming the semiconductor layer includes: A semiconductor material layer is formed on the inner wall of the first trench and the inner wall of the opening; the semiconductor material layer covers the surface of the wall structure away from the first electrode along the first direction; The semiconductor material layer extends through the bottom of the first trench along the first direction, retaining the semiconductor material layer in the opening to form the semiconductor layer.

24. The manufacturing method according to claim 23, characterized in that, The method of forming the semiconductor layer includes: When penetrating the semiconductor material layer, the residual portion of the semiconductor material layer forms a protrusion; wherein the protrusion structure includes: a main body and a first portion on two sidewalls disposed opposite to each other along the third direction of the opening, and a second portion at the bottom of the opening; the main body is close to the wall structure, and the protrusion is located outside the opening and extends in a direction away from the first portion.

25. The manufacturing method according to claim 18, characterized in that, The method for forming the first semiconductor structure further includes: A gate dielectric layer and a gate layer are formed on two sides of the wall structure along the third direction, the gate dielectric layer being located between the semiconductor layer and the gate layer; the gate layer extends along the second direction and is located between two adjacent semiconductor layers in the third direction.

26. The manufacturing method according to claim 25, characterized in that, A portion of the gate dielectric layer extends into the opening and is surrounded by the protruding structure on the inner wall of the opening.

27. The manufacturing method according to claim 25, characterized in that, The method for forming the first semiconductor structure further includes: A bit line extending in the third direction is formed on the side of the semiconductor layer near the second end, and the bit line is coupled to the second end.

28. The manufacturing method according to claim 27, characterized in that, The method for manufacturing the semiconductor device further includes: A second semiconductor structure, including peripheral circuitry, is bonded to the side of the bit line away from the semiconductor layer.

29. The manufacturing method according to claim 28, characterized in that, The method for forming the capacitor structure further includes: A second electrode is formed, and a fourth dielectric layer is formed between the second electrode and the first electrode. A portion of the fourth dielectric layer extends along the first direction, and a portion of the second electrode extending along the first direction is located between two adjacent first electrodes. The plurality of capacitor structures are coupled through the second electrode.

30. A memory system, characterized in that, include: The semiconductor device as described in any one of claims 1 to 16; And a memory controller, which is coupled to and controls the semiconductor device.

Images