Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which comprises a channel region and source and drain regions located at the two sides of the channel region, forming a channel laminated structure on the substrate, and enabling the channel laminated structure to comprise one or more channel laminated layers which are sequentially stacked in the longitudinal direction, the channel stack comprises a sacrificial layer and a channel layer located on the sacrificial layer, and a gate structure crossing the channel stack structure is formed on the substrate in the channel region; forming an epitaxial barrier layer in the sacrificial layer of the source-drain region; removing the channel lamination structure at the side part of the epitaxial barrier layer in the source-drain region, and forming a groove enclosed by the side wall of the channel lamination structure in the channel region, the side wall of the epitaxial barrier layer and the side wall of the channel layer below the epitaxial barrier layer; and forming source and drain doping layers in the groove, wherein the source and drain doping layers are sequentially stacked at intervals in the longitudinal direction. The contact resistance between the source-drain plug and the source-drain doping layer is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor transistors are evolving towards higher device density and higher integration, and semiconductor process nodes are continuously shrinking in accordance with Moore's Law. Transistors, as the most basic semiconductor material, are currently widely used. Therefore, as the device density and integration of semiconductor transistors increase, the channel length of transistors must be continuously shortened to adapt to the shrinking process nodes.

[0003] To better adapt to the requirement of proportionally shrinking transistor dimensions, semiconductor manufacturing processes have gradually transitioned from planar transistors to more efficient three-dimensional transistors, such as FinFETs and Gate-all-around (GAA) transistors. GAA transistors include vertical and horizontal types. In a GAA transistor, the gate surrounds the channel region from all sides. Compared to planar transistors, GAA transistors offer stronger control over the channel and better suppress short-channel effects.

[0004] As device size continues to shrink, improving the performance of fully enclosed gate structure devices becomes increasingly difficult and challenging. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to further improve the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate including a channel region and source / drain regions located on both sides thereof; a channel structure layer suspended on top of the substrate of the channel region, and the channel structure layer including one or more spaced-apart first channel layers; a device gate structure located on top of the substrate of the channel region and spanning the channel structure layer, the device gate structure surrounding the first channel layer; an epitaxial barrier layer located on top of the substrate of the source / drain region and extending in a direction perpendicular to the extension direction of the device gate structure, the epitaxial barrier layers being stacked at intervals in the longitudinal direction; and a second channel layer located on top of the substrate of the source / drain region, the second channel layer being located between adjacent epitaxial barrier layers and between the epitaxial barrier layer and the substrate. A trench, located in the source / drain region, is formed by the sidewalls of the channel structure layer of the channel region, the sidewalls of the device gate structure directly below the channel layer, the sidewalls of the epitaxial barrier layer, and the sidewalls of the second channel layer below the epitaxial barrier layer; a source / drain doped layer, located in the trench, wherein the source / drain doped layers are stacked and spaced apart in a longitudinal direction, and the source / drain doped layers are in contact with the first channel layer and the second channel layer; an interlayer dielectric layer, located on top of the substrate and covering the source / drain doped layers, the interlayer dielectric layer also covering the sidewalls of the device gate structure; a source / drain plug, located on top of the substrate in the source / drain region and penetrating the interlayer dielectric layer through the top and sidewalls of the source / drain doped layers, the source / drain plug surrounding and covering the source / drain doped layers, and the source / drain plug being electrically connected to the source / drain doped layers.

[0007] Optionally, the epitaxial barrier layer has a dimension of 3 nanometers to 10 nanometers in the extension direction of the device gate structure.

[0008] Optionally, the material of the epitaxial barrier layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

[0009] Optionally, the semiconductor structure further includes an inner sidewall layer located between the device gate structure and the source / drain doped layer directly below the source / drain doped layer.

[0010] Optionally, the material of the inner wall sidewall layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

[0011] Optionally, the device gate structure includes a gate dielectric layer surrounding the channel layer and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0012] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a channel region and source / drain regions located on both sides thereof, forming a channel stack structure on the substrate, the channel stack structure including one or more channel stacks sequentially stacked in a longitudinal direction, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and forming a gate structure across the channel stack structure on the substrate of the channel region, the gate structure covering a portion of the top and a portion of the sidewalls of the channel stack structure; along the... In the extending direction of the channel stack structure, an epitaxial barrier layer is formed in the sacrificial layer of the source / drain region, and the channel layer in the source / drain region exposes the epitaxial barrier layer; in the source / drain region, the channel stack structure on the side of the epitaxial barrier layer is removed to form a trench surrounded by the sidewall of the channel stack structure in the channel region, the sidewall of the epitaxial barrier layer, and the sidewall of the channel layer below the epitaxial barrier layer; a source / drain doped layer is formed in the trench, the source / drain doped layers are stacked and spaced apart in the longitudinal direction, and the source / drain doped layers are in contact with the channel layer.

[0013] Optionally, the step of forming the epitaxial barrier layer includes: in the source / drain region, with a direction perpendicular to the extension direction of the channel stack as a first direction, etching a portion of the sacrificial layer along the first direction to form a first groove, the first groove being surrounded by an adjacent channel layer and the sacrificial layer, or the first groove being surrounded by the substrate, the channel layer adjacent to the substrate, and the remaining sacrificial layer; and forming an epitaxial barrier layer in the first groove.

[0014] Optionally, the first direction is a direction perpendicular to the extension direction of the channel stack structure, and the size of the epitaxial barrier layer in the first direction is 3 nanometers to 10 nanometers.

[0015] Optionally, the material of the epitaxial barrier layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

[0016] Optionally, after forming the epitaxial barrier layer and before forming the trench, the method further includes: removing the topmost channel layer of the channel stack structure in the source / drain region to expose the top of the epitaxial barrier layer and the top of the sacrificial layer; the step of forming the trench includes: using the epitaxial barrier layer as a mask, etching away the channel stack structure on the side of the epitaxial barrier layer to form a trench surrounded by the sidewalls of the channel stack structure in the channel region, the sidewalls of the epitaxial barrier layer, and the sidewalls of the channel layer below the epitaxial barrier layer.

[0017] Optionally, in the step of forming the trench, the etching selectivity ratio between the trench stack structure and the epitaxial barrier layer is greater than 50:1.

[0018] Optionally, the process for forming the trench includes a dry etching process.

[0019] Optionally, after forming the trench and before forming the source / drain doped layer, the method further includes: etching a portion of the sacrificial layer exposed on the trench sidewall in the trench region, with a second direction perpendicular to the extension direction of the gate structure as the second direction, to form a second groove, the second groove being surrounded by an adjacent trench layer and the sacrificial layer, or the second groove being surrounded by the substrate, the trench layer adjacent to the substrate, and the remaining sacrificial layer; forming an inner wall sidewall layer in the second groove; and in the step of forming the source / drain doped layer, the source / drain doped layer is exposed on the inner wall sidewall layer.

[0020] Optionally, the material of the inner wall sidewall layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

[0021] Optionally, after forming the source / drain doped layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the source / drain doped layer on top of the substrate, the interlayer dielectric layer also covering the sidewalls of the gate structure; removing the gate structure and forming a gate opening in the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening and forming a via below the channel layer that communicates with the gate opening; forming a device gate structure in the gate opening and the via, the device gate structure surrounding the channel layer.

[0022] Optionally, after forming the gate structure of the device, the method for forming the semiconductor structure further includes: forming an opening in the interlayer dielectric layer of the source / drain region that exposes the source / drain doped layer, the opening being connected to the remaining space of the trench; forming a source / drain plug in the opening and the remaining space of the trench, the source / drain plug surrounding and covering the source / drain doped layer, and the source / drain plug being electrically connected to the source / drain doped layer.

[0023] Optionally, in the step of forming the device gate structure, the device gate structure includes a gate dielectric layer surrounding the channel layer and a gate electrode layer covering the gate dielectric layer; the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] This invention provides a method for forming a semiconductor structure. Along the extension direction of the channel stack structure, an epitaxial barrier layer is formed in the sacrificial layer of the source / drain region, and the channel layer in the source / drain region exposes the epitaxial barrier layer. During the subsequent formation of the source / drain doped layer in the trench, the source / drain doped layer is less likely to grow on the sidewalls of the epitaxial barrier layer, allowing it to grow only on the sidewalls of the channel layer. Since the channel layer is located above the sacrificial layer, it also means that the channel layer is located above the epitaxial barrier layer. Accordingly, during the formation of the source / drain doped layer, it grows only on the sidewalls of the channel layer. The source / drain doped layer forms a contact layer with the epitaxial barrier layer, while the source / drain doped layer does not grow on the sidewalls of the epitaxial barrier layer. This allows the source / drain doped layer to be suspended above the substrate. When the channel stack structure has multiple channel stacks arranged sequentially in the longitudinal direction, the source / drain doped layers are also arranged sequentially and spaced apart in the longitudinal direction. During the subsequent formation of the source / drain plug, the source / drain plug can surround and cover the source / drain doped layer, thereby increasing the contact area between the source / drain plug and the source / drain doped layer, reducing the contact resistance between the source / drain plug and the source / drain doped layer, and thus improving the performance of the semiconductor structure. Attached Figure Description

[0026] Figures 1 to 3 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0027] Figures 4 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0028] The performance of current semiconductor structures needs improvement. Especially in gate-all-around (GAA) transistors, during the formation of the source / drain plug on top of the source / drain doped layer, the plug is only located at the top of the doped layer. This means the contact surface between the plug and the doped layer is only the bottom surface of the plug and the top surface of the doped layer, resulting in a very small contact area. Since the contact area is inversely proportional to the contact resistance, a small contact area easily leads to excessively high contact resistance, thus affecting the performance of the semiconductor structure.

[0029] To address the technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a channel region and source / drain regions located on both sides thereof, forming a channel stack structure on the substrate, the channel stack structure including one or more channel stacks sequentially stacked in a longitudinal direction, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, and forming a gate structure across the channel stack structure on the substrate of the channel region, the gate structure covering a portion of the top and a portion of the sidewalls of the channel stack structure; Along the extension direction of the channel stack structure, an epitaxial barrier layer is formed in the sacrificial layer of the source / drain region, and the channel layer in the source / drain region exposes the epitaxial barrier layer; in the source / drain region, the channel stack structure on the side of the epitaxial barrier layer is removed to form a trench surrounded by the sidewall of the channel stack structure in the channel region, the sidewall of the etch barrier layer, and the sidewall of the channel layer below the etch barrier layer; a source / drain doped layer is formed in the trench, the source / drain doped layers are stacked and spaced apart in the longitudinal direction, and the source / drain doped layers are in contact with the channel layer.

[0030] This invention provides a method for forming a semiconductor structure. Along the extension direction of the channel stack structure, an epitaxial barrier layer is formed in the sacrificial layer of the source / drain region, and the channel layer in the source / drain region exposes the epitaxial barrier layer. During the subsequent formation of the source / drain doped layer in the trench, the source / drain doped layer is less likely to grow on the sidewalls of the epitaxial barrier layer, allowing it to grow only on the sidewalls of the channel layer. Since the channel layer is located above the sacrificial layer, it also means that the channel layer is located above the epitaxial barrier layer. Accordingly, during the formation of the source / drain doped layer, it grows only on the sidewalls of the channel layer. The source / drain doped layer forms a contact layer with the epitaxial barrier layer, while the source / drain doped layer does not grow on the sidewalls of the epitaxial barrier layer. This allows the source / drain doped layer to be suspended above the substrate. When the channel stack structure has multiple channel stacks arranged sequentially in the longitudinal direction, the source / drain doped layers are also arranged sequentially and spaced apart in the longitudinal direction. During the subsequent formation of the source / drain plug, the source / drain plug can surround and cover the source / drain doped layer, thereby increasing the contact area between the source / drain plug and the source / drain doped layer, reducing the contact resistance between the source / drain plug and the source / drain doped layer, and thus improving the performance of the semiconductor structure.

[0031] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figures 1 to 3 This is a schematic diagram of a corresponding structure in one embodiment of the semiconductor structure of the present invention. Wherein, Figure 1 This is a top view of the semiconductor structure. Figure 2 yes Figure 1 Cross-sectional view along the AA direction. Figure 3 yes Figure 1 A cross-sectional view along the BB direction.

[0033] The semiconductor structure includes: a substrate 205, the substrate 205 including a channel region 200B and source / drain regions 200A located on both sides thereon; a channel structure layer 202, suspended on top of the substrate 205 of the channel region 200B, and the channel structure layer 202 including one or more spaced-apart first channel layers 2022; and a device gate structure 233, located on top of the substrate 205 of the channel region 200B and spanning the channel structure layer 202, the device gate structure 233 surrounding the first channel layer 200A. A first channel layer 2022; an epitaxial barrier layer 210, located on top of the substrate 205 of the source / drain region 200A and extending in a direction perpendicular to the extension direction of the device gate structure 233, the epitaxial barrier layers 210 being stacked at intervals in the longitudinal direction; a second channel layer 2023, located on top of the substrate 205 of the source / drain region 200A, and the second channel layer 2023 being located between adjacent epitaxial barrier layers 210 and between the epitaxial barrier layers 210 and the substrate 205; a trench, located at... In the source / drain region 200A, the trench is formed by the sidewalls of the channel structure layer 202 of the channel region 200B, the sidewalls of the device gate structure 233 directly below the channel layer, the sidewalls of the epitaxial barrier layer 210, and the sidewalls of the second channel layer 2023 below the epitaxial barrier layer 210; a source / drain doped layer 221 is located in the trench, and the source / drain doped layers 221 are stacked and spaced apart in the longitudinal direction, and the source / drain doped layers 221 are connected to the first channel layer 2022 and the second channel layer 2023. 023 phase contact; interlayer dielectric layer 230, located on top of the substrate 205 and covering the source / drain doped layer 221, the interlayer dielectric layer 230 also covering the sidewall of the device gate structure 233; source / drain plug 260, located on top of the substrate 205 of the source / drain region 200A and penetrating the interlayer dielectric layer 230 of the top and sidewall of the source / drain doped layer 221, the source / drain plug 260 surrounds and covers the source / drain doped layer 221, and the source / drain plug 260 is electrically connected to the source / drain doped layer 221.

[0034] It should be noted that by setting the source and drain doped layers 221 with stacked intervals in the trench of the source and drain region 200A, the source and drain plug 260 surrounds and covers the source and drain doped layers 221, thereby increasing the contact area between the source and drain plug 260 and the source and drain doped layers 221, reducing the contact resistance between the source and drain plug 260 and the source and drain doped layers 221, and thus improving the performance of the semiconductor structure.

[0035] Substrate 205 provides a process platform for forming gate-all-around (GAA) transistors.

[0036] In this embodiment, the substrate 205 is a three-dimensional substrate 205, which includes a substrate 200 and a protrusion 201 protruding from the substrate 200.

[0037] In this embodiment, the substrate 200 is a silicon substrate 200. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0038] The protrusion 201 exposes a portion of the substrate 200, thereby providing a process basis for forming the isolation layer 207.

[0039] In this embodiment, the protrusion 201 is made of the same material as the substrate 200, which is silicon. In other embodiments, the protrusion may also be made of semiconductor materials suitable for forming protrusions, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the protrusion may also be different from that of the substrate.

[0040] In this embodiment, the substrate 205 includes a channel region 200B and source / drain regions 200A located on both sides thereon.

[0041] Specifically, the channel region 200B is the region of the transistor used to form a conductive channel, and the source / drain region 200A is the region of the transistor used to form the source / drain doped layer 221.

[0042] The channel structure layer 202 is used as a conductive channel for transistors.

[0043] The channel structure layer 202 includes one or more first channel layers 2022 spaced apart.

[0044] In this embodiment, the channel structure layer 202 includes a plurality of spaced first channel layers 2022, and the stacking direction of the plurality of stacked first channel layers 2022 is perpendicular to the surface of the substrate 200.

[0045] In this embodiment, the channel structure layer 202 and the protrusion 201 are made of the same material, and the material of the channel structure layer 202 is silicon.

[0046] The device gate structure 233 is used to control the opening and closing of the conductive channel when the device is working.

[0047] Specifically, the device gate structure 233 is a metal gate structure.

[0048] In this embodiment, the device gate structure 233 includes a gate dielectric layer (not shown) surrounding the first channel layer 2022 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0049] As an example, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0050] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers a portion of the top, a portion of the sidewalls, and a portion of the bottom of the first channel layer 2022, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0051] The gate electrode layer is used for electrical connection with external structures.

[0052] In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0053] Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.

[0054] In this embodiment, the semiconductor structure further includes an isolation layer 207 located on the substrate 200 on the side of the protrusion 201, wherein the isolation layer 207 exposes the channel structure layer 202.

[0055] Specifically, the isolation layer 207 is used to isolate adjacent protrusions 201.

[0056] In this embodiment, the material of the isolation layer 207 is silicon oxide.

[0057] In this embodiment, the semiconductor structure further includes a sidewall 207 located on the sidewall of the device gate structure 233.

[0058] Specifically, the sidewall 207 is also used to protect the sidewall of the device gate structure 233.

[0059] In this embodiment, the sidewall 207 is a single-layer structure, and the material of the sidewall 207 is silicon nitride.

[0060] It should be noted that the size of the epitaxial barrier layer 210 in the extension direction of the device gate structure 233 should not be too large or too small. If the size of the epitaxial barrier layer 210 in the first direction is too large, during the formation of the trench, the size of the trench along the first direction will easily become too small. In the formation process of the source / drain doped layer 221, the process window for forming the source / drain doped layer 221 in the trench will become smaller, increasing the difficulty of forming the source / drain doped layer 221, thereby affecting the performance of the semiconductor structure. If the size of the epitaxial barrier layer 210 in the first direction is too small, the etching mask function of the epitaxial barrier layer 210 will be affected in the trench formation process, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the size of the epitaxial barrier layer 210 in the extension direction of the device gate structure 233 is 3 nanometers to 10 nanometers.

[0061] It should also be noted that the epitaxial barrier layers 210 are stacked and spaced apart in the vertical direction. During the formation of the source / drain doped layers 221, the source / drain doped layers 221 are also stacked and spaced apart in the vertical direction. During the formation of the source / drain plugs 260, the source / drain plugs 260 can surround and cover the source / drain doped layers 221, thereby increasing the contact area between the source / drain plugs 260 and the source / drain doped layers 221, reducing the contact resistance between the source / drain plugs 260 and the source / drain doped layers 221, and thus improving the performance of the semiconductor structure.

[0062] In this embodiment, the material of the epitaxial barrier layer 210 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

[0063] Silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials. In the process of forming the source / drain doped layer 221, the material forming the source / drain doped layer 221 is not easy to grow on the sidewall of the epitaxial barrier layer 210, thereby reducing the probability of adjacent source / drain doped layers 221 merging in the longitudinal direction. This allows the source / drain plug 260 to surround and cover the source / drain doped layer 221, increasing the contact area between the source / drain plug 260 and the source / drain doped layer 221.

[0064] During the formation of the source / drain doped layer 221, the second channel layer 2023 serves as the deposition interface for the source / drain doped layer 221, which facilitates the growth of the source / drain doped layer 221 on the second channel layer 2023. Meanwhile, in the semiconductor structure formation process, the second channel layer 2023 and the first channel layer 2022 are an integral structure, and the material of the second channel layer 2023 is the same as that of the first channel layer 2022.

[0065] In this embodiment, the second channel layer 2023 is located on top of the substrate 205 of the source / drain region 200A, and the second channel layer 2023 is located between adjacent epitaxial barrier layers 210 and between the epitaxial barrier layer 210 and the substrate 205.

[0066] In other words, the second channel layer 2023 is stacked at intervals in the longitudinal direction. In the formation process of the source / drain doped layer 221, the source / drain doped layer 221 is grown only on the sidewall of the second channel layer 2023, which makes the source / drain doped layer 221 stacked at intervals in the longitudinal direction. This increases the contact area between the source / drain plug 260 and the source / drain doped layer 221 and reduces the contact resistance between the source / drain doped layer 221 and the source / drain plug 260.

[0067] Specifically, the trench provides space for the source / drain doped layers 221.

[0068] In this embodiment, the semiconductor structure further includes an inner sidewall layer 220, located between the device gate structure 233 and the source / drain doped layer 221 directly below it.

[0069] It should be noted that the inner wall sidewall layer 220 is located between the source / drain plug 260 and the device gate structure 233. The inner wall sidewall layer 220 can isolate the source / drain plug 260 and the device gate structure 233, which helps to reduce the parasitic capacitance between the source / drain plug 260 and the device gate structure 233.

[0070] It should also be noted that during the formation of the source / drain doped layer 221, the material forming the source / drain doped layer 221 is not easy to grow on the sidewall of the inner wall sidewall layer 220, which can further reduce the probability of adjacent source / drain doped layers 221 contacting each other in the longitudinal direction, thereby increasing the contact area between the subsequently formed source / drain plug 260 and the source / drain doped layer 221.

[0071] Specifically, the lateral dimension of the inner sidewall layer 220 should not be too large or too small in the direction parallel to the substrate 205 and perpendicular to the extension direction of the device gate structure 233. If the lateral dimension of the inner sidewall layer 220 is too small, it may affect the electrical isolation function between the inner sidewall layer 220 and the source / drain plug 260 and the device gate structure 233, increasing the parasitic capacitance between the source / drain doped layer 221 and the device gate structure 233, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the inner sidewall layer 220 is too large, the process window for forming the device gate structure 233 will be too small during the formation of the device gate structure 233, increasing the difficulty of forming the device gate structure 233, thereby affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the inner sidewall layer 220 is 3 nanometers to 10 nanometers in the direction parallel to the substrate 205 and perpendicular to the extension direction of the gate structure.

[0072] In this embodiment, the material of the inner wall sidewall layer 220 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

[0073] Specifically, silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials. In the process of forming the source / drain doped layer 221, the material forming the source / drain doped layer 221 is not easy to grow on the sidewall of the inner wall sidewall layer 220, thereby reducing the probability of adjacent source / drain doped layers 221 merging in the longitudinal direction. This allows the source / drain plug 260 to surround and cover the source / drain doped layer 221, increasing the contact area between the source / drain plug 260 and the source / drain doped layer 221.

[0074] It should be noted that silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials that can provide electrical isolation between the device gate structure 233 and the source / drain plug 260.

[0075] It should be noted that the source and drain doped layers 221 are used as the source and drain regions of the transistor.

[0076] It should also be noted that the source and drain doped layers 221 are stacked sequentially and spaced apart in the vertical direction, so that the source and drain plug 260 can surround and cover the source and drain doped layers 221, which increases the contact area between the source and drain plug 260 and the source and drain doped layers 221, reduces the contact resistance between the source and drain plug 260 and the source and drain doped layers 221, and thus improves the performance of the semiconductor structure.

[0077] Specifically, the interlayer dielectric layer 230 is used to achieve electrical isolation of the source-drain plug 260.

[0078] In this embodiment, the material of the interlayer dielectric layer 230 is silicon oxide.

[0079] It should be noted that the source / drain plug 260 is used to electrically connect with the source / drain doped layer 221, thereby enabling the source / drain doped layer 221 to be electrically connected to the external circuit structure through the source / drain plug 260.

[0080] It should also be noted that the source / drain plug 260 surrounds and covers the source / drain doped layer 221, increasing the contact area between the source / drain plug 260 and the source / drain doped layer 221, thereby reducing the contact resistance between the source / drain plug 260 and the source / drain doped layer 221, and thus improving the performance of the semiconductor structure.

[0081] As an example, the source / drain plug 260 is made of tungsten. In other embodiments, the source / drain plug may also be made of ruthenium.

[0082] Figures 4 to 23 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0083] refer to Figures 4 to 6 ,in, Figure 4 It is a top view. Figure 5 yes Figure 4 Cross-sectional view along the AA direction. Figure 6 yes Figure 4 A cross-sectional view along the BB direction provides a substrate 105, the substrate 105 including a channel region 100B and source / drain regions 100A located on both sides thereon, a channel stack structure 104 formed on the substrate 105, the channel stack structure 104 including one or more channel stacks 102 sequentially stacked in the longitudinal direction, the channel stack 102 including a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021, a gate structure 103 is formed on the substrate 105 of the channel region 100B that spans the channel stack structure 104, the gate structure 103 covering part of the top and part of the sidewalls of the channel stack structure 104.

[0084] The substrate 105 is used to provide a process platform for forming gate-all-around (GAA) transistors.

[0085] In this embodiment, the substrate 105 is a three-dimensional substrate 105, which includes a substrate 100 and a protrusion 101 protruding from the substrate 100.

[0086] In this embodiment, the substrate 100 is a silicon substrate 100. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc., and the substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0087] The protrusion 101 exposes a portion of the substrate 100, thereby providing a process basis for forming the isolation layer.

[0088] In this embodiment, the protrusion 101 is made of the same material as the substrate 100, which is silicon. In other embodiments, the protrusion may also be made of semiconductor materials suitable for forming protrusions, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, and the material of the protrusion may also be different from that of the substrate.

[0089] In this embodiment, the channel stack 102 is located on top of the protrusion 101, and the extension direction of the channel stack 102 is the same as the extension direction of the protrusion 101.

[0090] In this embodiment, there are multiple channel stacks 102, and the stacking direction of the multiple stacked channel stacks 102 is perpendicular to the surface of the substrate 100.

[0091] Each of the channel stacks 102 includes a sacrificial layer 1021 and a channel layer 1022 located on the sacrificial layer 1021. The channel stacks 102 provide a process basis for the subsequent formation of the spaced-apart channel layers 1022. Specifically, the sacrificial layer 1021 supports the channel layers 1022, thereby providing a process basis for the subsequent realization of the spaced-apart channel layers 1022, and also occupying space for the formation of the subsequent device gate structure. The channel layers 1022 are used to provide a conductive channel that fully surrounds the gate transistor.

[0092] Correspondingly, when there are multiple channel stacks 102, there are also multiple channel layers 1022, and the multiple channel layers 1022 are spaced apart.

[0093] In this embodiment, taking the number of channel layers 1022 as an example, the multiple channel layers 1022 arranged at intervals constitute a channel structure layer. In other embodiments, the channel structure layer may also include only one channel layer.

[0094] In this embodiment, the channel layer 1022 is made of Si, and the sacrificial layer 1021 is made of SiGe. During the subsequent removal of the sacrificial layer 1021, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 1021 to SiGe and the material of the channel layer 1022 to Si, the impact of the sacrificial layer 1021 removal process on the channel layer 1022 can be effectively reduced, thereby improving the quality of the channel layer 1022 and thus contributing to improved device performance. In other embodiments, when forming a PMOS transistor, to improve the performance of the PMOS transistor, SiGe channel technology can be used, with the bumps and channel layer made of SiGe and the sacrificial layer made of Si.

[0095] In this embodiment, an isolation layer is also formed on the substrate 100 on the side of the protrusion 101, and the isolation layer exposes the channel stack 102.

[0096] The isolation layer is used to isolate adjacent protrusions 101.

[0097] In this embodiment, the material of the isolation layer is silicon oxide.

[0098] In this embodiment, the gate structure 103 is a pseudo-gate structure, and the gate structure 103 occupies the space for the subsequent formation of the device gate structure.

[0099] In this embodiment, the gate structure 103 includes a dummy gate layer. The material of the dummy gate layer includes polysilicon.

[0100] In this embodiment, after forming the gate structure 103, the method for forming the semiconductor structure further includes forming a sidewall 107 on the sidewall of the gate structure 103.

[0101] The sidewall 107 is used as an etching mask for subsequent etching processes to define the formation region of the source and drain doped layers. The sidewall 107 is also used to protect the sidewall of the gate structure 103.

[0102] In this embodiment, the sidewall 107 is a single-layer structure, and the material of the sidewall 107 is silicon nitride.

[0103] In this embodiment, the substrate 105 includes a channel region 100B and source / drain regions 100A located on both sides thereon.

[0104] Specifically, the channel region 100B is the region of the transistor used to form a conductive channel, and the source / drain region 100A is the region of the transistor used to form a source / drain doped layer.

[0105] refer to Figure 8 Along the extension direction of the channel stack structure 104, an epitaxial barrier layer 110 is formed in the sacrificial layer 1021 of the source / drain region 100A, and the channel layer 1022 in the source / drain region 100A exposes the epitaxial barrier layer 110.

[0106] It should be noted that, along the extension direction of the channel stack structure 104, an epitaxial barrier layer 110 is formed in the sacrificial layer 1021 of the source / drain region 100A, and the channel layer 1022 in the source / drain region 100A exposes the epitaxial barrier layer 110. During the subsequent formation of the source / drain doped layer in the trench, the source / drain doped layer is less likely to grow on the sidewall of the epitaxial barrier layer 110, causing it to grow only on the sidewall of the channel layer 1022. Since the channel layer 1022 is located above the sacrificial layer 1021, it also means that the channel layer 1022 is located above the epitaxial barrier layer 110. Correspondingly, during the formation of the source / drain doped layer... In this process, source / drain doped layers are formed only on the sidewalls of the channel layer 1022, while no source / drain doped layers are grown on the sidewalls of the epitaxial barrier layer 110. This allows the source / drain doped layers to be suspended above the substrate 105. When the channel stack structure 104 has multiple channel stacks 102 arranged sequentially in the longitudinal direction, the source / drain doped layers are also arranged sequentially and spaced apart in the longitudinal direction. During the subsequent formation of the source / drain plug, the source / drain plug can surround and cover the source / drain doped layers, thereby increasing the contact area between the source / drain plug and the source / drain doped layers, reducing the contact resistance between the source / drain plug and the source / drain doped layers, and thus improving the performance of the semiconductor structure.

[0107] As an example, the step of forming the epitaxial barrier layer 110 includes: etching a portion of the sacrificial layer 1021 in the source / drain region 100A, with a first direction perpendicular to the extension direction of the channel stack structure 104 as a first direction, to form a first groove 109, wherein the first groove 109 is surrounded by adjacent channel layers 1022 and the sacrificial layer 1021, or the first groove 109 is surrounded by the substrate 105, the channel layer 1022 adjacent to the substrate 105, and the remaining sacrificial layer 1021; and forming the epitaxial barrier layer 110 in the first groove 109.

[0108] It should be noted that, taking the direction perpendicular to the extension direction of the channel stack structure 104 as the first direction, the size of the epitaxial barrier layer 110 in the first direction should not be too large or too small. If the size of the epitaxial barrier layer 110 in the first direction is too large, during the subsequent trench formation process, the size of the trench along the first direction will easily become too small, reducing the process window for forming the source / drain doped layer in the trench, increasing the difficulty of forming the source / drain doped layer, and thus affecting the performance of the semiconductor structure. If the size of the epitaxial barrier layer 110 in the first direction is too small, during the subsequent trench formation process, the etching mask function of the epitaxial barrier layer 110 will be affected, thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, taking the direction perpendicular to the extension direction of the channel stack structure 104 as the first direction, the size of the epitaxial barrier layer 110 in the first direction is 3 nanometers to 10 nanometers.

[0109] It should also be noted that the channel stack structure 104 has a plurality of channel stacks 102 stacked sequentially in the longitudinal direction. The channel stack 102 includes a sacrificial layer 1021 and a channel layer 1022 located on top of it. That is, the plurality of sacrificial layers 1021 are stacked and spaced apart in the longitudinal direction. Correspondingly, this also means that the epitaxial barrier layer 110 is stacked and spaced apart in the longitudinal direction. In the subsequent process of forming the source and drain doped layer, the source and drain doped layer is also stacked and spaced apart in the longitudinal direction. In the subsequent process of forming the source and drain plug, the source and drain plug can surround and cover the source and drain doped layer, thereby increasing the contact area between the source and drain plug and the source and drain doped layer, reducing the contact resistance between the source and drain plug and the source and drain doped layer, and thus improving the performance of the semiconductor structure.

[0110] In this embodiment, the material of the epitaxial barrier layer 110 includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

[0111] Silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials. In the subsequent process of forming source and drain doped layers, the material forming the source and drain doped layer is not easy to grow on the sidewall of the epitaxial barrier layer 110, thereby reducing the probability of adjacent source and drain doped layers merging in the vertical direction. This allows the subsequently formed source and drain plugs to surround and cover the source and drain doped layers, increasing the contact area between the source and drain plugs and the source and drain doped layers.

[0112] refer to Figures 9 and 10 In the source / drain region 100A, the topmost channel layer 1022 of the channel stack structure 104 is removed to expose the top of the epitaxial barrier layer 110 and the top of the sacrificial layer 1021.

[0113] It should be noted that removing the topmost channel layer 1022 of the channel stack structure 104 exposes the topmost epitaxial barrier layer 110. Accordingly, in the subsequent trench formation process, the etching selectivity between the epitaxial barrier layer 110 and the channel stack structure 104 can be used to make the epitaxial barrier layer 110 serve as an etching mask for forming the trench.

[0114] In this embodiment, the process of removing the topmost channel layer 1022 of the channel stack structure 104 includes a wet etching process.

[0115] refer to Figures 11 to 12 In the source / drain region 100A, the channel stack structure 104 on the side of the epitaxial barrier layer 110 is removed to form a trench 116 formed by the sidewall of the channel stack structure 104 in the channel region 100B, the sidewall of the epitaxial barrier layer 110, and the sidewall of the channel layer 1022 above the epitaxial barrier layer 110.

[0116] Specifically, trench 116 provides space for the subsequent formation of source and drain doped layers.

[0117] As an example, the step of forming the trench 116 includes: using the epitaxial barrier layer 110 as a mask, etching away the channel stack structure 104 on the side of the epitaxial barrier layer 110 to form a trench 116 surrounded by the sidewall of the channel stack structure 104 in the channel region 100B, the sidewall of the epitaxial barrier layer 110, and the sidewall of the channel layer 1022 below the epitaxial barrier layer 110.

[0118] In this embodiment, the process for forming the trench 116 includes a dry etching process.

[0119] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has better profile control, which is beneficial to improving the profile quality of the trench 116. Moreover, the dry etching process has high process controllability, which is beneficial to accurately control the depth of the trench 116. In addition, by selecting anisotropic dry etching process, it is beneficial to achieve a high etching selectivity, thereby reducing the probability of mis-etching other film layers.

[0120] It should be noted that in the step of forming the trench 116, the etching selectivity ratio between the channel stack structure 104 and the epitaxial barrier layer 110 should not be too small. If the etching selectivity ratio between the channel stack structure 104 and the epitaxial barrier layer 110 is too small, the etching rate of the channel stack structure 104 and the etching rate of the epitaxial barrier layer 110 will easily become close. Consequently, during the etching of the channel stack structure 104 using the epitaxial barrier layer 110 as an etching mask, the probability of the epitaxial barrier layer 110 also being etched away increases, affecting the etching mask function of the epitaxial barrier layer 110 and thus impacting the performance of the semiconductor structure. Therefore, in this embodiment, in the step of forming the trench 116, the etching selectivity ratio between the channel stack structure 104 and the epitaxial barrier layer 110 is greater than 50:1.

[0121] refer to Figures 13 to 14 In the channel region 100B, with the direction perpendicular to the extension direction of the gate structure 103 as the second direction, a portion of the sacrificial layer 1021 exposed on the sidewall of the trench 116 is etched along the second direction to form a second groove 118. The second groove 118 is surrounded by adjacent trench 116 layers and the sacrificial layer 1021, or the second groove 118 is surrounded by the substrate 105, the channel layer 1022 adjacent to the substrate 105, and the remaining sacrificial layer 1021; an inner wall sidewall layer 120 is formed in the second groove 118.

[0122] It should be noted that the second groove 118 provides space for the formation of the inner wall sidewall layer 120, so that the inner wall sidewall layer 120 is located between the subsequently formed source / drain plug and the device gate structure. The inner wall sidewall layer 120 can isolate the source / drain plug and the device gate structure, which helps to reduce the parasitic capacitance between the source / drain plug and the device gate structure.

[0123] It should also be noted that during the subsequent formation of the source / drain doped layer, the material forming the source / drain doped layer is not easy to grow on the sidewall of the inner wall sidewall layer 120, which can further reduce the probability of adjacent source / drain doped layers contacting each other in the longitudinal direction, thereby increasing the contact area between the subsequently formed source / drain plug and the source / drain doped layer.

[0124] Specifically, the lateral dimension of the inner sidewall layer 120 should not be too large or too small in the direction parallel to the substrate 105 and perpendicular to the extension direction of the gate structure 103. If the lateral dimension of the inner sidewall layer 120 is too small, it may affect the electrical isolation function between the inner sidewall layer 120 and the device gate structure, increasing the parasitic capacitance between the source / drain doped layer and the device gate structure, thereby affecting the performance of the semiconductor structure. If the lateral dimension of the inner sidewall layer 120 is too large, it may result in the size of the sacrificial layer 1021 in the channel region 100B being too small. Consequently, during the subsequent formation of the device gate structure, the process window for forming the device gate structure in the area occupied by the sacrificial layer 1021 will be too small, increasing the difficulty of forming the device gate structure and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the lateral dimension of the inner sidewall layer 120 is 3 nanometers to 10 nanometers in the direction parallel to the substrate 105 and perpendicular to the extension direction of the gate structure 103.

[0125] In this embodiment, the material of the inner wall sidewall layer 120 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

[0126] Specifically, silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials. In the subsequent process of forming the source and drain doped layers, the material forming the source and drain doped layers is not easy to grow on the sidewall of the inner sidewall layer 120, thereby reducing the probability of adjacent source and drain doped layers merging in the longitudinal direction. This allows the subsequently formed source and drain plugs to surround and cover the source and drain doped layers, increasing the contact area between the source and drain plugs and the source and drain doped layers.

[0127] It should be noted that silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride are all dielectric materials that can provide electrical isolation for the gate structure and source-drain plugs of the devices formed subsequently.

[0128] refer to Figures 15 to 16 Source and drain doped layers 121 are formed in the trench 116. The source and drain doped layers 121 are stacked and spaced apart in the longitudinal direction, and the source and drain doped layers 121 are in contact with the channel layer 1022.

[0129] It should be noted that the source and drain doped layers 121 are used as the source and drain regions of the transistor.

[0130] It should also be noted that the source and drain doped layers 121 are stacked sequentially and spaced apart in the vertical direction, so that the source and drain plugs formed subsequently can surround and cover the source and drain doped layers 121, which increases the contact area between the source and drain plugs and the source and drain doped layers 121, reduces the contact resistance between the source and drain plugs and the source and drain doped layers 121, and thus improves the performance of the semiconductor structure.

[0131] As an example, in the step of forming the source / drain doped layer 121, the source / drain doped layer 121 exposes the inner wall sidewall layer 120.

[0132] It should be noted that the source / drain doped layer 121 exposes the inner wall sidewall layer 120, which can leave the area on the side of the inner wall sidewall layer 120 empty, so that the source / drain plugs formed later can fill the empty area on the side of the inner wall sidewall layer 120.

[0133] In this embodiment, an epitaxial process is used to form a source / drain doped layer 121 in the trench 116.

[0134] refer to Figures 17 to 18 An interlayer dielectric layer 130 is formed on top of the substrate 105, covering the source / drain doped layer 121, and the interlayer dielectric layer 130 also covers the sidewall of the gate structure 103.

[0135] Specifically, the interlayer dielectric layer 130 is used to achieve electrical isolation of the subsequently formed source-drain plugs.

[0136] In this embodiment, the material of the interlayer dielectric layer 130 is silicon oxide.

[0137] In this embodiment, the step of forming the interlayer dielectric layer 130 includes: forming a dielectric material layer (not shown) on the substrate 105 of the sidewall of the gate structure 103, the dielectric material layer also covering the top of the gate structure 103; removing the dielectric material layer above the top of the gate structure 103, and the remaining dielectric material layer serving as the interlayer dielectric layer 130.

[0138] It should be noted that during the formation of the interlayer dielectric layer, due to the limited filling capacity of the deposition process, the interlayer dielectric layer did not fill the gap between the source and drain doped layers.

[0139] refer to Figure 19 Remove the gate structure 103 and form a gate opening 131 in the interlayer dielectric layer 130.

[0140] Specifically, the gate opening 131 provides a process window for the subsequent formation of the sacrificial layer 1021 and also provides a spatial location for the subsequent formation of the device gate structure.

[0141] In this embodiment, the process for removing the gate structure 103 includes a dry etching process.

[0142] refer to Figure 20 Remove the sacrificial layer 1021 exposed by the gate opening 131, and form a through groove 132 below the channel layer 1022 that communicates with the gate opening 131.

[0143] Specifically, the sacrificial layer 1021 is removed to form the through-slot 132, providing space for the subsequent formation of the device gate structure.

[0144] In this embodiment, the process of removing the sacrificial layer 1021 exposed by the gate opening 131 includes a wet etching process.

[0145] The sacrificial layer 1021 is removed after the source / drain doped layer 121 is formed. Therefore, after the sacrificial layer 1021 is removed, the two ends of the channel layer 1022 are connected to the source / drain doped layer 121 along the extension direction of the protrusion 101 and are suspended in the gate opening 131, thereby providing a basis for the subsequent device gate structure to surround the channel layer 1022.

[0146] After removing the sacrificial layer 1021, the channel layers 1022 are spaced apart, and the remaining channel layers 1022 constitute the channel structure layer (not shown). The channel structure layer is located on the protrusion 101 and is spaced apart from the protrusion 101.

[0147] refer to Figure 21 A device gate structure 133 is formed in the gate opening 131 and the through groove 132, and the device gate structure 133 surrounds the channel layer 1022.

[0148] The device gate structure 133 is used to control the opening and closing of the conductive channel when the device is working.

[0149] Specifically, the device gate structure 133 is a metal gate structure.

[0150] In this embodiment, the device gate structure 133 includes a gate dielectric layer (not shown) surrounding the channel layer 1022 and a gate electrode layer (not shown) covering the gate dielectric layer.

[0151] As an example, the material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0152] Specifically, the gate dielectric layer includes a gate oxide layer that conformally covers part of the top, part of the sidewalls, and part of the bottom of the conformally covered channel layer 1022, and a high-k gate dielectric layer that conformally covers the gate oxide layer. The high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide.

[0153] The gate electrode layer is used for subsequent electrical connection with external structures.

[0154] In this embodiment, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0155] Specifically, the gate electrode layer may include a work function layer and an electrode layer covering the work function layer, or the gate electrode layer may only include a work function layer.

[0156] refer to Figures 22 to 23 An opening (not shown) is formed in the interlayer dielectric layer 130 of the source / drain region 100A to expose the source / drain doped layer 121. The opening is connected to the remaining space of the trench 116. A source / drain plug 160 is formed in the opening and the remaining space of the trench 116. The source / drain plug 160 surrounds and covers the source / drain doped layer 121 and is electrically connected to the source / drain doped layer 121.

[0157] Specifically, the opening provides space for the formation of the source-drain plug 160.

[0158] In this embodiment, the process for forming the opening includes a dry etching process.

[0159] It should be noted that the source / drain plug 160 is used to electrically connect with the source / drain doped layer 121, thereby enabling the source / drain doped layer 121 to be electrically connected to the external circuit structure through the source / drain plug 160.

[0160] It should also be noted that the source / drain plug 160 surrounds and covers the source / drain doped layer 121, increasing the contact area between the source / drain plug 160 and the source / drain doped layer 121, thereby reducing the contact resistance between the source / drain plug 160 and the source / drain doped layer 121, and thus improving the performance of the semiconductor structure.

[0161] As an example, the source / drain plug 160 is made of tungsten. In other embodiments, the source / drain plug may also be made of ruthenium.

[0162] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a channel region and source / drain regions located on both sides thereof; A channel structure layer is suspended on top of a base in the channel region, and the channel structure layer includes one or more spaced-apart first channel layers; A device gate structure is located on top of the substrate in the channel region and spans the channel structure layer, the device gate structure surrounding and enclosing the first channel layer; An epitaxial barrier layer is located on top of the substrate of the source / drain region and extends in a direction perpendicular to the extension direction of the device gate structure; the epitaxial barrier layers are stacked at intervals in the longitudinal direction. The second channel layer is located on top of the substrate of the source / drain region, and the second channel layer is located between adjacent epitaxial barrier layers and between the epitaxial barrier layer and the substrate; The trench is located in the source / drain region and is formed by the sidewalls of the channel structure layer of the channel region, the sidewalls of the device gate structure directly below the channel layer, the sidewalls of the epitaxial barrier layer, and the sidewalls of the second channel layer above the epitaxial barrier layer. Source and drain doped layers are located in the trench, and the source and drain doped layers are stacked and spaced apart in the longitudinal direction, and the source and drain doped layers are in contact with the first channel layer and the second channel layer. An interlayer dielectric layer is located on top of the substrate and covers the source / drain doped layers. The interlayer dielectric layer also covers the sidewalls of the device gate structure. A source / drain plug is located on top of the substrate of the source / drain region and penetrates the interlayer dielectric layer of the top and sidewalls of the source / drain doped layer. The source / drain plug surrounds and covers the source / drain doped layer and is electrically connected to the source / drain doped layer.

2. The semiconductor structure as described in claim 1, characterized in that, The epitaxial barrier layer has a size of 3 nanometers to 10 nanometers in the extension direction of the device gate structure.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the epitaxial barrier layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes an inner sidewall layer located between the device gate structure and the source / drain doped layer directly below it.

5. The semiconductor structure as described in claim 4, characterized in that, The material of the inner wall sidewall layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

6. The semiconductor structure as described in claim 1, characterized in that, The device gate structure includes a gate dielectric layer surrounding the first channel layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a channel region and source / drain regions located on both sides thereon, a channel stack structure is formed on the substrate, the channel stack structure including one or more channel stacks sequentially stacked in a longitudinal direction, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer, a gate structure is formed on the substrate of the channel region that spans the channel stack structure, the gate structure covering a portion of the top and a portion of the sidewalls of the channel stack structure; Along the extension direction of the channel stack structure, an epitaxial barrier layer is formed in the sacrificial layer of the source / drain region, and the channel layer in the source / drain region exposes the epitaxial barrier layer. In the source / drain region, the channel stack structure on the side of the epitaxial barrier layer is removed to form a trench surrounded by the sidewall of the channel stack structure in the channel region, the sidewall of the epitaxial barrier layer, and the sidewall of the channel layer above the epitaxial barrier layer. Source and drain doped layers are formed in the trench, and the source and drain doped layers are stacked and spaced apart in the longitudinal direction, and the source and drain doped layers are in contact with the channel layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming the epitaxial barrier layer includes: in the source / drain region, with a direction perpendicular to the extension direction of the channel stack as a first direction, etching a portion of the sacrificial layer along the first direction to form a first groove, the first groove being surrounded by an adjacent channel layer and the sacrificial layer, or the first groove being surrounded by the substrate, the channel layer adjacent to the substrate, and the remaining sacrificial layer; An epitaxial barrier layer is formed in the first groove.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, With the direction perpendicular to the extension direction of the channel stack structure as the first direction, the size of the epitaxial barrier layer in the first direction is 3 nanometers to 10 nanometers.

10. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the epitaxial barrier layer includes one or more of silicon nitride, silicon oxide, silicon carbide, and silicon oxynitride.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the epitaxial barrier layer and before forming the trench, the method further includes: in the source / drain region, removing the topmost trench layer of the trench stack structure to expose the top of the epitaxial barrier layer and the top of the sacrificial layer; The step of forming the trench includes: using the epitaxial barrier layer as a mask, etching away the trench stack structure on the side of the epitaxial barrier layer to form a trench surrounded by the sidewall of the trench stack structure in the trench region, the sidewall of the epitaxial barrier layer, and the sidewall of the trench layer below the epitaxial barrier layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of forming the trench, the etching selectivity ratio between the trench stack structure and the epitaxial barrier layer is greater than 50:

1.

13. The method for forming a semiconductor structure as described in claim 7 or 11, characterized in that, The process for forming the trench includes a dry etching process.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the trench and before forming the source / drain doped layers, the method further includes: etching a portion of the sacrificial layer exposed on the trench sidewalls in the trench region, with a second direction perpendicular to the extension direction of the gate structure as the second direction, to form a second groove, the second groove being surrounded by adjacent trench layers and the sacrificial layer, or the second groove being surrounded by the substrate, the trench layer adjacent to the substrate, and the remaining sacrificial layer; forming an inner wall sidewall layer in the second groove; In the step of forming the source / drain doped layer, the source / drain doped layer is exposed to the inner wall sidewall layer.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the inner wall sidewall layer includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and silicon carbide.

16. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the source / drain doped layer, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the source / drain doped layer on top of the substrate, wherein the interlayer dielectric layer also covers the sidewalls of the gate structure; Remove the gate structure and form a gate opening in the interlayer dielectric layer; Remove the sacrificial layer exposed by the gate opening, and form a through trench below the channel layer that communicates with the gate opening; A device gate structure is formed in the gate opening and the through-slot, the device gate structure surrounding the channel layer.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, After forming the gate structure of the device, the method for forming the semiconductor structure further includes: forming an opening in the interlayer dielectric layer of the source-drain region to expose the source-drain doped layer, the opening being connected to the remaining space of the trench; forming a source-drain plug in the opening and the remaining space of the trench, the source-drain plug surrounding and covering the source-drain doped layer, and the source-drain plug being electrically connected to the source-drain doped layer.

18. The method for forming a semiconductor structure as described in claim 16, characterized in that, In the step of forming the device gate structure, the device gate structure includes a gate dielectric layer surrounding the channel layer and a gate electrode layer covering the gate dielectric layer; The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3; The material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

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