Vertical gate structure and manufacturing method thereof

Abstract

The invention provides a vertical gate structure and a manufacturing method thereof, and belongs to the field of semiconductors. The vertical gate structure manufacturing method comprises the following steps: providing a semiconductor substrate structure; and forming a groove, wherein the groove extends to the silicon oxide layer from the barrier layer. Forming a protective film on the side wall of the groove; and etching the substrate by taking the barrier layer as a mask to form a deep hole groove. And forming an oxide layer on the side wall of the deep hole groove. And removing the barrier layer. And depositing polycrystalline silicon on the surface of the oxide layer to form a vertical gate structure. According to the method, the protective film is formed on the side wall of the groove before the deep hole groove is formed, so that the side wall of the groove is more resistant to etching, the CD deviation is reduced, the problem that the CD deviation is increased along with the decrease of ADI CD can be solved, and the purpose of improving the etching process window of the vertical gate structure is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a vertical gate structure and its fabrication method. Background Technology

[0002] In the entire chip manufacturing process, the core step is pattern transfer during etching, which involves transferring the design pattern from the original layout onto the silicon wafer to form the target pattern. During pattern transfer, many intermediate patterns are generated, such as photomask patterns, ADI (After Develop Inspection) patterns, and AEI (After Etch Inspection) patterns, to assist in forming the target pattern. Due to the complexity of the manufacturing process and the unavoidable presence of defects, both these intermediate and target patterns require defect detection to ensure they do not contain logical errors such as bridges, open circuits, or short circuits when compared to the original design pattern.

[0003] The etched outline of the vertical gate structure determines the amount of charge a photodiode can store and its deep readout speed. By simulating the feature size of the vertical gate structure trench and reducing its feature size, the full-well capacity (FWC) and deep-substrate photoresponse (SP) performance of the photodiode can be optimized. However, as the feature size of the ADI pattern decreases, the deviation between the ADI pattern feature size (i.e., ADI CD) and the AEI pattern feature size (AEI CD) gradually increases. To ensure that the final feature size of the vertical gate structure reaches the set size, the ADI CD is reduced. However, if the ADI CD is too small, it leads to insufficient exposure windows for the vertical gate structure pattern, resulting in problems such as abnormal development.

[0004] It should be noted that the information disclosed in the background section of this invention is intended only to enhance the understanding of the general background of this invention, and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a method for fabricating a vertical gate structure and the fabrication method thereof, so as to solve the problem that insufficient process window for vertical gate structures will result when ADI CD is lower than the target value.

[0006] To solve the above technical problems, the present invention provides a method for fabricating a vertical gate structure, comprising:

[0007] A semiconductor substrate structure is provided, the semiconductor substrate structure including a substrate, a silicon oxide layer and a barrier layer sequentially formed on the surface of the substrate;

[0008] A trench is formed, the trench extending from the barrier layer to the silicon oxide layer;

[0009] A protective film is formed on the sidewall of the trench;

[0010] The substrate is etched using a barrier layer as a mask to form deep hole trenches;

[0011] An oxide layer is formed on the sidewall of the deep hole trench;

[0012] Remove the blocking layer;

[0013] Polycrystalline silicon is deposited on the surface of the oxide layer to form a vertical gate structure;

[0014] Preferably, forming a trench extending from the barrier layer to the silicon oxide layer includes:

[0015] A hard mask layer is formed on the surface of the barrier layer;

[0016] Photoresist is spin-coated onto the surface of the hard mask layer to form a photoresist layer;

[0017] The photoresist layer is exposed and developed to form a photolithographic pattern on the photoresist layer;

[0018] Using the photoresist layer as a mask, the hard mask layer is etched to transfer the photolithographic pattern to the hard mask layer;

[0019] The barrier layer is etched using the hard mask layer as a mask to form the trench.

[0020] Preferably, the hard mask layer includes, from the substrate upwards, an initial amorphous carbon hard mask layer, a nitrogen-free dielectric anti-reflective coating, a nitrogen-free dielectric anti-reflective coating, and a bottom anti-reflective layer;

[0021] Preferably, a steady-state etching process is used to etch the hard mask layer to transfer the photolithographic pattern to the hard mask layer.

[0022] Preferably, forming a protective membrane on the sidewall of the trench includes:

[0023] A protective film is formed on the inner wall of the trench using O2, SF6, and C4F8 gases. The flow rate of O2 is 15–20 sccm, the flow rate of SF6 is 15–20 sccm, the flow rate of C4F8 is 300–400 sccm, the plasma power is 1000–1200 W, the bias voltage of the instrument is 100–300 V, and the pressure is 30 mtorr.

[0024] Preferably, the Bosch process is used to etch the substrate using a barrier layer as a mask to form deep hole trenches.

[0025] Preferably, the etching of the substrate using the barrier layer as a mask to form deep hole trenches includes:

[0026] A deposition film was formed on the sidewall using O2, SF6 and C4F8, wherein the flow rate of O2 was 15-20 sccm, the flow rate of SF6 was 10-20 sccm, and the flow rate of C4F8 was 300-400 sccm.

[0027] The trench is cleaned by introducing SF6 gas into the machine, wherein the flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 100-200V.

[0028] The grooves are etched by introducing SF6 gas into the machine to form countersunk grooves. The flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 200-300V.

[0029] A protective layer is deposited on the inner wall of the deep hole trench by introducing C4F8 gas into the instrument. The flow rate of C4F8 gas is 200-300 sccm, the plasma power is 600-1000W, and the bias voltage of the instrument is 100-200V.

[0030] Preferably, forming an oxide layer on the sidewall of the deep hole trench includes:

[0031] O2 is introduced into the instrument to form an oxide layer on the surface of the protective layer. The flow rate of O2 gas is 100-200 sccm, the plasma power is 1000-1200 W, and the pressure is 30 mtorr.

[0032] Preferably, the barrier layer is removed by wet etching.

[0033] Based on the same inventive concept, the present invention also provides a vertical gate structure, which is fabricated using the vertical gate structure fabrication method described above.

[0034] Compared with the prior art, the vertical gate structure fabrication method of the present invention has the following advantages:

[0035] This invention provides a semiconductor substrate structure comprising a substrate, a silicon oxide layer and a barrier layer sequentially formed on the substrate surface. A trench is formed, extending from the barrier layer to the silicon oxide layer. A protective film is formed on the sidewalls of the trench. The substrate is etched using the barrier layer as a mask to form a deep-hole trench. An oxide layer is formed on the sidewalls of the deep-hole trench. The barrier layer is removed. Polysilicon is deposited on the surface of the protective layer to form a vertical gate structure. Therefore, the vertical gate structure fabrication method provided by this invention, by forming a protective film on the sidewalls of the trench before forming the deep-hole trench, makes the sidewalls of the trench more resistant to etching, reduces CD deviation, and solves the problem that CD deviation increases as the ADI CD decreases, thereby improving the etching process window for the vertical gate structure.

[0036] The vertical gate structure provided by this invention and the vertical gate structure fabrication method provided by this invention belong to the same inventive concept. Therefore, the vertical gate structure provided by this invention has at least all the advantages of the vertical gate structure fabrication method provided by this invention, and can solve the problem that the CD deviation increases as the ADI CD decreases, so as to improve the etching process window of the vertical gate structure. Attached Figure Description

[0037] Figure 1 This is one embodiment of different ADI CDs and their corresponding AEI CDs and slice graphics;

[0038] Figure 2 This is one implementation method for the influence of ADI CD on AEI CD and the trend of deviation between ADI CD and AEI CD;

[0039] Figure 3 This is a flowchart of a method for fabricating a vertical gate structure according to an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of a structure in which silicon oxide is formed on the surface of a substrate according to an embodiment of the present invention;

[0041] Figure 5 This is a schematic diagram of a structure in which a barrier layer and a hard mask layer are sequentially formed on the surface of the silicon oxide in one embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of a structure in which a photolithographic pattern is formed on the surface of a photoresist layer according to an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of the structure forming the trench in one embodiment of the present invention;

[0044] Figure 8 This is a schematic diagram of the structure for removing the initial amorphous carbon hard mask layer in one embodiment of the present invention;

[0045] Figure 9 This is a schematic diagram of a protective film formed in a trench according to an embodiment of the present invention;

[0046] Figure 10 This is a schematic diagram of a substrate being etched to form a deep hole trench in one embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of a structure for forming a protective film in a deep hole trench according to an embodiment of the present invention;

[0048] Figure 12 This is a schematic diagram of the structure for removing the blocking layer in one embodiment of the present invention;

[0049] Figure 13 This is a schematic diagram of a vertical gate structure formed by depositing polysilicon in a deep trench according to an embodiment of the present invention.

[0050] Figure 14 This is a slice image of AEI CD at 115nm and 80nm in one embodiment;

[0051] In the figure,

[0052] 100 - Substrate; 200 - Silicon oxide layer;

[0053] 300 - Barrier layer; 400 - Initial amorphous carbon hard mask layer;

[0054] 500 - Nitrogen-free dielectric anti-reflective coating; 600 - Carbon-doped silicon oxide;

[0055] 700 - Bottom anti-reflective layer; 800 - Photoresist layer;

[0056] 310 - Groove; 320 - Protective membrane;

[0057] 330 - Oxide layer; 410 - Deep hole trench;

[0058] 810 - Photolithography pattern. Detailed Implementation

[0059] To make the objectives, advantages, and features of the present invention clearer, the following further elaborates on the method for manufacturing a vertical gate structure and its manufacturing method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are in very simplified forms and are all in non-precise proportions, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present invention. It should be understood that the specific structures shown in the drawings of the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to explain certain principles of the present invention in the drawings of the specification will also adopt slightly simplified drawing methods. The specific design features of the present invention disclosed herein, such as specific dimensions, directions, positions, and shapes, will be partially determined by the specific application and usage environment. Also, in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to represent the same parts or parts with the same functions, and the repeated description thereof is omitted. In this specification, similar reference numerals and letters are used to represent similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0060] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.

[0061] In the description of this specification, the description referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0062] Refer Figure 1 and Figure 2 as shown, Figure 1 are the data of different ADI CD and corresponding AEI CD and their sliced images when the characteristic dimension (VTG CD) of the vertical gate structure is in the range of 80 nm to 120 nm. As can be seen from Figure 1 that the CD biases (CD Bias) after etching of different ADI CD are not the same, and their changing trends are as Figure 2 shown. As can be seen from Figure 2 It can be seen that as the CD aperture decreases, during ion bombardment etching, the vertical etching rate slows down due to the shorter free path of the ions, while the lateral etching rate increases, leading to an expansion of the final AEI CD. In other words, the CD bias gradually increases as the ADI CD shrinks. If the ADI CD is lower than the target value, it will result in insufficient process windows for the vertical gate structure, thereby reducing the yield of semiconductor devices.

[0063] The core idea of ​​this invention is to provide a method for fabricating a vertical gate structure that can solve the problem that CD deviation increases as ADICD decreases, thereby improving the etching process window of the vertical gate structure.

[0064] To achieve the above-mentioned goals, this invention provides a method for fabricating a vertical gate structure, as described above. Figures 3 to 14 A specific embodiment of the disclosed method for fabricating a vertical gate structure is described. This method includes the following steps S1 to S7.

[0065] Step S1: Provide a semiconductor substrate structure, the semiconductor substrate structure including at least a substrate 100, a silicon oxide layer 200 and a barrier layer 300 sequentially formed on the surface of the substrate 100.

[0066] Specifically, refer to Figures 3 to 6 As shown, a semiconductor substrate structure is provided, which includes at least a substrate 100, and a silicon oxide layer 200 and a barrier layer 300 forming the surface of the substrate 100. The silicon oxide layer 200 is made of silicon dioxide. The barrier layer 300 serves as an etching barrier layer and a hard mask layer for subsequent etching processes. The barrier layer 300 can be made of silicon nitride, silicon carbide, etc., and in this embodiment, silicon nitride is preferred as the material of the barrier layer 300.

[0067] Step S2: Forming a trench 310, the trench 310 extending from the barrier layer 300 to the silicon oxide layer 200.

[0068] Specifically, refer to Figures 3 to 8 As shown, the formation of trench 310, which extends from the barrier layer 300 to the silicon oxide layer 200, includes:

[0069] A hard mask layer is formed on the surface of the barrier layer 300. To improve etching accuracy, in addition to the barrier layer 300 as a hard mask layer, other hard mask layers are also formed on the surface of the barrier layer 300. From the substrate 100 upwards, the surface of the barrier layer 300 also has an initial amorphous carbon hard mask layer 400 (APF), a nitrogen-free dielectric antireflective coating 500 (DARC), a nitrogen-free carbon-doped silicon oxide 600 (e.g., SiCO), and a bottom antireflective layer 700 (BARC).

[0070] Photoresist is spin-coated onto the surface of the hard mask layer to form a photoresist layer 800. Photoresist is also spin-coated onto the surface of the bottom anti-reflective layer 700 to form a photoresist layer 800.

[0071] The photoresist layer 800 is exposed and developed to form a photolithographic pattern 810 on its surface. By exposing and developing the photoresist layer 800, the areas to be etched in the VTG are exposed, forming the photolithographic pattern 810. The photolithographic pattern 810 is the VTG pattern.

[0072] Using the photoresist layer 800 as a mask, the hard mask layer is etched to transfer the photolithographic pattern 810 to the hard mask layer. Because the VTG pattern is quite deep, it is difficult to complete the etching in one step. Therefore, in this step, a steady-state etching process is used to etch the hard mask layer to transfer the VTG pattern to the hard mask layer. First, the photoresist layer 800 is used as a barrier layer to transfer the VTG pattern to the hard mask layer. That is, the VTG pattern is transferred to the initial amorphous carbon hard mask layer 400.

[0073] The barrier layer 300 is etched using the hard mask layer as a mask to form the trench 310. The initial amorphous carbon hard mask layer 400 is used as a hard mask, and the barrier layer 300 is used to form the trench 310. The trench 310 extends to the silicon oxide layer 200.

[0074] Step S3: A protective film 320 is formed on the sidewall of the trench 310.

[0075] Specifically, refer to Figures 3 to 8 As shown, forming a protective film 320 on the sidewall of the trench 310 includes:

[0076] A semiconductor substrate structure is loaded into the instrument, and O2, SF6, and C4F8 gases are introduced into the instrument to form a protective film 320 on the inner wall of the trench 310. The flow rate of O2 is 15-20 sccm, the flow rate of SF6 is 15-20 sccm, the flow rate of C4F8 is 300-400 sccm, the plasma power is 1000-1200W, the bias voltage of the instrument is 100-300V, and the pressure is 30mtorr.

[0077] Step S4: Using the barrier layer 300 as a mask, the substrate 100 is etched to form a deep hole trench 410.

[0078] Specifically, refer to Figure 3 and Figure 10 As shown, Bosch process is used to etch the substrate 100 using the barrier layer 300 as a hard mask to form deep hole trenches 410.

[0079] The step of etching the substrate using the barrier layer 300 as a hard mask to form the deep hole trench 410 includes:

[0080] O2, SF6 and C4F8 were used to form a deposited film on the sidewall, wherein the flow rate of O2 was 15-20 sccm, the flow rate of SF6 was 10-20 sccm and the flow rate of C4F8 was 300-400 sccm.

[0081] The trench 310 is cleaned by introducing SF6 gas into the machine, wherein the flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 100-200V.

[0082] The groove 310 is etched by introducing SF6 gas into the machine to form a countersunk hole groove 410. The flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 200-300V.

[0083] A protective layer is deposited on the inner wall of the deep hole trench 410 using C4F8 gas introduced into the equipment. The C4F8 gas flow rate is 200–300 sccm, the plasma power is 600–1000 W, and the equipment bias voltage is 100–200 V. During deposition, C4F8 is dissociated by the plasma into a (CF2)n polymer, which is not reacted with SF6 during etching, thus forming the protective layer. The surface of the deep hole trench is then oxidized to repair the etched damage layer.

[0084] Step S5: An oxide layer 330 is formed on the sidewall of the deep hole trench 410.

[0085] Specifically, refer to Figure 3 and Figure 11 As shown, forming an oxide layer 330 on the sidewall of the deep hole trench 410 includes:

[0086] O2 is introduced into the instrument to form an oxide layer 330 on the surface of the protective layer. The flow rate of O2 gas is 100-200 sccm, the plasma power is 1000-1200 W, and the pressure is 30 mtorr. O2 reacts with the etched silicon surface to generate SiO2, which fills the physical damage caused by etching. In addition, it can also react with other residues and volatilize, thus achieving a cleaning effect.

[0087] Step S6: Remove the blocking layer 300.

[0088] Specifically, refer to Figure 3 and Figure 11As shown, the barrier layer 300 is removed by wet etching. The reagent for wet etching is a commonly used cleaning agent that can remove silicon nitride materials. For example, it can be hydrofluoric acid, sulfuric acid, etc. There are no special requirements for the cleaning agent of the barrier layer 300, as long as it can remove silicon nitride.

[0089] Step S7: Deposit polysilicon 900 on the surface of the oxide layer 330 to form a vertical gate structure.

[0090] Specifically, referring to Figure 3 and Figure 13 As shown, a polysilicon 900 deposition process is used on the surface of the oxide layer 330. For example, silane (SiH4) is introduced into the machine, and the silane thermally decomposes or thermally decomposes and deposits polysilicon 900 at a temperature of 580 - 650 degrees Celsius to form a vertical gate structure.

[0091] Referring to Figure 13 As shown, Figure 13 is the measured AEI CD data obtained by an electron scanning microscope during the fabrication of the vertical gate structure using the method provided in this embodiment. From Figure 13 it can be obtained that the CD of the vertical gate structure is 80nm and 115nm, meeting the development requirements, improving the process window of VTG pattern exposure, and thus improving the yield of the vertical gate structure.

[0092] In the development of the VTG 80nm deep hole, before forming the deep hole trench 410, a protective film is formed on the sidewall of the trench 310, making the sidewall of the trench 310 more resistant to etching, reducing the CD deviation, and enabling the ADI CD to increase from 65nm to 80nm. As a result, the CD of the vertical gate structure is 80nm, meeting the development requirements, improving the process window of VTG pattern exposure, and thus improving the yield of the vertical gate structure.

[0093] To achieve the above idea, this embodiment also provides a vertical gate structure, including:

[0094] It is fabricated using the method for fabricating a vertical gate structure as described above.

[0095] The vertical gate structure provided in this embodiment and the method for fabricating the vertical gate structure provided in this embodiment belong to the same inventive concept. Therefore, the vertical gate structure provided in this embodiment has at least all the advantages of the method for fabricating the vertical gate structure provided in this embodiment, can solve the problem that the CD deviation increases as the ADI CD becomes smaller, and aims to improve the etching process window of the vertical gate structure.

[0096] In summary, the above embodiments have provided a detailed description of the vertical gate structure fabrication method and its different configurations. Of course, the above description is only a description of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences from the above embodiments. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a vertical gate structure, characterized in that, include: A semiconductor substrate structure is provided, the semiconductor substrate structure including a substrate, a silicon oxide layer and a barrier layer sequentially formed on the surface of the substrate; A trench is formed, the trench extending from the barrier layer to the silicon oxide layer; A protective film is formed on the sidewall of the trench; The substrate is etched using a barrier layer as a mask to form deep hole trenches; An oxide layer is formed on the sidewall of the deep hole trench; Remove the blocking layer; Polycrystalline silicon is deposited on the surface of the oxide layer to form a vertical gate structure.

2. The method for fabricating a vertical gate structure according to claim 1, characterized in that, The formation of the trench, the trench extending from the barrier layer to the silicon oxide layer, includes: A hard mask layer is formed on the surface of the barrier layer; Photoresist is spin-coated onto the surface of the hard mask layer to form a photoresist layer; The photoresist layer is exposed and developed to form a photolithographic pattern on the photoresist layer; Using a photoresist layer as a mask, the hard mask layer is etched to transfer the photolithographic pattern to the hard mask layer; The barrier layer is etched using the hard mask layer as a mask to form the trench.

3. The method for fabricating a vertical gate structure according to claim 2, characterized in that, The hard mask layer, from the substrate upwards, includes an initial amorphous carbon hard mask layer, a nitrogen-free dielectric anti-reflective coating, a nitrogen-free dielectric anti-reflective coating, and a bottom anti-reflective layer.

4. The method for fabricating a vertical gate structure according to claim 2, characterized in that, The hard mask layer is etched using a steady-state etching process to transfer the photolithographic pattern to the hard mask layer.

5. The method for fabricating a vertical gate structure according to claim 1, characterized in that, The formation of a protective membrane on the sidewall of the trench includes: A protective film is formed on the inner wall of the trench using O2, SF6, and C4F8 gases. The flow rate of O2 is 15–20 sccm, the flow rate of SF6 is 15–20 sccm, the flow rate of C4F8 is 300–400 sccm, the plasma power is 1000–1200 W, the bias voltage of the instrument is 100–300 V, and the pressure is 30 mtorr.

6. The method for fabricating a vertical gate structure according to claim 1, characterized in that, Using Bosch's process, the substrate is etched with a barrier layer as a mask to form deep hole trenches.

7. The method for fabricating a vertical gate structure according to claim 6, characterized in that, The etching of the substrate using a barrier layer as a mask to form deep hole trenches includes: A deposition film was formed on the sidewall using O2, SF6 and C4F8, wherein the flow rate of O2 was 15-20 sccm, the flow rate of SF6 was 10-20 sccm, and the flow rate of C4F8 was 300-400 sccm. The trench is cleaned by introducing SF6 gas into the machine, wherein the flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 100-200V. The grooves are etched by introducing SF6 gas into the machine to form countersunk grooves. The flow rate of SF6 is 100-200 sccm, the plasma power is 400-600W, and the bias voltage of the machine is 200-300V. A protective layer is deposited on the inner wall of the deep hole trench by introducing C4F8 gas into the instrument. The flow rate of C4F8 gas is 200-300 sccm, the plasma power is 600-1000W, and the bias voltage of the instrument is 100-200V.

8. The method for fabricating a vertical gate structure according to claim 7, characterized in that, The formation of an oxide layer on the sidewall of the deep hole trench includes: O2 is introduced into the instrument to form an oxide layer on the surface of the protective layer. The flow rate of O2 gas is 100-200 sccm, the plasma power is 1000-1200 W, and the pressure is 30 mtorr.

9. The method for fabricating a vertical gate structure according to claim 1, characterized in that, The barrier layer was removed by wet etching.

10. A vertical gate structure, characterized in that, include: The vertical gate structure is fabricated using the fabrication method described in any one of claims 1-9.

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