Formation method of semiconductor structure
By forming a first through-channel and a second through-channel in the semiconductor structure and using a bottom isolation layer to support the channel bump structure, the problem of sacrificial layer residue is solved, and the performance and reliability of the semiconductor structure are improved.
Patent Information
- Application Number
- CN202410453757.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-15
- Publication Date
- 2025-10-28
AI Technical Summary
The performance of existing semiconductor structures still needs to be improved, especially since the sacrificial layer is prone to residue when it is removed, which affects the quality of the bottom isolation structure and the formation of the device gate structure.
During the semiconductor structure formation process, a first through-channel and a second through-channel are formed in the first and second regions of the channel protrusion structure, respectively. The first bottom isolation layer and the second bottom isolation layer are used to support the channel protrusion structure, reducing the probability of collapse. The residual sacrificial layer is reduced through protective layer and selective etching technology.
This improved the quality of the bottom isolation structure, reduced the probability of sacrificial layer residue, and enhanced the performance and reliability of the semiconductor structure.
Smart Images
Figure CN120857597A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a method for forming a semiconductor structure. Background Technology
[0002] With the rapid development of the integrated circuit (IC) industry, semiconductor technology, driven by Moore's Law, continues to advance towards smaller process nodes, enabling integrated circuits to develop in the direction of smaller size, higher circuit precision, and higher circuit complexity.
[0003] To better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually transitioned from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a GAA transistor, the gate surrounds the channel area from all sides. Compared to planar transistors, GAA transistors have stronger control over the channel and can better suppress short-channel effects.
[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention
[0005] The problem addressed by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0006] To address the aforementioned problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein one or more channel bump structures are formed on the substrate, the same channel bump structure including adjacent first and second regions along its extension direction, the channel bump structure including a first sacrificial layer on the substrate and a channel bump portion on the first sacrificial layer; removing the first sacrificial layer of the first region to form a first through-hole; forming a first bottom isolation layer in the first through-hole, the first bottom isolation layer being used to support the channel bump structure; under the support of the first bottom isolation layer, removing the first sacrificial layer of the second region to form a second through-hole; forming a second bottom isolation layer in the second through-hole, the second bottom isolation layer and the first bottom isolation layer constituting a bottom isolation structure.
[0007] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:
[0008] In the semiconductor structure formation method provided by the embodiments of the present invention, the same channel bump structure includes an adjacent first region and a second region along its extension direction. A first sacrificial layer of the first region is removed to form a first through-groove, and a first bottom isolation layer is formed in the first through-groove. Under the support of the first bottom isolation layer, the first sacrificial layer of the second region is removed to form a second through-groove. During the formation of the first through-groove, the first sacrificial layer of the second region can support the channel bump in the first region, reducing the probability of the channel bump structure in the first region collapsing. During the formation of the second through-groove, the first bottom isolation layer can support the channel bump in the second region, reducing the probability of the channel bump structure in the second region collapsing. Compared to the approach of removing the first sacrificial layer after the formation of the dummy gate structure, in the steps of removing the first sacrificial layer in the first region and the second region, the sidewalls of the first sacrificial layer are not covered by the dummy gate structure. This makes it easier to remove the first sacrificial layer, thereby reducing the probability of the first sacrificial layer remaining. This is beneficial to improving the quality of the bottom isolation structure. It also reduces the probability that the material corresponding to the device gate structure will be formed at the location where the first sacrificial layer material remains due to the removal of the residual first sacrificial layer in subsequent process steps, thus improving the performance of the semiconductor structure. Attached Figure Description
[0009] Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0010] Figures 10 to 29 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation
[0011] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example. Figures 1 to 9 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.
[0012] refer to Figures 1 to 3 A substrate 10 is provided, on which a channel protrusion structure 11 is formed. The channel protrusion structure 11 includes a first sacrificial layer 12 on the substrate 10 and a channel protrusion 13 on the first sacrificial layer 12. The channel protrusion 13 includes one or more channel stacks 14 stacked longitudinally. The channel stack 14 includes a second sacrificial layer 15 and a channel layer 16 on the second sacrificial layer 15. The top and sidewalls of the channel protrusion structure 11 are covered with a pseudo-gate dielectric layer 17.
[0013] in, Figure 1 This is a 3D diagram of a semiconductor structure. Figure 2 for Figure 1 Sectional view at AA1 Figure 3 for Figure 1 Sectional view at BB1.
[0014] Continue to refer to Figures 1 to 3 A pseudo-gate layer 18 is formed on the substrate 10 and the pseudo-gate dielectric layer 17, spanning the channel protrusion structure 11. The pseudo-gate layer 18 covers part of the top and part of the sidewalls of the channel protrusion structure 11. The pseudo-gate layer 18 and the pseudo-gate dielectric layer 17 at its bottom constitute a pseudo-gate structure (not shown).
[0015] refer to Figures 4 to 5 After the pseudo gate layer 18 is formed, the pseudo gate dielectric layer 17 exposed by the pseudo gate layer 18 is removed to expose the top and sidewalls of the channel protrusion structure 11 that are not covered by the pseudo gate layer 18.
[0016] in, Figure 4 for Figure 2 A cross-sectional view after removing the pseudo-gate layer and exposing the pseudo-gate dielectric layer. Figure 5 for Figure 3 Cross-sectional view after removing the pseudo-gate layer and exposing the pseudo-gate dielectric layer.
[0017] refer to Figures 6 to 7 The first sacrificial layer 12 is removed through the exposed sidewall of the first sacrificial layer 12 to form a through groove 20.
[0018] in, Figure 6 for Figure 4 Cross-sectional view after removing the first sacrificial layer Figure 7 for Figure 5 Sectional view after removing the first sacrificial layer.
[0019] refer to Figures 8 to 9 and in conjunction with references Figures 6 to 7 A bottom isolation structure 21 is formed in the through groove 20.
[0020] in, Figure 8 for Figure 6 A sectional view after the bottom isolation structure has been formed. Figure 9 for Figure 7 Cross-sectional view after the bottom isolation structure has been formed.
[0021] Research revealed that before removing the first sacrificial layer 12, a pseudo-gate layer 18 was formed across the channel protrusion structure 11. This pseudo-gate layer 18 covered part of the sidewall of the channel protrusion structure 11, making it easy for material corresponding to the first sacrificial layer 12 to remain at the bottom of the pseudo-gate layer 18 after the removal of the first sacrificial layer 12 (such as...). Figure 7 (As shown in the dashed box), this results in poor quality of the bottom isolation structure 21, which in turn affects the performance of the semiconductor structure; moreover, it also makes it easy for the residual first sacrificial layer 12 material to be removed during the subsequent removal of the second sacrificial layer 15, causing the material corresponding to the device gate structure to be formed at the location where the residual first sacrificial layer 12 material remains, which further affects the performance of the semiconductor structure.
[0022] To address the aforementioned technical problems, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein one or more channel bump structures are formed on the substrate, the same channel bump structure including adjacent first and second regions along its extension direction, the channel bump structure including a first sacrificial layer on the substrate and a channel bump portion on the first sacrificial layer; removing the first sacrificial layer of the first region to form a first through-hole; forming a first bottom isolation layer in the first through-hole, the first bottom isolation layer being used to support the channel bump structure; under the support of the first bottom isolation layer, removing the first sacrificial layer of the second region to form a second through-hole; forming a second bottom isolation layer in the second through-hole, the second bottom isolation layer and the first bottom isolation layer constituting a bottom isolation structure.
[0023] In the semiconductor structure formation method provided by the embodiments of the present invention, the same channel protrusion structure includes an adjacent first region and a second region along its extension direction. A first sacrificial layer of the first region is removed to form a first through-hole, and a first bottom isolation layer is formed in the first through-hole. Under the support of the first bottom isolation layer, the first sacrificial layer of the second region is removed to form a second through-hole. During the formation of the first through-hole, the first sacrificial layer of the second region can support the channel protrusion of the first region, reducing the probability of the channel protrusion of the first region collapsing. During the formation of the second through-hole, the first bottom isolation layer can support the channel protrusion of the second region, reducing the probability of the channel protrusion of the second region collapsing. Compared to the approach of removing the first sacrificial layer after the formation of the dummy gate structure, in the steps of removing the first sacrificial layer in the first region and the second region, the sidewalls of the first sacrificial layer are not covered by the dummy gate structure. This makes it easier to remove the first sacrificial layer, thereby reducing the probability of the first sacrificial layer remaining. This is beneficial to improving the quality of the bottom isolation structure. It also reduces the probability that the material corresponding to the device gate structure will be formed at the location where the first sacrificial layer material remains due to the removal of the residual first sacrificial layer in subsequent process steps, thus improving the performance of the semiconductor structure.
[0024] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0025] Figures 10 to 29 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.
[0026] refer to Figures 10 to 11 A substrate 100 is provided, on which one or more channel protrusion structures 110 are formed. The same channel protrusion structure 110 includes a first region I and a second region II adjacent to each other along its extension direction. The channel protrusion structure 110 includes a first sacrificial layer 111 located on the substrate 100 and a channel protrusion portion 112 located on the first sacrificial layer 111.
[0027] in, Figure 10 This is a top view. Figure 11 for Figure 10 Sectional view at CC1.
[0028] It should be noted that, in order to clearly show the semiconductor structure, Figure 10 The channel protrusions and the third sacrificial layer are omitted.
[0029] The substrate 100 provides a process platform for subsequent process fabrication. In this embodiment, the substrate 100 is used to form a field-effect transistor.
[0030] In this embodiment, in the step of providing the substrate 100, the substrate 100 includes a substrate 101 and a bottom fin 102 protruding from the substrate 101.
[0031] It should be noted that the substrate 101 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.
[0032] As an example, the substrate 101 and the bottom fin 102 are an integral structure.
[0033] Accordingly, in this embodiment, the channel protrusion structure 110 is located on the bottom fin 102.
[0034] During the process of removing the first sacrificial layer 111 of the first zone I to form the first through groove, the first sacrificial layer 111 of the second zone II can play the role of supporting the channel protrusion structure 110 of the first zone I, reducing the probability of the channel protrusion structure 110 of the first zone I collapsing.
[0035] In this embodiment, the same channel protrusion structure 110 includes multiple first regions I and multiple second regions II, and the first regions I and the second regions II are arranged alternately.
[0036] The same channel protrusion structure 110 includes multiple alternating first zones I and second zones II, which is beneficial to ensure that during the removal of the first sacrificial layer 111 of the first zone I, the first sacrificial layer 111 of the second zone II can provide support for the channel protrusion structure 110 of the first zone I at different positions. This helps to improve the uniformity of the support effect of the first sacrificial layer 111 of the second zone II on the channel protrusion structure 110 of the first zone I, and further reduces the probability of the channel protrusion structure 110 of the first zone I collapsing.
[0037] It should be noted that the area of the first region I should not be too small or too large compared to the sum of the areas of the first region I and the second region II. If the area of the first region I is too small compared to the sum of the areas of the first region I and the second region II, the subsequent formation of the first bottom isolation layer may result in poor support for the channel protrusion structure 110. If the area of the first region I is too large compared to the sum of the areas of the first region I and the second region II, the area of the second region II will be too small compared to the sum of the areas of the first region I and the second region II, resulting in poor support for the channel protrusion structure 110 of the first region I by the first sacrificial layer 111 in the second region II. Therefore, in this embodiment, the area of the first region I is 5% to 95% of the sum of the areas of the first region I and the second region II.
[0038] Understandably, when the difference between the area of the first region I and the area of the second region II is small, it is easier to achieve better uniformity in the support effect of the first sacrificial layer 111 in the second region II and the support effect of the subsequently formed first bottom isolation layer. As an example, the area of the first region I is 40% to 60% of the sum of the areas of the first region I and the second region II. In a specific embodiment, the area of the first region I is 50% of the sum of the areas of the first region I and the second region II.
[0039] The first sacrificial layer 111 is also used to reserve space for the subsequent formation of the bottom isolation layer.
[0040] In this embodiment, the material of the first sacrificial layer 111 is silicon germanide. As an example, the concentration of germanium in the first sacrificial layer 111 is 50%. In other embodiments, the first sacrificial layer may also be selected from other materials that have a removal selectivity ratio with respect to the material corresponding to the channel protrusion.
[0041] The protrusion 112 in the channel provides a technological basis for the subsequent formation of effective fins.
[0042] In this embodiment, during the step of providing the substrate 100, the channel protrusion 112 includes one or more channel stacks 115 stacked sequentially in the longitudinal direction. The channel stack 115 includes a second sacrificial layer 113 and a channel layer 114 located on the second sacrificial layer 113.
[0043] The channel stack 115 provides a process basis for the subsequent formation of the channel layer 114 with suspended space partitions.
[0044] Specifically, the channel layer 114 serves as the conductive channel of the field-effect transistor, and the second sacrificial layer 113 is used to support the channel layer 114, thereby providing a process basis for the subsequent implementation of the spaced floating arrangement of the channel layer 114. The second sacrificial layer 113 is also used to occupy space for the gate structure of the device to be formed later.
[0045] The material of the channel layer 114 can be one or more of silicon, germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide and indium gallium.
[0046] Specifically, the channel layer 114 is made of silicon, and the second sacrificial layer 113 is made of silicon germanide. During the subsequent removal of the second sacrificial layer 113, the etching selectivity of silicon germanide and silicon is relatively high. Therefore, by setting the material of the second sacrificial layer 113 to silicon germanide and the material of the channel layer 114 to silicon, the impact of the removal process of the second sacrificial layer 113 on the channel layer 114 can be reduced, thereby improving the quality of the channel layer 114 and consequently improving the performance of the semiconductor device. In other embodiments, the channel layer material may also be silicon germanide, and the sacrificial layer material may be silicon.
[0047] As an example, the first sacrificial layer 111 is made of silicon germanide with a germanium concentration of 50%. In order to achieve a removal selectivity ratio between the second sacrificial layer 113 and the first sacrificial layer 111, the second sacrificial layer 113 can be made of silicon germanide with a germanium concentration of 29%.
[0048] In this embodiment, the channel protrusion structure 110 further includes a third sacrificial layer 116 located between the first sacrificial layer 111 and the channel protrusion 112.
[0049] The third sacrificial layer 116 is used to protect the second sacrificial layer 113 during the removal of the first sacrificial layer 111.
[0050] As an example, the material of the third sacrificial layer 116 is silicon.
[0051] In this embodiment, after providing the substrate 100 and before forming the first through groove, the method further includes: forming a shallow trench isolation structure (STI) 120 on the substrate 101 on the side of the trench protrusion structure 110, the shallow trench isolation structure 120 surrounding and covering the sidewall of the bottom fin 102.
[0052] The shallow trench isolation structure 120 is used to isolate adjacent semiconductor devices to prevent leakage current between devices. Moreover, before forming the first through-slot, a shallow trench isolation structure 120 is formed around and covering the bottom fin 102, so that the shallow trench isolation structure 120 can provide some support for the channel protrusion structure 110 through the bottom fin 102, reducing the probability of the channel protrusion structure 110 tilting during the formation of the first through-slot.
[0053] In other embodiments, a shallow trench isolation structure may be formed after the bottom isolation structure is formed.
[0054] Specifically, the shallow trench isolation structure 120 is made of silicon oxide. In other embodiments, the shallow trench isolation structure may also be made of other insulating materials such as silicon nitride or silicon oxynitride.
[0055] refer to Figures 12 to 17 In this embodiment, after providing the substrate 100 and before forming the first through groove, the method further includes: forming a protective layer 130 in the second region II that covers the sidewalls and top of the channel protrusion structure 110.
[0056] in, Figure 12 for Figure 10 Top view after the protective material layer is formed. Figure 13 for Figure 12 Sectional view at CC1 Figure 14 for Figure 12 Top view after the mask structure is formed Figure 15 for Figure 14 Sectional view at CC1 Figure 16 for Figure 14 In the top view where the protective layer is formed, Figure 17 for Figure 16 Sectional view at CC1.
[0057] It should be noted that, in order to clearly show the semiconductor structure, Figure 12 , Figure 14 ,as well as Figure 16 The channel protrusions and the third sacrificial layer are omitted in the text. Figure 12 , Figure 13 , Figure 14 ,as well as Figure 15 The protective material layer on the base of the side of the channel protrusion structure is omitted. Figure 16 and Figure 17 The protective layer on the base of the side of the channel protrusion structure is omitted.
[0058] The protective layer 130 is used as a mask in the subsequent removal of the first sacrificial layer 111 in the first region I, thereby helping to reduce the impact of the process of removing the first sacrificial layer 111 in the first region I on the first sacrificial layer 111 in the second region II.
[0059] As an example, a protective layer 130 is formed after the shallow trench isolation structure 120 is formed. In other embodiments, the protective layer may be formed before the shallow trench isolation structure is formed.
[0060] Specifically, the material of the protective layer 130 includes one or more of silicon nitride, silicon oxide, and a low-k dielectric material, wherein the low-k dielectric material contains carbon and nitrogen elements. As an example, the material of the protective layer 130 is silicon nitride.
[0061] Low-K dielectric materials refer to dielectric materials with a relative permittivity of less than 3.9.
[0062] Silicon nitride, silicon oxide, and low-k dielectric materials containing carbon and nitrogen elements are advantageous for achieving a large removal selectivity between the protective layer 130 and the first sacrificial layer 111 material (e.g., silicon germanide). In other embodiments, the protective layer material may also be other materials suitable as masks.
[0063] It should be noted that, in the step of forming the protective layer 130, the thickness W1 of the protective layer 130 should not be too small or too large in the direction perpendicular to the extension direction of the channel protrusion structure 110. If the thickness W1 of the protective layer 130 is too small, the protective layer 130 may not function well as a mask; if the thickness W1 of the protective layer 130 is too large, it may increase the difficulty of subsequent removal of the protective layer 130. Therefore, in this embodiment, in the step of forming the protective layer 130, the thickness W1 of the protective layer 130 in the direction perpendicular to the extension direction of the channel protrusion structure 110 ranges from 10 angstroms to 50 angstroms.
[0064] In this embodiment, the step of forming the protective layer 130 includes: as follows Figures 12 to 13 As shown, a protective material layer 131 is formed on the sidewalls and top of the channel protrusion structure 110 in the first region I and the second region II. The protective material layer 131 is also formed on the base 100 on the side of the channel protrusion structure 110; as Figures 14 to 15 As shown, in the second region II, a mask structure 140 is formed that covers the protective material layer 131 and spans the channel protrusion structure 110; as Figures 16 to 17 As shown, using the mask structure 140 as a mask, the protective material layer 131 on the side of the mask structure 140 is removed to expose the sidewall of the first sacrificial layer 111 in the first region I, and the remaining protective material layer 131 serves as the protective layer 130; after forming the protective layer 130, the process also includes: removing the mask structure 140.
[0065] It is understandable that since a shallow trench isolation structure 120 was formed before the protective layer 130 was formed, the protective material layer 131 is also formed on the base 100 on the side of the trench protrusion structure 110, which means that the protective material layer 131 is formed on the shallow trench isolation structure 120 on the side of the trench protrusion structure 110.
[0066] After forming a protective material layer 131 on the sidewalls and top of the channel protrusion structure 110 in the first region I and the second region II, and on the base 100 on the side of the channel protrusion structure 110, a mask structure 140 covering the protective material layer 131 and spanning the channel protrusion structure 110 is first formed in the second region II. Then, using the mask structure 140 as a mask, the protective material layer 131 on the side of the mask structure 140 is removed, exposing the sidewall of the first sacrificial layer 111 in the first region I. This helps to reduce the difficulty of forming the protective layer 130 and improve the quality of the protective layer 130.
[0067] Specifically, the mask structure 140 can be a stacked structure; for example, it includes a spin-on carbon (SOC) layer, a low-temperature oxide (LTO) layer, and a photoresist (PR) layer stacked sequentially from bottom to top. The mask structure 140 can also be a single-layer structure; for example, it includes only a photoresist layer.
[0068] Accordingly, the process for removing the mask structure 140 includes one or both of ashing and wet cleaning processes. As an example, the mask structure 140 is subjected to ashing and wet cleaning processes in sequence to remove the mask structure 140 and reduce the probability that the material corresponding to the mask structure 140 remains on other film layers (e.g., the channel protrusion structure 110).
[0069] In this embodiment, the process for forming the protective material layer 131 includes one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the process for forming the protective material layer 131 includes ALD.
[0070] The film prepared by atomic layer deposition has advantages such as uniform film thickness and good step coverage, which helps to improve the uniformity of the thickness of the protective material layer 131 and the quality of the protective material layer 131.
[0071] In this embodiment, the protective material layer 131 on the side of the mask structure 140 is removed by using a free radical etching process. The process parameters of the free radical etching process include: the reaction gas includes a mixture of H2 and NF3, the volume ratio of H2 to NF3 is in the range of 1 to 20, the reaction temperature is in the range of 15 degrees Celsius to 80 degrees Celsius, the pressure of the reaction chamber is in the range of 300 mTorr to 1500 mTorr, the radio frequency power is in the range of 350 watts to 1000 watts, and the reaction time is in the range of 5 seconds to 250 seconds.
[0072] The free radical etching process facilitates a high etching selectivity between the etched object (i.e., the protective material layer 131) and other film layers (e.g., the mask structure 140).
[0073] By setting the volume ratio of each reactive gas, reaction temperature, radio frequency power, reaction chamber pressure, and reaction time within a reasonable range and coordinating them with each other in the free radical etching process, the etching target can achieve a high etching selectivity with other film layers, while improving etching efficiency and process stability, and reducing process costs and side effects.
[0074] refer to Figures 18 to 19 Remove the first sacrificial layer 111 of the first region I to form the first through groove 151.
[0075] in, Figure 18 for Figure 16 Top view after the first through slot is formed. Figure 19 for Figure 18 Sectional view at CC1.
[0076] It should be noted that, in order to clearly show the semiconductor structure, Figure 18 The text omits the trench protrusion, the third sacrificial layer, and the protective layer on the base of the trench protrusion structure. Figure 19 The protective layer on the base of the side of the channel protrusion structure is omitted.
[0077] The first channel 151 provides a process basis for the subsequent formation of the first bottom isolation layer.
[0078] Furthermore, during the formation of the first through groove 151, the first sacrificial layer 111 of the second region II can support the channel protrusion 112 of the first region I, reducing the probability of the channel protrusion structure 110 of the first region I collapsing. In the subsequent formation of the second through groove, the first bottom isolation layer formed in the first through groove 151 can support the channel protrusion 112 of the second region II, reducing the probability of the channel protrusion structure 110 of the second region II collapsing. Compared to the approach of removing the first sacrificial layer after the formation of the dummy gate structure, in the steps of removing the first sacrificial layer 111 in the first region I and the first sacrificial layer 111 in the second region II, the sidewalls of the first sacrificial layer 111 are not covered by the dummy gate structure. This makes it easier to remove the first sacrificial layer 111, thereby reducing the probability of the first sacrificial layer 111 remaining. This is beneficial to improving the quality of the subsequent bottom isolation structure. It also reduces the probability that the material corresponding to the device gate structure will be formed at the location where the first sacrificial layer 111 remains due to the removal of the remaining first sacrificial layer 111 in subsequent process steps, thus improving the performance of the semiconductor structure.
[0079] In this embodiment, using the protective layer 130 as a mask, the first sacrificial layer 111 of the first region I is removed along a direction perpendicular to the extension direction of the channel protrusion structure 110, that is, perpendicular to the sidewall of the channel protrusion structure 110, to form the first through groove 151.
[0080] Using the protective layer 130 as a mask to remove the first sacrificial layer 111 of the first region I is beneficial to reduce the probability of damage to the first sacrificial layer 111 of the second region II during the removal of the first sacrificial layer 111 of the first region I, thereby making the first sacrificial layer 111 of the second region II provide better support for the channel protrusion 112 of the first region I.
[0081] It should be noted that during the removal of the first sacrificial layer 111 in the first region I, the removal selectivity ratio between the first sacrificial layer 111 and the protective layer 130 should not be too small. If the removal selectivity ratio between the first sacrificial layer 111 and the protective layer 130 is too small, the effect of reducing the damage probability of the first sacrificial layer 111 in the second region II will be poor. Therefore, in this embodiment, during the removal of the first sacrificial layer 111 in the first region I, the removal selectivity ratio between the first sacrificial layer 111 and the protective layer 130 is greater than 15.
[0082] In this embodiment, a wet etching process is used to remove the first sacrificial layer 111 of the first region I.
[0083] Wet etching processes facilitate the achievement of a larger etching selectivity, which helps reduce the probability of damage to the channel protrusions 112.
[0084] Specifically, the process parameters of the wet etching process include: the etching solution is a mixture of a solution containing F ions and a H2O2 solution, wherein the volume percentage concentration of the H2O2 solution is greater than 1%, the solution temperature is 20 degrees Celsius to 50 degrees Celsius, and the process time is 10 seconds to 1800 seconds.
[0085] As an example, the F-ion-containing solution includes a mixture of ammonium fluoride solution, ammonium hydroxide solution, and acetic acid solution. In one specific embodiment, the mixture of ammonium fluoride solution, ammonium hydroxide solution, and acetic acid solution is composed of an ammonium fluoride solution with a mass percentage concentration of 5% to 15%, an ammonium hydroxide solution with a mass percentage concentration of less than or equal to 1%, and an acetic acid solution with a mass percentage concentration of 0.3% to 5%. In other embodiments, the etching solution may also include an SC1 solution, which refers to a mixture of aqueous ammonia solution and aqueous hydrogen peroxide solution.
[0086] It should be noted that the volume percentage concentration of the H2O2 solution should not be too low. If the volume percentage concentration of the H2O2 solution is too low, the etching rate will be too low, which is not conducive to improving process efficiency. Therefore, in this embodiment, the volume percentage concentration of the H2O2 solution is greater than 1%.
[0087] It should also be noted that the solution temperature should not be too low or too high. If the solution temperature is too low, the etching rate will be too low, which is not conducive to improving etching efficiency; if the solution temperature is too high, the etching selectivity will be poor, thereby increasing the probability of damage to other film layers (such as protective layer 130). Therefore, in this embodiment, the temperature of the etching solution is 20 degrees Celsius to 50 degrees Celsius.
[0088] It is also important to note that the process time should not be too short or too long. If the process time is too short, the probability of material residue corresponding to the first sacrificial layer 111 in the first region I is easily increased; if the process time is too long, the probability of damage to other film layers is easily increased. Therefore, in this embodiment, the process time is 10 seconds to 1800 seconds.
[0089] In other embodiments, a dry etching process can also be used to remove the first sacrificial layer in the first region.
[0090] In this embodiment, after forming the first through groove 151, the method further includes: removing a portion of the first sacrificial layer 111 in the second region II via the first through groove 151. This helps to reduce the probability of the material corresponding to the first sacrificial layer 111 remaining in the first through groove 151, thereby improving the quality of the subsequently formed first bottom sacrificial layer.
[0091] Accordingly, in this embodiment, after forming the first through groove 151, the method further includes: removing the protective layer 130.
[0092] refer to Figures 20 to 23 A first bottom isolation layer 156 is formed in the first channel 151, and the first bottom isolation layer 156 is used to support the channel protrusion structure 110.
[0093] in, Figure 20 for Figure 18 Top view after the first bottom insulating material is formed. Figure 21 for Figure 20 Sectional view at CC1 Figure 22 for Figure 20 Top view after the first bottom isolation layer has been formed. Figure 23 for Figure 22 Sectional view at CC1.
[0094] It should be noted that, in order to clearly show the semiconductor structure, Figure 20The text omits the trench protrusion, the third sacrificial layer, the protective layer on the base of the trench protrusion structure side, and the first bottom isolation material layer on the base of the trench protrusion structure side. Figure 21 The protective layer on the base of the side of the channel protrusion structure is omitted. Figure 22 The channel protrusions and the third sacrificial layer are omitted.
[0095] During the subsequent formation of the second channel, the first bottom isolation layer 156 can support the channel protrusion 112 of the second zone II, reducing the probability of the channel protrusion structure 110 of the second zone II collapsing.
[0096] As an example, the material of the first bottom isolation layer 156 includes one or more of silicon nitride, silicon oxide, and low-k dielectric materials. In other embodiments, the material of the first bottom isolation layer may also be other suitable dielectric materials.
[0097] In this embodiment, the process for forming the first bottom insulating layer 156 includes: as follows Figures 20 to 21 As shown, a first bottom insulating material layer 156' is formed in the first channel 151, and the first bottom insulating material layer 156' also covers the top and sidewalls of the channel protrusion structure 110, as well as the base 100 on the side of the channel protrusion structure 110; as Figures 22 to 23 As shown, the first bottom isolation material layer 156' located on the top and sidewalls of the channel protrusion structure 110 and on the base 100 located on the side of the channel protrusion structure 110 is removed, exposing the sidewall of the first sacrificial layer 111 of the second region II, and the remaining first bottom isolation material layer 156' serves as the first bottom isolation layer 156.
[0098] It is understood that the first bottom isolation material layer 156' also covers the base 100 on the side of the channel protrusion structure 110, which means that the first bottom isolation material layer 156' also covers the shallow trench isolation structure 120 on the side of the channel protrusion structure 110.
[0099] First, a first bottom isolation material layer 156' is formed in the first channel 151, on the top and side walls of the channel protrusion structure 110, and on the base 100 on the side of the channel protrusion structure 110. Then, the first bottom isolation material layer 156' located on the top and side walls of the channel protrusion structure 110 and on the base 100 on the side of the channel protrusion structure 110 is removed. The remaining first bottom isolation material layer 156' serves as the first bottom isolation layer 156, which helps to reduce the difficulty of forming the first bottom isolation layer 156.
[0100] Specifically, the process for forming the first bottom insulating material layer 156' includes one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the process for forming the first bottom insulating material layer 156' includes ALD.
[0101] Atomic layer deposition (ALD) has a high gap-filling capability, which is beneficial to improving the filling quality of the first bottom isolation material layer 156' in the first through groove 151 and reducing the probability of voids and other defects in the first bottom isolation material layer 156', thereby improving the quality of the first bottom isolation layer 156.
[0102] It should be noted that the process of removing the first bottom isolation material layer 156' located on the top and sidewalls of the trench protrusion structure 110 and on the substrate 100 located on the side of the trench protrusion structure 110 includes a wet etching process. The wet etching process has relatively low cost, simple operation steps, and can achieve a large etching selectivity.
[0103] In this embodiment, in the step of removing the first bottom isolation material layer 156' located on the top and sidewalls of the channel protrusion structure 110 and on the base 100 located on the side of the channel protrusion structure 110, a portion of the width of the first bottom isolation material layer 156' located in the first through groove 151 is also removed.
[0104] In the step of removing the first bottom isolation material layer 156' located on the top and sidewalls of the channel protrusion structure 110 and on the base 100 located on the side of the channel protrusion structure 110, a portion of the width of the first bottom isolation material layer 156' located in the first through groove 151 is also removed, which facilitates the exposure of the sidewalls of the first sacrificial layer 111 of the second region II, thereby reducing the difficulty of subsequently removing the first sacrificial layer 111 of the second region II.
[0105] It should be noted that the reference Figures 20 to 21 and in conjunction with references Figures 18 to 19 In the step of forming the first bottom isolation material layer 156', the proportion of the width W2 of the first bottom isolation material layer 156' located on the sidewall of the channel protrusion structure 110 to the height H1 of the first through groove 151 should not be too small. If the proportion of the width W2 of the first bottom isolation material layer 156' located on the sidewall of the channel protrusion structure 110 to the height H1 of the first through groove 151 is too small, it is easy to increase the probability that the first bottom isolation material layer 156' will not completely fill the first through groove 151, which will correspondingly make the quality of the first bottom isolation layer 156 poor. Therefore, in this embodiment, in the step of forming the first bottom isolation material layer 156', the width W2 of the first bottom isolation material layer 156' located on the sidewall of the channel protrusion structure 110 is greater than 50% of the height H1 of the first through groove 151;
[0106] In this embodiment, during the step of forming the first bottom isolation layer 156, the material of the first bottom isolation layer 156 is the same as the material of the protective layer 130. As an example, the material of the first bottom isolation layer 156 is silicon nitride.
[0107] The material of the first bottom insulating layer 156 is the same as that of the protective layer 130, which helps to reduce process costs. It can be understood that the material of the first bottom insulating layer 156 is the same as that of the protective layer 130, meaning the material of the first bottom insulating material layer 156 is the same as that of the protective layer 130.
[0108] As an example, in the step of removing the first bottom isolation material layer 156' located on the top and sidewalls of the channel protrusion structure 110, the protective layer 130 is removed.
[0109] In the step of removing the first bottom isolation material layer 156' located on the top and sidewalls of the channel protrusion structure 110, removing the protective layer 130 helps to simplify the process flow and improve process efficiency.
[0110] It should be noted that the reference Figures 22 to 23 and in conjunction with references Figures 18 to 19 In the step of forming the first bottom isolation layer 156, the proportion of the width W4 of the first bottom isolation layer 156 to the width W3 of the first through groove 151 should not be too small. If the proportion of the width W4 of the first bottom isolation layer 156 to the width W3 of the first through groove 151 is too small, the support effect of the first bottom isolation layer 156 on the channel protrusion 112 of the second region II will be poor. Therefore, in this embodiment, in the step of forming the first bottom isolation layer 156, the width W4 of the first bottom isolation layer 156 is greater than or equal to 50% of the width W3 of the first through groove 151.
[0111] refer to Figures 24 to 25 Remove the first sacrificial layer 111 of the second zone II to form the second through groove 152.
[0112] in, Figure 24 for Figure 22 Top view after the second through slot is formed. Figure 25 for Figure 24 Sectional view at CC1.
[0113] It should be noted that, in order to clearly show the semiconductor structure, Figure 24 The channel protrusions and the third sacrificial layer are omitted.
[0114] Since the first bottom isolation layer 156 is used to support the channel protrusion structure, removing the first sacrificial layer 111 of the second region II to form the second through groove 152 means that, under the support of the first bottom isolation layer 156, the first sacrificial layer 111 of the second region II is removed to form the second through groove 152.
[0115] The second channel 152 provides a process basis for the subsequent formation of the second bottom isolation layer.
[0116] Similar to the reason for removing the first sacrificial layer 111 of the first region I, in this embodiment, a wet etching process is used to remove the first sacrificial layer 111 of the second region II. The process parameters of the wet etching process include: the etching solution includes a mixed solution of a solution containing F ions and a H2O2 solution, wherein the volume percentage concentration of H2O2 is greater than 1%, the solution temperature is 20 degrees Celsius to 50 degrees Celsius, and the process time is 10 seconds to 1800 seconds.
[0117] As an example, the F-ion-containing solution includes a mixture of ammonium fluoride solution, ammonium hydroxide solution, and acetic acid solution. In one specific embodiment, the mixture of ammonium fluoride solution, ammonium hydroxide solution, and acetic acid solution is composed of an ammonium fluoride solution with a mass percentage concentration of 5% to 15%, an ammonium hydroxide solution with a mass percentage concentration of less than or equal to 1%, and an acetic acid solution with a mass percentage concentration of 0.3% to 5%. In other embodiments, the etching solution may also include an SC1 solution, which refers to a mixture of aqueous ammonia solution and aqueous hydrogen peroxide solution.
[0118] It should be noted that the specific description of the process for forming the second through groove 152 is similar to the process for removing the first sacrificial layer 111 of the first region I in the aforementioned embodiment, and can be referred to in conjunction with the corresponding description in the aforementioned embodiment, and will not be repeated here.
[0119] refer to Figures 26 to 29 A second bottom isolation layer 157 is formed in the second channel 152, and the second bottom isolation layer 157 and the first bottom isolation layer 156 constitute a bottom isolation structure 159.
[0120] in, Figure 26 for Figure 24 Top view after the second bottom isolation material layer is formed. Figure 27 for Figure 26 Sectional view at CC1 Figure 28 for Figure 26 Top view after the second bottom isolation layer is formed. Figure 29 for Figure 28 Sectional view at CC1.
[0121] It should be noted that, in order to clearly show the semiconductor structure, Figure 26The text omits the trench protrusion, the third sacrificial layer, and the second bottom isolation material layer on the base of the trench protrusion structure side. Figure 28 The channel protrusions and the third sacrificial layer are omitted.
[0122] Bottom Dielectric Isolation 159 is used to isolate the channel from the substrate 100, thereby reducing the probability of forming parasitic devices and correspondingly reducing the probability of leakage problems between the channel and the source / drain doped layers.
[0123] As an example, the material of the second bottom isolation layer 157 includes one or more of silicon nitride, silicon oxide, and low-k dielectric materials. In other embodiments, the material of the second bottom isolation layer may also be other suitable dielectric materials.
[0124] In this embodiment, the step of forming the second bottom insulating layer includes: as follows Figures 26 to 27 As shown, a second bottom insulating material layer 157' is formed in the second channel 152. The second bottom insulating material layer 157' also covers the top and sidewalls of the channel protrusion structure 110, the base 100 on the side of the channel protrusion structure 110, and the sidewalls of the first bottom insulating layer 156; Figures 28 to 29 As shown, the second bottom isolation material layer 157' located on the top and sidewalls of the channel protrusion structure 110 and on the base 100 located on the side of the channel protrusion structure 110 is removed, exposing the sidewalls of the channel protrusion structure 110, and the remaining second bottom isolation material layer 157' serves as the second bottom isolation layer 157.
[0125] It is understandable that the second bottom isolation material layer 157' also covers the base 100 on the side of the channel protrusion structure 110, which means that the second bottom isolation material layer 157' also covers the shallow trench isolation structure 120 on the side of the channel protrusion structure 110.
[0126] Specifically, the process for forming the second bottom insulating material layer 157' includes one or both of atomic layer deposition (ALD) and chemical vapor deposition (CVD). As an example, the process for forming the second bottom insulating material layer 157' includes ALD.
[0127] It should be noted that the process of removing the second bottom isolation material layer 157' located on the top and sidewalls of the trench protrusion structure 110 and on the substrate 100 located on the side of the trench protrusion structure 110 includes a wet etching process.
[0128] It should also be noted that, in the step of forming the second bottom isolation material layer 157', the width W5 of the second bottom isolation material layer 157' located on the side wall of the channel protrusion structure 110 is greater than 50% of the height H2 of the second through groove 152.
[0129] It should also be noted that the specific description of the process for forming the second bottom isolation layer 157 is similar to that for forming the first bottom isolation layer 156 in the aforementioned embodiments, and can be referred to in conjunction with the corresponding descriptions in the aforementioned embodiments, and will not be repeated here.
[0130] In this embodiment, in the step of forming the second bottom isolation layer 157, the material of the second bottom isolation layer 157 is the same as the material of the first bottom isolation layer 156. As an example, the material of the second bottom isolation layer 157 is silicon nitride.
[0131] In the step of forming the second bottom isolation layer 157, the material of the second bottom isolation layer 157 is the same as that of the first bottom isolation layer 156, which is beneficial to improving the adhesion between the second bottom isolation layer 157 and the first bottom isolation layer 156, thereby improving the quality of the bottom isolation structure 159.
[0132] It should be noted that in other embodiments, a shallow trench isolation structure may be formed after the bottom isolation structure is formed. That is, after forming the bottom isolation structure, the method further includes: forming a shallow trench isolation structure on the substrate on the side of the trench protrusion structure, the shallow trench isolation structure surrounding the sidewall covering the bottom fin and the sidewall covering the bottom isolation structure.
[0133] The subsequent steps will not be described again in this embodiment.
[0134] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which one or more channel protrusion structures are formed, the same channel protrusion structure including adjacent first and second regions along its extension direction, the channel protrusion structure including a first sacrificial layer on the substrate and a channel protrusion portion on the first sacrificial layer; Remove the first sacrificial layer in the first region to form the first through groove; A first bottom isolation layer is formed in the first through groove, and the first bottom isolation layer is used to support the channel protrusion structure; Remove the first sacrificial layer in the second region to form the second through groove; A second bottom isolation layer is formed in the second through groove, and the second bottom isolation layer and the first bottom isolation layer constitute a bottom isolation structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The same channel protrusion structure includes multiple first regions and multiple second regions, and the first regions and second regions are arranged alternately.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, After providing the substrate and before forming the first through groove, the method further includes: forming a protective layer in the second region that covers the sidewalls and top of the channel protrusion structure; Using the protective layer as a mask, the first sacrificial layer in the first region is removed along a direction perpendicular to the extension direction of the channel protrusion structure to form the first through groove; After forming the first through groove, the process also includes: removing the protective layer.
4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The steps for forming the protective layer include: A protective material layer is formed on the sidewalls and top of the channel protrusion structure in the first and second regions, and the protective material layer is also formed on the base of the side of the channel protrusion structure; In the second region, a mask structure is formed that covers the protective material layer and spans the channel protrusion structure; Using the mask structure as a mask, the protective material layer on the side of the mask structure is removed to expose the sidewall of the first sacrificial layer in the first region, and the remaining protective material layer serves as a protective layer. After forming the protective layer, the process further includes: removing the mask structure.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process for forming the protective material layer includes one or both of atomic layer deposition and chemical vapor deposition.
6. The method for forming a semiconductor structure as described in claim 4, characterized in that, The protective material layer on the side of the mask structure is removed by using a free radical etching process. The process parameters of the free radical etching process include: the reaction gas is a mixture of H2 and NF3, the volume ratio of H2 to NF3 is in the range of 1 to 20, the reaction temperature is in the range of 15 degrees Celsius to 80 degrees Celsius, the pressure of the reaction chamber is in the range of 300 mTorr to 1500 mTorr, the radio frequency power is in the range of 350 watts to 1000 watts, and the reaction time is in the range of 5 seconds to 250 seconds.
7. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the protective layer, the thickness of the protective layer ranges from 10 angstroms to 50 angstroms in a direction perpendicular to the extension direction of the channel protrusion structure.
8. The method for forming a semiconductor structure as described in claim 3, characterized in that, The protective layer is made of one or more of silicon nitride, silicon oxide, and low-K dielectric materials, wherein the low-K dielectric material contains carbon and nitrogen elements.
9. The method for forming a semiconductor structure as described in claim 3, characterized in that, In the step of forming the first bottom isolation layer, the material of the first bottom isolation layer is the same as the material of the protective layer.
10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the first bottom insulating layer includes: A first bottom isolation material layer is formed in the first channel, and the first bottom isolation material layer also covers the top and sidewalls of the channel protrusion structure, as well as the base of the side of the channel protrusion structure; Remove the first bottom isolation material layer located on the top and sidewalls of the channel protrusion structure and on the base located on the side of the channel protrusion structure to expose the sidewalls of the first sacrificial layer in the second region. The remaining first bottom isolation material layer serves as the first bottom isolation layer. The step of forming the second bottom insulating layer includes: A second bottom isolation material layer is formed in the second channel, and the second bottom isolation material layer also covers the top and sidewalls of the channel protrusion structure, the base of the side of the channel protrusion structure, and the sidewalls of the first bottom isolation layer; Remove the second bottom isolation material layer located on the top and sidewalls of the channel protrusion structure and on the base located on the side of the channel protrusion structure to expose the sidewalls of the channel protrusion structure, leaving the remaining second bottom isolation material layer as the second bottom isolation layer.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of removing the first bottom isolation material layer located on the top and sidewalls of the channel protrusion structure and on the base located on the side of the channel protrusion structure, a portion of the width of the first bottom isolation material layer located in the first through groove is also removed.
12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for removing the first bottom isolation material layer located on the top and sidewalls of the channel protrusion structure and on the substrate located on the side of the channel protrusion structure includes a wet etching process; the process for removing the second bottom isolation material layer located on the top and sidewalls of the channel protrusion structure and on the substrate located on the side of the channel protrusion structure includes a wet etching process.
13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for forming the first bottom isolation material layer includes one or both of atomic layer deposition and chemical vapor deposition; the process for forming the second bottom isolation material layer includes one or both of atomic layer deposition and chemical vapor deposition.
14. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of forming the first bottom isolation material layer, the width of the first bottom isolation material layer located on the sidewall of the channel protrusion structure is greater than 50% of the height of the first through groove; In the step of forming the second bottom isolation material layer, the width of the second bottom isolation material layer located on the sidewall of the channel protrusion structure is greater than 50% of the height of the second channel.
15. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, In the step of forming the first bottom isolation layer, the width of the first bottom isolation layer is greater than or equal to 50% of the width of the first through groove.
16. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, In the step of forming the second bottom isolation layer, the material of the second bottom isolation layer is the same as the material of the first bottom isolation layer.
17. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, The area of the first zone is 5% to 95% of the sum of the areas of the first and second zones.
18. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, The first sacrificial layer in the first region and the first sacrificial layer in the second region are removed by a wet etching process. The process parameters of the wet etching process include: the etching solution is a mixture of a solution containing F ions and a H2O2 solution, wherein the volume percentage concentration of the H2O2 solution is greater than 1%, the solution temperature is 20 degrees Celsius to 50 degrees Celsius, and the process time is 10 seconds to 1800 seconds.
19. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, In the step of providing the substrate, the channel protrusion includes one or more channel stacks stacked longitudinally, the channel stack including a second sacrificial layer and a channel layer located on the second sacrificial layer.
20. The method for forming a semiconductor structure according to any one of claims 1 to 14, characterized in that, In the step of providing the substrate, the substrate includes a substrate and a bottom fin protruding from the substrate; After providing the substrate and before forming the first through groove, the method further includes: forming a shallow trench isolation structure on the substrate on the side of the trench protrusion structure, the shallow trench isolation structure surrounding and covering the sidewall of the bottom fin; or, After forming the bottom isolation structure, the method further includes: forming a shallow trench isolation structure on the substrate on the side of the channel protrusion structure, the shallow trench isolation structure surrounding the sidewall covering the bottom fin and the sidewall covering the bottom isolation structure.