Solar cell and method for manufacturing solar cell

Abstract

The application relates to a solar cell and a preparation method thereof, which comprises a semiconductor substrate, a first conductive structure, a second conductive structure and a controllable resistance insulation layer. The semiconductor substrate comprises oppositely arranged first and second surfaces, the first surface comprises alternately arranged first and second regions; the first conductive structure is arranged at least in the first region; the second conductive structure is arranged at least in the second region; the conductive type of the first conductive structure is opposite to that of the second conductive structure; along the direction perpendicular to the first surface, the first conductive structure and the second conductive structure have an overlapping region; and the controllable resistance insulation layer is located in the overlapping region and arranged between the first conductive structure and the second conductive structure. The above-mentioned solar cell can realize micro-leakage through the controllable resistance insulation layer itself, thereby relieving the hot spot effect of the solar cell, making the overall power generation efficiency of the solar cell relatively stable, and because the controllable resistance insulation layer is relatively convenient to process and prepare, the processing cost is relatively low.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic modules, in particular to a solar cell and a preparation method of the solar cell. BACKGROUND

[0002] The back contact cell is widely used and mass-produced because its electrodes are located on the back surface, the front surface is not shielded by any metal, and light can be 100% incident on the active layer, thereby significantly improving the short-circuit current and the photoelectric conversion efficiency. However, since the current is concentrated on the back surface, when the current is too large, hot spot effect is easily caused, which increases the internal resistance of the cell, blocks the current, and thus reduces the overall power generation efficiency, accelerates the aging of the module, and increases the reliability risks such as fire, greatly increasing the operation and maintenance costs. In the related art, the current is usually guided by laser grooving surface plating a composite layer or embedding a micron-level copper foil, which makes the processing and preparation more complex, thereby making the preparation of the cell more time-consuming and high-cost. SUMMARY

[0003] Therefore, it is necessary to provide a solar cell to solve the problems of time-consuming and complex processing and preparation and high cost for reducing hot spot effect of the back contact cell.

[0004] A solar cell includes:

[0005] A semiconductor substrate including a first surface and a second surface arranged opposite to each other, the first surface including first regions and second regions arranged alternately;

[0006] A first conductive structure provided at least in the first regions;

[0007] A second conductive structure provided at least in the second regions; the conductive type of the first conductive structure is opposite to the conductive type of the second conductive structure; the first conductive structure and the second conductive structure have an overlapping region in a direction perpendicular to the first surface;

[0008] A controllable resistance insulating layer located in the overlapping region and arranged between the first conductive structure and the second conductive structure.

[0009] In some embodiments, the controllable resistance insulating layer is a doped semiconductor layer; the doping element of the doped semiconductor layer is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm 3 .

[0010] In some embodiments, in the overlapping region, the second conductive structure, the controllable resistance insulating layer, and the first conductive structure are sequentially stacked in the direction perpendicular to the first surface, and the first conductive structure is arranged on the side close to the semiconductor substrate.

[0011] The controllable resistance insulating layer is flush with an end surface of the second conductive structure on a side close to the first conductive structure.

[0012] In some embodiments, in the overlapping region, the second conductive structure, the controllable resistance insulating layer, and the first conductive structure are sequentially stacked in a direction perpendicular to the first surface, and the first conductive structure is disposed on a side close to the semiconductor substrate.

[0013] The controllable resistance insulating layer is flush with an end surface of the second conductive structure on a side close to the first conductive structure.

[0014] In some embodiments, a thickness h1 of the controllable resistance insulating layer in a direction perpendicular to the first surface satisfies the condition:

[0015] 5nm≤h1≤15nm.

[0016] In some embodiments, a ratio of a width d1 of the controllable resistance insulating layer in a first direction to a width d2 of the first region in the first direction is between 0.05 and 0.2; the first direction is a direction in which the first region points to the second region.

[0017] In some embodiments, the solar cell includes a first transparent conductive layer;

[0018] The first transparent conductive layer is disposed on a side of the first conductive structure away from the semiconductor substrate; and a projection of the first transparent conductive layer and a projection of the controllable resistance insulating layer have a first spacing.

[0019] In some embodiments, the solar cell includes a second transparent conductive layer;

[0020] The second transparent conductive layer is disposed on a side of the second conductive structure away from the semiconductor substrate; and a projection of the second transparent conductive layer and a projection of the controllable resistance insulating layer have a second spacing.

[0021] In some embodiments, the first conductive structure includes a first passivation layer and a first doped semiconductor layer which are sequentially stacked; and the first passivation layer is disposed between the first doped semiconductor layer and the semiconductor substrate.

[0022] In some embodiments, the second conductive structure includes a second passivation layer and a second doped semiconductor layer which are sequentially stacked; and the second passivation layer is disposed on a side of the second doped semiconductor layer close to the semiconductor substrate.

[0023] In some embodiments, the controllable resistance insulating layer has a thickness h1 perpendicular to the first surface, and the second passivation layer has a thickness h2 perpendicular to the first surface, and the following condition is satisfied:

[0024] 0.5h2≤h1≤h2.

[0025] In some embodiments, the second passivation layer comprises a first sub-layer, a second sub-layer and a third sub-layer connected in sequence;

[0026] The first sub-layer is in contact with the semiconductor substrate;

[0027] The second sub-layer extends in a first direction, and the first direction is perpendicular to the first surface;

[0028] The third sub-layer is in contact with a side of the controllable resistance insulating layer away from the first conductive structure.

[0029] In some embodiments, a side of the controllable resistance insulating layer close to the second conductive structure is in contact with the second sub-layer.

[0030] In some embodiments, the controllable resistance insulating layer is a continuous structure.

[0031] The present application also provides a method for preparing a solar cell, comprising:

[0032] forming a semiconductor substrate;

[0033] forming a first conductive structure on a first surface of the semiconductor substrate;

[0034] forming a controllable resistance insulating layer on a predetermined area of a side of the first conductive structure away from the semiconductor substrate;

[0035] forming a second conductive structure on a side of the controllable resistance insulating layer away from the first conductive structure, and on a second area of the first surface;

[0036] wherein the predetermined area is an overlapping area of the first conductive structure and the second conductive structure, and the second area and the first area are arranged alternately.

[0037] In some embodiments, the step of forming a controllable resistance insulating layer on a predetermined area of a side of the first conductive structure away from the semiconductor substrate specifically comprises:

[0038] forming a crystalline silicon base layer;

[0039] boron-doping on the crystalline silicon base layer to form the controllable resistance insulating layer, and the boron-doping flow rate is greater than 0 and less than 2000sccm, and the crystalline silicon base layer comprises at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon; or

[0040] phosphorus doping on the crystalline silicon base layer to form the controllable resistance insulation layer, and the phosphorus doping flow is greater than 0 and less than 2000sccm, and the crystalline silicon base layer comprises at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

[0041] The solar cell described above can realize micro-leakage through the controllable resistance insulation layer itself due to the arrangement of the controllable resistance insulation layer in the overlapping area of the first conductive structure and the second conductive structure, thereby relieving the hot spot effect of the solar cell, making the overall power generation efficiency of the solar cell relatively stable, and due to the convenience of the controllable resistance insulation layer in processing and preparation, the time required for the preparation process is reduced, and the cost is relatively low. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 The structure schematic diagram of the solar cell provided for some embodiments of the present application.

[0043] Figure 2 For Figure 1 the local enlarged view at A shown.

[0044] Figure 3 For preparing Figure 1 the first state schematic diagram of the solar cell shown.

[0045] Figure 4 For preparing Figure 1 the second state schematic diagram of the solar cell shown.

[0046] Figure 5 For preparing Figure 1 the third state schematic diagram of the solar cell shown.

[0047] Figure 6 For preparing Figure 1 the fourth state schematic diagram of the solar cell shown.

[0048] Figure 7 For preparing Figure 1 the fifth state schematic diagram of the solar cell shown.

[0049] Figure 8 For preparing Figure 1 the sixth state schematic diagram of the solar cell shown.

[0050] Figure 9 For preparing Figure 1 the seventh state schematic diagram of the solar cell shown.

[0051] Figure 10 For preparing Figure 1 the eighth state schematic diagram of the solar cell shown.

[0052] Figure 11 A schematic diagram of a method for manufacturing a solar cell is shown.

[0053] 100 - semiconductor substrate; 110 - first surface; 111 - first region; 112 - second region; 120 - second surface; 200 - first conductive structure; 210 - first passivation layer; 220 - first doped semiconductor layer; 300 - second conductive structure; 310 - second passivation layer; 311 - first sub-layer; 312 - second sub-layer; 313 - third sub-layer; 320 - second doped semiconductor layer; 400 - controllable resistance insulating layer; 410 - mask plate; 500 - first transparent conductive layer; 600 - second transparent conductive layer; 710 - first interval; 720 - second interval; 810 - first electrode; 820 - second electrode; 910 - third passivation layer; 920 - fourth passivation layer. DETAILED DESCRIPTION

[0054] In order to make the above objectives, features and advantages of the present application more clear and easily understood, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of different manners, which are different from those described herein, and it can be apparent that similar modifications of this kind can be made by those skilled in the art without departing from the scope of the present application, and therefore the present application is not limited to the specific embodiments disclosed below.

[0055] In the description of the present application, it should be understood that if there are terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., these terms indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0056] In addition, if there are terms such as "first", "second", these terms are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, if the term "a plurality of" appears, the meaning of "a plurality of" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0057] In the present application, unless specifically defined otherwise, if there are any appearances of the terms "installation", "connection", "linkage", "fixation" and the like, these terms should be interpreted in a broad sense. For example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium; it can be internal connection of two elements, or interaction relationship between two elements, unless otherwise specifically defined. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0058] In the present application, unless specifically defined otherwise, if there are any appearances of the terms "installation", "connection", "linkage", "fixation" and the like, these terms should be interpreted in a broad sense. For example, it can be fixed connection, or detachable connection, or integrated; it can be mechanical connection, or electrical connection; it can be direct connection, or indirect connection through intermediate medium; it can be internal connection of two elements, or interaction relationship between two elements, unless otherwise specifically defined. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0059] It should be noted that if an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can be a middle element. If an element is referred to as "connected to" another element, it can be directly connected to the other element or there can be a middle element. If present, the terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used in the present application are for illustrative purposes only and do not represent the only implementation.

[0060] Referring to Figure 1 and Figure 2 , Figure 1 A structural schematic diagram of a solar cell provided by some embodiments of the present application is shown. Figure 2 A structural schematic diagram of a solar cell provided by some embodiments of the present application is shown. Figure 1 A partial enlarged view of A shown in the figure.

[0061] Some embodiments of the present application provide a solar cell, which includes a semiconductor substrate 100, a first conductive structure 200, a second conductive structure 300, and a controllable resistance insulating layer 400. The semiconductor substrate 100 includes a first surface 110 and a second surface 120 arranged oppositely, the first surface 110 includes first regions 111 and second regions 112 arranged alternately; the first conductive structure 200 is arranged at least in the first regions 111; the second conductive structure 300 is arranged at least in the second regions 112; the first conductive structure 200 and the second conductive structure 300 have opposite conductive types; the first conductive structure 200 and the second conductive structure 300 have an overlapping region in a direction perpendicular to the first surface 110; the controllable resistance insulating layer 400 is arranged between the first conductive structure 200 and the second conductive structure 300 in the overlapping region; and the direction perpendicular to the first surface 110 is the yy' direction in the coordinate system shown in FIG. 1. Figure 1 and Figure 2

[0062] The solar cell described above can realize micro-leakage through the controllable resistance insulating layer 400 itself, thereby relieving the hot spot effect of the solar cell, making the overall power generation efficiency of the solar cell more stable, and because the controllable resistance insulating layer 400 is convenient to prepare, the time required for the preparation process is reduced, and the cost is lower.

[0063] The solar cell provided by the embodiments of the present application can rely on the existing process route to relieve the problems caused by the hot spot effect of the solar cell module at a lower cost investment.

[0064] In some embodiments, the controllable resistance insulating layer 400 is a doped semiconductor layer; the doping element is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm 3 When the first regions 111 are N regions and the second regions 112 are P regions, the doping element can be boron. When the first regions 111 are P regions and the second regions 112 are N regions, the doping element can be phosphorus. By limiting the concentration of the doping element to the range of 5E18-1E21 at / cm 3 , the doping concentration is appropriate, neither too high to make the short-circuit current between the first conductive structure 200 and the second conductive structure 300 too large, nor too low to make the effect of micro-leakage too weak. The range of the doping concentration can form a weak PN junction between the controllable resistance insulating layer 400 and the first regions 111 to realize the technical effect of micro-leakage. By being within the range, the difference between the cell pieces and the difference between the batches can also be reduced, so that the resistance of the controllable resistance insulating layer 400 has a small amplitude fluctuation within a certain range, which is beneficial to the processing and preparation in the actual production line.

[0065] ​In some embodiments, the concentration of the dopant element is 5E18 at / cm³. 3 In some of these embodiments, the concentration of the dopant element is 1E21 at / cm³. 3 In some embodiments, the concentration of the dopant element is 1E20 at / cm³. 3 .

[0066] Please see Figure 1 and Figure 2 In some embodiments, in the overlapping area, along a direction perpendicular to the first surface 110, the second conductive structure 300, the controllable resistance insulating layer 400, and the first conductive structure 200 are sequentially stacked, and the first conductive structure 200 is disposed on the side close to the semiconductor substrate 100; the side of the controllable resistance insulating layer 400 close to the second conductive structure 300 is flush with the end face of the first conductive structure 200 close to the second conductive structure 300.

[0067] By aligning the side of the controllable resistance insulating layer 400 near the second conductive structure 300 with the end face of the first conductive structure 200 near the second conductive structure 300, that is, by making the two sides flush... Figure 1 and Figure 2 The right edges in the xx' direction coincide, which makes the controllable resistance insulating layer 400 easier to process and prepare. It can be patterned using laser equipment, which reduces the processing time.

[0068] Please see Figure 1 and Figure 2 In some embodiments, in the overlapping area, along a direction perpendicular to the first surface 110, the second conductive structure 300, the controllable resistance insulating layer 400, and the first conductive structure 200 are sequentially stacked, and the first conductive structure 200 is disposed on the side close to the semiconductor substrate 100; the side of the controllable resistance insulating layer 400 close to the first conductive structure 200 is flush with the end face of the second conductive structure 300 close to the first conductive structure 200.

[0069] By aligning the side of the controllable resistance insulating layer 400 near the first conductive structure 200 with the end face of the second conductive structure 300 near the first conductive structure 200, that is, by making the two sides flush... Figure 2 and Figure 1 The left edges in the xx' direction coincide, which makes the controllable resistance insulating layer 400 easier to process and prepare. It can be patterned using laser equipment, which reduces the processing time.

[0070] Please see Figure 2In some embodiments, the controllable resistance insulation layer 400 has a thickness h1 perpendicular to the first surface 110 satisfying the condition: 5nm≤h1≤15nm. By limiting the thickness h1 of the controllable resistance insulation layer 400 to a range of greater than or equal to 5nm and less than or equal to 15nm, the thickness of the controllable resistance insulation layer 400 is reasonable, which can realize the effect of micro-leakage when the battery has hot spot effect, at least partially conduct the first conductive structure 200 and the second conductive structure 300, thereby reducing the size of the current transmitted by the battery, relieving the hot spot effect, and the process of preparation is also more convenient.

[0071] In some embodiments, the thickness h1 of the controllable resistance insulation layer 400 perpendicular to the first surface 110 is 5nm, so that the thickness of the controllable resistance insulation layer 400 is not too thin, effectively ensuring that the first conductive structure 200 and the second conductive structure 300 are in an insulating state when the battery is working normally, and also easy and convenient to process, avoiding being completely etched away during subsequent mask removal processing. In some embodiments, the thickness h1 of the controllable resistance insulation layer 400 perpendicular to the first surface 110 is 15nm, so that the thickness of the controllable resistance insulation layer 400 is not too thick, so that when the battery has hot spot effect, the controllable resistance insulation layer 400 can realize the effect of micro-leakage by itself, at least partially conduct the first conductive structure 200 and the second conductive structure 300, to relieve the hot spot effect, and also can make the resistance of the controllable resistance insulation layer 400 not too large, thereby affecting the series resistance of the battery and affecting the photoelectric conversion efficiency of the battery. In some embodiments, the thickness h1 of the controllable resistance insulation layer 400 perpendicular to the first surface 110 is 10nm. Of course, in some embodiments, the thickness h1 of the controllable resistance insulation layer 400 perpendicular to the first surface 110 can also be 6nm, 8nm, 12nm, 14nm, etc.

[0072] Please refer to Figure 1 and combine with Figure 2 In some embodiments, the ratio of the width d1 of the controllable resistance insulation layer 400 along the first direction to the width d2 of the first region 111 along the first direction is between 0.05 and 0.2; the first direction is the direction in which the first region 111 points to the second region 112; for example, the first direction is the direction in which the first region 111 points to the second region 112. Figure 1 and Figure 2The ratio of the width dl of the controllable resistance insulation layer 400 along the first direction to the width d2 of the first region 111 along the first direction is set to be between 0.05 and 0.2, so that the width ratio of the controllable resistance insulation layer 400 to the first region 111 is reasonable, neither too large nor too small. When the battery is working normally, the controllable resistance insulation layer 400 can well insulate the first conductive structure 200 and the second conductive structure 300, and when the battery has hot spot effect, the controllable resistance insulation layer 400 can at least partially conduct some of the first conductive structure 200 and the second conductive structure 300 to alleviate the hot spot effect.

[0073] In some embodiments, the ratio of the width dl of the controllable resistance insulation layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.05. In some embodiments, the ratio of the width dl of the controllable resistance insulation layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.2. In some embodiments, the ratio of the width dl of the controllable resistance insulation layer 400 along the first direction to the width d2 of the first region 111 along the first direction is 0.1.

[0074] Please refer to Figure 1 and Figure 2 In some embodiments, the solar cell includes a first transparent conductive layer 500; the first transparent conductive layer 500 is arranged on the side of the first conductive structure 200 away from the semiconductor substrate 100; and the orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulation layer 400 have a first interval 710. By arranging the first transparent conductive layer 500, the incident light can be transmitted to a greater extent, and the functions of collecting and transmitting carriers can be realized. The orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulation layer 400 have a first interval 710, so that the first transparent conductive layer 500 and the controllable resistance insulation layer 400 are disconnected through the first interval 710 to avoid short-circuit connection of the first conductive structure 200 and the second conductive structure 300 through the first transparent conductive layer 500.

[0075] Please refer to Figure 1 and Figure 1In some embodiments, the solar cell further comprises a second transparent conductive layer 600, the second transparent conductive layer 600 is disposed on the side of the second conductive structure 300 away from the semiconductor substrate 100, and the second transparent conductive layer 600 has a second interval 720 with the orthographic projection of the controllable resistance insulation layer 400. By disposing the second transparent conductive layer 600, the incident light can be transmitted more, and the functions of collecting and transmitting carriers can be realized. The second transparent conductive layer 600 has the second interval 720 with the orthographic projection of the controllable resistance insulation layer 400, so that the first conductive structure 200 and the second conductive structure 300 are disconnected through the second interval 720 to avoid short circuit connection through the second transparent conductive layer 600.

[0076] Referring to Figure 2 In some embodiments, the first conductive structure 200 comprises a first passivation layer 210 and a first doped semiconductor layer 220 which are disposed in layers, and the first passivation layer 210 is disposed between the first doped semiconductor layer 220 and the semiconductor substrate 100. Through the cooperation of the first passivation layer 210 and the first doped semiconductor layer 220, the technical effects of efficient carrier selective collection and surface passivation of the first region 111 can be realized.

[0077] In some embodiments, the first passivation layer 210 can be a tunneling passivation layer or an intrinsic amorphous silicon layer.

[0078] In some embodiments, the first doped semiconductor layer 220 can be at least one of a doped polysilicon layer, a doped monocrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0079] Referring to Figure 1 In some embodiments, the second conductive structure 300 comprises a second passivation layer 310 and a second doped semiconductor layer 320 which are disposed in layers, and the second passivation layer 310 is disposed on the side of the second doped semiconductor layer 320 close to the semiconductor substrate 100. Through the cooperation of the second passivation layer 310 and the second doped semiconductor layer 320, the technical effects of efficient carrier selective collection and surface passivation of the second region 112 can be realized.

[0080] In some embodiments, the second passivation layer 310 can be a tunneling passivation layer or an intrinsic amorphous silicon layer.

[0081] In some embodiments, the second doped semiconductor layer 320 can be at least one of a doped polysilicon layer, a doped monocrystalline silicon layer, a doped amorphous silicon layer, a doped microcrystalline silicon layer, and a doped nanocrystalline silicon layer.

[0082] Referring to Figure 2In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the direction perpendicular to the first surface 110 is equal to 0.5 times the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110.

[0083] By limiting the thickness h1 of the controllable resistance insulating layer 400 along the direction perpendicular to the first surface 110 to be equal to or greater than 0.5 times the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110 and less than or equal to 1 times the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110, the thickness ratio of the controllable resistance insulating layer 400 to the second passivation layer 310 is reasonable, and a better micro-leakage effect can be achieved.

[0084] In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the direction perpendicular to the first surface 110 is equal to 0.5 times the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110. In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the direction perpendicular to the first surface 110 is equal to the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110. In some embodiments, the thickness h1 of the controllable resistance insulating layer 400 along the direction perpendicular to the first surface 110 is equal to 0.8 times the thickness h2 of the second passivation layer 310 along the direction perpendicular to the first surface 110.

[0085] Please refer to Figure 1 and Figure 2 In some embodiments, the second passivation layer 310 comprises a first sub-layer 311, a second sub-layer 312 and a third sub-layer 313 connected in sequence; the first sub-layer 311 is in contact with the semiconductor substrate 100; the second sub-layer 312 extends along a first direction, and the first direction is perpendicular to the extending direction of the first surface 110; and the third sub-layer 313 is in contact with the side of the controllable resistance insulating layer 400 away from the first conductive structure 200. In the preparation of the solar cell provided in the embodiments of the present application, the controllable resistance insulating layer 400 is first deposited, and then the second passivation layer 310 is deposited, so that the second passivation layer 310 can form the first sub-layer 311, the second sub-layer 312 and the third sub-layer 313 in different deposition areas, that is, the controllable resistance insulating layer 400 is first prepared, so that the controllable resistance insulating layer 400 can act as a sacrificial layer for the first region 111 during the laser etching operation of the first region 111, thereby protecting the first conductive structure 200 in the first region 111.

[0086] Please refer to Figure 1 and Figure 2In some embodiments, the controllable resistance insulation layer 400 is in contact with the second sub-layer 312 on the side close to the second conductive structure 300. The controllable resistance insulation layer 400 and the second passivation layer 310 are prepared in a structure of first depositing the controllable resistance insulation layer 400 and then depositing the second passivation layer 310, so that the controllable resistance insulation layer 400 is in contact with the second sub-layer 312 on the side close to the second conductive structure 300. When the hot spot effect occurs in the battery, the controllable resistance insulation layer 400 and the second sub-layer 312 are in micro-leakage, thereby relieving the damage of the hot spot effect to the battery.

[0087] Referring to Figure 11 and Figure 11 In some embodiments, the controllable resistance insulation layer 400 is a continuous structure. By setting the controllable resistance insulation layer 400 as a continuous structure, the controllable resistance insulation layer 400 is simple and convenient to process and prepare. Compared with the traditional structure of opening a groove on the surface by laser and plating a composite layer or embedding a micron-level copper foil to realize the current conduction, the processing and preparation are more simple and convenient, the time required for the preparation process is reduced, and the cost is lower.

[0088] The present application provides a preparation method of a solar cell, referring to Figures 3-10 , Figure 1 A flow chart of a preparation method of a solar cell provided by some embodiments of the present application is shown, and the preparation method of the solar cell comprises the following steps:

[0089] S10: forming a semiconductor substrate 100;

[0090] S20: forming a first conductive structure 200 on the first area 111 of the first surface 110 of the semiconductor substrate 100;

[0091] S30: forming a controllable resistance insulation layer 400 on the preset area on the side of the first conductive structure 200 away from the semiconductor substrate 100;

[0092] S40: forming a second conductive structure 300 on the side of the controllable resistance insulation layer 400 away from the first conductive structure 200 and the second area 112 of the first surface 110; wherein the preset area is the overlapping area of the first conductive structure 200 and the second conductive structure 300, and the second area 112 and the first area 111 are arranged alternately.

[0093] By forming the controllable resistance insulation structure on the side of the first conductive structure 200 away from the semiconductor substrate 100 after the first conductive structure 200 is prepared, and by processing to finally form the controllable resistance insulation layer 400 in the preset area, and finally forming the second conductive structure 300 in the second region 112 of the semiconductor substrate 100, since the controllable resistance insulation layer 400 is arranged in the overlapping area of the first conductive structure 200 and the second conductive structure 300, micro-leakage can be realized by the controllable resistance insulation layer 400 itself, thereby relieving the hot spot effect of the solar cell, making the overall power generation efficiency of the solar cell relatively stable, and since the controllable resistance insulation layer 400 is relatively convenient to process and prepare, the time required for the preparation process is reduced, and the cost is relatively low.

[0094] In some embodiments, the step of forming the controllable resistance insulation layer 400 in the preset area on the side of the first conductive structure 200 away from the semiconductor substrate 100 specifically includes:

[0095] forming a crystalline silicon base layer;

[0096] boron-doping the crystalline silicon base layer to form the controllable resistance insulation layer 400, and the boron-doping flow is greater than 0 and less than 2000 sccm, and the crystalline silicon base layer includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon; or

[0097] phosphorus-doping the crystalline silicon base layer to form the controllable resistance insulation layer 400, and the phosphorus-doping flow is greater than 0 and less than 2000 sccm, and the crystalline silicon base layer includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon.

[0098] When the first region 111 is an N region and the second region 112 is a P region, boron is doped on the crystalline silicon base layer. When the first region 111 is a P region and the second region 112 is an N region, phosphorus is doped on the crystalline silicon base layer.

[0099] The controllable resistance insulation layer 400 is formed by boron-doping or phosphorus-doping on the crystalline silicon base layer, and the boron-doping or phosphorus-doping flow is greater than 0 and less than 2000 sccm, so that the concentration of the doping element of the finally formed controllable resistance insulation layer 400 is between 5E18-1E21 at / cm 3 . In this way, the doping concentration is appropriate, neither too high to make the short-circuit current between the first conductive structure 200 and the second conductive structure 300 too large, nor too low to make the effect of micro-leakage too weak. The range of the doping concentration can form a weak PN junction between the controllable resistance insulation layer 400 and the first region 111 to achieve the technical effect of micro-leakage. By being within this range, the differences between the cell pieces and the differences between the batches can also be reduced, so that the resistance of the controllable resistance insulation layer 400 has a small amplitude fluctuation within a certain range, which is beneficial to the processing and preparation in the actual production line.

[0100] It should be understood that in the embodiments of the present application, at least part of the steps in the preparation method can include multiple steps or multiple stages, which are not necessarily performed at the same time, but can be performed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be alternately performed with other steps or at least part of the steps or stages in other steps.

[0101] The following refers to Figure 3 The steps for preparing a solar cell as Figure 4 indicated are described as an example:

[0102] The semiconductor substrate 100 of the present embodiment is taken as an example of a single crystal N-type silicon wafer, and of course in other embodiments, it can also be other types, such as a P-type silicon wafer, etc., which are not specially limited.

[0103] (1) The semiconductor substrate 100 is subjected to a polishing process using a slot polisher. A double-sided polished wafer with a tower size of 15-30 um is formed on the surface of the semiconductor substrate 100, and the final topography is as shown in Figure 5 .

[0104] (2) On the first surface 110 of the semiconductor substrate 100, that is, the back light surface, a first passivation layer 210 and an intrinsic polysilicon layer are formed in a phosphorus diffusion furnace tube. The thickness of the first passivation layer 210 is 1.2-1.8 nm, and the thickness of the intrinsic polysilicon layer is 90-300 nm.

[0105] (3) In the phosphorus diffusion furnace tube, the intrinsic polysilicon layer is doped to form a first doped semiconductor layer 220, which can be an N-type polysilicon material layer, and a layer of phosphorus-silicon glass is formed on the surface of the first doped semiconductor layer 220.

[0106] (4) In a slot cleaner, the phosphorus-silicon glass on the surface of the semiconductor substrate 100 is cleaned, and at the same time, the surface of the semiconductor substrate 100 is subjected to RCA cleaning. The surface resistance of the phosphorus-silicon glass after cleaning is 30Ω / sq-70Ω / sq, and the final topography is as shown in Figure 6 .

[0107] (5) On the first surface 110 of the semiconductor substrate 100, a controllable resistance insulation structure and a mask plate 410 are deposited by PECVD. The thickness of the controllable resistance insulation structure can be 5-15 nm, the B doping flow rate is 0-2000, or the P doping flow rate is 0-2000; the thickness of the mask plate 410 can be 70-110 nm, and the mask plate 410 can be a silicon nitride mask plate 410. The final topography is as shown in Figure 7 .

[0108] (6) Using a laser to pattern the controllable resistance insulation structure and the mask plate 410, exposing the second area 112, i.e., the region corresponding to the P+ area, and the remaining part of the first passivation layer 210 and the first doped semiconductor layer 220 form the first conductive structure 200, and the final topography is as shown in Figure 8

[0109] (7) A chain cleaning machine removes the controllable resistance insulation structure and the mask plate 410. In a slot cleaning machine, the first surface 110 is grooved and the second surface 120 is textured to form a small textured structure. Finally, the mask plate 410 is removed or partially removed in the HF tank. The final topography is as shown in Figure 9

[0110] (8) In a CVD device, a third passivation layer 910 is deposited on the second surface 120. The third passivation layer 910 can be an intrinsic amorphous silicon layer, and the thickness of the third passivation layer 910 can be 5-20 nm. Then, a second passivation layer 310 and a second doped semiconductor layer 320 are deposited on the first surface 110 in turn. The second passivation layer 310 can be an intrinsic amorphous silicon layer, and the thickness of the second passivation layer 310 can be 5-20 nm. The second doped semiconductor layer 320 can be a B-doped amorphous silicon layer, and the thickness of the second doped semiconductor layer 320 can be 15-35 nm. Finally, a fourth passivation layer 920 is deposited on the second surface 120. The fourth passivation layer 920 can be a silicon nitride layer, and the thickness of the fourth passivation layer 920 can be 70-85 nm. The final topography is as shown in Figure 9

[0111] (9) Using a laser to remove or partially remove the second passivation layer 310 and the second doped semiconductor layer 320 deposited on the surface of the first area 111 (N+ area), exposing the area where the first semiconductor layer contacts the first transparent conductive layer 500, and the second passivation layer 310 and the second doped semiconductor layer 320 above the second area 112 (P+ area) form the second conductive structure 300. In this laser processing process, the controllable resistance insulation layer 400 can act as a sacrificial layer for the first area 111, thereby protecting the first conductive structure 200 of the first area 111, thereby ensuring the passivation effect of the first conductive structure 200.

[0112] (10) In a chain cleaning machine, the first surface 110 of the battery piece is placed downward into the HF tank, and the oxide layer and the controllable resistance insulation structure in the laser grooving area in step (9) are removed. Finally, it is washed in a water tank and dried. The final topography is as shown in Figure 10

[0113] (11) In a PVD device, a transparent conductive structure is formed on the surface of the first surface 110. The thickness of the transparent conductive structure can be 70-100 nm. ​​​​

[0114] (12) Using the screen printing method, the etching paste is printed on the isolation area, the position of the isolation area can be at the junction of the P+ / N+ area, or above the N+ area, the position of the isolation area is the area of the first distance and the second distance.

[0115] (13) Using the slot cleaning machine, the solar cell structure shown in Figure 1 is immersed in low concentration alkali and hydrogen peroxide, the etching paste and the transparent conductive structure below it in step (12) are removed to complete the insulation of P+ / N+, so that the transparent conductive structure forms the first transparent conductive layer 500 and the second transparent conductive layer 600, and the orthographic projection of the first transparent conductive layer 500 and the orthographic projection of the controllable resistance insulation layer 400 have a first distance, and the orthographic projection of the second transparent conductive layer 600 and the orthographic projection of the controllable resistance insulation layer 400 have a second distance, and the final appearance is shown in ​ .

[0116] (14) Using the screen printing method, the sub-grid of the first electrode 810 and the sub-grid of the second electrode 820 are formed, after drying, the insulation glue is printed at the position of different polarity to complete the insulation between the main and sub-grid of different polarity, after drying, the printing of the main grid is carried out, and finally the solidification is carried out. Complete the collection of electrons and holes, and the final solar cell structure is shown in ​ .

[0117] The technical features of the above-mentioned embodiments can be combined arbitrarily, in order to make the description simple, not all possible combinations of the technical features in the above-mentioned embodiments are described, however, as long as the combination of these technical features does not exist contradictory, it should be considered as the scope of the present application.

[0118] The above-mentioned embodiments only express several embodiments of the present application, the description is more specific and detailed, but it should not be understood as limiting the scope of the patent application. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A solar cell, characterized in that, The solar cell includes: The semiconductor substrate (100) includes a first surface (110) and a second surface (120) disposed opposite to each other, wherein the first surface (110) includes an alternately arranged first region (111) and a second region (112). The first conductive structure (200) is at least provided in the first region (111). The second conductive structure (300) is at least provided in the second region (112); the conductivity type of the first conductive structure (200) is opposite to that of the second conductive structure (300); the first conductive structure (200) and the second conductive structure (300) have an overlapping area along the direction perpendicular to the first surface (110); A controllable resistance insulating layer (400) is located in the overlapping region and disposed between the first conductive structure (200) and the second conductive structure (300). The controllable resistance insulating layer (400) is a doped semiconductor layer. The doping element of the doped semiconductor layer is boron or phosphorus, and the concentration of the doping element is 5E18-1E21 at / cm³. 3 When the first region (111) is an N-region and the second region (112) is a P-region, the doping element is boron; when the first region (111) is a P-region and the second region (112) is an N-region, the doping element is phosphorus; the controllable resistance insulating layer (400) is a continuous structure. In this process, a controllable resistance insulation structure and a mask plate (410) are deposited using PECVD. The controllable resistance insulation structure and the mask plate (410) are patterned using a laser. The mask plate (410) is removed, and the oxide layer in the laser-grooved area and the controllable resistance insulation structure are removed, so that the remaining controllable resistance insulation structure is formed into the controllable resistance insulation layer (400).

2. The solar cell according to claim 1, characterized in that, In the overlapping area, along a direction perpendicular to the first surface (110), the second conductive structure (300), the controllable resistance insulating layer (400), and the first conductive structure (200) are stacked sequentially, and the first conductive structure (200) is disposed on the side close to the semiconductor substrate (100). The side of the controllable resistance insulating layer (400) near the second conductive structure (300) is flush with the end face of the first conductive structure (200) near the second conductive structure (300).

3. The solar cell according to claim 1, characterized in that, In the overlapping area, along a direction perpendicular to the first surface (110), the second conductive structure (300), the controllable resistance insulating layer (400), and the first conductive structure (200) are stacked sequentially, and the first conductive structure (200) is disposed on the side close to the semiconductor substrate (100). The side of the controllable resistance insulating layer (400) near the first conductive structure (200) is flush with the end face of the second conductive structure (300) near the first conductive structure (200).

4. The solar cell according to claim 1, characterized in that, The controllable resistance insulating layer (400) along its thickness h1 perpendicular to the first surface (110) satisfies the following condition: 5nm≤h1≤15nm.

5. The solar cell according to claim 1, characterized in that, The ratio of the width d1 of the controllable resistance insulating layer (400) along the first direction to the width d2 of the first region (111) along the first direction is between 0.05 and 0.2; the first direction is the direction from the first region (111) to the second region (112).

6. The solar cell according to claim 1, characterized in that, The solar cell includes a first transparent conductive layer (500); The first transparent conductive layer (500) is disposed on the side of the first conductive structure (200) away from the semiconductor substrate (100); and there is a first gap (710) between the orthographic projection of the first transparent conductive layer (500) and the orthographic projection of the controllable resistance insulating layer (400).

7. The solar cell according to claim 1, characterized in that, The solar cell includes a second transparent conductive layer (600). The second transparent conductive layer (600) is disposed on the side of the second conductive structure (300) away from the semiconductor substrate (100); and there is a second spacing (720) between the orthographic projection of the second transparent conductive layer (600) and the orthographic projection of the controllable resistance insulating layer (400).

8. The solar cell according to claim 1, characterized in that, The first conductive structure (200) includes a first passivation layer (210) and a first doped semiconductor layer (220) stacked together; and the first passivation layer (210) is disposed between the first doped semiconductor layer (220) and the semiconductor substrate (100).

9. The solar cell according to claim 8, characterized in that, The second conductive structure (300) includes a second passivation layer (310) and a second doped semiconductor layer (320) stacked together; and the second passivation layer (310) is disposed on the side of the second doped semiconductor layer (320) close to the semiconductor substrate (100).

10. The solar cell according to claim 9, characterized in that, The thickness h1 of the controllable resistance insulating layer (400) perpendicular to the first surface (110) and the thickness h2 of the second passivation layer (310) perpendicular to the first surface (110) satisfy the following condition: 0.5h2≤h1≤h2.

11. The solar cell according to claim 9, characterized in that, The second passivation layer (310) includes a first sublayer (311), a second sublayer (312), and a third sublayer (313) connected in sequence. The first sublayer (311) is in contact with the semiconductor substrate (100); The second sublayer (312) extends along a first direction, which intersects the extension direction of the first surface (110); The third sublayer (313) is in contact with the side of the controllable resistance insulating layer (400) opposite to the first conductive structure (200).

12. The solar cell according to claim 11, characterized in that, The controllable resistance insulating layer (400) is in contact with the second sublayer (312) on the side near the second conductive structure (300).

13. A method for preparing a solar cell, characterized in that, The method for preparing the solar cell includes: Forming a semiconductor substrate (100); A first conductive structure (200) is formed in a first region (111) of a first surface (110) of the semiconductor substrate (100). A controllable resistance insulating layer (400) is formed in a predetermined region on the side of the first conductive structure (200) facing away from the semiconductor substrate (100); the controllable resistance insulating layer (400) is a continuous structure; wherein, the controllable resistance insulating structure and the mask (410) are deposited by PECVD, the controllable resistance insulating structure and the mask (410) are patterned by a laser, the mask (410) is removed, and the oxide layer and the controllable resistance insulating structure in the laser-grooved area are removed, so that the remaining controllable resistance insulating structure is formed as the controllable resistance insulating layer (400). A second conductive structure (300) is formed on the side of the controllable resistance insulating layer (400) opposite to the first conductive structure (200) and in the second region (112) of the first surface (110). The preset region is the overlapping area of ​​the first conductive structure (200) and the second conductive structure (300), and the second region (112) and the first region (111) are arranged alternately; the controllable resistance insulating layer (400) is a doped semiconductor layer; the doping element of the doped semiconductor layer is boron or phosphorus, and the concentration of the doping element is 5E18-1E21at / cm³. 3 When the first region (111) is an N-region and the second region (112) is a P-region, the doping element is boron; when the first region (111) is a P-region and the second region (112) is an N-region, the doping element is phosphorus.

14. The method for preparing a solar cell according to claim 13, characterized in that, The step of forming a controllable resistance insulating layer (400) in a predetermined region on the side of the first conductive structure (200) opposite to the semiconductor substrate (100) specifically includes: Forming a crystalline silicon substrate; Boron is doped onto the crystalline silicon substrate to form the controllable resistance insulating layer (400), and the boron doping current is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon, or nanocrystalline silicon; or The controllable resistance insulating layer (400) is formed by doping phosphorus on the crystalline silicon substrate, and the phosphorus doping flow rate is greater than 0 and less than 2000 sccm. The crystalline silicon substrate includes at least one of polycrystalline silicon, monocrystalline silicon, amorphous silicon, microcrystalline silicon or nanocrystalline silicon.

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