Semiconductor stack, semiconductor element and manufacturing method thereof

Abstract

The invention discloses a semiconductor stack, a semiconductor element and a manufacturing method thereof. The semiconductor device includes a first semiconductor layer and a light emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant, and a second dopant. The light-emitting structure is located on the first semiconductor layer and comprises an active structure. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, and the second dopant is hydrogen.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201911373222.7, application date: December 27, 2019, invention title: semiconductor stack, semiconductor element and manufacturing method thereof). Technical Field

[0002] This invention relates to a semiconductor element, and more particularly to a light-emitting element comprising a semiconductor stack. Background Technology

[0003] With the rapid advancement of technology, semiconductor components play a crucial role in information transmission and energy conversion, and research and development of related materials continues unabated. For example, III-V semiconductor materials containing group III and group V elements can be used in various optoelectronic components such as light-emitting diodes (LEDs), laser diodes (LDs), and solar cells, as well as in lighting, medical applications, displays, communications, sensing, and power systems. LEDs are suitable for solid-state lighting and offer advantages such as low power consumption and long lifespan, thus gradually replacing traditional light sources and being widely used in traffic signals, backlight modules, various lighting and medical devices. Summary of the Invention

[0004] This invention provides a semiconductor device comprising a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a light-emitting structure. The first semiconductor layer comprises a first III-V group semiconductor material, a first dopant, a second dopant, and a third dopant. The second semiconductor layer is located below the first semiconductor layer and comprises a second III-V group semiconductor material. The light-emitting structure is located on the first semiconductor layer and comprises an active structure. The third semiconductor layer is located between the first semiconductor layer and the light-emitting structure and comprises a third III-V group semiconductor material and a third dopant. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0005] In one embodiment of the present invention, the second semiconductor layer contains a third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer.

[0006] In one embodiment of the present invention, the second semiconductor layer further includes a first dopant and a second dopant.

[0007] In one embodiment of the present invention, the third semiconductor layer further includes a first dopant and a second dopant.

[0008] In one embodiment of the present invention, the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the difference between the first lattice constant and the second lattice constant is more than 2% and less than 10%.

[0009] In one embodiment of the present invention, the first III-V semiconductor material is the same as the third III-V semiconductor material.

[0010] In one embodiment of the present invention, the first III-V semiconductor material is different from the second III-V semiconductor material.

[0011] In one embodiment of the present invention, the third dopant is silicon.

[0012] In one embodiment of the present invention, when the semiconductor element is in operation, the active structure emits infrared light.

[0013] In one embodiment of the present invention, the infrared light has a peak wavelength between 800 nm and 1700 nm.

[0014] In one embodiment of the present invention, the concentration curve of the first dopant in the first semiconductor layer has a periodic variation pattern.

[0015] In one embodiment of the present invention, the concentration curve of the first dopant includes i local maxima and i local minima, where i is a positive integer greater than or equal to 5.

[0016] In one embodiment of the present invention, the light-emitting structure does not contain nitrogen.

[0017] In one embodiment of the present invention, the second III-V semiconductor material is a binary III-V semiconductor material.

[0018] The present invention also provides a method for manufacturing a semiconductor device, comprising: forming a first semiconductor layer comprising a first III-V semiconductor material, a first dopant, a second dopant, and a third dopant; providing a second semiconductor layer below the first semiconductor layer and comprising the second III-V semiconductor material; forming a light-emitting structure on the first semiconductor layer and comprising an active structure; and providing a third semiconductor layer between the first semiconductor layer and the light-emitting structure, comprising the third III-V semiconductor material and the third dopant. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, and the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0019] In one embodiment of the present invention, providing the first semiconductor layer further includes: a first step, comprising growing a portion of the first semiconductor layer at a first temperature; a second step, comprising providing a second temperature greater than the first temperature, wherein the second temperature is not less than 750°C; and repeating the first step and the second step.

[0020] In one embodiment of the present invention, the first step and the second step are repeated more than ten times.

[0021] In one embodiment of the present invention, the difference between the first temperature and the second temperature is not less than 300°C.

[0022] In one embodiment of the present invention, the growth of the first semiconductor layer is not performed at the second temperature.

[0023] The present invention also provides a semiconductor stack comprising a first semiconductor layer and a second semiconductor layer. The first semiconductor layer comprises a first III-V semiconductor material, a first dopant, and a second dopant. The second semiconductor layer is adjacent to the first semiconductor layer and comprises a second III-V semiconductor material. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, and the first dopant is carbon, the second dopant is hydrogen, and under X-ray diffraction analysis, the first semiconductor layer has a full width at half maximum (FWHM) of less than 300 arcsec.

[0024] In one embodiment of the present invention, the first semiconductor layer and the second semiconductor layer further include a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the second semiconductor layer.

[0025] In one embodiment of the present invention, the constituent elements of the second III-V semiconductor material are different from those of the first III-V semiconductor material.

[0026] In one embodiment of the present invention, the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the first lattice constant is greater than the second lattice constant.

[0027] In one embodiment of the present invention, the difference between the first lattice constant and the second lattice constant is greater than 2% and less than 10%.

[0028] In one embodiment of the present invention, a light-emitting structure is further included, which is located on the first semiconductor layer and includes an active structure.

[0029] In one embodiment of the present invention, a third semiconductor layer is further included, located between the first semiconductor layer and the light-emitting structure, wherein the third semiconductor layer comprises a third III-V group semiconductor material.

[0030] In one embodiment of the present invention, the first semiconductor layer and the third semiconductor layer further include a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0031] In one embodiment of the present invention, the third dopant is silicon.

[0032] In one embodiment of the present invention, when the semiconductor device is in operation, the active structure emits infrared light.

[0033] In one embodiment of the present invention, the infrared light has a peak wavelength between 800 nm and 1700 nm.

[0034] In one embodiment of the present invention, the concentration curve of the first dopant in the first semiconductor layer has a periodic variation pattern.

[0035] In one embodiment of the present invention, the concentration curve of the first dopant includes i local maxima and i local minima, where i is a positive integer greater than or equal to 5.

[0036] In one embodiment of the present invention, the light-emitting structure does not contain nitrogen.

[0037] In one embodiment of the present invention, the second semiconductor layer contains the third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of a semiconductor stack structure according to an embodiment of the present invention;

[0039] Figure 2A This is a partial structural schematic diagram of a semiconductor element according to an embodiment of the present invention;

[0040] Figure 2B This is a partial structural schematic diagram of a semiconductor element according to an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of the structure of a semiconductor element according to an embodiment of the present invention;

[0043] Figures 5A to 5D This is a schematic diagram of a method for manufacturing a semiconductor stack according to an embodiment of the present invention;

[0044] Figure 5E This is a graph showing the relationship between elemental concentration and depth over a portion of a semiconductor element according to an embodiment of the present invention.

[0045] Figure 5F for Figure 5E A magnified schematic diagram of a portion of the carbon (C) concentration curve;

[0046] Figure 6 This is a schematic diagram of the packaging structure of a semiconductor element according to an embodiment of the present invention.

[0047] Explanation of symbols

[0048] 10: Semiconductor stack-up

[0049] 20, 20', 30, 40, 60: Semiconductor components

[0050] 61: Packaging substrate

[0051] 62: Through hole

[0052] 63: Carrier

[0053] 63a: Part 1

[0054] 63b: Part Two

[0055] 65: Joint line

[0056] 66: Contact Structure

[0057] 66a, 66b: Contact pads

[0058] 68: Packaging materials

[0059] 100, 300, 400, 500: First semiconductor layer

[0060] 102, 402, 502: Second semiconductor layer

[0061] 204, 304, 404, 504: Third semiconductor layer

[0062] 206, 306, 406: Light-emitting structures

[0063] 208, 308, 408: Fourth semiconductor layer

[0064] 210, 310, 410: Active structures

[0065] 212, 312, 412: Fifth semiconductor layer

[0066] 414: Window layer

[0067] 416: Contact layer

[0068] 600: Package structure

[0069] 318, 418: First electrode

[0070] 320, 420: Second electrode

[0071] S510, S520, S530, S540: Steps

[0072] C1: First concentration

[0073] C2: Second concentration

[0074] C3: Second concentration

[0075] C L1 、C L2 、C Li 、C M1 、C M2 、C Mi : Concentrations Detailed implementation manners

[0076] The following embodiments will illustrate the concept of the present invention with accompanying drawings. In the drawings or the description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or sizes of the components in the drawings are only illustrative and are not actually limited thereto. It should be noted in particular that the components not shown or described in the figures may be in forms known to those skilled in the art.

[0077] The general formula InGaAsP represents In x1 Ga 1-x1 As 1-y1 P y1 , where 0 < x1 < 1, 0 < y1 < 1; AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x2 In x2 As, where 0 < x2 < 1, 0 < y2 < 1; the general formula AlGaInP represents (Al y3 Ga (1-y3) ) 1-x3 In x3 P, where 0 < x3 < 1, 0 < y3 < 1; the general formula InGaAs represents In x4 Ga 1-x4As, where 0 < x4 < 1; the composition, additives, and dopants of each layer included in the semiconductor device of the present disclosure can be analyzed by any suitable method, such as a secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be analyzed by any suitable method, such as transmission electron microscopy (TEM) or scanning electron microscopy (SEM). In addition, the dopants mentioned in the present disclosure can be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and / or by implanting with a p-type or n-type dopant after epitaxial growth. Unintentional addition is, for example, due to the design of the manufacturing process.

[0078] Those of ordinary skill in the art should understand that other components can be added based on the embodiments described below. For example, in the case where it is not specifically stated, the description of "forming a second layer on a first layer" may include an embodiment in which the first layer and the second layer are in direct contact, or may include an embodiment in which there are other layers between the first layer and the second layer and they are not in direct contact with each other. In addition, the up-and-down relationship of each layer may change depending on the operation or use of the structure or component in different orientations. Furthermore, in the present disclosure, the description that a layer "substantially consists of X material" means that the main composition of the layer is X material, but does not exclude the inclusion of dopants or inevitable impurities.

[0079] Figure 1 FIG. 7 is a schematic structural diagram of a semiconductor stack 10 according to an embodiment of the present disclosure. The semiconductor stack 10 includes a first semiconductor layer 100 and a second semiconductor layer 102. The second semiconductor layer 102 is adjacent to the first semiconductor layer 100. In this embodiment, a surface 100a of the first semiconductor layer 100 is in direct contact with a surface 102a of the second semiconductor layer 102. There is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the second semiconductor layer 102.

[0080] In this embodiment, the first semiconductor layer 100 comprises a first group III-V semiconductor material. The first group III-V semiconductor material is, for example, a binary group III-V semiconductor material. The first group III-V semiconductor material is a material composed of elements from groups III and V of the periodic table. Group III elements may be gallium (Ga) or indium (In). Group V elements may be arsenic (As) or phosphorus (P), and preferably do not contain nitrogen (N). In one embodiment, the first semiconductor layer 100 is substantially composed of a first group III-V semiconductor material, for example, substantially composed of a binary group III-V semiconductor material. In one embodiment, the first semiconductor layer 100 may comprise InP, preferably substantially composed of InP. The first semiconductor layer 100 may comprise dopants. In one embodiment, the first semiconductor layer 100 comprises a first dopant and a second dopant. In this embodiment, the concentration of the second dopant in the first semiconductor layer 100 is greater than the concentration of the first dopant. The first dopant is, for example, carbon (C), and the second dopant is, for example, hydrogen (H). Therefore, the first semiconductor layer 100 can have a surface with stable properties and fewer epitaxial defects, for example, a surface that can be used for epitaxial layer growth. In one embodiment, the first semiconductor layer 100 may include a third dopant. The third dopant is, for example, silicon (Si). In one embodiment, the dopants in the first semiconductor layer 100 may each have an independent density of about 1 × 10⁻⁶. 16 / cm 3 To approximately 1×10 19 / cm 3 The doping concentration, for example, is about 5 × 10⁻⁶. 16 / cm 3 Approximately 5×10 17 / cm 3 The doping concentration, or approximately 6 × 10⁻⁶. 17 / cm 3 Approximately 5×10 18 / cm 3 The doping concentration, etc. In one embodiment, the concentration of the third dopant in the first semiconductor layer 100 is less than 1 × 10⁻⁶. 19 / cm 3 For example, in approximately 6×10 16 / cm 3 To approximately 1×10 17 / cm 3 The range. When the dopants in the first semiconductor layer 100 have an appropriate doping concentration, the first semiconductor layer 100 can have better conductivity characteristics. In one embodiment, the conductivity type of the first semiconductor layer 100 is N-type.

[0081] In this embodiment, the second semiconductor layer 102 comprises a second group III-V semiconductor material. The second semiconductor layer 102 is, for example, a binary group III-V semiconductor material. The second group III-V semiconductor material is a material composed of elements from groups III and V of the periodic table. The group III element may be gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), and preferably does not contain nitrogen (N). The second group III-V semiconductor material differs from the first group III-V semiconductor material. In one embodiment, all constituent elements of the second group III-V semiconductor material are different from those of the first group III-V semiconductor material. In one embodiment, the second semiconductor layer 102 is substantially composed of a second group III-V semiconductor material, for example, substantially composed of a binary group III-V semiconductor material. In one embodiment, the second semiconductor layer 102 may comprise GaAs, preferably substantially composed of GaAs. The second semiconductor layer 102 may contain multiple dopants. The multiple dopants in the second semiconductor layer 102 can each independently have approximately 5 × 10⁻⁶ ppm. 15 / cm 3 To approximately 1×10 20 / cm 3 The doping concentration, for example, is about 1 × 10⁻⁶. 17 / cm 3 To approximately 1×10 18 / cm 3 The doping concentration is approximately 1 × 10⁻⁶. 18 / cm 3 To approximately 1×10 19 / cm 3 The doping concentration, or approximately 1 × 10⁻⁶. 19 / cm 3 To approximately 1×10 20 / cm 3 The doping concentration. When the dopants in the second semiconductor layer 102 have an appropriate doping concentration, the second semiconductor layer 102 can have better conductivity characteristics. The dopants in the second semiconductor layer 102 may include silicon (Si), zinc (Zn), carbon (C), or hydrogen (H), etc. In one embodiment, the conductivity type of the second semiconductor layer 102 is N-type. In some embodiments, the first semiconductor layer 100 and the second semiconductor layer 102 have the same conductivity type, for example, both are P-type or N-type. In one embodiment, the resistivity of the second semiconductor layer 102 is above 10⁻⁶. 7 Ω·cm or more and 10 9 In the range below Ω·cm, for example, in 10 8 Ω·cm or higher.

[0082] In some embodiments, both the first semiconductor layer 100 and the second semiconductor layer 102 contain a first dopant, a second dopant, and a third dopant. In some embodiments, the concentration of the third dopant in the second semiconductor layer 102 is higher than the concentration of the third dopant in the first semiconductor layer 100. In some embodiments, the concentration of the second dopant in the second semiconductor layer 102 is higher than the concentration of the second dopant in the first semiconductor layer 100. In some embodiments, the concentration of the first dopant in the second semiconductor layer 102 is lower than the concentration of the first dopant in the first semiconductor layer 100. The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). By containing specific dopants, the first semiconductor layer 100 and the second semiconductor layer 102 can obtain appropriate conductivity characteristics and epitaxial quality.

[0083] On the other hand, the first semiconductor layer 100 has a first lattice constant L1, and the second semiconductor layer 102 has a second lattice constant L2. In this embodiment, the first lattice constant L1 is greater than the second lattice constant L2, and the difference ΔL% between the first lattice constant L1 and the second lattice constant L2 is 2% or more, preferably 2.5% or more or 3% or more, and less than 10%, preferably less than 5%. Specifically, the difference between the first lattice constant L1 and the second lattice constant L2 can be calculated using the following formula: The lattice constants mentioned above are obtained by measuring the X-ray diffraction patterns of semiconductor materials at a temperature of 300 K. Only a few semiconductor compounds are listed here for reference, as shown in Table 1 below.

[0084] Table 1

[0085]

[0086] The first semiconductor layer 100 and the second semiconductor layer 102 can be formed by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In this embodiment, the first semiconductor layer 100 is directly formed on the second semiconductor layer 102, which serves as a substrate. The thickness of the first semiconductor layer can be less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm, and can be greater than 1 μm. In one embodiment, the thickness of the first semiconductor layer is 2 μm. When the thickness of the first semiconductor layer 100 is within the above range, it can have better structural stability and further reduce the impact caused by lattice mismatch. The thickness of the second semiconductor layer 102 can be in the range of about 50 μm to about 1000 μm, for example, about 100 μm to about 400 μm or about 150 μm to about 350 μm. Setting the thickness within the above range allows for a more stable semiconductor structure to be subsequently grown on it. When the semiconductor stack 10 containing the first semiconductor layer 100 and the second semiconductor layer 102 is observed using an electron microscope, fewer epitaxial defects can be observed on the surface of the first semiconductor layer 100. In some embodiments, under X-ray diffraction analysis (XRD), the full width at half maximum (FWHM) of the first semiconductor layer 100 can be below 500 arcsec, preferably below 350 arcsec, more preferably below 300 arcsec, and in the range of more than 100 arcsec to less than 200 arcsec. Therefore, the surface of the first semiconductor layer 100 is more suitable for the growth of other epitaxial layers. Specifically, the first semiconductor layer 100 or the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 can be used as a growth substrate for semiconductor devices.

[0087] Figure 2AThis is a partial structural schematic diagram of a semiconductor element 20 according to an embodiment of the present invention. In this embodiment, the semiconductor element 20 includes a first semiconductor layer 100, a third semiconductor layer 204, and a light-emitting structure 206. The composition of the first semiconductor layer 100, etc., can be referred to the foregoing description of the first semiconductor layer 100, and will not be repeated here. Furthermore, the third semiconductor layer 204 and the light-emitting structure 206 can be sequentially formed on the first semiconductor layer 100 by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In some embodiments, the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 are sequentially formed on a second semiconductor layer 102 as described in the previous embodiment, and then the second semiconductor layer 102 is removed to form the structure described above. Figure 2A The structure shown.

[0088] like Figure 2A As shown, the third semiconductor layer 204 is located on and adjacent to the first semiconductor layer 100. In this embodiment, there are no other structures (such as buffer layers) between the first semiconductor layer 100 and the third semiconductor layer 204. The third semiconductor layer 204 may contain a third III-V semiconductor material. The third III-V semiconductor material is, for example, a binary III-V semiconductor material. The third III-V semiconductor material is a material composed of elements from groups three and five of the periodic table. The group three elements may be gallium (Ga) or indium (In). The group five elements may be arsenic (As) or phosphorus (P), and preferably do not contain nitrogen (N). In some embodiments, the third III-V semiconductor material is the same as the aforementioned first III-V semiconductor material. More specifically, in some embodiments, the third semiconductor layer 204 is substantially composed of a third III-V semiconductor material, for example, substantially composed of a binary III-V semiconductor material. In one embodiment, the third semiconductor layer 204 may comprise InP, preferably the third semiconductor layer 204 is substantially composed of InP. Furthermore, the third semiconductor layer 204 may also comprise multiple dopants. In some embodiments, the multiple dopants in the third semiconductor layer 204 may each independently have approximately 5 × 10⁻⁶ ppm. 16 / cm 3 Approximately 5×10 18 / cm 3The doping concentration, for example, is about 5 × 10⁻⁶. 17 / cm 3 Approximately 2×10 18 / cm 3 The doping concentration, or approximately 5 × 10⁻⁶. 16 / cm 3 Approximately 5×10 17 / cm 3 The doping concentration is specified. In some embodiments, both the first semiconductor layer 100 and the third semiconductor layer 204 contain a first dopant, a second dopant, and a third dopant. The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). In some embodiments, forming the third semiconductor layer 204 on the first semiconductor layer 100 helps to further stabilize the epitaxial surface quality. In some embodiments, the third semiconductor layer 204 can serve as a window layer to improve the luminous efficiency of the semiconductor device 20, and the third semiconductor layer 204 is transparent to the light emitted by the light-emitting structure 206. Furthermore, in one embodiment, the conductivity type of the third semiconductor layer 204 is N-type.

[0089] The light-emitting structure 206 includes an active structure 210, a fourth semiconductor layer 208, and a fifth semiconductor layer 212. The active structure 210 may comprise a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. When the semiconductor device 20 is in operation, the active structure 210 emits radiation. This radiation is preferably infrared light, such as near-infrared (NIR) light. Specifically, when the radiation is near-infrared light, it can have a peak wavelength between 800 nm and 1700 nm, such as: 810 nm, 840 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, etc. The active structure 110 may contain a Group IV III-V semiconductor material, preferably the active structure 110 is substantially composed of a Group IV III-V semiconductor material. The Group IV III-V semiconductor material is a material composed of elements from Groups III and V of the periodic table. The Group III element can be gallium (Ga) or indium (In). The Group V element can be arsenic (As) or phosphorus (P), preferably without nitrogen (N). The Group IV III-V semiconductor material can be a quaternary Group III-V semiconductor material. In some embodiments, the active structure 110 may comprise a quaternary III-V semiconductor material (such as InGaAsP or AlGaInAs), preferably the active structure 110 is substantially composed of a quaternary III-V semiconductor material (such as InGaAsP or AlGaInAs).

[0090] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 are located on opposite sides of the active structure 210, and the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may have opposite conductivity types. For example, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be n-type semiconductors and p-type semiconductors, respectively, to provide electrons and holes. Alternatively, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be p-type semiconductors and n-type semiconductors, respectively, to provide holes and electrons. The fourth semiconductor layer 208 and the third semiconductor layer 204 may have the same conductivity type, such as both being n-type semiconductor layers. Furthermore, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively contain a group III-V semiconductor material and a group III-V semiconductor material. The group III-V semiconductor material and the group III-V semiconductor material may be binary, ternary, or quaternary group III-V semiconductor materials, respectively. Group III-V semiconductor materials refer to materials composed of elements from groups III and V of the periodic table. Group III elements may be gallium (Ga) or indium (In). Group V elements may be arsenic (As) or phosphorus (P), and preferably do not contain nitrogen (N). In one embodiment, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively comprise quaternary semiconductor materials (such as InGaAsP, AlGaInP, or AlGaInAs), and preferably the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are substantially composed of quaternary semiconductor materials (such as InGaAsP, AlGaInP, or AlGaInAs).

[0091] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 have different conductivity types by adding different dopants. Specifically, the dopants include magnesium (Mg), zinc (Zn), silicon (Si), tellurium (Te), etc., but are not limited to these. In some embodiments, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 can be doped by in-situ doping during epitaxial growth and / or by implanting with P-type or N-type dopants after epitaxial growth. In one embodiment, the dopants in the fourth semiconductor layer 208 and the fifth semiconductor layer 212 can each independently have a conductivity of approximately 2 × 10⁻⁶. 17 / cm 3 To approximately 1×10 20 / cm 3 The doping concentration, for example, is about 5 × 10⁻⁶. 17 / cm 3 Approximately 5×10 19 / cm 3 The doping concentration.

[0092] In some embodiments, an etch barrier layer may be further disposed between the first semiconductor layer 100 and the light-emitting structure 206. Please refer to... Figure 2A For example, an etch stop layer (not shown) may be located between the first semiconductor layer 100 and the third semiconductor layer 204. Then, the first semiconductor layer 100 may be removed according to the requirements of the device structure, thereby forming a structure as shown below. Figure 2B The semiconductor element 20' shown is illustrated. By providing an etch barrier layer, damage to the third semiconductor layer 204 and the light-emitting structure 206 can be avoided when removing the first semiconductor layer 100. Next, the semiconductor element 20' may include a bonding layer (not shown) and be bonded to a support substrate through the bonding layer for subsequent fabrication processes. In one embodiment, the semiconductor element 20' only includes the following: Figure 2B The structure shown does not have a supporting substrate. In some embodiments, the etch stop layer comprises a Group 7 III-V semiconductor material. The Group 7 III-V semiconductor material may be a ternary or quaternary Group 7 III-V semiconductor material. Group 7 III-V semiconductor materials are materials composed of elements from Groups 3 and 5 of the periodic table. Group 3 elements may be aluminum (Al), gallium (Ga), or indium (In). Group 5 elements may be arsenic (As) or phosphorus (P), preferably without nitrogen (N). The etch stop layer preferably comprises a Group 5 element different from the Group 5 element in the composition of the first semiconductor layer 100. In one embodiment, the etch stop layer may comprise a ternary Group 7 III-V semiconductor material (e.g., InGaAs), preferably the etch stop layer is substantially composed of a ternary semiconductor material (e.g., InGaAs).

[0093] Based on the above, since the first semiconductor layer 100 can have a surface with a low defect density, it is more suitable as a base layer for growing semiconductor epitaxial layers. Specifically, when a third semiconductor layer 204 and other semiconductor layers are further formed on the first semiconductor layer 100, each semiconductor layer can still have good epitaxial quality.

[0094] Figure 3 This is a schematic diagram of a semiconductor element according to an embodiment of the present invention. In this embodiment, the semiconductor element 30 includes a first semiconductor layer 300, a third semiconductor layer 304, a light-emitting structure 306, a window layer 314, a first electrode 318, and a second electrode 320. The composition of the first semiconductor layer 300, the third semiconductor layer 304, and the light-emitting structure 306 can be referred to the foregoing descriptions of the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206, respectively, and will not be repeated here. Specifically, the composition of the fourth semiconductor layer 308, the active structure 310, and the fifth semiconductor layer 312 in the light-emitting structure 306 can be referred to the foregoing descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212, respectively.

[0095] In this embodiment, the window layer 314 is located on the light-emitting structure 306, adjacent to the fifth semiconductor layer 312 in the light-emitting structure 306. Furthermore, the conductivity type of the window layer 314 is opposite to that of the third semiconductor layer 304; for example, when the window layer 314 is a P-type semiconductor layer, the third semiconductor layer 304 is an N-type semiconductor layer. The window layer 314 can serve as a light extraction layer, thereby further improving the luminous efficiency of the semiconductor device 30. In addition, the window layer 314 is transparent to the light emitted by the light-emitting structure 306.

[0096] The first electrode 318 and the second electrode 320 can be electrically connected to an external power source, and are also electrically connected to the light-emitting structure 306. In this embodiment, the first electrode 320 is adjacent to the window layer 314, and the second electrode 318 is adjacent to the first semiconductor layer 300, but this is not a limitation. Furthermore, the materials of the first electrode 318 and the second electrode 320 can be the same or different, and may include, for example, transparent conductive materials, metals, or alloys. Transparent conductive materials include metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), zinc aluminum oxide (AZO), zinc tin oxide (ZTO), zinc gallium oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO), or indium zinc oxide (IZO). Metals may include, for example, gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu), or nickel (Ni). Examples of alloys include germanium-nickel alloy (GeAuNi), beryllium alloy (BeAu), germanium-gold alloy (GeAu), and zinc-gold alloy (ZnAu).

[0097] Figure 4 This is a schematic diagram of a semiconductor element according to an embodiment of the present invention. In this embodiment, the semiconductor element 40 includes a first semiconductor layer 400, a second semiconductor layer 402, a third semiconductor layer 404, a light-emitting structure 406, a window layer 414, a contact layer 416, a first electrode 420, and a second electrode 418. The main difference between the semiconductor element 40 and the aforementioned semiconductor element 30 is that it further includes a second semiconductor layer 402 and a contact layer 416. The composition of the first semiconductor layer 400, the second semiconductor layer 402, the third semiconductor layer 404, the light-emitting structure 406, the window layer 414, the first electrode 420, and the second electrode 418 can be referred to the description of the foregoing embodiment, and will not be repeated here. Specifically, the composition of the fourth semiconductor layer 408, the active structure 410, and the fifth semiconductor layer 412 in the light-emitting structure 406 can be referred to the foregoing description of the fourth semiconductor layer 408, the active structure 410, and the fifth semiconductor layer 412, respectively.

[0098] Contact layer 416 is located between the first electrode 420 and the window layer 414 for conducting current. Contact layer 416 may have the same conductivity type as window layer 414, such as a P-type semiconductor layer. In this embodiment, contact layer 416 is adjacent to the first electrode 420. Specifically, contact layer 416 may be a doped or undoped semiconductor material layer, and may contain a Group III-V semiconductor material. The Group III-V semiconductor material may be a binary or ternary Group III-V semiconductor material, such as GaAs or InGaAs. When the first electrode 420 contains a metal or alloy, an ohmic contact can be formed between the first electrode 420 and contact layer 416, enabling good electrical contact between the first electrode 420 and the light-emitting structure 406.

[0099] Figures 5A to 5B This is a schematic cross-sectional view of a method for manufacturing a semiconductor stack according to an embodiment of the present invention. Figure 5C This is a flowchart illustrating the fabrication process of a semiconductor stack according to one embodiment. The aforementioned semiconductor stack is, for example, a partial structure of a semiconductor device. Figure 5A and Figure 5B As shown, a second semiconductor layer 502 is first provided, and a first semiconductor layer 500 is formed on the second semiconductor layer 502. A description of the first semiconductor layer 500 and the second semiconductor layer 502 can be found in the descriptions of the first semiconductor layer 100 and the second semiconductor layer 102 in the foregoing embodiments, and will not be repeated here.

[0100] refer to Figures 5A to 5C Step S510 is performed to grow a portion of a first semiconductor layer 500 at a first temperature. The growth of the first semiconductor layer 500 is achieved, for example, by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal-organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). The first temperature is, for example, below 650°C and above 400°C, preferably not exceeding 520°C, and more preferably in the range of 450°C to 510°C or 420°C to 500°C. By growing the first semiconductor layer 500 within the above temperature range, better epitaxial quality can be further obtained.

[0101] Next, step S520 is performed, providing a second temperature higher than the first temperature. The second temperature is, for example, above 700°C and below 850°C, preferably above 750°C, and more preferably within the range of 760°C to 810°C or 780°C to 800°C. In step S520, the epitaxial ambient temperature is adjusted from the first temperature to the second temperature, for example. In some embodiments, the difference between the first temperature and the second temperature is not less than 300°C, thereby achieving a better epitaxial effect. Furthermore, at the second temperature, the growth of the first semiconductor layer 500 may not be performed. In this step, high-temperature tempering is performed by adjusting the ambient temperature to the higher second temperature. Not continuing the growth of the first semiconductor layer 500 at the second temperature allows for stress regulation in the portion of the first semiconductor layer 500 previously grown at the first temperature, reducing epitaxial defects.

[0102] Then, proceed to step S530 to confirm whether the thickness of the first semiconductor layer 500 has reached the predetermined thickness. When the first semiconductor layer 500 has reached the predetermined thickness, the fabrication of the first semiconductor layer 500 and the second semiconductor layer 502 is completed. In some embodiments, the predetermined thickness may be less than 20 μm, preferably less than 10 μm, more preferably less than 5 μm, and may be greater than 1 μm. If the first semiconductor layer 500 has not yet reached the predetermined thickness, proceed to step S540 and repeat steps S510 and S520, for example, repeating steps S510 and S520 at least twice. In some embodiments, steps S510 and S520 may be repeated more than ten times to obtain a semiconductor stack of appropriate thickness and more stable epitaxial quality. Furthermore, the number of times steps S510 and S520 are repeated may be less than thirty times.

[0103] Based on the above, by heating and cooling during the preparation of the first semiconductor layer 500, it is not necessary to use other buffer structures or manufacturing processes to adjust for problems such as stress caused by lattice mismatch between the first semiconductor layer 500 and the second semiconductor layer 502, and a structure with good epitaxial quality can be obtained.

[0104] In some embodiments, the stack of the first semiconductor layer 500 and the second semiconductor layer 502 can be used as a substrate layer for subsequent epitaxial structure growth as needed, such as directly forming a light-emitting structure on the stack of the first semiconductor layer 500 and the second semiconductor layer 502.

[0105] like Figure 5DAs shown, a third semiconductor layer 504 can be further formed on the first semiconductor layer 500 and the second semiconductor layer 502. A description of the third semiconductor layer 504 can be found in the description of the third semiconductor layer 204 in the foregoing embodiments, and will not be repeated here. As previously mentioned, the light-emitting structure can be formed on the third semiconductor layer 504. One side of the first semiconductor layer 500 is adjacent to the second semiconductor layer 502, and the other side is adjacent to the third semiconductor layer 504. Surface 500a of the first semiconductor layer 500 directly contacts surface 502a of the second semiconductor layer 502, and another surface 500b directly contacts surface 504a of the third semiconductor layer 504.

[0106] Figure 5E This is a graph showing the relationship between elemental concentration and depth for a portion of a semiconductor device according to an embodiment of the present invention. Specifically, Figure 5E It includes such as Figure 5D The results of secondary ion mass spectrometry (SIMS) analysis of a portion of the semiconductor device shown are as follows. Figure 5E As shown, based on the thickness and order of each layer in the semiconductor device, it can be roughly divided into a first region Z1, a second region Z2, and a third region Z3. Specifically, the first region Z1 corresponds to the second semiconductor layer 502, the second region Z2 corresponds to the first semiconductor layer 500, and the third region Z3 corresponds to the third semiconductor layer 504. In this embodiment, both the first semiconductor layer 500 and the third semiconductor layer 504 contain multiple dopants and are substantially composed of InP, while the second semiconductor layer 502 contains multiple dopants and is substantially composed of GaAs. The aforementioned dopants include at least a first dopant, a second dopant, and a third dopant. The first dopant is carbon (C) and is represented by C1, the second dopant is hydrogen (H) and is represented by C2, and the third dopant is silicon (Si) and is represented by C3. The concentrations of C1, C2, and C3 of the first, second, and third dopants are shown in [reference needed]. Figure 5E The left vertical axis. In this embodiment, the first and second dopants are unintentional dopants, and the third dopant is intentional dopant.

[0107] The first semiconductor layer 500, with a single-layer structure, is grown in the manner described above, such that the unintentionally doped first and second dopants have a density greater than 10 in the first semiconductor layer 500. 16 / cm 3 The doping concentration is such that the carbon (C) concentration curve exhibits a pattern resembling periodic variation. For example... Figure 5EAs shown, in the second region Z2, the concentration of the second dopant is higher than the concentration of the first dopant, meaning the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the carbon (C) concentration. Furthermore, the concentration of the third dopant in the second region Z2 is lower than the concentration of the third dopant in the first region Z1 and also lower than the concentration of the third dopant in the third region Z3. That is, the silicon (Si) concentration in the first semiconductor layer 500 is lower than the silicon (Si) concentration in the second semiconductor layer 502 or the third semiconductor layer 504. On the other hand, in the second region Z2, the concentration of the second dopant is higher than the concentration of the third dopant, meaning the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the silicon (Si) concentration.

[0108] Figure 5F for Figure 5E A magnified view of the concentration curve of the first dopant (carbon (C)) within the dashed box area of ​​region Z2 in the second region. (See diagram below.) Figure 5F As shown, in this embodiment, the concentration distribution of the first dopant (carbon (C)) contains at least i local maxima (concentration C as indicated in the figure). L1 C L2 ..., C Li ) and i local minima (concentration C as shown in the figure) M1 C M2 ..., C Mi ), where i is, for example, a positive integer greater than or equal to 5, in such cases... Figure 5F In the local region shown, i=8. Local maxima and local minima alternate, and either local maximum is greater than either local minimum. For example... Figure 5E As shown, at some depths in the second region Z2, the concentration of the third dopant is less than some local maxima; at some depths in the second region Z2, the concentration of the third dopant is greater than some local minima. That is, in the second region Z2, the concentration of the third dopant can be less than some local maxima and greater than some local minima.

[0109] like Figure 5E As shown, in this embodiment, the silicon (Si) doping concentration in the first semiconductor layer 500 is 1×10⁻⁶. 17 / cm 3 Below, and in approximately 5×10 16 / cm 3 Approximately 9×10 16 / cm 3 The range; carbon (C) concentration is approximately 4 × 10⁻⁶. 16 / cm 3 Approximately 9×10 16 / cm 3 The range; hydrogen (H) concentration is approximately 1 × 10⁻⁶. 17 / cm 3Approximately 5×10 17 / cm 3 The range. On the other hand, in some embodiments, the first region Z1, the second region Z2, and the third region Z3 also contain unavoidable impurities, such as oxygen (O), which are not shown here for simplicity. In one embodiment, the oxygen (O) concentration in the first region Z1, the second region Z2, and the third region Z3 is distributed within a range of 3 × 10⁻⁶. 15 / cm 3 to 2×10 16 / cm 3 Within this range, it approaches the detection limit of secondary ion mass spectrometry (SIMS) analysis.

[0110] Figure 6 This is a schematic diagram of the packaging structure of a semiconductor device according to an embodiment of the present invention. Please refer to... Figure 6 The package structure 600 includes a semiconductor element 60, a package substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a package material 68. The package substrate 61 may contain ceramic or glass material. The package substrate 61 has a plurality of through-holes 62. The through-holes 62 may be filled with a conductive material such as metal to facilitate conductivity and / or heat dissipation. The carrier 63 is located on one side of the surface of the package substrate 61 and also contains a conductive material such as metal. The contact structure 66 is located on the other side of the surface of the package substrate 61. In this embodiment, the contact structure 66 includes contact pads 66a and 66b, and the contact pads 66a and 66b are electrically connected to the carrier 63 through the through-holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between contact pads 66a and 66b. The semiconductor element 60 is located on the carrier 63 and may be the semiconductor element described in any embodiment of the present invention. In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b. The semiconductor element 60 is electrically connected to the second portion 63b of the carrier 63 via a bonding wire 65. The bonding wire 65 may be made of a metal, such as gold, silver, copper, aluminum, or an alloy containing at least any of the above elements. An encapsulation material 68 covers the semiconductor element 60, providing protection for the semiconductor element 60. Specifically, the encapsulation material 68 may contain a resin material such as epoxy resin, silicone resin, etc. The encapsulation material 68 may also contain a plurality of wavelength-converting particles (not shown) to convert the first light emitted by the semiconductor element 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0111] The semiconductor element of the present invention can be applied to products in the fields of lighting, medical, display, communication, sensing, and power systems, such as lamps, monitors, mobile phones, tablet computers, automotive dashboards, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, medical devices, etc.

[0112] Based on the above, according to some embodiments of the present invention, a semiconductor structure with good surface epitaxial quality can be provided, for example, it can be used as a substrate for semiconductor devices, and it is beneficial to further reduce the production cost of semiconductor devices. According to some embodiments of the present invention, a semiconductor device and its manufacturing method can be provided, which achieves excellent technical effects in adjusting the stress caused by lattice mismatch between heteroepitaxial layers, and can avoid defects in the epitaxial layer at the interface.

[0113] While the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the invention. Those skilled in the art will understand that modifications or alterations can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the appended claims. Furthermore, the above embodiments can be combined or substituted with each other where appropriate, and are not limited to the specific embodiments described. For example, the parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of protection of the present invention.

Claims

1. A semiconductor component, characterized in that, Include: The first semiconductor layer comprises a first III-V group semiconductor material; A light-emitting structure is located on the first semiconductor layer and includes an active structure; The second semiconductor layer is located below the first semiconductor layer and contains a second III-V group semiconductor material; as well as The third semiconductor layer is located between the first semiconductor layer and the light-emitting structure and contains a third III-V group semiconductor material; The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer contain a first dopant and a second dopant. The concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the second semiconductor layer, and the concentration of the first dopant in the first semiconductor layer is greater than the concentration of the first dopant in the third semiconductor layer. The concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the second semiconductor layer, and the concentration of the second dopant in the first semiconductor layer is lower than the concentration of the second dopant in the third semiconductor layer.

2. The semiconductor component of claim 1, wherein the light-emitting structure emits near-infrared light with a peak wavelength between 800 nm and 1700 nm.

3. The semiconductor component of claim 1, wherein the second III-V semiconductor material is different from the first III-V semiconductor material.

4. The semiconductor component of claim 1, wherein the light-emitting structure includes a fourth semiconductor layer located between the third semiconductor layer and the active structure, and the fourth semiconductor layer comprises a binary, ternary, or quaternary III-V group semiconductor material.

5. The semiconductor component of claim 1, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer further comprise a third dopant.

6. The semiconductor component of claim 1, wherein the doping concentrations of the first dopant and the second dopant in the first semiconductor layer may be between 1 × 10⁻⁶. 16 / cm 3 Up to 1×10 19 / cm 3 between.

7. The semiconductor component of claim 1, wherein the first dopant and the second dopant comprise silicon (Si), zinc (Zn), carbon (C), or hydrogen (H).

8. The semiconductor component of claim 1, wherein in the second semiconductor layer, the concentration of the first dopant is lower than the concentration of the second dopant.

9. The semiconductor component of claim 1, wherein in the third semiconductor layer, the concentration of the first dopant is lower than the concentration of the second dopant.

10. A packaging structure for a semiconductor component, comprising: carrier; A semiconductor component, located on the carrier and being a semiconductor component as described in any one of claims 1 to 9; and Encapsulation material is applied to the semiconductor component.

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