Internal spacer liner for gate-all-around devices.

Abstract

Semiconductor devices (e.g., gate-all-around (GAA) devices), processing tools for fabricating GAA devices, methods for fabricating GAA devices, and internal spacer liners and internal spacers for GAA devices are described. The methods include forming an internal spacer liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure has a plurality of recessed semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) arranged alternately in a plurality of stacked pairs. The internal spacer liner includes a crystalline silicon-containing liner formed by a selective epitaxial growth (SEG) process. The crystalline silicon-containing liner can be doped with a dopant (e.g., with a p-type dopant or an n-type dopant). One or more steps of the methods described herein are performed in situ in an integrated processing tool system.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to semiconductor devices. More particularly, embodiments of the present disclosure are directed to gate-all-around (GAA) devices and methods of forming GAA devices with inner spacer liners. [Background technology]

[0002] Transistors are key components of most integrated circuits. A transistor's drive current, and therefore its speed, is proportional to its gate width, so faster transistors generally require larger gate widths. Therefore, there is a trade-off between transistor size and speed. To address the conflicting goals of maximum drive current and minimum size, "fin" field-effect transistors (finFETs) were developed. FinFETs feature a fin-shaped channel region that allows for a significant increase in transistor size without significantly increasing the transistor's footprint, and are currently used in many integrated circuits. However, FinFETs have their own drawbacks.

[0003] As transistor device feature sizes continue to shrink to enable increased circuit density and higher performance, improved transistor device structures are required to improve capacitive coupling and reduce adverse effects such as parasitic capacitance and off-state leakage current. Examples of transistor device structures include planar structures, fin field-effect transistor (FinFET) structures, and horizontal gate-all-around (hGAA) structures. The hGAA device structure includes multiple lattice-matched channels suspended in a stacked configuration and connected by source / drain regions. The hGAA structure offers good electrostatic control and can be widely adopted in complementary metal oxide semiconductor (CMOS) wafer fabrication.

[0004] One of the challenges in CMOS wafer fabrication (and GAA formation) is reducing parasitic capacitance. The selective etching process used to form the recesses / cavities for internal spacer formation is very difficult, and as a result of the selective etching process, silicon (Si) loss at the corners of the recesses / cavities in the semiconductor material layer is unavoidable. The silicon (Si) loss shrinks the current path and may even lead to current crowding if the silicon (Si) loss at the corners is not properly handled. Furthermore, silicon (Si) loss significantly degrades direct current (DC) performance. The DC performance is further degraded as the channel layer becomes thinner.

[0005] Therefore, there is a need for a method to reduce the amount of silicon (Si) loss in gate-all-around (GAA) devices. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to a method of manufacturing an electronic device. In some embodiments, the method includes forming a crystalline silicon-containing liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure includes a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers, arranged alternately in a plurality of stacked pairs. In some embodiments, the crystalline silicon-containing liner is formed along the recessed semiconductor material layers and the corresponding channel layers by a selective epitaxial growth (SEG) process. The method includes forming an interior spacer directly on the crystalline silicon-containing liner, the interior spacer adjacent to the source and drain regions.

[0007] Further embodiments of the present disclosure are directed to methods of manufacturing electronic devices. In some embodiments, the method includes forming a crystalline silicon-containing liner within a superlattice structure formed on an upper surface of a semiconductor substrate. The superlattice structure includes a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers, arranged alternately in a plurality of stacked pairs. In some embodiments, the crystalline silicon-containing liner is formed along the recessed semiconductor material layers and the corresponding plurality of channel layers by a selective epitaxial growth (SEG) process. The method further includes forming interior spacers directly on the crystalline silicon-containing liner, the interior spacers adjacent to source and drain regions; etching portions of the interior spacers; removing the replacement metal gate and the recessed semiconductor material layer from the semiconductor substrate; and then etching inner sidewall portions of the crystalline silicon-containing liner.

[0008] Further embodiments of the present disclosure are directed to a processing tool. In some embodiments, the processing tool includes a central transfer station including a robot configured to move semiconductor substrates; a plurality of processing stations, each connected to the central transfer station and providing a processing region separated from the processing region of an adjacent processing station, the plurality of processing stations including a pre-clean chamber, a selective epitaxial growth (SEG) chamber, and a low-k silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber; and a controller connected to the central transfer station and the plurality of processing stations. The controller is configured to operate the robot to move semiconductor substrates between the processing stations and to control processing cycles for forming a crystalline silicon-containing liner for a gate-all-around (GAA) device. The processing cycle includes pre-cleaning a semiconductor substrate; forming a crystalline silicon-containing liner within a superlattice structure formed on an upper surface of the semiconductor substrate by a selective epitaxial growth (SEG) process, the superlattice structure including a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers arranged alternately in a plurality of stacked pairs, the semiconductor material layers including silicon germanium (SiGe) and the channel layers including silicon (Si); forming the crystalline silicon-containing liner along the recessed semiconductor material layers and the corresponding plurality of channel layers; and forming an inner spacer directly on the crystalline silicon-containing liner, the inner spacer adjacent to a source region and a drain region.

[0009] So that the above-mentioned features of the present disclosure can be understood in detail, a more particular description of the present disclosure, briefly summarized above, can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the present disclosure is susceptible to other equally effective embodiments, and therefore, the accompanying drawings depict only typical embodiments of the present disclosure and should not be considered as limiting the scope of the present disclosure. [Brief explanation of the drawings]

[0010] [Figure 1] 1 illustrates a process flow diagram of a method for forming an electronic device according to one or more embodiments. [Figure 2A] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2B] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2C] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2D] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2E] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2F] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2G] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2H] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2I] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2J] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2K] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 2L] 1 shows a schematic cross-sectional view of an electronic device according to one or more embodiments. [Figure 3] 1 shows a schematic top view of an exemplary multi-chamber processing system for forming electronic devices, according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] To facilitate understanding, the same reference numerals have been used, where possible, to designate identical elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further description.

[0012] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following specification. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0013] As used herein and in the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that when reference is made to a substrate, it may refer to only a portion of the substrate, unless the context clearly indicates otherwise. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate upon which one or more films or features have been deposited or formed.

[0014] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers and may be referred to as "semiconductor substrates." Substrates may be exposed to pretreatment processes that polish, etch, reduce, oxidize, hydroxylate (or otherwise generate or graft target chemical moieties to impart chemical functionality), anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, the present disclosure also allows any of the disclosed film processing steps to be performed on underlying layers formed on the substrate, as disclosed in more detail below. The term "substrate surface" is intended to include such underlying layers, as the context indicates. Thus, for example, if a film / layer or partial film / layer is being deposited on a substrate surface, the exposed surface of the newly deposited film / layer would be the substrate surface. What a given substrate surface comprises will depend on what film is being deposited and the particular chemistry used.

[0015] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.

[0016] As used herein, the term "in situ" refers to processes that are all performed within the same processing chamber or within various processing chambers connected as part of a processing system, such that each process is performed without a vacuum break. As used herein, the term "ex situ" refers to processes that are performed in at least two different processing chambers, such that one or more processes are performed with an interruption due to a vacuum break. In some embodiments, the processes are performed without a vacuum break or exposure to ambient air.

[0017] A transistor is a circuit component or element that is often formed on a semiconductor device. In addition to capacitors, inductors, resistors, diodes, conductive lines, or other elements, transistors are formed on the semiconductor device according to the circuit design. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise doped regions of a substrate and exhibit a doping profile appropriate for a particular application. The gate is disposed above the channel region and includes a gate dielectric interposed between the gate electrode and the channel region in the substrate.

[0018] As used herein, the term "field effect transistor" or "FET" refers to a transistor that uses an electric field to control the electrical behavior of the device. Enhancement mode field effect transistors generally exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by an electric field within the device, which is generated by a voltage difference between the body and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers exit the channel; and the gate (G), which adjusts the conductivity of the channel. Conventionally, the current entering the channel at the source (S) is known as I S , the current entering the channel at the drain (D) is I D The drain-source voltage is called V DSBy applying a voltage to the gate (G), a current (i.e., I D ) can be controlled.

[0019] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET). It has an insulated gate, and the voltage across the gate determines the device's conductivity. This ability to change conductivity with the amount of applied voltage is used to amplify or switch electronic signals. MOSFETs rely on the change in charge concentration due to the capacitance of a metal-oxide-semiconductor (MOS) between a body electrode and a gate electrode located above the body and insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET contains two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be p-type or n-type, but both are the same type, opposite the type of the body region. The source and drain are highly doped (unlike the body), and a "+" symbol is indicated after the doping type.

[0020] If the MOSFET is an n-channel or nMOS FET, the source and drain are n+ regions and the body is a p region. If the MOSFET is a p-channel or pMOS FET, the source and drain are p+ regions and the body is an n region. The source is so named because it is the source of charge carriers (electrons for n-channel and holes for p-channel) that flow through the channel; similarly, the drain is where the charge carriers exit the channel.

[0021] As used herein, the term "fin field-effect transistor (FinFET)" refers to a MOSFET transistor fabricated on a substrate with gates located on two or three sides of the channel, forming a double-gate or triple-gate structure. FinFET devices are given the generic name FinFET because the channel region forms a "fin" on the substrate. FinFET devices have fast switching times and high current densities.

[0022] The term "gate all-around (GAA)" is used herein to refer to an electronic device, e.g., a transistor, in which a gate material surrounds the entire surface of the channel region. The channel region of a GAA transistor may comprise a nanowire or nanoslab, or a nanosheet, a rod-like channel, or other suitable channel configuration known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or bars, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0023] As used herein, the term "nanowire" refers to a wire having a diameter of nanometers (10 -9Nanowires refer to nanostructures on the order of 1000 nanometers. Nanowires may also be defined as those with a length to width ratio greater than 1000. Alternatively, nanowires may be defined as structures whose thickness or diameter is limited to tens of nanometers or less, but whose length is not. Nanowires are used in transistor and some laser applications and, in one or more embodiments, are made of semiconducting, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and nonvolatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness in the range of about 0.1 nm to about 1000 nm.

[0024] Embodiments of the present disclosure are illustrated by figures that illustrate devices (e.g., transistors) and processes for forming transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely examples of possible uses of the disclosed processes, and one of ordinary skill in the art will recognize that the disclosed processes are not limited to the applications illustrated.

[0025] FIG. 1 illustrates a process flow diagram of a method 100 for forming an electronic device (e.g., a gate-all-around (GAA) device) according to some embodiments of the present disclosure. Method 100 is described below with reference to FIGS. 2A-2L, which illustrate stages in the fabrication of a semiconductor structure according to some embodiments of the present disclosure. FIGS. 2A-2L illustrate cross-sectional views of a GAA device according to one or more embodiments. Method 100 may be part of a multi-step fabrication process for semiconductor devices. Thus, method 100 may be performed in any suitable processing chamber coupled to a cluster tool, such as processing system 400 shown in FIG. 3. Processing system 400 may include processing chambers for fabricating semiconductor devices, such as chambers configured for pre-clean, etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), selective epitaxial growth (SEG), oxidation, or any other suitable chamber used in the fabrication of semiconductor devices.

[0026] FIG. 2A shows a semiconductor substrate 200 having a top surface 202. As used herein, the terms "semiconductor substrate 200" and "substrate 200" may be used interchangeably. Optionally, method 100 includes one or more etching processes (step 102), further described below, to form substrate 200 shown in FIG. 2A. In some embodiments, substrate 200 may be a bulk semiconductor substrate. As used herein, the term "bulk semiconductor substrate" refers to a substrate made entirely of semiconductor material. A bulk semiconductor substrate may include any suitable semiconductor material and / or combination of semiconductor materials for forming a semiconductor structure. For example, a semiconductor layer may be formed of crystalline silicon (e.g., Si <100> or Si <111> The semiconductor substrate 200 may comprise one or more materials such as silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or unpatterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconductor materials. In some embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate 200 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 200 comprises one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although some examples of materials that may form the substrate are described herein, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic device) may be constructed may fall within the spirit and scope of the present disclosure.

[0027] In some embodiments, the semiconductor material can be a doped material, such as n-type doped silicon (n-Si) or p-type doped silicon (p-Si). In some embodiments, the substrate can be doped using any suitable process, such as an ion implantation process. As used herein, the term "n-type" refers to a semiconductor created by introducing an electron-donor element into an intrinsic semiconductor during fabrication. The term n-type comes from the negative charge of the electrons. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the wells (or holes). Relative to n-type semiconductors, p-type semiconductors have a higher hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers. In one or more embodiments, the dopant is selected from one or more of boron (B), gallium (Ga), phosphorus (P), arsenic (As), other semiconductor dopants, or combinations thereof. In some embodiments, the substrate may be doped to provide a high dose of dopant at a first location on the surface of the substrate 200 to prevent turn-on of the parasitic bottom device.

[0028] At least one superlattice structure 204 is formed on the top surface 202 of the substrate 200. The superlattice structure 204 includes a plurality of semiconductor material layers 226 and a corresponding plurality of channel layers 224, arranged alternately in a plurality of stacked pairs. As used herein, the terms "semiconductor material layer 226" and "dummy semiconductor layer 226" may be used interchangeably. In some embodiments, the plurality of stacked layers includes silicon (Si), germanium (Ge), and silicon germanium (SiGe). In some embodiments, the silicon germanium (SiGe) may contain germanium (Ge) at a mole fraction amount in the range of 0% to 50%. In some embodiments, the plurality of semiconductor material layers 226 includes silicon germanium (SiGe), and the plurality of channel layers 224 includes silicon (Si). In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include any number of lattice-matched material pairs suitable for forming the superlattice structure 204. In some embodiments, the plurality of semiconductor material layers 226 and the corresponding plurality of channel layers 224 include between about 2 pairs and about 50 pairs of lattice-matched materials. In some embodiments, the plurality of channel layers 224 may be doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga).

[0029] In one or more embodiments, the thickness of the semiconductor material layers 226 and the channel layers 224 is in the range of about 2 nm to about 50 nm, including any subranges and values ​​therebetween, such as in the range of about 3 nm to about 20 nm, or in the range of about 2 nm to about 15 nm.

[0030] 2A also shows a replacement gate structure (e.g., dummy gate structure 209) formed and patterned on the superlattice structure 204. The dummy gate structure 209 defines a channel region of a transistor device. The dummy gate structure 209 may be formed using any suitable conventional deposition and patterning process known in the art. The dummy gate structure 209 may comprise any suitable material known to those skilled in the art. In some embodiments, the dummy gate structure 209 may comprise one or more of a sacrificial oxide layer 210 and a dummy gate polysilicon layer 212. In some embodiments, sidewall spacers 214 are formed along the outer sidewalls of the dummy gate structure 209. The sidewall spacers 214 in some embodiments comprise a suitable insulating material known in the art, such as, for example, silicon nitride, silicon oxide, silicon oxynitride, or silicon carbide. In some embodiments, the sidewall spacers 214 are formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, or low-pressure chemical vapor deposition.

[0031] 2B , in step 104, in some embodiments, source trenches 232 and drain trenches 234 are formed adjacent to superlattice structure 204 on opposite sides thereof. In some embodiments, source trench 232 is formed adjacent to a first end surface of superlattice structure 204, and drain trench 234 is formed adjacent to a second, opposite end surface of superlattice structure 204. In the embodiment shown in FIG. 2B , one of source trench 232 or drain trench 234 is not shown on the front surface of superlattice structure 204. The other end surface of superlattice structure 204 includes the other of source trench 232 or drain trench 234. In some embodiments, source trench 232 and drain trench 234 include source and drain regions formed therein, respectively. Stated another way, in some embodiments, a source region is formed in source trench 232 and a drain region is formed in drain trench 234. In some embodiments, the source and / or drain regions are formed from any suitable semiconductor material, such as, but not limited to, silicon, germanium, silicon germanium, silicon phosphorous, or silicon arsenic. In some embodiments, the source and drain regions may be separately doped with one or more of phosphorus (P), arsenic (As), boron (B), and gallium (Ga). In some embodiments, the source and drain regions may be formed using any suitable deposition process, such as an epitaxial deposition process.

[0032] 2C, in step 106, a portion of semiconductor material layer 226 is isotropically cavity etched to form recessed semiconductor material layer 226′. In one or more embodiments, an opening may be formed by isotropically etching under superlattice structure 204. In some embodiments, superlattice structure 204 includes alternating layers of silicon (Si) (e.g., channel layers 224) and silicon germanium (SiGe) (e.g., semiconductor material layers 226), which are isotropically etched to form a cavity opening under superlattice structure 204, for example, by a dry etching process, a wet etching process, an RIE process, or a combination thereof. In some embodiments, the dry etching process includes using a fluorine-based etchant such as HF, CF, SF, CHF, CHF, CF, other fluorine-containing etchants, or a combination thereof. In some embodiments, the wet etching process includes using an etchant including nitric acid (HNO), ammonium hydroxide (NHOH), ammonium fluoride (NHF), hydrogen peroxide (HO), other suitable etchants, or combinations thereof. In some embodiments, the etching process is controlled by factors such as duration, temperature, pressure, source power, bias voltage, bias power, etchant flow rate, and / or other suitable parameters to remove a desired amount of semiconductor material layer 226. In some embodiments, the amount of semiconductor material layer 226 removed in step 106 is controlled by the duration of the etching process to ensure that a sufficient channel length L is maintained for forming a metal gate stack in subsequent processing steps.

[0033] In some embodiments, a pre-cleaning process may be performed after cavity etching of the semiconductor material layer in step 106 and before inner spacer liner and inner spacer formation in step 108. The pre-cleaning process may include any suitable pre-cleaning process known to those skilled in the art. In some embodiments, the pre-cleaning process includes etching a portion of the plurality of semiconductor material layers 226 with dilute hydrofluoric acid (dilute hydrogen fluoride (HF)) (including greater than 100:1, e.g., 130:1 dilute hydrogen fluoride (HF)) to etch away native oxide on the substrate and form a hydrophobic surface. In some embodiments, the pre-cleaning process may include conventional plasma etching or a remote plasma-assisted dry etching process (e.g., a SiCoNi® etching process available from Applied Materials, Inc., Santa Clara, California). In a SiCoNi® etching process, the device is exposed to plasma species of H, NF, and / or NH (e.g., plasma-excited hydrogen and fluorine species). For example, in some embodiments, the device may be subjected to simultaneous exposure to plasmas of H, NF, and NH. The SiCoNi™ etch process may be performed in a SiCoNi™ pre-clean chamber that may be incorporated into one of a variety of multi-processing platforms, including, for example, the Centura™, Dual ACP, Producer™ GT, and Endura™ platforms available from Applied Materials.

[0034] The wet etching process may include a hydrofluoric (HF) acid last process (i.e., a so-called "HF last" process), in which an HF etch of the surface is performed, leaving the surface hydrogen terminated. Alternatively, any other liquid-based pre-epitaxial pre-cleaning process may be employed. In some embodiments, the process includes a sublimation etch for native oxide removal. The etching process may be plasma-based or thermal-based. The plasma treatment may be any suitable plasma (e.g., conductively coupled plasma, inductively coupled plasma, microwave plasma).

[0035] 2D, in step 110, after the semiconductor material layer cavity etch in step 106 and, optionally, after the pre-clean process in step 108, inner spacer liner 250 is formed. Inner spacer liner 250 is particularly useful in nMOS FET structures, pMOS FET structures, and GAA devices, although described in that context, inner spacer liner 250 is not limited to these applications.

[0036] Embodiments of the present disclosure are directed to inner spacer liners that improve overall GAA device performance. Some embodiments are directed to selective inner spacer liner growth before inner spacer formation to compensate for silicon (Si) corner loss during recess / cavity etching. Some embodiments advantageously provide full ion / current loss recovery by growing the selective inner spacer liner before inner spacer formation.

[0037] The embodiments of the present disclosure provide an overall lower effective capacitance (C effSome embodiments are directed to inner spacer liner configurations with GAA device dimensions below 3 nm that provide an overall lower effective capacitance (C ) compared to conventional inner spacers where no inner spacer liner is present in a comparable GAA device. eff The present invention is directed to an inner spacer liner configuration that advantageously has a spacer liner along the sidewall. The presence of the inner spacer liner along the sidewall is believed to improve the window of the wire-release process, which subsequently benefits static random-access memory (SRAM) yield.

[0038] In some embodiments, a crystalline silicon-containing liner 250 is formed along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224, and an interior spacer 260 is formed directly on the crystalline silicon-containing liner 250. In some embodiments, the interior spacer 260 is adjacent to the source trench 232 and the drain trench 234.

[0039] 1 and 2D , in some embodiments, in step 110, a crystalline silicon-containing liner 250 is formed by performing a selective epitaxial growth (SEG) process to form the crystalline silicon-containing liner 250 along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224. The SEG process may include any method of depositing or growing a monocrystalline film, where the deposited film adopts the same lattice structure and orientation as the substrate, as known to those skilled in the art. In one or more embodiments, the crystalline silicon-containing liner 250 is selectively formed along the recessed semiconductor material layer 226′ and the corresponding plurality of channel layers 224, and is not selectively formed along the sidewall spacers 214.

[0040] The SEG process can be performed until the crystalline silicon-containing liner 250 is formed to a desired thickness. In some embodiments, the crystalline silicon-containing liner 250 has a thickness in the range of 0.5 nm to 3 nm, including all subranges and values ​​therebetween. In some embodiments, the thickness of the crystalline silicon-containing liner 250 varies according to the amount of silicon (Si) loss.

[0041] For example, in some embodiments, the crystalline silicon-containing liner 250 has a thickness of about 1 nm when there is about 1 nm of silicon (S) loss. In certain embodiments, where the crystalline silicon-containing liner 250 has a thickness of about 1 nm when there is about 1 nm of silicon (S) loss, the GAA device has a reduced effective capacitance (C) of the GAA device, measured in fF / μm (femtofarads per micrometer), compared to a GAA device without an inner spacer liner. eff In other embodiments, the crystalline silicon-containing liner 250 has a thickness of about 2 nm when there is about 1 nm of silicon (S) loss. In a particular embodiment, where the crystalline silicon-containing liner 250 has a thickness of about 2 nm when there is about 1 nm of silicon (S) loss, the GAA device has a reduced effective capacitance (C) of the GAA device, measured in fF / μm, compared to a GAA device without an inner spacer liner. eff ) is reduced.

[0042] In one or more embodiments, the crystalline silicon-containing liner 250 is doped with a dopant. Doping the crystalline silicon-containing liner 250 with a p-type or n-type dopant has been found to advantageously improve the alternating current (AC) and direct current (DC) performance of the GAA device. In embodiments where the dopant comprises an n-type dopant, the n-type dopant includes, but is not limited to, one or more of phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), or lithium (Li). In embodiments where the dopant comprises a p-type dopant, the p-type dopant includes, but is not limited to, one or more of boron (B), aluminum (Al), gallium (Ga), or indium (In). In some embodiments, the p-type dopant includes boron (B) and the n-type dopant includes phosphorus (P).

[0043] The dopant may have any suitable dopant concentration. 19 atoms / cm 3 or more, for example, 10 20 atoms / cm 3 , 10 21 atoms / cm 3 , or 10 22 atoms / cm 3 The dopant concentration is

[0044] 1 and 2E, in some embodiments, in step 112, inner spacers 260 are formed directly on the crystalline silicon-containing liner 250. In some embodiments, the inner spacers 260 are adjacent to the source trench 232 and the drain trench 234.

[0045] The inner spacer 260 may comprise any suitable insulating material known in the art, such as a low-κ dielectric material. In one or more embodiments, the low-κ dielectric material has a κ value of 4.2 or less. In some embodiments, the low-κ dielectric material of the inner spacer 260 comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics. In one or more embodiments, the low-κ dielectric material of the inner spacer 260 comprises one or more of silicon oxycarbide (SiOC) or silicon oxynitride (SiON). In some embodiments, the inner spacer 260 is formed using any suitable conventional deposition and patterning process known in the art, such as atomic layer deposition, plasma-enhanced atomic layer deposition, plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, isotropic deposition, or the like. In some embodiments, the inner spacer 260 comprises a thickness in the range of 2 nm to 5 nm, including all subranges and values ​​therebetween.

[0046] The inner spacers 260 may be deposited on the crystalline silicon-containing liner 250 by any suitable deposition process known to those skilled in the art. In some embodiments, the inner spacers 260 are formed by a chemical vapor deposition process at a temperature ranging from 400° C. to 650° C., including all subranges and values ​​therebetween.

[0047] In some embodiments, the interior spacers 260 are conformally deposited. As used herein, the term "conformal" means that a layer conforms to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of a layer deposited on the sidewalls of a feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate. In some embodiments, the interior spacers 260 are deposited by a thermal CVC process with conformality within a range of 70% to 90%. In this context, conformality within a range of 70% to 90% means that the ratio of the average thickness of the layer deposited on the sidewalls of a feature to the average thickness of the same deposited layer on the field (or top surface) of the substrate is within a range of 70% to 90%.

[0048] The inner spacer 260 can be any suitable shape, including but not limited to, circular, square, rectangular, or other polygonal shapes.

[0049] In some embodiments, the inner spacer 260 is substantially free of seams and / or voids. In this context, "substantially free" means that, on an atomic basis, less than about 5%, less than about 4%, less than about 3%, less than about 2%, less than about 1%, less than about 0.5%, and less than about 0.1% of the total composition of the inner spacer 260 comprises seams and / or voids.

[0050] 1 and 2F, in step 114, method 100 includes etching a portion of inner spacer 260 to form etched inner spacer 260'. The etching process of step 114 may include any suitable etching process, including, but not limited to, a pre-clean process, a wet etching process, or a dry etching process described herein.

[0051] Referring to Figure 2G, method 100 includes a source / drain epitaxial growth and interlayer dielectric formation process (step 116), a replacement metal gate formation and polysilicon removal (step 118). In Figure 2G, the GAA device includes highly doped epitaxial source / drain junctions 270, a protective dielectric layer 272, such as silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof, on the highly doped epitaxial source / drain junctions 270, and an interlayer dielectric 274 formed on the protective dielectric layer 272. Such processes and layers shown in Figure 2G are known to those skilled in the art.

[0052] In some embodiments, in step 118, dummy gate structure 209 is removed to expose the channel region of superlattice structure 204. The above-described layers 270, 272, and 274 protect source / drain trenches 232 / 234 during removal of dummy gate structure 209. Dummy gate structure 209 can be removed using any conventional etching process, such as a pre-clean process, a wet etch process, or a dry etch process described herein. In some embodiments, dummy gate structure 209 includes one or more of sacrificial oxide layer 210 and dummy gate polysilicon layer 212, and the entire dummy gate structure 209 is removed by a selective etching process. In embodiments, if dummy gate structure 209 includes sidewall spacers, such as sidewall spacer 214, sidewall spacer 214 is not removed in step 114. Figure 2H illustrates the removal of sacrificial oxide layer 210. The sacrificial oxide layer 210 may be removed by any suitable etching process, including, but not limited to, the pre-cleaning process, wet etching process, or dry etching process described herein.

[0053] 2I, in step 120, the method 100 includes removing the recessed semiconductor material layer 226′ in the superlattice structure 204. In step 120, the recessed semiconductor material layer 226′ is selectively etched between the plurality of channel layers 224 in the superlattice structure 204. For example, if the superlattice structure 204 is composed of a silicon (Si) layer and a silicon germanium (SiGe) layer, the silicon germanium (SiGe) is selectively etched to form channel nanowires. The recessed semiconductor material layer 226′, which includes, for example, silicon germanium (SiGe), can be removed using any well-known etchant that is selective to the plurality of channel layers 224. Here, the etchant etches the recessed semiconductor material layer 226′ at a much faster rate than the plurality of channel layers 224. In some embodiments, a pre-clean process, a selective dry etch process, or a wet etch process as described herein may be used. In some embodiments, when the plurality of channel layers 224 is silicon (Si) and the recessed semiconductor material layer 226′ is silicon germanium (SiGe), the silicon germanium layer may be selectively removed using a wet etchant such as, but not limited to, a carboxylic acid / nitric acid / HF solution and a citric acid / nitric acid / HF solution.

[0054] In one or more embodiments, removal of the semiconductor material layers 226 (and / or recessed semiconductor material layer 226′) leaves voids between the channel layers 224, as shown in FIG. 2I. The voids between the channel layers 224 have a thickness of about 3 nm to about 20 nm, including all subranges and values ​​therebetween. The remaining channel layers 224 form a vertical array of channel nanowires coupled to the source / drain regions in the source / drain trenches 232, 234. The channel nanowires extend parallel to the top surface 202 of the substrate 200 and are aligned with each other to form a single column of channel nanowires.

[0055] Referring to FIG. 2J , in step 122, the method 100 includes etching a portion of the crystalline silicon-containing liner 250 to form an etched crystalline silicon-containing liner 250′. In one or more embodiments, the portion of the crystalline silicon-containing liner 250 etched in step 122 is a portion previously formed along the recessed semiconductor material layer 226′, which was removed in step 120 shown in FIG. 2I. In one or more embodiments, the portion of the crystalline silicon-containing liner 250 previously formed along the recessed semiconductor material layer 226′ (removed in step 120 shown in FIG. 2I) may be referred to as an inner sidewall or inner sidewall portion. The portion of the crystalline silicon-containing liner 250 formed along the plurality of channel layers 224 is not etched.

[0056] In step 122, the portion of the crystalline silicon-containing liner 250 formed along the inner sidewall is etched to form an etched crystalline silicon-containing liner 250′, which reduces the effective capacitance (C) of the GAA device, measured in fF / μm (femtofarads per micrometer), compared to a GAA device without an inner spacer liner. eff ) is advantageously found to be reduced.

[0057] For example, in some embodiments, the crystalline silicon-containing liner 250 has a thickness of about 1 nm when there is about 1 nm of silicon (S) loss. In a particular embodiment where the crystalline silicon-containing liner 250 has a thickness of about 1 nm when there is about 1 nm of silicon (Si) loss, and the portion of the crystalline silicon-containing liner 250 formed along the inner sidewall is etched in step 122 to form an etched crystalline silicon-containing liner 250', the GAA device has a lower effective capacitance (C measured in fF / μm) compared to a GAA device without an inner spacer liner. eff ) is reduced.

[0058] In other embodiments, the crystalline silicon-containing liner 250 has a thickness of about 2 nm when there is about 1 nm of silicon (S) loss. In a particular embodiment where the crystalline silicon-containing liner 250 has a thickness of about 2 nm when there is about 1 nm of silicon (Si) loss, and the portion of the crystalline silicon-containing liner 250 formed along the inner sidewall is etched in step 122 to form an etched crystalline silicon-containing liner 250', the GAA device has a lower effective capacitance (C measured in fF / μm) compared to a GAA device without an inner spacer liner. eff ) is reduced.

[0059] 2K, in step 124, the method 100 includes forming an interlayer dielectric (ILD) 276 on each of the remaining channel layers 224. In some embodiments, the ILD 276 encapsulates the remaining channel layers 224 and covers all portions of the channel layers 224 except for portions (e.g., interior sidewalls) covered by the etched crystalline silicon-containing liner 250′. The ILD 276 can be deposited using conventional chemical vapor deposition methods (e.g., plasma-enhanced chemical vapor deposition and low-pressure chemical vapor deposition). In one or more embodiments, the ILD 276 is formed from any suitable dielectric material, such as, but not limited to, undoped silicon oxide, doped silicon oxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride.

[0060] Referring to FIG. 2L , at step 126, the method 100 includes one or more processes known to those skilled in the art to complete the hGAA device, such as replacement metal gate formation. In one or more embodiments, a high-κ dielectric 278 is formed on the ILD 276. The high-κ dielectric 278 can be any suitable high-κ dielectric material deposited by any suitable deposition technique known to those skilled in the art. In some embodiments, the high-κ dielectric 278 includes hafnium oxide. In some embodiments, a conductive material, such as titanium nitride (TiN), tungsten (W), cobalt (Co), or aluminum (Al), is deposited on the high-κ dielectric. The conductive material can be formed using any suitable deposition process, such as, but not limited to, atomic layer deposition (ALD), to ensure that a layer of uniform thickness is formed around each of the plurality of channel layers 224.

[0061] Additional embodiments of the present disclosure are directed to a processing system 400 and described methods (e.g., method 100) for forming a crystalline silicon-containing liner 250 and inner spacer 260 of an electronic device (e.g., a GAA device), as shown in Figure 3. Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Centura®, Dual ACP, Producer® GT, and Endura® platforms available from Applied Materials®, Inc. of Santa Clara, California, although other processing systems may also be utilized. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.

[0062] Processing system 400 may include any dielectric deposition product (DDP) available from Applied Materials, Inc. of Santa Clara, Calif. In some embodiments, processing system 400 includes a low-k silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber. In some embodiments, processing system 400 includes an advanced unit process solution by combining a low-k silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber with a Sym3™ etch system available from Applied Materials, Inc. of Santa Clara, Calif. to provide an integrated tool solution (e.g., an integrated annular CVD deposition and etch processing system).

[0063] In some embodiments, one or more steps of the methods of the present disclosure are performed in situ, as described herein. In some embodiments, one or more steps of the methods of the present disclosure are performed ex situ, as described herein. In some embodiments, one or more steps of method 100 are performed in situ in an integrated processing tool, such as processing system 400. As used herein, the terms “integrated processing tool,” “integrated tool system,” “cluster tool,” “processing tool,” and “processing system 400” may be used interchangeably to refer to processing system 400 shown in FIG. 3 , unless otherwise specified.

[0064] One or more steps of method 100 may be performed in situ by an integrated module within an integrated processing tool system, such as processing system 400. The integrated modules described herein are performed in situ within an integrated processing tool system, such as processing system 400, unless otherwise specified.

[0065] In some embodiments, the processing system 400 includes integrated modules for performing a pre-cleaning process prior to the formation of the inner spacer liner and inner spacers (step 108 of method 100), for selectively forming a crystalline silicon-containing liner (step 110 of method 100), and for forming inner spacers directly on the crystalline silicon-containing liner (step 112 of method 100).

[0066] In some embodiments, the processing system 400 includes integrated modules for cavity etching of the semiconductor material layer (step 106 of method 100), then performing a pre-cleaning process prior to the formation of the inner spacer liner and inner spacers (step 108 of method 100), selectively forming a crystalline silicon-containing liner (step 110 of method 100), and forming inner spacers directly on the crystalline silicon-containing liner (step 112 of method 100).

[0067] In some embodiments, the processing system 400 includes integrated modules for cavity etching of the semiconductor material layer (step 106 of method 100), then performing a pre-cleaning process prior to the formation of the inner spacer liner and inner spacers (step 108 of method 100), selectively forming a crystalline silicon-containing liner (step 110 of method 100), and forming inner spacers directly on the crystalline silicon-containing liner (step 112 of method 100), and etching a portion of the inner spacers (step 114 of method 100).

[0068] In some embodiments, the processing system 400 is also particularly useful for forming contact / sidewall spacers in 3D memory horizontal wordline applications.

[0069] In some embodiments, the steps of the methods described herein are each performed in the same processing chamber. In some embodiments, the steps of the methods described herein are each performed in different processing chambers. In some embodiments, the various processing chambers are connected as part of a processing system. In some embodiments, the steps of the methods described herein are performed without a vacuum break.

[0070] 3 is a schematic top view of an example multi-chamber processing system 400 according to an embodiment of the present disclosure. The processing system 400 generally includes a factory interface 402, load lock chambers 404, 406, transfer chambers 408, 410 with respective transfer robots 412, 414, holding chambers 416, 418, and processing chambers 420, 422, 424, 426, 428, 430. As described in detail herein, wafers within the processing system 400 can be processed within and transferred between various chambers without exposing the wafers to an ambient environment outside the processing system 400 (e.g., an atmospheric ambient environment that may exist within a factory). For example, wafers can be processed within and transferred between various chambers in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low-pressure or vacuum environment between various processes performed on the wafers within the processing system 400. Thus, processing system 400 can provide an integrated solution for any processing of wafers.

[0071] 3, the factory interface 402 includes a docking station 440 and a factory interface robot 442 to facilitate the transfer of substrates. The docking station 440 is configured to accommodate one or more front opening unified pods (FOUPs) 444. In some examples, each factory interface robot 442 generally includes a blade 448 located at one end of each factory interface robot 442 configured to transfer wafers from the factory interface 402 to the load lock chambers 404, 406.

[0072] The load lock chambers 404, 406 have respective ports 450, 452 coupled to the factory interface 402 and respective ports 454, 456 coupled to the transfer chamber 408. The transfer chamber 408 further has respective ports 458, 460 coupled to the holding chambers 416, 418 and respective ports 462, 464 coupled to the processing chambers 420, 422. Similarly, the transfer chamber 410 has respective ports 466, 468 coupled to the holding chambers 416, 418 and respective ports 470, 472, 474, 476 coupled to the processing chambers 424, 426, 428, 430. Ports 454, 456, 458, 460, 462, 464, 466, 468, 470, 472, 474, 476 may be slit valve openings, including slit valves for passing wafers by transfer robots 412, 414 and for providing seals between chambers to prevent gas from passing between them. Generally, every port is open for transferring wafers. The port is closed otherwise.

[0073] The load lock chambers 404, 406, the transfer chambers 408, 410, the holding chambers 416, 418, and the processing chambers 420, 422, 424, 426, 428, 430 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 442 transfers a wafer from a FOUP 444 to the load lock chamber 404 or 406 through port 450 or 452. The gas and pressure control system then pumps down the load lock chamber 404 or 406. The gas and pressure control system further maintains an internal low-pressure or vacuum environment (which may include an inert gas) within the transfer chambers 408, 410 and the holding chambers 416, 418. Thus, pumping down the load lock chambers 404 or 406 facilitates passing wafers between, for example, the atmospheric environment of the factory interface 402 and the low pressure or vacuum environment of the transfer chamber 408 .

[0074] With the wafer in the load lock chamber 404 or 406 pumped down, the transfer robot 412 transfers the wafer from the load lock chamber 404 or 406 to the transfer chamber 408 via port 454 or 456. The transfer robot 412 can then transfer the wafer to and / or between any of the processing chambers 420, 422 via respective ports 462, 464 for processing, and can transfer the wafer to the holding chambers 416, 418 via respective ports 458, 460 for holding awaiting further transfer. Similarly, the transfer robot 414 can access wafers in the holding chambers 416 or 418 via ports 466 or 468, and can transfer wafers to and / or between any of the processing chambers 424, 426, 428, 430 for processing via respective ports 470, 472, 474, 476, and can transfer wafers to the holding chambers 416, 418 via respective ports 466, 468 for holding awaiting further transfer. The transfer and holding of wafers in and between the various chambers can be performed in a low pressure or vacuum environment provided by a gas and pressure control system.

[0075] The processing chambers 420, 422, 424, 426, 428, and 430 may be any suitable chambers for processing wafers. In some embodiments, the processing chambers 420, 422, 424, 426, 428, and 430 include a pre-clean chamber, a selective epitaxial growth (SEG) chamber, a low-k silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber, and an etch chamber. In some embodiments, the processing chamber 420 may perform an annealing process, the processing chamber 422 may perform a cleaning process, and the processing chambers 424, 426, 428, and 430 may perform an epitaxial growth process. In some examples, the processing chamber 422 may perform a cleaning process, the processing chamber 420 may perform an etch process, and the processing chambers 424, 426, 428, and 430 may perform the respective epitaxial growth processes. Processing chamber 422 may be a SiCoNi® pre-clean chamber available from Applied Materials, Inc. of Santa Clara, Calif. Processing chamber 420 may be a Selectra® etch chamber available from Applied Materials, Inc. of Santa Clara, Calif.

[0076] A system controller 490 is connected to the processing system 400 to control the processing system 400 or its components. For example, the system controller 490 can control the operation of the processing system 400 using direct control of the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430 of the processing system 400 or by controlling the controllers associated with the chambers 404, 406, 408, 416, 418, 410, 420, 422, 424, 426, 428, 430. During operation, the system controller 490 enables data collection and feedback from each chamber to adjust the performance of the processing system 400.

[0077] The system controller 490 generally includes a central processing unit (CPU) 492, memory 494, and support circuits 496. The CPU 492 can be any type of general-purpose processor useful in an industrial environment. The memory 494, or non-transitory computer-readable medium, is accessible by the CPU 492 and can be one or more memories, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or other forms of local or remote digital storage. The support circuits 496 are connected to the CPU 492 and can include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be performed by the CPU 492 executing computer instruction codes stored in the memory 494 (or the memory of a particular process chamber) as, for example, software routines under the control of the CPU 492. When the computer instruction codes are executed by the CPU 492, the CPU 492 controls the chamber to perform processes according to various methods.

[0078] Other processing systems may have other configurations. For example, more or fewer processing chambers may be connected to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 408, 410 and holding chambers 416, 418. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as a transfer apparatus within a processing system.

[0079] The processes may generally be stored in the memory of the system controller 490 as software routines that, when executed by a processor, cause the processing chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Some or all of the methods of the present disclosure may also be performed in hardware. Thus, the processes may be implemented in software and executed using a computer system with hardware, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls the operation of the chamber so that the processes are performed.

[0080] One or more embodiments of the present disclosure are directed to a non-transitory computer-readable medium containing instructions that, when executed by a controller of a processing chamber, cause the processing chamber to perform a method described herein, such as method 100.

[0081] The use of the terms "a" and "an" and "the," and similar referents, in the context of describing the materials and methods discussed herein (particularly in the context of the claims below), should be construed to cover both the singular and the plural unless otherwise stated herein or clearly contradicted by context. Recitation of numerical ranges herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually set forth herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "such as") provided herein, is intended only to better describe the materials and methods and does not impose a limitation on the scope unless specifically claimed. No language herein should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0082] Throughout this specification, references to "one embodiment," "certain embodiment," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0083] Although the disclosure herein has been described with reference to particular embodiments, those skilled in the art will recognize that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Accordingly, the disclosure may include modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. 1. A method of manufacturing an electronic device, comprising: forming a crystalline silicon-containing liner within a superlattice structure formed on an upper surface of a semiconductor substrate, the superlattice structure including a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers arranged in alternating stacked pairs, the crystalline silicon-containing liner being formed along the recessed semiconductor material layers and the corresponding channel layers by a selective epitaxial growth (SEG) process; forming inner spacers directly on the crystalline silicon-containing liner, the inner spacers adjacent to source and drain regions; A method comprising:

2. The method of claim 1 , further comprising pre-cleaning the semiconductor substrate before forming the crystalline silicon-containing liner.

3. 3. The method of claim 2, wherein pre-cleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the interior spacer are performed in an integrated tool system without breaking vacuum.

4. The method of claim 1 , wherein the crystalline silicon-containing liner is doped with a dopant comprising a p-type dopant or an n-type dopant.

5. 5. The method of claim 4, wherein the p-type dopant comprises boron (B) and the n-type dopant comprises phosphorus (P).

6. The method of claim 1 , wherein the crystalline silicon-containing liner has a thickness in the range of 0.5 nm to 3 nm.

7. The method of claim 1 , wherein the inner spacer comprises a low-k dielectric material.

8. 10. The method of claim 1, wherein the semiconductor material layer comprises silicon germanium (SiGe) and the channel layer comprises silicon (Si).

9. The method of claim 1 , further comprising etching a portion of the inner spacer and a portion of the crystalline silicon-containing liner.

10. The method of claim 1 , wherein the electronic device is a gate-all-around (GAA) device.

11. 1. A method of manufacturing an electronic device, comprising: Pre-cleaning a semiconductor substrate; and forming a crystalline silicon-containing liner within a superlattice structure formed on an upper surface of the semiconductor substrate, the superlattice structure including a plurality of recessed semiconductor material layers and a plurality of corresponding channel layers arranged in alternating stacked pairs, the crystalline silicon-containing liner being formed along the recessed semiconductor material layers and the corresponding channel layers by a selective epitaxial growth (SEG) process; forming inner spacers directly on the crystalline silicon-containing liner, the inner spacers adjacent to source and drain regions; Etching a portion of the inner spacer; removing the replacement metal gate and the recessed semiconductor material layer on the semiconductor substrate, and then etching an inner sidewall portion of the crystalline silicon-containing liner; A method comprising:

12. 12. The method of claim 11, wherein pre-cleaning the semiconductor substrate, forming the crystalline silicon-containing liner, and forming the interior spacer are performed in an integrated tool system without breaking vacuum.

13. The method of claim 11 , wherein the crystalline silicon-containing liner is doped with a p-type dopant or an n-type dopant.

14. 14. The method of claim 13, wherein the p-type dopant comprises boron (B) and the n-type dopant comprises phosphorus (P).

15. The method of claim 11, wherein the crystalline silicon-containing liner has a thickness in the range of 0.5 nm to 3 nm.

16. The method of claim 11 , wherein the inner spacer comprises a low-k dielectric material.

17. 12. The method of claim 11, wherein the semiconductor material layer comprises silicon germanium (SiGe) and the channel layer comprises silicon (Si).

18. The method of claim 11 , wherein the electronic device is a gate-all-around (GAA) device.

19. 1. A processing tool comprising: a central transfer station including a robot configured to move semiconductor substrates; a plurality of processing stations, each processing station connected to the central transfer station and providing a processing area isolated from the processing areas of adjacent processing stations, the plurality of processing stations including a pre-clean chamber, a selective epitaxial growth (SEG) chamber, and a low-k silicon oxycarbide (SiOC) dielectric chemical vapor deposition (CVD) chamber; a controller connected to the central transfer station and the plurality of processing stations, the controller configured to operate a robot to move the semiconductor substrate between the processing stations and to control processing cycles to form a crystalline silicon-containing liner for a gate-all-around (GAA) device; The processing cycle comprises: pre-cleaning the semiconductor substrate; forming the crystalline silicon-containing liner within a superlattice structure formed on an upper surface of the semiconductor substrate by a selective epitaxial growth (SEG) process, the superlattice structure including a plurality of recessed semiconductor material layers and a corresponding plurality of channel layers arranged alternately in a plurality of stacked pairs, the semiconductor material layers including silicon germanium (SiGe) and the channel layers including silicon (Si); forming the crystalline silicon-containing liner along the recessed semiconductor material layer and the corresponding plurality of channel layers; forming inner spacers directly on the crystalline silicon-containing liner, the inner spacers adjacent to source and drain regions; Processing tools, including:

20. 20. The processing tool of claim 19, wherein the plurality of processing stations further comprises an etching chamber for etching a portion of the inner spacer and a portion of the crystalline silicon-containing liner.

Images