Boost DC-DC current detection circuit
By adding a delay unit and a high-precision response module to the drive control module, the problem of unstable current detection in boost DC-DC converters under transient voltage interference is solved, achieving fast and accurate current sensing and ensuring the stability and accuracy of the loop under interference conditions.
Patent Information
- Application Number
- CN202511124534.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-12
- Publication Date
- 2025-10-31
AI Technical Summary
Existing boost DC-DC converters cannot provide stable current sensing for the loop quickly and accurately under transient voltage disturbances, resulting in loop instability.
By adding a delay unit and a first switching transistor to the drive control module, the conduction of the first switching transistor is controlled by delay. Combined with the delayed conduction of the buffer and the second switching transistor, a high-precision response module and a current output module are formed to ensure the stability and accuracy of current detection.
It can quickly and accurately sense small currents under external interference, ensuring the stability of the loop and the accuracy of current detection, especially maintaining stable output under small duty cycle PWM modulation.
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Figure CN120870651A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of integrated circuit technology, and more particularly to a boost DC-DC current detection circuit. Background Technology
[0002] In recent years, with the continuous emergence of consumer electronics products, the requirements for power management chips in various products have become increasingly stringent. The most important characteristics of power modules are high efficiency and stability. For NFC (Near Field Communication) chips, different communication scenarios require low-power, low-noise, and high-precision power modules to ensure performance. Compared to LDOs (Low Dropout Linear Regulators), DC-DC converters offer advantages such as high conversion efficiency, low loss, and a wide input range. Furthermore, they can perform boost conversion, making boost-type DC-DC converters a focus of widespread attention.
[0003] Boost DC-DC converters require a stable closed-loop feedback system to accurately achieve the boost effect. Well-known feedback control modes are divided into voltage-mode and current-mode. In voltage-mode, the output voltage is obtained through a resistor divider, and then fed into an error amplifier along with Vref. This error amplifier is then compared with a fixed-frequency ramp voltage Vramp, and finally sent to the PWM controller to control the gates of the upper and lower transistors. Therefore, voltage-mode operation is simple and easy to implement, but because it can only sense changes in output voltage, its response to inductor current is slow. Therefore, current-mode has a more significant advantage in DC-DC converters. The most common current mode is peak current mode, whose current feedback control system is as follows: Figure 1 As shown, Figure 1 It is a relatively common current feedback control system. Figure 1 Compared to voltage-mode feedback systems, current-mode feedback systems add a current loop, which can respond quickly to changes in inductor current. Meanwhile, when the input-output voltage difference is large (duty cycle greater than 50%), the slope compensation circuit only intervenes to eliminate harmonic oscillations.
[0004] The current sensing circuit is a key module in the entire current loop. Its detection accuracy affects the comparator's toggling time, thus influencing the turn-on time of the upper and lower transistors. Furthermore, the response speed of the current sensing circuit is crucial to the stability of the entire loop. Existing boost DC-DC converters experience transient voltage disturbances during actual operation, such as power-on overshoot or load jumps. This can prevent the current sensing circuit from quickly providing a stable output for the entire loop, especially when the duty cycle is very small.
[0005] Therefore, providing a high-precision boost DC-DC current detection circuit that can quickly and accurately sense small currents even under transient interference and ensure loop stability is a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] To address the aforementioned technical problems, this disclosure provides a boost DC-DC current detection circuit to solve the problem that existing boost DC-DC current detection circuits, in practical operation, cannot quickly and accurately provide a stable output to the loop due to instantaneous voltage interference.
[0007] This disclosure provides a current detection circuit for a boost DC-DC converter, including: a drive control module, a high-precision response module, and a current output module;
[0008] The drive control module includes at least a lower power transistor, a current mirror transistor, and a first switching transistor; wherein, the gate of the lower power transistor is electrically connected to the drive control signal, and a delay unit is electrically connected between the gate of the first switching transistor and the drive control signal;
[0009] The source of the lower power transistor and the source of the current mirror transistor are electrically connected and both are grounded. The drain of the lower power transistor and the source of the first switching transistor are electrically connected. The drain of the first switching transistor and the drain of the current mirror transistor are electrically connected to the high-precision response module. The output of the high-precision response module is electrically connected to the current output module.
[0010] The current output module includes at least a buffer and a second switching transistor. The input terminal of the buffer is electrically connected to the gate of the first switching transistor, and the output terminal of the buffer is electrically connected to the gate of the second switching transistor. The source of the second switching transistor is the induced current output terminal of the current output module.
[0011] Optionally, the gate of the current mirror is electrically connected to a first power supply voltage, and the current mirror is configured to remain normally open.
[0012] Optionally, the high-precision response module includes a Cascode structure.
[0013] Further optionally, the high-precision response module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically connected, and the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are electrically connected to a fixed bias voltage.
[0014] The gate of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, the drain of the first NMOS transistor is electrically connected to the source of the third NMOS transistor, the drain of the second NMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is electrically connected to the current output module.
[0015] The source of the first NMOS transistor is electrically connected to the drain of the first switching transistor, and the source of the second NMOS transistor is electrically connected to the drain of the current mirror transistor.
[0016] Optionally, it also includes an input inductor and a voltage input terminal, with the input inductor electrically connected between the voltage input terminal and the drain of the lower power transistor.
[0017] Optionally, the channel width-to-length ratio of the power transistor and the channel width-to-length ratio of the current mirror transistor are M:1.
[0018] Further optional, a first current mirror unit may also be included;
[0019] The first current mirror unit includes a first PMOS transistor and a second PMOS transistor. The gate of the first PMOS transistor and the gate of the second PMOS transistor are electrically connected and connected to the positive terminal of the current source. The drain of the first PMOS transistor is connected to the positive terminal of the current source. The drain of the second PMOS transistor is electrically connected to the drain of the third NMOS transistor. The source of the first PMOS transistor and the source of the second PMOS transistor are both electrically connected to the second power supply voltage.
[0020] The channel width-to-length ratio of the first PMOS transistor and the channel width-to-length ratio of the second PMOS transistor are 1:N.
[0021] Further optional, a third PMOS transistor and a fourth PMOS transistor may also be included, and the current output module may also include a fifth PMOS transistor and a sixth PMOS transistor;
[0022] The third PMOS transistor and the fifth PMOS transistor form the second current mirror unit, and the fourth PMOS transistor and the sixth PMOS transistor form the third current mirror unit.
[0023] The gates of the third PMOS transistor and the fifth PMOS transistor are electrically connected and connected to the positive terminal of the current source. The drain of the third PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the drain of the fifth PMOS transistor is electrically connected to the drain of the second switching transistor.
[0024] The gate of the fourth PMOS transistor is electrically connected to the gate of the sixth PMOS transistor, and is also electrically connected to the drain of the fourth NMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the drain of the current mirror transistor, and the drain of the sixth PMOS transistor is electrically connected to the drain of the second switching transistor.
[0025] The sources of the third, fourth, fifth, and sixth PMOS transistors are all electrically connected to the second power supply voltage.
[0026] Further optionally, the channel width-to-length ratio of the second PMOS transistor and the channel width-to-length ratio of the third PMOS transistor are 1:1.
[0027] The ratio of the channel width-to-length ratio of the third PMOS transistor to that of the fifth PMOS transistor is n:1.
[0028] The ratio of the channel width-to-length ratio of the fourth PMOS transistor to that of the sixth PMOS transistor is n:1.
[0029] Optionally, the lower power transistor, the current mirror transistor, and the first switching transistor are all laterally diffused metal-oxide-semiconductor transistors.
[0030] The technical solution provided in this disclosure has the following advantages compared with the prior art:
[0031] The boost DC-DC current detection circuit disclosed herein includes a drive control module comprising at least a lower power transistor, a current mirror transistor, and a first switching transistor. The gate of the lower power transistor is electrically connected to the drive control signal, and a delay unit is electrically connected between the gate of the first switching transistor and the drive control signal. By adding a delay unit and a first switching transistor to the drive control module, when the voltage at point A in the circuit is disturbed, the drive control signal passes through a delay unit before controlling the first switching transistor to turn on. This ensures that the voltage at point B is not affected by fluctuations at point A, and that the voltages at both points quickly reach a steady state within a delay unit, improving the accuracy of the induced current. The current output module includes at least a buffer and a second switching transistor. The input terminal of the buffer is electrically connected to the gate of the first switching transistor, and the output terminal of the buffer is electrically connected to the gate of the second switching transistor. The source of the second switching transistor is the induced current output terminal of the current output module. The control signal for the gate of the first switching transistor passes through a buffer before controlling the second switching transistor to turn on, ensuring that the current output to the slope compensation circuit of the boost DC-DC current detection circuit disclosed herein is more stable. This disclosure adds a delay unit to the drive control module, which allows the current sensing loop to turn on after a delay when disturbed, and then outputs the induced current after a delay. This enables the circuit to output a small current quickly and stably even under small duty cycle PWM modulation. When external interference occurs, the first switch is delayed in turning on, and the second switch in the current output module turns on after the first switch, further ensuring the accuracy of the induced current. This current detection circuit can still quickly sense a small current even under interference, thereby ensuring loop stability. Attached Figure Description
[0032] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.
[0033] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 It is a relatively common current feedback control system;
[0035] Figure 2 This is a schematic diagram of an electrical connection structure of a boost DC-DC current detection circuit provided in an embodiment of the present disclosure;
[0036] Figure 3 It is a common type of current detection circuit without operational amplifier in the prior art;
[0037] Figure 4 This is a waveform diagram of the drive control signal for the gate electrical connection of the lower power transistor over time, and a voltage comparison diagram of the drive control module output without and with a delay unit, provided in an embodiment of this disclosure.
[0038] Figure 5 This is a schematic diagram of another electrical connection structure of the current detection circuit of the boost DC-DC provided in the embodiments of this disclosure;
[0039] Figure 6 Is adopted Figure 5 The diagram shows the waveforms of the detected induced current and the current on the input inductor as a function of time obtained by the current detection circuit of the boost DC-DC converter. Detailed Implementation
[0040] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.
[0041] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.
[0042] Please refer to Figure 2 , Figure 2 This is a schematic diagram of an electrical connection structure of a boost DC-DC current detection circuit provided in this embodiment. The boost DC-DC current detection circuit provided in this embodiment includes: a drive control module 10, a high-precision response module 20, and a current output module 30.
[0043] The drive control module 10 includes at least a lower power transistor NLDMP, a current mirror transistor NLDM0, and a first switching transistor NLDM1; wherein, the gate of the lower power transistor NLDMP is electrically connected to the drive control signal CRT, and the gate OEN of the first switching transistor NLDM1 and the drive control signal CRT are electrically connected to a delay unit 101.
[0044] The source of the lower power transistor NLDMP and the source of the current mirror transistor NLDM0 are electrically connected and both are grounded to GND. The drain of the lower power transistor NLDMP and the source of the first switching transistor NLDM1 are electrically connected. The drain of the first switching transistor NLDM1 and the drain of the current mirror transistor NLDM0 are electrically connected to the high-precision response module 20. The output of the high-precision response module 20 is electrically connected to the current output module 30.
[0045] The current output module 30 includes at least a buffer 301 and a second switch NM5. The input terminal of the buffer 301 is electrically connected to the gate OEN of the first switch NM1, and the output terminal of the buffer 301 is electrically connected to the gate of the second switch NM5. The source of the second switch NM5 is the induced current output terminal of the current output module.
[0046] Specifically, the boost DC-DC current detection circuit provided in this embodiment can be applied to the boost DC-DC converter of NFC chips, and can also be applied to other DC-DC converters that operate in current mode. For scenarios that require both light and heavy loads, it can perform the boost function well.
[0047] Existing technologies typically employ two circuit structures for sampling transistor current. One uses an operational amplifier (op-amp) to clamp the voltage between the positive and negative points, ensuring accurate current mirroring. However, because the op-amp generates more power and its bandwidth is limited, the loop response speed is affected. Therefore, existing technologies usually opt for an op-amp-less current sensing circuit, such as... Figure 3 As shown, Figure 3 It is a common type of current detection circuit without operational amplifier in the existing technology, but this circuit structure has certain drawbacks. Figure 3 In this diagram, power transistor NMP is the lower power transistor in the DC-DC converter. The N-transistor drive signal jointly drives both power transistor NMP and current mirror transistor NM0. The ratio of the channel width-to-length ratio of power transistor NMP to that of current mirror transistor NM0 is M:1, ultimately inducing a current of... Different process variations result in varying circuit response times. When a DC-DC converter needs to perform PWM modulation at a low duty cycle, if there is overshoot or interference at point A, the voltages at points A and B cannot quickly reach equality, leading to inaccurate current mirroring and ultimately affecting loop stability. Furthermore, the induced current Isen needs to be obtained from the resistor Rsen, which is greatly affected by temperature and process parameters, thus also causing poor circuit consistency.
[0048] To address the aforementioned problems, this embodiment provides a boost DC-DC current detection circuit, such as... Figure 2 As shown, it includes: a drive control module 10, a high-precision response module 20, and a current output module 30; wherein, the drive control module 10 includes at least a lower power transistor NLDMP, a current mirror transistor NLDM0, and a first switching transistor NLDM1; wherein, the gate of the lower power transistor NLDMP is electrically connected to the drive control signal CRT, and the gate OEN of the first switching transistor NLDM1 is electrically connected to the drive control signal CRT via a delay unit 101; the source of the lower power transistor NLDMP and the source of the current mirror transistor NLDM0 are electrically connected and both are grounded to GND, and the drain of the lower power transistor NLDMP and the first switching transistor NLDM1 are connected to the first switching transistor NLDM1 via a delay unit 101; The source of transistor NLDM1 is electrically connected, and the drain of the first switching transistor NLDM1 and the drain of the current mirror transistor NLDM0 are electrically connected to the high-precision response module 20, respectively. The output of the high-precision response module 20 is electrically connected to the current output module 30. The current output module 30 includes at least a buffer 301 and a second switching transistor NM5. The input of the buffer 301 is electrically connected to the gate OEN of the first switching transistor NLDM1, and the output of the buffer 301 is electrically connected to the gate of the second switching transistor NM5. The source of the second switching transistor NM5 is the induced current output terminal of the current output module, used to output the induced current Isen. In this embodiment, a delay unit 101 and a first switching transistor NLDM1 are added to the drive control module 10. When the voltage at point A is disturbed, the drive control signal CRT passes through a delay unit 101 before controlling the first switching transistor NLDM1 to turn on, so that the voltage at point B is not affected by the fluctuation at point A, and the two points quickly reach a steady state after a delay unit, improving the accuracy of the induced current. Optionally, such as Figure 2 As shown, in this embodiment, the gate of the current mirror transistor NLDM0 is electrically connected to the first power supply voltage VDD, and the current mirror transistor NLDM0 is configured to remain in a normally open state, compared to... Figure 3In existing circuits, the CRT drive control signal only needs to drive the lower power transistor NLDMP, which reduces the requirements for the front-end drive circuit. In this embodiment, a second switch NM5 is added to the current output module 30 for the current detection circuit. The gate of the second switch NM5 is electrically connected to the gate OEN of the first switch NLDM1. The control signal of the gate OEN of the first switch NLDM1 passes through a buffer 301 before controlling the second switch NM5 to turn on. This ensures that the current output from the boost DC-DC current detection circuit provided in this embodiment to the slope compensation circuit is more stable.
[0049] The boost DC-DC current detection circuit provided in this embodiment is compared to... Figure 3 The existing technology, by adding a delay unit 101, allows the current sensing loop to turn on with a delay after being disturbed, and then outputs the induced current Isen after the delay. The source of the second switch NM5 is the induced current output terminal of the current output module 30, used to output the induced current Isen, so that the circuit can quickly and stably output a small current even under small duty cycle PWM modulation. Specifically, when external interference occurs, the first switch NLDM1 is delayed in turning on, and at the same time, the second switch NM5 in the current output module 30 is delayed in turning on after the first switch NLDM1, further ensuring the accuracy of the induced current Isen. This current detection circuit can still quickly sense a small current even under interference, thereby ensuring loop stability. Figure 4 As shown, Figure 4 This is a waveform diagram of the drive control signal for the gate electrical connection of the lower power transistor over time, provided in an embodiment of this disclosure, and a comparison diagram of the voltage output by the drive control module with and without a delay unit. Figure 4 Figure (a) shows the waveform of the drive control signal CRT connected to the gate of the lower power transistor NLDMP over time. It can be seen that in actual operation, due to external parasites, the voltage of the drive control signal CRT is not an absolute square wave. Therefore, if it is not processed in the current sensing circuit, the induced current can easily be disturbed. Figure 4 Figure (b) shows the waveforms of the voltages at points A and B without any delay processing for the first switching transistor NLDM1. Figure 4 Figure (c) shows the waveforms of the voltage at points A and B after delay processing of the first switching transistor NLDM1. From... Figure 4 As can be seen from Figures (b) and (c), without the addition of delay unit 101 to delay the conduction of the first switching transistor NLDM1, the voltages at points A and B are severely affected by external interference. If the duty cycle is small, the switching transistor may not conduct sufficiently, and the voltages at points A and B may not reach consistency for a long time, leading to instability in the current loop. Figure 4The simulation results of Figure (c) show that the voltage at point A and the voltage at point B quickly reach the same level, which significantly improves the circuit's anti-interference capability.
[0050] It should be noted that, in order to improve the response speed of the sampling circuit and make the voltages at points A and B reach consistency as quickly as possible within one pulse width, the drive control signal CRT, which is electrically connected to the gate of the lower power transistor NLDMP, is connected to the gate OEN of the first switching transistor NLDM1 through a delay unit 101, as the gate control signal of the first switching transistor NLDM1. Usually, the delay unit 101 is most commonly an RC delay circuit. This embodiment does not limit the specific circuit structure of the delay unit 101, and the structure of the RC delay circuit in related technologies can be referred to for understanding.
[0051] In some alternative embodiments, please refer to the references. Figure 2 , Figure 4 and Figure 5 , Figure 5 This is a schematic diagram of another electrical connection structure of the current detection circuit of the boost DC-DC provided in this embodiment. In this embodiment, the high-precision response module 20 in the current detection circuit of the boost DC-DC is designed as a Cascode structure. Specifically, the high-precision response module 20 includes a first NMOS transistor NM1, a second NMOS transistor NM2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The gate of the first NMOS transistor NM1 and the gate of the second NMOS transistor NM2 are electrically connected, and the gate of the third NMOS transistor NM3 and the gate of the fourth NMOS transistor NM4 are electrically connected to a fixed bias voltage VB.
[0052] The gate of the first NMOS transistor NM1 is electrically connected to the drain of the third NMOS transistor NM3, the drain of the first NMOS transistor NM1 is electrically connected to the source of the third NMOS transistor NM3, the drain of the second NMOS transistor NM2 is electrically connected to the source of the fourth NMOS transistor NM4, and the drain of the fourth NMOS transistor NM4 is electrically connected to the current output module 30.
[0053] The source of the first NMOS transistor NM1 is electrically connected to the drain of the first switching transistor NLDM1, and the source of the second NMOS transistor NM2 is electrically connected to the drain of the current mirror transistor NLDM0.
[0054] The high-precision response module 20 in this embodiment adopts a low-voltage Cascode structure. The high-precision response module 20 preferably adopts a low-voltage Cascode structure, which can not only ensure that the current mirror transistor NLDM0 consumes a lower voltage margin, but also "shield" the interference signals below because the low-voltage Cascode structure has a larger output impedance than the ordinary current mirror, thus helping to obtain a more stable current in the current detection circuit of this embodiment.
[0055] Optionally, it also includes an input inductor L and a voltage input terminal Vin, with the input inductor L electrically connected between the voltage input terminal Vin and the drain of the lower power transistor NLDMP.
[0056] The channel width-to-length ratio of the lower power transistor NLDMP and the channel width-to-length ratio of the current mirror transistor NLDM0 are M:1, which represents the current I of the lower power transistor NLDMP. P The ratio of the current I0 of the current mirror transistor NLDM0 to the current I0 is M:1.
[0057] Optionally, the current detection circuit of the boost DC-DC converter in this embodiment further includes a first current mirror unit; the first current mirror unit includes a first PMOS transistor PM1 and a second PMOS transistor PM2, the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are electrically connected and connected to the positive terminal of a current source, the drain of the first PMOS transistor PM1 is connected to the positive terminal of the current source, the drain of the second PMOS transistor PM2 is electrically connected to the drain of a third NMOS transistor NM3, and the sources of the first PMOS transistor PM1 and the second PMOS transistor PM2 are both electrically connected to a second power supply voltage VDD2; the channel width-to-length ratio of the first PMOS transistor PM1 and the channel width-to-length ratio of the second PMOS transistor PM2 are 1:N. It can be understood that in this embodiment, the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are electrically connected and connected to the positive terminal of the current source, and the drain of the first PMOS transistor PM1 is connected to the positive terminal of the current source, so current can be input to the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 through the current source. In this embodiment, the gate of the first PMOS transistor PM1 and the gate of the second PMOS transistor PM2 are electrically connected and connected to the positive terminal of the current source, which can obtain a stable bias current and ensure that the first PMOS transistor PM1 and the second PMOS transistor PM2 work in the saturation region, thereby forming a stable current mirror.
[0058] It also includes a third PMOS transistor PM3 and a fourth PMOS transistor PM4, and the current output module 30 also includes a fifth PMOS transistor PM5 and a sixth PMOS transistor PM6; the third PMOS transistor PM3 and the fifth PMOS transistor PM5 form a second current mirror unit, and the fourth PMOS transistor PM4 and the sixth PMOS transistor PM6 form a third current mirror unit; the gate of the third PMOS transistor PM3 and the gate of the fifth PMOS transistor PM5 are electrically connected and connected to the positive terminal of the current source, the drain of the third PMOS transistor PM3 is electrically connected to the drain of the fourth PMOS transistor PM4, and the fifth PMOS transistor PM6... The drain of M5 is electrically connected to the drain of the second switching transistor NM5; the gate of the fourth PMOS transistor PM4 and the gate of the sixth PMOS transistor PM6 are electrically connected, and are also electrically connected to the drain of the fourth NMOS transistor NM4. The drain of the fourth PMOS transistor PM4 is electrically connected to the drain of the current mirror transistor NLDM0. The drain of the sixth PMOS transistor PM6 is electrically connected to the drain of the second switching transistor NM5; the sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, and the sixth PMOS transistor PM6 are all electrically connected to the second power supply voltage VDD2.
[0059] Among them, the channel width-to-length ratio of the second PMOS transistor PM2 and the channel width-to-length ratio of the third PMOS transistor PM3 are 1:1; the channel width-to-length ratio of the third PMOS transistor PM3 and the channel width-to-length ratio of the fifth PMOS transistor PM5 are n:1; the channel width-to-length ratio of the fourth PMOS transistor PM4 and the channel width-to-length ratio of the sixth PMOS transistor PM6 are n:1. Then, as follows... Figure 5 As shown, the channel width-to-length ratio of the first PMOS transistor PM1 and the second PMOS transistor PM2 is 1:N. Therefore, the channel width-to-length ratio of the second PMOS transistor PM2 and the third PMOS transistor PM3 is N:N, and the channel width-to-length ratio of the third PMOS transistor PM3 and the fifth PMOS transistor PM5 is N:N. The ratio of the channel width-to-length ratio of the fourth PMOS transistor PM4 to that of the sixth PMOS transistor PM6 is K: It should be noted that, regarding Figure 5 Other circuit structures for the current detection circuit of the medium boost DC-DC converter are fundamental topics in integrated circuit design and will not be elaborated upon here.
[0060] like Figure 5 The current detection circuit of the boost DC-DC converter shown ultimately obtains the induced current I. senIt consists of two parts: one part is the current of the sixth PMOS transistor PM6, the channel width-to-length ratio of the fourth PMOS transistor PM4, and the channel width-to-length ratio of the sixth PMOS transistor PM6, with a ratio of n:1; the other part is the current of the fifth PMOS transistor PM5, the channel width-to-length ratio of the third PMOS transistor PM3, and the channel width-to-length ratio of the fifth PMOS transistor PM5, with a ratio also of n:1. The current I on the input inductor L... L =I P -I b , among which, I P I is the current of the lower power transistor NLDMP. b This refers to the current of the fourth NMOS transistor NM4 in the Cascode structure of the high-precision response module 20, and also the current of the third PMOS transistor PM3; while the current induced by the current mirror transistor NLDM0 is... Among them, I u The current is the current of the fourth PMOS transistor PM4, while the induced current is... Therefore I b +I u =nI sen Combining the above Get I p =nMI sen Therefore, the input inductor current I L and the output induced current I sen The relationship is: I L =I P -I b =nMI sen -I b Since M is usually a very large positive integer, such as 8000-20000, while I b Very small, in the μA range, the sampling accuracy of the detected induced current reaches over 99%, therefore the current I on the input inductor L is... L The induced current I of the detected output sen It can guarantee a linear relationship and is highly accurate. Furthermore, the current detection circuit of the boost DC-DC converter provided in this embodiment senses the induced current I. sen The induced current I will no longer be affected by the temperature characteristics of the resistor. sen By adding currents in a certain proportion, the small current output to the ramp compensation current connected to the current detection circuit of the boost DC-DC converter in this embodiment becomes more linear, ensuring that the circuit can accurately sense the small current under transient interference.
[0061] Optionally, this embodiment can be used. Figure 5 The current detection circuit of the boost DC-DC converter shown is as follows: Figure 6 As shown, Figure 6 Is adopted Figure 5The diagram shows the waveforms of the detected induced current and the current on the input inductor over time obtained from the current detection circuit of the boost DC-DC converter. Figure 6 The induced current I can be seen in the image. sen The circuit exhibits good linearity and a settling time of only 25ns, indicating that it can quickly and accurately sense large currents.
[0062] In some optional embodiments, the lower power transistor NLDMP, current mirror transistor NLDM0, and first switching transistor NLDM1 in this embodiment are all laterally diffused metal-oxide-semiconductor transistors, i.e., LDMOS transistors. Due to their inherent device characteristics, they can achieve a smaller area compared to ordinary high-voltage transistors, while possessing higher withstand voltage and stability, and are also safer from a product perspective. In this embodiment, the lower power transistor NLDMP, current mirror transistor NLDM0, and first switching transistor NLDM1 in the drive control module 10 are all designed as LDMOS transistors, which can reduce the chip area of the overall detection circuit integration, enhance the product's safety and stability, and thus achieve the effect of reducing product costs and increasing efficiency.
[0063] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0064] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A current detection circuit for a boost DC-DC converter, characterized in that, include: Drive control module, high-precision response module, current output module; The drive control module includes at least a lower power transistor, a current mirror transistor, and a first switching transistor; wherein, the gate of the lower power transistor is electrically connected to a drive control signal, and a delay unit is electrically connected between the gate of the first switching transistor and the drive control signal; The source of the lower power transistor and the source of the current mirror transistor are electrically connected and both are grounded. The drain of the lower power transistor and the source of the first switching transistor are electrically connected. The drain of the first switching transistor and the drain of the current mirror transistor are respectively electrically connected to the high-precision response module. The output terminal of the high-precision response module is electrically connected to the current output module. The current output module includes at least a buffer and a second switching transistor. The input terminal of the buffer is electrically connected to the gate of the first switching transistor, and the output terminal of the buffer is electrically connected to the gate of the second switching transistor. The source of the second switching transistor is the induced current output terminal of the current output module.
2. The current detection circuit for the boost DC-DC converter according to claim 1, characterized in that, The gate of the current mirror is electrically connected to a first power supply voltage, and the current mirror is configured to remain normally open.
3. The current detection circuit for the boost DC-DC converter according to claim 1, characterized in that, The high-precision response module includes a Cascode structure.
4. The current detection circuit for the boost DC-DC converter according to claim 3, characterized in that, The high-precision response module includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; the gate of the first NMOS transistor and the gate of the second NMOS transistor are electrically connected, and the gate of the third NMOS transistor and the gate of the fourth NMOS transistor are electrically connected to a fixed bias voltage. The gate of the first NMOS transistor is electrically connected to the drain of the third NMOS transistor, the drain of the first NMOS transistor is electrically connected to the source of the third NMOS transistor, the drain of the second NMOS transistor is electrically connected to the source of the fourth NMOS transistor, and the drain of the fourth NMOS transistor is electrically connected to the current output module. The source of the first NMOS transistor is electrically connected to the drain of the first switching transistor, and the source of the second NMOS transistor is electrically connected to the drain of the current mirror transistor.
5. The current detection circuit for the boost DC-DC converter according to claim 1, characterized in that, It also includes an input inductor and a voltage input terminal, wherein the input inductor is electrically connected between the voltage input terminal and the drain of the lower power transistor.
6. The current detection circuit for the boost DC-DC converter according to claim 1, characterized in that, The ratio of the channel width-to-length ratio of the lower power transistor to the channel width-to-length ratio of the current mirror transistor is M:
1.
7. The current detection circuit for the boost DC-DC converter according to claim 4, characterized in that, It also includes a first current mirror unit; The first current mirror unit includes a first PMOS transistor and a second PMOS transistor. The gates of the first PMOS transistor and the second PMOS transistor are electrically connected and connected to the positive terminal of the current source. The drain of the first PMOS transistor is connected to the positive terminal of the current source. The drain of the second PMOS transistor is electrically connected to the drain of the third NMOS transistor. The sources of the first PMOS transistor and the second PMOS transistor are both electrically connected to the second power supply voltage. The ratio of the channel width-to-length ratio of the first PMOS transistor to the channel width-to-length ratio of the second PMOS transistor is 1:N.
8. The current detection circuit for the boost DC-DC converter according to claim 7, characterized in that, It also includes a third PMOS transistor and a fourth PMOS transistor, and the current output module also includes a fifth PMOS transistor and a sixth PMOS transistor; The third PMOS transistor and the fifth PMOS transistor form a second current mirror unit, and the fourth PMOS transistor and the sixth PMOS transistor form a third current mirror unit; The gate of the third PMOS transistor and the gate of the fifth PMOS transistor are electrically connected and connected to the positive terminal of the current source. The drain of the third PMOS transistor is electrically connected to the drain of the fourth NMOS transistor, and the drain of the fifth PMOS transistor is electrically connected to the drain of the second switching transistor. The gate of the fourth PMOS transistor is electrically connected to the gate of the sixth PMOS transistor and is also electrically connected to the drain of the fourth NMOS transistor. The drain of the fourth PMOS transistor is electrically connected to the drain of the current mirror transistor, and the drain of the sixth PMOS transistor is electrically connected to the drain of the second switching transistor. The sources of the third, fourth, fifth, and sixth PMOS transistors are all electrically connected to the second power supply voltage.
9. The current detection circuit for the boost DC-DC converter according to claim 8, characterized in that, The ratio of the channel width-to-length ratio of the second PMOS transistor to that of the third PMOS transistor is 1:
1. The ratio of the channel width-to-length ratio of the third PMOS transistor to that of the fifth PMOS transistor is n:
1. The ratio of the channel width-to-length ratio of the fourth PMOS transistor to that of the sixth PMOS transistor is n:
1.
10. The current detection circuit for the boost DC-DC converter according to claim 1, characterized in that, The lower power transistor, the current mirror transistor, and the first switching transistor are all laterally diffused metal-oxide-semiconductor transistors.