Method and system for detecting power amplifier mismatch harmonics and storage medium

Abstract

The application belongs to the field of communication technology, and particularly relates to a power amplifier mismatch harmonic detection method. The method comprises the following steps: connecting a first power detection unit with a coupler through a control unit, adjusting the standing wave ratio of a power amplifier chip to be detected to 1:1 through a tuner, and adjusting the power of an input signal of a vector signal generator until the target power of the power amplifier chip to be detected is reached; connecting a second power detection unit with the coupler through the control unit, adjusting the output standing wave ratio of the power amplifier chip to be detected to a preset ratio through the tuner, and recording the harmonic power of the power amplifier chip to be detected at each phase through the second power detection unit when the tuner is modulated at each interval of a preset phase. Compared with the prior art, the application can accurately test and evaluate the harmonic of the power amplifier chip to be detected under the mismatch standing wave condition, so as to evaluate the harmonic index of the power amplifier chip to be detected.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to a method, system and storage medium for detecting mismatched harmonics in a power amplifier. Background Technology

[0002] With the continuous evolution of mobile communication technology, especially the widespread adoption of 5G, communication systems face increasingly stringent requirements for communication quality. In mobile phone systems, harmonics have a particularly significant impact on communication quality, making the harmonic performance of the mobile phone power amplifier a key factor in ensuring communication performance.

[0003] Currently, most existing mobile phone power amplifiers are limited to 50Ω matching harmonic detection under a 1:1 standing wave ratio. However, in actual mobile phone design, antennas are often located around the perimeter of the phone casing. This layout makes it very easy for the phone's antennas to mismatch during daily use, whether the user is holding the phone, placing it casually, or placing it on a metal surface.

[0004] When a mobile phone antenna mismatch occurs, it significantly degrades the harmonics of the internal power amplifier. According to the explicit requirements of the 3GPP (3rd Generation Partnership Project) regulations, the harmonics of a mobile phone must be kept below -30dBm in all operating environments to ensure unaffected communication quality. Therefore, accurately detecting the harmonics of a mobile phone power amplifier under mismatch standing wave conditions has become a critical problem that urgently needs to be solved in the field of mobile communication technology.

[0005] Therefore, there is an urgent need for a new method, system, and storage medium for detecting mismatch harmonics in power amplifiers to solve the above-mentioned technical problems. Summary of the Invention

[0006] This invention provides a method, system, and storage medium for detecting mismatched harmonics in a power amplifier, aiming to accurately test the harmonics under mismatched standing wave conditions in a power amplifier.

[0007] In a first aspect, the present invention provides a method for detecting mismatch harmonics in a power amplifier. The detection method is based on a mismatch harmonic detection device, which is used to test the input power of a power amplifier chip under test and to perform mismatch detection on the power amplifier chip under test.

[0008] The mismatch harmonic detection device includes a vector signal generator, a first filter, a coupler, a first power detection unit, a second power detection unit, a control unit, and a tuner;

[0009] The output of the vector signal generator is connected to the input of the first filter, and the vector signal generator is used to provide an input signal for the power amplifier chip under test.

[0010] The output terminal of the first filter is used to connect to the input terminal of the power amplifier chip under test, and the first filter is used to filter out noise in the input signal outside the preset frequency band.

[0011] The input terminal of the coupler is used to connect to the output terminal of the power amplifier chip under test, the first output terminal of the coupler is connected to the control unit, and the second output terminal of the coupler is connected to the input terminal of the tuner.

[0012] The control unit is used to connect the input terminal of the first power detection unit or the input terminal of the second power detection unit to the first output terminal of the coupler;

[0013] The first power detection unit is used to detect the input power of the power amplifier chip under test, and the second power detection unit is used to detect the harmonic power of the power amplifier chip under test.

[0014] The tuner is used to adjust the output VSWR of the power amplifier chip under test.

[0015] The detection method includes the following steps:

[0016] S1. The first power detection unit is connected to the coupler through the control unit, and the standing wave ratio of the power amplifier chip under test is adjusted to 1:1 through the tuner. The power of the input signal of the vector signal generator is adjusted until the target power of the power amplifier chip under test is reached.

[0017] S2. The second power detection unit is connected to the coupler through the control unit. The output VSWR of the power amplifier chip under test is adjusted to a preset ratio through the tuner. When the tuner modulates the phase at preset intervals, the harmonic power of the power amplifier chip under test in each phase is recorded by the second power detection unit to obtain the mismatch harmonic detection result.

[0018] Preferably, the second power detection unit includes a second filter and a first spectrum analyzer. The input terminal of the second filter serves as the input terminal of the second power detection unit, and the output terminal of the second filter is connected to the input terminal of the first spectrum analyzer. The second filter is used to filter out the preset frequency band signal of the input signal. The first spectrum analyzer is used to record the harmonic power of the power amplifier chip under test.

[0019] Preferably, the video bandwidth of the first spectrum analyzer is 3MHz, and the resolution bandwidth of the first spectrum analyzer is 1MHz.

[0020] Preferably, the first spectrum analyzer detects the input signal by setting the frequency span of the first spectrum analyzer to 30MHz and the scan time of the first spectrum analyzer to 500ms, and performing detection based on the average power of the resolution bandwidth and the maximum amplitude peak value during the recording of the harmonic power of the power amplifier chip under test.

[0021] Preferably, the preset degree is 15 degrees.

[0022] Preferably, the first power detection unit includes a second spectrum analyzer or a power meter, and the input terminal of the second spectrum analyzer or the input terminal of the power meter serves as the input terminal of the first power detection unit.

[0023] Secondly, the present invention also provides a detection system for mismatch harmonics of a power amplifier chip under test. The detection system includes a mismatch harmonic detection device, a power adjustment module, and an evaluation detection module. The mismatch harmonic detection device is used to test the input power of the power amplifier chip under test and to perform mismatch detection on the power amplifier chip under test.

[0024] The mismatch harmonic detection device includes a vector signal generator, a first filter, a coupler, a first power detection unit, a second power detection unit, a control unit, and a tuner;

[0025] The output of the vector signal generator is connected to the input of the first filter, and the vector signal generator is used to provide an input signal to the power amplifier chip under test.

[0026] The output terminal of the first filter is used to connect to the input terminal of the power amplifier chip under test, and the first filter is used to filter out noise in the input signal outside the preset frequency band.

[0027] The input terminal of the coupler is used to connect to the output terminal of the power amplifier chip under test, the first output terminal of the coupler is connected to the control unit, and the second output terminal of the coupler is connected to the input terminal of the tuner.

[0028] The control unit is used to connect the input terminal of the first power detection unit or the input terminal of the second power detection unit to the second output terminal of the coupler;

[0029] The first power detection unit is used to detect the input power of the power amplifier chip under test, and the second power detection unit is used to detect the harmonic power of the power amplifier chip under test.

[0030] The tuner is used to adjust the output VSWR of the power amplifier chip under test.

[0031] The power adjustment module is used to connect the first power detection unit to the coupler through the control unit, and to adjust the standing wave ratio of the power amplifier chip under test to 1:1 through the tuner, and adjust the power of the input signal of the vector signal generator until the target power of the power amplifier chip under test is reached.

[0032] The evaluation and detection module is used to connect the second power detection unit to the coupler through the control unit, adjust the output VSWR of the power amplifier chip under test to a preset value through the tuner, and record the harmonic power of the power amplifier chip under test in each phase through the second power detection unit when the tuner modulates the phase at a preset interval to obtain the mismatch harmonic detection result.

[0033] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a power amplifier mismatch harmonic detection program stored in the memory and executable on the processor, wherein when the processor executes the power amplifier mismatch harmonic detection program, it implements the steps of the power amplifier mismatch harmonic detection method as described in any of the above embodiments.

[0034] Fourthly, the present invention also provides a computer-readable storage medium storing a power amplifier mismatch harmonic detection program, wherein the power amplifier mismatch harmonic detection program, when executed by a processor, implements the steps of the power amplifier mismatch harmonic detection method as described in any of the above embodiments.

[0035] Compared with existing technologies, this invention connects a first power detection unit to a coupler via a control unit, and adjusts the standing wave ratio (SWR) of the power amplifier chip under test (DPDT) to 1:1 via a tuner. The power of the input signal from the vector signal generator is adjusted until the target power of the DPDT is reached. A second power detection unit is connected to the coupler via the control unit, and the output SWR of the DPDT is adjusted to a preset value via a tuner. When the tuner modulates the phase at preset intervals, the second power detection unit records the harmonic power of the DPDT at each phase, obtaining the mismatch harmonic detection result. Thus, this invention can accurately test and evaluate the harmonics of the DPDT under mismatch SWR conditions, thereby assessing the harmonic performance of the DPDT. Attached Figure Description

[0036] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0037] Figure 1 This is a structural block diagram of the mismatch harmonic detection device of the power amplifier mismatch harmonic detection method provided in this embodiment of the invention;

[0038] Figure 2 This is a flowchart of the power amplifier mismatch harmonic detection method provided in the embodiments of the present invention;

[0039] Figure 3 This is a schematic diagram of the power amplifier mismatch harmonic detection system provided in an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0042] Example 1

[0043] Please refer to Figures 1-2 The present invention provides a method for detecting mismatch harmonics in a power amplifier. The detection method is based on a mismatch harmonic detection device 100, which is used to test the input power of a power amplifier chip 3 under test and to perform mismatch detection on the power amplifier chip 3 under test.

[0044] The mismatch harmonic detection device 100 includes a vector signal generator 1, a first filter 2, a coupler 4, a first power detection unit 7, a second power detection unit 8, a control unit 6, and a tuner 5.

[0045] The output terminal of the vector signal generator 1 is connected to the input terminal of the first filter 2, and the vector signal generator 1 is used to provide an input signal for the power amplifier chip 3 under test.

[0046] The output terminal of the first filter 2 is used to connect to the input terminal of the power amplifier chip 3 under test. The first filter 2 is used to filter out noise from the input signal outside the preset frequency band. In this embodiment of the invention, the preset frequency band signal is the main frequency band signal of the input signal that has been preset.

[0047] The input terminal of the coupler 4 is connected to the output terminal of the power amplifier chip 3 under test. The first output terminal of the coupler 4 is connected to the control unit 6, and the second output terminal of the coupler 4 is connected to the input terminal of the tuner 5. In this embodiment of the invention, the coupler 4 is an external cavity coupler 4.

[0048] The control unit 6 is used to connect the input terminal of the first power detection unit 7 or the input terminal of the second power detection unit 8 to the first output terminal of the coupler 4. When the control unit 6 connects the input terminal of the first power detection unit 7 to the first output terminal of the coupler 4, it enables the testing of the input power required for the target power of the power amplifier chip 3 before mismatch harmonics.

[0049] The first power detection unit 7 is used to detect the input power of the power amplifier chip 3 under test, and the second power detection unit 8 is used to detect the harmonic power of the power amplifier chip 3 under test.

[0050] In this embodiment of the invention, the first power detection unit 7 is a second spectrum analyzer or a power meter, and the input terminal of the second spectrum analyzer or the input terminal of the power meter serves as the input terminal of the first power detection unit 7.

[0051] The tuner 5 is used to adjust the output standing wave ratio of the power amplifier chip 3 under test.

[0052] In this embodiment of the invention, the second power detection unit 8 includes a second filter 81 and a first spectrum analyzer 82. The input terminal of the second filter 81 serves as the input terminal of the second power detection unit 8, and the output terminal of the second filter 81 is connected to the input terminal of the first spectrum analyzer 82. The second filter 81 is used to filter out the preset frequency band signal of the input signal. The first spectrum analyzer 82 is used to record the harmonic power of the power amplifier chip 3 under test.

[0053] In this embodiment of the invention, the video bandwidth of the first spectrum analyzer 82 is 3MHz (VBW: 3MHz), and the resolution bandwidth of the first spectrum analyzer 82 is 1MHz (RBW: 1MHz).

[0054] The first spectrum analyzer 82 uses an RMS max hold, Span 30MHz, Sweep Time 500ms mode to detect the input signal. Specifically, the frequency span of the first spectrum analyzer 82 is set to 30MHz, and the sweep time is set to 500ms. Detection is performed based on the average power of the resolution bandwidth and the maximum amplitude peak during the recording of the harmonic power of the power amplifier chip 3 under test. Specifically, when using a second spectrum analyzer, its settings are the same as the first spectrum analyzer 82.

[0055] When the first spectrum analyzer 82 operates according to the above settings, its operating mode is as follows: it scans within a frequency range of 30MHz, taking 0.5 seconds; it uses a 1MHz bandwidth filter to distinguish the signal, while simultaneously smoothing the waveform with a 3MHz bandwidth; it prioritizes capturing the maximum amplitude of the signal and reflects the signal characteristics in an RMS manner, making it suitable for measuring signals with fluctuating or bursty components (such as RF pulses, modulated signals, etc.). This setting balances measurement efficiency with signal resolution and peak capture capability, thereby more accurately capturing the harmonic power of the power amplifier chip 3 under test.

[0056] The detection method includes the following steps:

[0057] S1. The first power detection unit 7 is connected to the coupler 4 through the control unit 6, and the standing wave ratio of the power amplifier chip 3 under test is adjusted to 1:1 through the tuner 5. The power of the input signal of the vector signal generator 1 is adjusted until the target power of the power amplifier chip 3 under test is reached.

[0058] In this embodiment of the invention, after calibrating the insertion loss of the RF path between the antenna port (ANT port) and the mismatch harmonic detection device 100, the input power of the power amplifier chip 3 under test is detected in real time by the first power detection unit 7, and the power of the input signal of the vector signal generator 1 is adjusted until the target power of the power amplifier chip 3 under test is reached.

[0059] S2. The second power detection unit 8 is connected to the coupler 4 through the control unit 6. The output standing wave ratio of the power amplifier chip 3 under test is adjusted to a preset ratio through the tuner 5. When the tuner 5 modulates the phase at a preset interval, the second power detection unit 8 records the harmonic power of the power amplifier chip 3 under test in each phase to obtain the mismatch harmonic detection result.

[0060] In this embodiment of the invention, a preset VSWR of 3:1 or 5:1 is feasible and can be set according to actual conditions, and is not limited to 3:1 or 5:1 as described above. The second power detection unit 8 records the worst harmonics of the power amplifier chip 3 under test in each phase as evaluation data, thereby obtaining the mismatch harmonic detection result.

[0061] The preset degree is 15 degrees. It should be noted that the preset degree is not limited to 15 degrees and can be set according to the actual situation.

[0062] Compared with existing technologies, this invention connects a first power detection unit to a coupler via a control unit, and adjusts the standing wave ratio (SWR) of the power amplifier chip under test (DPDT) to 1:1 via a tuner. The power of the input signal from the vector signal generator is adjusted until the target power of the DPDT is reached. A second power detection unit is connected to the coupler via the control unit, and the output SWR of the DPDT is adjusted to a preset value via a tuner. When the tuner modulates the phase at preset intervals, the second power detection unit records the harmonic power of the DPDT at each phase, obtaining the mismatch harmonic detection result. Thus, this invention can accurately test and evaluate the harmonics of the DPDT under mismatch SWR conditions, thereby assessing the harmonic performance of the DPDT.

[0063] Example 2

[0064] This invention also provides a system for detecting mismatched harmonics in a power amplifier. Please refer to [link / reference]. Figure 3 , Figure 3 This is a schematic diagram of the power amplifier mismatch harmonic detection system 200 provided in an embodiment of the present invention.

[0065] The detection system includes a mismatch harmonic detection device 100, a power adjustment module 201, and an evaluation and detection module 202; the mismatch harmonic detection device 100 is used to test the input power of the power amplifier chip 3 under test and to perform mismatch detection on the power amplifier chip 3 under test.

[0066] The mismatch harmonic detection device 100 includes a vector signal generator 1, a first filter 2, a coupler 4, a first power detection unit 7, a second power detection unit 8, a control unit 6, and a tuner 5.

[0067] The output of the vector signal generator 1 is connected to the input of the first filter 2, and the vector signal generator 1 is used to provide an input signal to the power amplifier chip 3 under test.

[0068] The output of the first filter 2 is connected to the input of the power amplifier chip 3 under test. The first filter 2 is used to filter out noise from the input signal outside the preset frequency band. In this embodiment of the invention, the preset frequency band signal is the main frequency band signal of the input signal that has been pre-set.

[0069] The input terminal of the coupler 4 is connected to the output terminal of the power amplifier chip 3 under test, the first output terminal of the coupler 4 is connected to the control unit 6, and the second output terminal of the coupler 4 is connected to the input terminal of the tuner 5. In this embodiment of the invention, the coupler 4 is an external cavity coupler 4.

[0070] The control unit 6 is used to connect the input terminal of the first power detection unit 7 or the input terminal of the second power detection unit 8 to the second output terminal of the coupler 4. When the control unit 6 connects the input terminal of the first power detection unit 7 to the second output terminal of the coupler 4, it enables the testing of the input power required for the target power of the power amplifier chip 3 before mismatch harmonics.

[0071] The first power detection unit 7 is used to detect the input power of the power amplifier chip 3 under test, and the second power detection unit 8 is used to detect the harmonic power of the power amplifier chip 3 under test.

[0072] In this embodiment of the invention, the first power detection unit 7 includes a second spectrum analyzer or a power meter, and the input terminal of the second spectrum analyzer or the input terminal of the power meter serves as the input terminal of the first power detection unit 7.

[0073] The tuner 5 is used to adjust the output standing wave ratio of the power amplifier chip 3 under test.

[0074] In this embodiment of the invention, the second power detection unit 8 includes a second filter 81 and a first spectrum analyzer 82. The input terminal of the second filter 81 serves as the input terminal of the second power detection unit 8, and the output terminal of the second filter 81 is connected to the input terminal of the first spectrum analyzer 82. The second filter 81 is used to filter out the preset frequency band signal of the input signal. The first spectrum analyzer 82 is used to record the harmonic power of the power amplifier chip 3 under test.

[0075] In this embodiment of the invention, the video bandwidth of the first spectrum analyzer 82 is 3MHz (VBW: 3MHz), and the resolution bandwidth of the first spectrum analyzer 82 is 1MHz (RBW: 1MHz).

[0076] The first spectrum analyzer 82 uses an RMS max hold, Span 30MHz, Sweep Time 500ms mode to detect the input signal. Specifically, the frequency span of the first spectrum analyzer 82 is set to 30MHz, and the sweep time is set to 500ms. Detection is performed based on the average power of the resolution bandwidth and the maximum amplitude peak during the recording of the harmonic power of the power amplifier chip 3 under test. Specifically, when using a second spectrum analyzer, its settings are the same as the first spectrum analyzer 82.

[0077] When the first spectrum analyzer 82 operates according to the above settings, its operating mode is as follows: it scans within a frequency range of 30MHz, taking 0.5 seconds; it uses a 1MHz bandwidth filter to distinguish the signal, while simultaneously smoothing the waveform with a 3MHz bandwidth; it prioritizes capturing the maximum amplitude of the signal and reflects the signal characteristics in an RMS manner, making it suitable for measuring signals with fluctuating or bursty components (such as RF pulses, modulated signals, etc.). This setting balances measurement efficiency with signal resolution and peak capture capability, thereby more accurately capturing the harmonic power of the power amplifier chip 3 under test.

[0078] 201. A power adjustment module is used to connect the first power detection unit 7 to the coupler 4 through the control unit 6, and to adjust the standing wave ratio of the power amplifier chip 3 under test to 1:1 through the tuner 5, and adjust the power of the input signal of the vector signal generator 1 until the target power of the power amplifier chip 3 under test is reached.

[0079] In this embodiment of the invention, after calibrating the insertion loss of the RF path between the antenna port (ANT port) and the mismatch harmonic detection device 100, the input power of the power amplifier chip 3 under test is detected in real time by the first power detection unit 7, and the power of the input signal of the vector signal generator 1 is adjusted until the target power of the power amplifier chip 3 under test is reached.

[0080] 202. Evaluation and detection module, used to connect the second power detection unit 8 to the coupler 4 through the control unit 6, adjust the output standing wave ratio of the power amplifier chip 3 under test to a preset ratio through the tuner 5, and record the harmonic power of the power amplifier chip 3 under test in each phase through the second power detection unit 8 when the tuner 5 modulates the phase at a preset degree interval to obtain the mismatch harmonic detection result.

[0081] In this embodiment of the invention, a preset VSWR of 3:1 or 5:1 is feasible and can be set according to actual conditions, and is not limited to 3:1 or 5:1 as described above. The second power detection unit 8 records the worst harmonics of the power amplifier chip 3 under test in each phase as evaluation data, thereby obtaining the mismatch harmonic detection result.

[0082] The preset degree is 15 degrees. It should be noted that the preset degree is not limited to 15 degrees and can be set according to the actual situation.

[0083] The power amplifier mismatch harmonic detection system 200 can implement the steps in the power amplifier mismatch harmonic detection method in the above embodiments and achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0084] Example 3

[0085] This invention also provides a computer device, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a mismatch harmonic detection program stored in the memory 302 and executable on the processor 301.

[0086] The processor 301 calls the power amplifier mismatch harmonic detection program stored in the memory 302 and executes the steps in the power amplifier mismatch harmonic detection method provided in this embodiment of the invention. Please refer to... Figure 2 Specifically, it includes the following steps:

[0087] S1. The first power detection unit 7 is connected to the coupler 4 through the control unit 6, and the standing wave ratio of the power amplifier chip 3 under test is adjusted to 1:1 through the tuner 5. The power of the input signal of the vector signal generator 1 is adjusted until the target power of the power amplifier chip 3 under test is reached.

[0088] In this embodiment of the invention, after calibrating the insertion loss of the RF path between the antenna port (ANT port) and the mismatch harmonic detection device 100, the input power of the power amplifier chip 3 under test is detected in real time by the first power detection unit 7, and the power of the input signal of the vector signal generator 1 is adjusted until the target power of the power amplifier chip 3 under test is reached.

[0089] S2. The second power detection unit 8 is connected to the coupler 4 through the control unit 6. The output standing wave ratio of the power amplifier chip 3 under test is adjusted to a preset ratio through the tuner 5. When the tuner 5 modulates the phase at a preset interval, the second power detection unit 8 records the harmonic power of the power amplifier chip 3 under test in each phase to obtain the mismatch harmonic detection result.

[0090] In this embodiment of the invention, a preset VSWR of 3:1 or 5:1 is feasible and can be set according to actual conditions, and is not limited to 3:1 or 5:1 as described above. The second power detection unit 8 records the worst harmonics of the power amplifier chip 3 under test in each phase as evaluation data, thereby obtaining the mismatch harmonic detection result.

[0091] The preset degree is 15 degrees. It should be noted that the preset degree is not limited to 15 degrees and can be set according to the actual situation.

[0092] The computer device 300 provided in this embodiment of the invention can implement the steps in the power amplifier mismatch harmonic detection method as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0093] Example 4

[0094] This invention also provides a computer-readable storage medium storing a power amplifier mismatch harmonic detection program. When executed by a processor, the power amplifier mismatch harmonic detection program implements the various processes and steps in the power amplifier mismatch harmonic detection method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0095] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0096] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0097] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0098] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A method of detecting power amplifier mismatch harmonics, the method comprising: The detection method is based on a mismatch harmonic detection device for testing input power of a to-be-tested power amplifier chip and performing mismatch detection on the to-be-tested power amplifier chip; The mismatch harmonic detection device comprises a vector signal generator, a first filter, a coupler, a first power detection unit, a second power detection unit, a control unit and a tuner; An output end of the vector signal generator is connected to an input end of the first filter, and the vector signal generator is configured to provide an input signal for the to-be-tested power amplifier chip; An output end of the first filter is configured to be connected to an input end of the to-be-tested power amplifier chip, and the first filter is configured to filter out noise of the input signal other than signals in a preset frequency band; An input end of the coupler is configured to be connected to an output end of the to-be-tested power amplifier chip, a first output end of the coupler is connected to the control unit, and a second output end of the coupler is connected to an input end of the tuner; The control unit is configured to connect an input end of the first power detection unit or an input end of the second power detection unit to the first output end of the coupler; The first power detection unit is configured to detect input power of the to-be-tested power amplifier chip, and the second power detection unit is configured to detect harmonic power of the to-be-tested power amplifier chip; The tuner is configured to adjust an output standing wave ratio of the to-be-tested power amplifier chip; The detection method comprises the following steps: S1, connecting the first power detection unit to the coupler through the control unit, adjusting the standing wave ratio of the to-be-tested power amplifier chip to 1:1 through the tuner, adjusting the power of the input signal of the vector signal generator until the target power of the to-be-tested power amplifier chip is reached; S2, connecting the second power detection unit to the coupler through the control unit, adjusting the output standing wave ratio of the to-be-tested power amplifier chip to a preset ratio through the tuner, recording the harmonic power of the to-be-tested power amplifier chip at each phase through the second power detection unit when the tuner modulates the phase by a preset number of degrees each time, and obtaining a mismatch harmonic detection result.

2. The method of claim 1, wherein the step of detecting the power amplifier mismatch harmonic comprises: The second power detection unit comprises a second filter and a first frequency spectrometer, an input end of the second filter is used as an input end of the second power detection unit, an output end of the second filter is connected to an input end of the first frequency spectrometer, the second filter is configured to filter out the preset frequency band signals of the input signal, and the first frequency spectrometer is configured to record the harmonic power of the to-be-tested power amplifier chip.

3. The method of claim 2, wherein the step of determining the power amplifier mismatch harmonic comprises: determining the power amplifier mismatch harmonic based on the first and second power amplifier output signals. The video bandwidth of the first frequency spectrometer is 3MHz, and the resolution bandwidth of the first frequency spectrometer is 1MHz.

4. The method of claim 3, wherein the step of determining the power amplifier mismatch harmonic comprises: determining the power amplifier mismatch harmonic based on the first and second power amplifier output signals. The detection mode of the first frequency spectrometer on the input signal is that the frequency span of the first frequency spectrometer is set to 30MHz, the scanning time of the first frequency spectrometer is set to 500ms, and the detection is performed according to the average power of the resolution bandwidth and the maximum amplitude peak in the process of recording the harmonic power of the to-be-tested power amplifier chip.

5. The method of claim 1, wherein the step of detecting the power amplifier mismatch harmonic comprises: determining a ratio of the first and second power amplifier output signals; and determining the power amplifier mismatch harmonic based on the ratio. The preset number of degrees is 15 degrees.

6. The method of claim 1, wherein, The first power detection unit comprises a second frequency spectrum analyzer or a power meter, and an input end of the second frequency spectrum analyzer or an input end of the power meter serves as an input end of the first power detection unit.

7. A system for detecting power amplifier mismatch harmonics, comprising: The detection system comprises a mismatch harmonic detection device, a power adjustment module and an evaluation detection module; the mismatch harmonic detection device is used for testing input power of a to-be-tested power amplifier chip and performing mismatch detection on the to-be-tested power amplifier chip; The mismatch harmonic detection device comprises a vector signal generator, a first filter, a coupler, a first power detection unit, a second power detection unit, a control unit and a tuner; An output end of the vector signal generator is connected to an input end of the first filter, and the vector signal generator is used for providing an input signal to the to-be-tested power amplifier chip; An output end of the first filter is used for connecting to an input end of the to-be-tested power amplifier chip, and the first filter is used for filtering out noise of the input signal other than signals in a preset frequency band; An input end of the coupler is used for connecting to an output end of the to-be-tested power amplifier chip, a first output end of the coupler is connected to the control unit, and a second output end of the coupler is connected to an input end of the tuner; The control unit is used for connecting an input end of the first power detection unit or an input end of the second power detection unit to the second output end of the coupler; The first power detection unit is used for detecting input power of the to-be-tested power amplifier chip, and the second power detection unit is used for detecting harmonic power of the to-be-tested power amplifier chip; The tuner is used for adjusting an output standing wave ratio of the to-be-tested power amplifier chip; The power adjustment module is used for connecting the first power detection unit to the coupler through the control unit, adjusting the standing wave ratio of the to-be-tested power amplifier chip to 1:1 through the tuner, adjusting power of the input signal of the vector signal generator until a target power of the to-be-tested power amplifier chip is reached; The evaluation detection module is used for connecting the second power detection unit to the coupler through the control unit, adjusting the output standing wave ratio of the to-be-tested power amplifier chip to a preset ratio through the tuner, recording harmonic power of the to-be-tested power amplifier chip at each phase through the second power detection unit when the tuner is modulated at each interval of a preset phase, and obtaining a mismatch harmonic detection result.

8. A computer device, comprising: comprise: a memory, a processor and a power amplifier mismatch harmonic detection program stored in the memory and executable on the processor, and the processor implements the steps in the power amplifier mismatch harmonic detection method according to any one of claims 1-6 when executing the power amplifier mismatch harmonic detection program.

9. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a power amplifier mismatch harmonic detection program, and the power amplifier mismatch harmonic detection program implements the steps in the power amplifier mismatch harmonic detection method according to any one of claims 1-6 when executed by a processor.

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