Open / short circuit test carrier plate and open / short circuit test equipment for oversized packaged chip

Abstract

The invention relates to the field of semiconductor packaging testing, in particular to an open and short circuit testing carrier plate and open and short circuit testing equipment for an oversized packaging chip, the open and short circuit testing carrier plate comprises a plurality of sub-plates and a plurality of adapter plates which are stacked in sequence, and two adjacent sub-plates are vertically interconnected through the adapter plates by electric signals. The first daughter board on the uppermost layer is connected with a tested chip signal pin, peripheral preset turns of signals are connected to a test machine through wires, and meanwhile, inner-circle signals are led to the bottom layer through conductive via holes and transmitted to the next daughter board through an adapter board; and the subsequent daughter board repeats the process until all the signals are connected to the test machine. According to the scheme, the problems that the number of layers of a traditional single PCB is increased dramatically, and a special process is needed when the ratio of the board thickness to the aperture exceeds the limit are solved, the manufacturing cost of the PCB is greatly reduced, and full-pin open-short circuit test connection of the super-large packaging chip is efficiently completed.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging and testing, and in particular to open and short circuit test carrier boards and open and short circuit test equipment for ultra-large packaged chips. Background Technology

[0002] With the rapid development of semiconductor technology, chip packaging is evolving towards high density and multi-functionality, and the application of ultra-large packaged chips (such as multi-chip integrated CPUs, chiplets, or high pin-count FPGAs) is becoming increasingly widespread. These chips typically contain a large number of pins (more than 1,000, and some even more than 5,000), covering various types such as power, ground, and signals, significantly increasing the complexity and cost of their packaging processes.

[0003] In the chip packaging production process, open and short circuit testing is a key step to ensure packaging quality: by scanning each pin of the chip to detect whether there is an open circuit or short circuit failure, two core objectives can be achieved: first, to sample the packaged chips to optimize process parameters and improve yield; second, to conduct full inspection before batch chips enter high-cost functional testing, to eliminate defective packaged products and avoid waste of resources.

[0004] Currently, open and short circuit testing mainly relies on a dedicated test PCB to connect the device under test (DUT) to the test machine: the PCB needs to connect all the chip pins to the corresponding channels of the test machine one by one to achieve effective signal transmission.

[0005] Existing testing solutions use a single thick, multi-layer PCB as the test substrate, which has the following prominent problems: Firstly, the number of PCB layers increases dramatically with the number of pins, making design and manufacturing more difficult: chip pins are arranged in a two-dimensional array, with signals on the inner ring pins being blocked by the outer ring, requiring vias to be brought out to the inner layers of the PCB. As the number of pins increases, the number of PCB layers increases linearly (e.g., a BGA256 package requires 8 layers, while BGA900 and higher packages may require more than 20 layers), directly leading to a significant increase in PCB manufacturing costs. Secondly, the process requirements are stringent, and the yield rate is difficult to guarantee: In order to offset the pressure deformation of the test seat spring pin, the thickness of the test carrier plate needs to be ≥4.0mm, while the hole diameter is only about 0.2mm. The ratio of plate thickness to hole diameter (aspect ratio) is ≥20, which requires special processes to ensure the production yield rate, further increasing the cost. Third, the overall economic efficiency is poor and it is difficult to adapt to large-scale applications: Due to the above-mentioned design requirements of "thick board and multi-layer", the cost of traditional test carrier board is much higher than that of ordinary "thin board and few-layer" PCB (the price can be more than 10 times). Moreover, as the number of chip pins increases further, the cost will continue to rise, making it difficult to meet the economic requirements of large-scale testing of ultra-large packaged chips. Summary of the Invention

[0006] Therefore, the technical problem to be solved by the present invention is that the traditional ultra-large package chip open and short circuit test carrier board uses a single thick board (thickness > 4.0 mm) and multi-layer (number of layers > 20 layers) PCB, which leads to a dramatic increase in the number of layers with the number of pins, excessive board thickness and hole diameter ratio requiring special processes, extremely high cost, and difficulty in adapting to large-scale applications.

[0007] To address the aforementioned technical problems, this invention provides an open / short circuit test carrier board and an open / short circuit test device for ultra-large packaged chips. The open / short circuit test carrier board includes: multiple sub-boards stacked sequentially and multiple adapter boards; wherein adjacent sub-boards are vertically interconnected by electrical signals through the adapter boards, including: The first board located on the top layer is electrically connected to each signal pin of the packaged chip under test. The first board connects the signals of the packaged chip under test with a preset number of processing turns to the open and short circuit tester through traces. At the same time, the remaining inner ring signals of the packaged chip under test are led to its own bottom layer through conductive vias, and then transmitted to the next board through the first adapter board. After the next board receives the inner ring signal transmitted from the previous board, it connects the same peripheral preset processing number of signals to the open / short circuit tester through a trace in the newly received inner ring signal. Meanwhile, the remaining inner ring signals are led to the bottom layer through conductive vias, and then transmitted to the next sub-board through the second adapter board. This process is repeated until all signal pins of the packaged chip under test are connected to the open / short circuit tester.

[0008] In one embodiment of the present invention, each sub-board is provided with PCB pads. The first sub-board is electrically connected to each signal pin of the packaged chip under test through the PCB pads, and each of the remaining sub-boards receives the pin signals transmitted by the previous sub-board through the PCB pads.

[0009] In one embodiment of the invention, the size of the PCB pad is matched with the pin area that receives signals transmitted from the previous sub-board.

[0010] In one embodiment of the invention, the size of the adapter board is matched to the signal pin area transmitted to the next sub-board.

[0011] In one embodiment of the present invention, the number of sub-boards is determined according to the total number of turns of the signal pins of the packaged chip under test. When the total number of turns is N, the number of sub-boards is the ratio of N rounded up to the preset number of processing turns.

[0012] In one embodiment of the present invention, the open / short circuit test carrier board further includes a test socket for placing the packaged chip under test. The test socket is located above the uppermost first chip board, and the first chip board is electrically connected to the signal pins of the packaged chip under test through the test socket.

[0013] In one embodiment of the present invention, the test socket is provided with a contact element corresponding to the signal pin of the packaged chip under test, and the signal pin of the packaged chip under test is connected to the first chip board through the contact element.

[0014] In one embodiment of the present invention, the open / short circuit test carrier plate further includes a support plate, which is located below the lowest sub-plate and is fixedly connected to the test tube base.

[0015] In one embodiment of the present invention, each sub-board is provided with positioning holes, and the positioning holes of adjacent sub-boards are coaxially aligned.

[0016] In one embodiment of the present invention, the test tube base is provided with a first mounting hole, and the support plate is provided with a second mounting hole. The first mounting hole passes through the positioning holes of all sub-plates and is fixedly connected to the second mounting hole by positioning pins and screws.

[0017] In one embodiment of the present invention, the thickness of the sub-plate is less than 2.0 mm.

[0018] Based on the same inventive concept, the present invention also provides an open / short circuit test device, which includes the above-mentioned open / short circuit test carrier board, signal connector, and open / short circuit tester; wherein, the peripheral preset number of processing turns signal of each sub-board in the open / short circuit test carrier board is sent to the open / short circuit tester through the signal connector.

[0019] The technical solution of the present invention has the following advantages compared with the prior art: By splitting the traditional single thick plate, multi-layer test carrier board into multiple thin plates and fewer layers of sub-boards, and using an adapter board to achieve vertical interconnection of electrical signals between sub-boards, each sub-board is only responsible for the transmission of outer ring signals and inner ring signals of a preset number of processing turns. This not only avoids the problems of the number of PCB layers increasing dramatically with the number of pins and the need for special processes when the board thickness and aperture ratio exceed the limits in the traditional solution, but also significantly reduces the PCB manufacturing cost and can efficiently complete the open and short circuit test connection of all signal pins of ultra-large packaged chips. Attached Figure Description

[0020] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings, wherein... Figure 1 This is a schematic diagram of a test carrier structure used in existing technologies for ultra-large packaged chips; Figure 2 This is a schematic diagram of the signal partitioning of a 16×16 two-dimensional array packaged chip; Figure 3 Taking a 16×16 two-dimensional array packaged chip as an example, using Figure 1 The test carrier in the diagram shows the signal connection diagram of the pin signals of the packaged chip under test to the open and short circuit tester, where (a) represents the signal connection of column 1 and column 2, and (b) to (g) represent the signal connection of column 3 to 8 respectively; Figure 4 This is a schematic diagram of the structure of an open / short circuit test carrier board for ultra-large packaged chips provided in an embodiment of the present invention; Figure 5 yes Figure 4 A schematic diagram of the test tube socket structure in the diagram; Explanation of reference numerals in the accompanying drawings: 100, chip under test; 10, test socket; 20, PCB board; 201, solder pad; 202, communication interface; 1. Sub-board; 11. PCB pads; 12. Positioning holes; 2. Adapter board; 3. Test tube socket; 31. First mounting hole; 32. Contact element; 4. Support plate; 41. Second mounting hole. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0022] Example 1: Existing test carriers for ultra-large packaged chips, such as Figure 1 As shown, it includes a test socket 10 and a single PCB board 20 formed by multi-layer sub-board packaging.

[0023] The PCB board 20 has pads 201 on its upper surface and multiple communication interfaces 202 on its lower surface. The uppermost PCB board 20 is connected to the packaged chip under test 10 via the test socket 10 through the pads 201. After the pin signals of the packaged chip under test 100 are led to its bottom layer, it is connected to the open / short circuit tester through the multiple communication interfaces 202.

[0024] by Figure 2 Taking the 16×16 two-dimensional array packaged chip (such as BGA256) as an example, all its pin signals are divided into 4 sector areas. Each sector area contains 8 columns from the outside to the inside. Therefore, the pin signals of the entire packaged chip can be regarded as 8 turns of signals.

[0025] Combination Figure 1The single PCB open / short circuit test carrier board shown has the following signal connection method: Figure 3 As shown in (a) to (g): The chip pins are arranged in a 16×16 two-dimensional array. The carrier board needs to connect the signal of each pin to the corresponding channel of the open / short circuit tester via traces. Since the signal path of the inner ring pins is blocked by the outer ring pins, it needs to be led to the inner layer of the PCB board through vias to achieve signal conduction. The surface layer (first layer) of the PCB board 20 is responsible for leading out the pin signals of the outermost column 1 and column 2; The pin signals of column 3 need to be led out to the second layer of traces through the through hole; The pin signals of column 4 are led out to the third layer of traces through the through-hole; Similarly, for each additional ring of signal pins added to the chip, the PCB board 20 needs to add a corresponding layer of wiring. For a 16×16 array package chip, a total of 8 layers of PCB wiring are required (e.g., the pin signal of column 8 needs to be routed to the seventh layer). The bottom layer (eighth layer) is not allowed to have wiring according to process requirements, and only serves as a structural support.

[0026] Meanwhile, in order to counteract the pressure deformation generated by the spring pin in the test holder 10, the thickness of the PCB board 20 in the test carrier must be ≥4.0mm, the hole diameter is about 0.2mm, and the ratio of board thickness to hole diameter (aspect ratio) must be ≥20. Special processes must be used to ensure the production yield of the circuit board. Finally, all signals are connected to the open and short circuit tester through cables and connectors.

[0027] To reduce the design cost and wiring complexity of the aforementioned circuit boards, see [link / reference]. Figure 4 This invention provides an open / short circuit test carrier board for ultra-large packaged chips, comprising: a plurality of sub-boards 1 stacked sequentially and a plurality of adapter boards 2; wherein adjacent sub-boards 1 are vertically interconnected by electrical signals through the adapter boards 2, including: The first board 1 located on the top layer is electrically connected to each signal pin of the packaged chip 100 under test. The first board 1 connects the signal of the packaged chip 100 under test with a preset number of processing turns n to the open and short circuit tester through the traces. At the same time, the remaining inner ring signal of the packaged chip 100 under test is led to its own bottom layer through conductive vias, and then transmitted to the next board 1 through the first adapter board 2. After receiving the inner ring signal transmitted by the previous board 1, the next board 1 will connect the same peripheral preset processing number n signal to the open and short circuit tester through the wiring in the newly received inner ring signal. Meanwhile, the remaining inner ring signals are led to the bottom layer through conductive vias, and then transmitted to the next sub-board 1 through the second adapter board 2, and so on, until all signal pins of the packaged chip 100 under test are connected to the open / short circuit tester.

[0028] Based on the above technical solution, the present invention splits the traditional single PCB test carrier into multiple sub-boards stacked sequentially, and uses the adapter board 2 to realize the vertical interconnection of electrical signals between adjacent sub-boards 1. Each sub-board 1 is only responsible for processing the peripheral signal output of a preset number of processing rounds and transmitting the remaining inner circle signals downwards. This effectively avoids the problem of the number of PCB layers increasing linearly with the expansion of the chip pin array in the traditional solution. At the same time, it simplifies the wiring process and can efficiently realize the connection of all signal pins of ultra-large packaged chips to the open and short circuit tester.

[0029] Furthermore, in this embodiment, the thickness of each sub-board 1 is less than 2.0 mm, and each sub-board 1 is provided with PCB pads 11. The first sub-board 1 is electrically connected to each signal pin of the packaged chip under test 100 through the PCB pads 11 on its surface, and each of the remaining sub-boards 1 receives the pin signals transmitted by the previous sub-board 1 through the PCB pads 11.

[0030] Optionally, the PCB pads 11 are arranged in a two-dimensional array that matches the pin array of the packaged chip under test 100 or the signal transmission area of ​​the upper daughterboard 1. Each PCB pad 11 is a circular or square metal conductor, for example, made of copper base and gold plating, with a gold layer thickness ≥0.8μm to reduce contact resistance. The center spacing of each PCB pad 11 is consistent with the pitch of the corresponding signal pin.

[0031] Each PCB pad 11 is surrounded by a ring-shaped grounding isolation strip (width ≥ 0.15mm). The isolation strip is insulated from the pad by a solder mask layer, which can effectively reduce signal crosstalk between adjacent pads. It is especially suitable for transmission isolation in the inner high-density signal area and ensures signal integrity.

[0032] Furthermore, the size of the PCB pad 11 matches the pin area that receives signals transmitted from the previous sub-board 1. Specifically, for the pads of the sub-board 1 that receive signals transmitted from the previous sub-board 1, the array size is reduced in a stepwise manner as the inner signal area shrinks (e.g., the first sub-board 1 pads cover a 16×16 array, and the second sub-board 1 pads cover an 8×8 array), and the center of the pad is precisely aligned with the center of the signal endpoint transmitted by the previous sub-board through the adapter board 2 (alignment deviation ≤ 0.05mm), ensuring the reliability of vertical interconnection.

[0033] Furthermore, the bottom of the PCB pad 11 is connected to the internal trace layer of the sub-board 1 through a conductive via. The diameter of the conductive via is set to 0.2~0.3mm, and the copper thickness of the via wall is ≥20μm, so as to realize the efficient transmission of pad signals to the bottom layer or inner layer of the sub-board 1. The distance between the conductive via and the edge of the pad is ≥0.1mm to avoid copper peeling at the connection between the pad and the via.

[0034] Specifically, in this embodiment, the adapter board 2 is the core component for vertical signal interconnection between adjacent sub-boards 1. Its size is matched with the signal pin area transmitted to the next sub-board 1. That is, the length and width of the adapter board 2 are designed according to the pin array boundary size of the next sub-board 1 receiving the signal, with a redundancy of 0.5mm to 1mm reserved on each side.

[0035] For example, when the pin area for transmitting signals is an 8×8 array with a spacing of 0.4mm, the size of the adapter board 2 is set to 3.7mm×3.7mm, including boundary redundancy, and the thickness is controlled between 0.3mm and 0.8mm, preferably with a ceramic substrate thickness of 0.5mm, to balance mechanical support and signal transmission efficiency. The conductive contact array on its upper and lower surfaces corresponds completely to the layout of the PCB pads 11 on the next sub-board 1. The contact diameter is 0.05mm to 0.1mm smaller than the pad diameter (e.g., when the pad diameter is 0.35mm, the contact diameter is set to 0.3mm). The contact spacing is consistent with the spacing of the pin area for transmitting signals (deviation ≤0.02mm) to ensure signal transmission without offset.

[0036] Preferably, the substrate of the adapter board 2 is an organic substrate such as FR-4 or BT resin. It optimizes manufacturing costs by relying on the low-cost characteristics of organic materials and ensures the reliability of signal transmission through high-precision processing technology, which can meet the vertical interconnection requirements of the multi-subboard 1 stacked structure in this technical solution.

[0037] Furthermore, the number of sub-boards 1 is determined based on the total number of turns of the signal pins of the packaged chip under test. When the total number of turns is N, the number of sub-boards is the ratio of N rounded up to the preset number of processing turns n.

[0038] Specifically, for a 16×16 two-dimensional array packaged chip (containing 8 turns of signal), when making pin connections based on the open / short circuit test carrier board of this invention, a preset processing number of turns n=2 is set, and signal conduction is achieved through a stacked structure of 4 sub-boards 1 and 3 adapter boards 2: The first sub-board 1 (top layer) is electrically connected to all signal pins of the 16×16 array of chips through the test socket 3. The signals of the outer 1st and 2nd rings are led to the signal connector at the edge of the sub-board 1 through the surface traces. At the same time, the signals of the inner 12×12 array (corresponding to the 3rd to 8th rings) are led to the bottom layer through conductive vias and transmitted to the second sub-board through the first adapter board. After receiving the 12×12 inner ring signal, the second chip board 1 leads the outer ring 3-4 signal to its own signal connector through the trace, and the remaining 8×8 array signal (corresponding to the 5th-8th ring) is transmitted to the third chip board through conductive vias and the second adapter board; The third chip board 1 processes the 5th and 6th turns of the 8×8 inner ring signal and leads them to the outer connector. The remaining 4×4 array signal (corresponding to the 7th and 8th turns) is transmitted to the fourth chip board via the third adapter board. After receiving the 4×4 inner ring signal, the fourth chip board 1 directly leads the 7th and 8th ring signals to its own signal connector through the trace, completing the output of all signals.

[0039] All four sub-boards 1 mentioned above adopt a thin board design with a thickness of <2.0mm and fewer than 8 layers. Compared with the existing technology that requires 8 thick boards (thickness ≥4.0mm) for 16×16 array chips, this structure avoids the high cross-bit process requirements by modularly stacking multiple thin boards with fewer layers, significantly reducing PCB manufacturing costs.

[0040] Furthermore, for 2D array packaged chips with a larger size of 16×16, the preset processing number of turns n is the number of peripheral turns that each sub-board 1 can independently complete for signal extraction, preferably 8 turns. This parameter is set based on the number of layers (<8 layers), wiring space, and signal transmission efficiency of the sub-board 1. For example, when the total number of signal turns of the packaged chip 100 under test is 25 turns and the preset processing number of turns is 8 turns, the calculation... This means configuring 4 daughterboards – the first 3 daughterboards process 8 turns of signal each, and the 4th daughterboard processes the remaining 1 turn of signal, ensuring that all signal pins can be connected to the open / short circuit tester through the corresponding daughterboard.

[0041] This quantitative configuration method avoids the problem of a dramatic increase in the number of layers due to the increase in the total number of turns in traditional single PCBs. It also achieves precise matching of the number of sub-boards through standardized turn allocation logic. While ensuring full signal coverage, it minimizes the cost loss caused by sub-board redundancy and adapts to the testing needs of ultra-large packaged chips of different specifications.

[0042] Furthermore, the open / short circuit test carrier board also includes a test socket 3 for placing the packaged chip 100 under test and a support plate 4 for structural support. The test socket 3 is integrated above the uppermost first chip board 1, and the first chip board 1 is electrically connected to the signal pins of the packaged chip 100 under test via the test socket 3.

[0043] The support plate 4 is located below the bottommost sub-plate 1 and is fixedly connected to the test tube base 3 through a through-type fastening structure, providing anti-deformation support for the overall stacked structure.

[0044] Furthermore, each sub-board 1 has four positioning holes 12 with a diameter of φ1.0mm on its edge area, with the hole position accuracy controlled within ±0.01mm. The positioning holes 12 of adjacent sub-boards 1 form a coaxial through structure when stacked. The test tube base 3 has four first mounting holes 31 that match the positioning holes 12 at the corresponding positions, and the support plate 4 has second mounting holes 41 that match the size of the first mounting holes 31. The first mounting holes 31, the positioning holes 12 of all sub-boards 1, and the second mounting holes 41 are fixed by hardened steel positioning pins with a diameter of φ0.98mm. The fit clearance between the positioning pin and the hole wall is controlled within 0.01~0.02mm to ensure that the alignment deviation of the entire stacked structure is ≤0.05mm. Meanwhile, the test tube base 3 and the support plate 4 are rigidly locked together by four sets of stainless steel fastening screws that pass through the positioning holes 12 of all sub-boards 1. The screw torque is set to 5.0±0.5N・m, so that the overall flatness of the stacked structure is controlled within 0.1mm / m, ensuring the signal interconnection stability between each layer of sub-board 1 and the adapter board 2.

[0045] like Figure 5 As shown, the test socket 3 is provided with contact elements 32 corresponding to the signal pins of the packaged chip 100 under test. The signal pins of the packaged chip 100 under test are connected to the first board 1 through the contact elements 32. The contact element 32 is an elastic probe. One end of the elastic probe is precisely aligned with the pin of the packaged chip 100 under test, and the other end forms reliable conductivity with the PCB pad 11 of the first board 1. The alignment deviation is controlled within ±0.05mm to ensure that no signal from each pin is missed during transmission.

[0046] Example 2: Based on the same inventive concept as Embodiment 1, the present invention also provides an open / short circuit test device, which includes the open / short circuit test carrier board, signal connector, and open / short circuit tester described in Embodiment 1.

[0047] The open / short circuit test carrier board serves as the core connecting component. Each sub-board 1 has a pre-set number of signal processing turns (e.g., 8 turns) on its periphery, which are led to the signal connector interface at the edge through the traces on the surface of the sub-board. This interface adopts an insulated displacement connector (IDC) or board-to-board connector structure with a pin pitch of 1.27mm. The contacts are made of gold-plated phosphor bronze (gold plating thickness 0.8μm) to ensure low contact resistance (≤50mΩ) and mating resistance (≥100,000 times) for signal transmission.

[0048] The signal connector is connected to the corresponding channel of the open / short circuit tester via a shielded cable. The shielded cable uses a multi-core twisted-pair structure with a single core diameter of 0.12mm², and is wrapped with a double shielding layer of aluminum foil and braided mesh (shielding effectiveness ≥80dB@1GHz), which can effectively suppress external electromagnetic interference (EMI) and signal crosstalk. The open / short circuit tester is equipped with ≥256 independent test channels, each channel supporting 0~5V test voltage output and 1mA constant current source drive. It can acquire the signals transmitted by each daughterboard in real time and perform open / short circuit judgment (short circuit threshold ≤100Ω, open circuit threshold ≥10MΩ), and finally output the test results through the human-machine interface.

[0049] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this invention.

Claims

1. A test substrate board for open / short circuit testing of an ultra-large packaged chip, used to connect all signal pins of the packaged chip under test to an open / short circuit tester, wherein the signal pins of the packaged chip under test are arranged in a two-dimensional array, characterized in that, The open / short circuit test carrier board includes: multiple sub-boards stacked sequentially and multiple adapter boards; wherein adjacent sub-boards are vertically interconnected by electrical signals through the adapter boards, including: The first board located on the top layer is electrically connected to each signal pin of the packaged chip under test. The first board connects the signals of the packaged chip under test with a preset number of processing turns to the open and short circuit tester through traces. At the same time, the remaining inner ring signals of the packaged chip under test are led to its own bottom layer through conductive vias, and then transmitted to the next board through the first adapter board. After the next board receives the inner ring signal transmitted from the previous board, it connects the same peripheral preset processing number of signals to the open / short circuit tester through a trace in the newly received inner ring signal. Meanwhile, the remaining inner ring signals are led to the bottom layer through conductive vias, and then transmitted to the next sub-board through the second adapter board. This process is repeated until all signal pins of the packaged chip under test are connected to the open / short circuit tester.

2. The open / short circuit test carrier board for ultra-large packaged chips according to claim 1, characterized in that, Each sub-board has PCB pads. The first sub-board is electrically connected to each signal pin of the chip under test through the PCB pads. Each of the remaining sub-boards receives the pin signals transmitted from the previous sub-board through the PCB pads.

3. The open / short circuit test carrier board for ultra-large packaged chips according to claim 2, characterized in that, The size of the PCB pads is matched to the pin area that receives signals transmitted from the previous sub-board.

4. The open / short circuit test carrier board for ultra-large packaged chips according to claim 2, characterized in that, The dimensions of the adapter board are matched to the signal pin area transmitted to the next sub-board.

5. The open / short circuit test carrier board for ultra-large packaged chips according to claim 1, characterized in that, The number of sub-boards is determined based on the total number of turns of the signal pins of the packaged chip under test. When the total number of turns is N, the number of sub-boards is the ratio of N rounded up to the preset number of processing turns.

6. The open / short circuit test carrier board for ultra-large packaged chips according to claim 1, characterized in that, The open / short circuit test carrier board also includes a test socket for placing the packaged chip under test. The test socket is located above the topmost first chip board, and the first chip board is electrically connected to the signal pins of the packaged chip under test through the test socket.

7. The open / short circuit test carrier board for ultra-large packaged chips according to claim 6, characterized in that, The test socket is provided with contact elements corresponding to the signal pins of the packaged chip under test, and the signal pins of the packaged chip under test are connected to the first chip board through the contact elements.

8. The open / short circuit test carrier board for ultra-large packaged chips according to claim 6, characterized in that, The open / short circuit test carrier plate also includes a support plate, which is located below the lowest sub-plate and is fixedly connected to the test tube base.

9. The open / short circuit test carrier board for ultra-large packaged chips according to claim 8, characterized in that, Each board has positioning holes, and the positioning holes of adjacent boards are coaxially aligned.

10. The open / short circuit test carrier board for ultra-large packaged chips according to claim 9, characterized in that, The test tube socket is provided with a first mounting hole, and the support plate is provided with a second mounting hole. The first mounting hole passes through the positioning holes of all sub-plates and is fixedly connected to the second mounting hole by positioning pins and screws.

11. The open / short circuit test carrier board for ultra-large packaged chips according to claim 1, characterized in that, The thickness of the sub-plate is less than 2.0 mm.

12. An open / short circuit testing device, characterized in that, It includes the open / short circuit test carrier board, signal connector, and open / short circuit tester as described in any one of claims 1 to 11; wherein, the peripheral preset number of processing turns signal of each sub-board in the open / short circuit test carrier board is sent to the open / short circuit tester through the signal connector.

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