Universal FLASH chip function test system

Abstract

The invention discloses a universal FLASH chip function test system, which relates to the technical field of chip test, and comprises a test main control board, a test bottom board and a test sub-board, the test main control board is configured to be electrically connected with the test bottom board through the communication interface; the test bottom plate is configured to be provided with a plurality of stations, and each station is provided with a European-style socket; the test daughter board is configured to comprise a test clamp and a plurality of packaging selection resistors, the test clamp is used for clamping a FLASH chip to be tested, the packaging selection resistors are pull-down resistors, different types of FLASH chips are defined by setting the packaging selection resistors, and connection with the test bottom board is realized through cooperation of a European-style plug and a European-style socket; and the test main control board downloads a test program through the serial port, and performs function test on the FLASH chip to be tested. According to the invention, a set of test system is used for completing multi-station automatic function test of FLASH chips with different pin numbers, different packages and different capacities, and the screening efficiency of the FLASH chips is improved.

Description

Technical Field

[0001] This invention relates to the field of FLASH chip testing technology, and in particular to a general-purpose FLASH chip functional testing system. Background Technology

[0002] Currently, there are more and more FLASH chip models on the market, and their capacities are also getting larger and larger. The demand for testing different models of FLASH chips is becoming more and more urgent, and higher requirements are being placed on the efficiency of chip screening. This is for testing FLASH chips with different operating voltages, different packaging forms, and different capacities (chip capacities include 128Mbit, 256Mbit, 512Mbit, 1Gbit and 2Gbit; packaging forms are divided into SOP8, SOP16, WSON8 and BGA24 and other packaging forms).

[0003] The current testing method involves writing corresponding test programs on the T800 digital integrated circuit platform according to the specific FLASH chip model to perform electrical parameter and functional tests. However, this testing method has the following two problems: First, the functional testing of FLASH chips is time-consuming, and the current testing method requires testing on the T800 platform, resulting in high platform occupancy and low chip testing efficiency. Second, the different packaging forms and pin numbers of FLASH chips result in a lack of portability in test development, and have disadvantages such as high test development difficulty and long cycle.

[0004] Given the aforementioned testing challenges, there is an urgent need for a general-purpose FLASH chip functional testing system to perform multi-station automated functional testing of FLASH chips with different pin counts, packages, and capacities, thereby reducing the difficulty and time required for test development. Summary of the Invention

[0005] In view of this, this application provides a general-purpose FLASH chip functional testing system to address the shortcomings of the existing technology.

[0006] The first aspect of this application provides a general-purpose FLASH chip functional testing system, comprising: Test the main control board, test the baseboard, and test the sub-board; The test main control board is configured to be electrically connected to the test baseboard via a communication interface; The test base plate is configured to have multiple workstations, each with a European-style socket, and each workstation is used to complete the functional test of a single FLASH chip under test. The test subboard is configured to include a test fixture and multiple package selection resistors. The test fixture is used to hold the FLASH chip under test. All package selection resistors are pull-down resistors. Different models of FLASH chips are defined by setting the package selection resistors. The test subboard is connected to the test baseboard by using a European plug to cooperate with the European socket of the test baseboard. The test control board downloads the test program via serial port to perform functional tests on the FLASH chip under test.

[0007] In one possible implementation of the first aspect, the test main control board further includes: The first control chip is an STM32F103ZET6. A debugging interface is provided for downloading debugging programs to debug the test main control board. The first voltage conversion circuit is used to power the test main control board; The second voltage conversion circuit is connected to the first control chip through multiple voltage interfaces to supply power to the test sub-board. The Start Test button, together with the Start Test indicator and the Test Complete indicator, completes the test of the FLASH chip under test; The FLASH chip model selection button and corresponding indicator light are used to select the model of the FLASH chip under test. Workstation indicator lights are used to observe the status of each workstation on the test base plate.

[0008] In one possible implementation of the first aspect, selecting the model of the FLASH chip under test by means of the selection button and corresponding indicator light includes: The voltage selection button, in conjunction with the high voltage indicator and the low voltage indicator, allows for the selection of the operating voltage of the FLASH chip under test. The capacity selection button, in conjunction with multiple capacity indicator lights, allows for the selection of the capacity of the FLASH chip under test; The package selection button, in conjunction with multiple package indicator lights, allows you to select the package for the FLASH chip under test.

[0009] In one possible implementation of the first aspect, the first voltage conversion circuit is a 5V to 3.3V circuit, and the second voltage conversion circuit includes a 5V to 3.3V circuit and a 5V to 1.8V circuit.

[0010] In one possible implementation of the first aspect, the test main control board further includes: A reset button is used to restore the test main control board to its initial state; Multiple spare buttons are used as trigger keys for preset functions that can be configured later; Multiple temperature indicator lights are used to visualize the monitored temperature status of the test main control board.

[0011] In one possible implementation of the first aspect, the test main control board is electrically connected to the test baseboard via a communication interface, including: The test main control board is connected to the communication circuit through the communication interface, and then electrically connected to the communication interface on the test baseboard to achieve electrical connection with the test baseboard.

[0012] In one possible implementation of the first aspect, the test base plate further includes: The second control chip is an STM32F103CBT7. A debugging interface is provided for downloading debugging programs to debug the test baseboard. The JTAG serial port is used to download the control program of the second control chip and control the second control chip. The workstation status display interface, in conjunction with the workstation indicator lights on the main test control board, displays the status of each workstation on the test base plate; The first I / O port is connected to the power supply of the test sub-board; The second I / O port is connected to the package selection circuit of the test sub-board; The SPI interface is connected to the FLASH chip under test on the test sub-board.

[0013] In one possible implementation of the first aspect, each test sub-board includes three package selection resistors. The three package selection resistors are set by the package selection circuit to define nine different types of FLASH chips.

[0014] In one possible implementation of the first aspect, the test base plate is provided with 8 workstations, all 8 workstations are arranged symmetrically in two rows.

[0015] In one possible implementation of the first aspect, the functional testing of the FLASH chip under test includes: The FLASH chip under test is subjected to full-chip erase test, blank test, full-chip write data test and full-chip verification data test.

[0016] Its beneficial effects are as follows: This invention discloses a universal FLASH chip functional testing system, including a test main control board, a test baseboard, and a test sub-board; the test main control board is configured to be electrically connected to the test baseboard via a communication interface; the test baseboard is configured to have multiple workstations, each with a European-style socket, each workstation being used to complete the functional testing of a single FLASH chip under test; the test sub-board is configured to include test fixtures and multiple package selection resistors, the test fixtures being used to clamp the FLASH chip under test, and the package selection resistors being pull-down resistors, different models of FLASH chips being defined by setting the package selection resistors, and connecting to the test baseboard via European-style plugs and European-style sockets; the test main control board downloads test programs via a serial port to perform functional testing on the FLASH chip under test. This invention uses a single testing system to perform multi-station automated functional testing of FLASH chips with different pin counts, packages, and capacities, reducing the difficulty and cycle of test development, significantly reducing the equipment occupancy rate of FLASH chip testing, and improving the efficiency of FLASH chip screening. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of a general FLASH chip functional testing system framework provided in an embodiment of this application; Figure 2 This is a hardware block diagram of a test main control board in a general FLASH chip functional test system provided in an embodiment of this application; Figure 3 This is a simplified PCB diagram of the test main control board in a general FLASH chip functional test system provided in this application embodiment; Figure 4 This is a hardware block diagram of a test baseboard in a general FLASH chip functional testing system provided in an embodiment of this application; Figure 5 This is a simplified PCB diagram of the test baseboard in a general FLASH chip functional testing system provided in this application embodiment. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] In this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0021] Example In the existing technology, the current testing method involves writing corresponding test programs on the T800 digital integrated circuit platform according to the specific FLASH chip model to perform electrical parameter and functional tests. However, this testing method has the following two problems: First, the functional testing of FLASH chips is time-consuming, and the current testing method requires testing on the T800 platform, resulting in high platform occupancy and low chip testing efficiency. Second, the different packaging forms and pin numbers of FLASH chips result in a lack of portability in test development, and have disadvantages such as high test development difficulty and long cycle.

[0022] Therefore, this application provides a general-purpose FLASH chip functional testing system, such as... Figure 1 As shown, it includes: Test the main control board, test the baseboard, and test the sub-board; The test main control board is configured to be electrically connected to the test baseboard via a communication interface; The test base plate is configured to have multiple workstations, each with a European-style socket, and each workstation is used to complete the functional test of a single FLASH chip under test. The test subboard is configured to include a test fixture and multiple package selection resistors. The test fixture is used to hold the FLASH chip under test. All package selection resistors are pull-down resistors. Different models of FLASH chips are defined by setting the package selection resistors. The test subboard is connected to the test baseboard by using a European plug to cooperate with the European socket of the test baseboard. The test control board downloads the test program via serial port to perform functional tests on the FLASH chip under test.

[0023] This embodiment is a general testing system for FLASH chip functionality, which includes hardware and software components. The hardware is further divided into a test main control board, a test baseboard, and test daughter boards. The software component is a general test program framework that uses 485 communication to achieve data exchange between the test main control board and the test baseboard. The operator only needs to select the package, operating voltage, and capacity of the FLASH chip to be tested on the test main control board. The test main control board will automatically verify the chip model on the test daughter board against the manually selected model. Once the two match, the test can be performed.

[0024] Please refer to the details. Figure 2 and Figure 3 The test main control board includes: The first control chip is an STM32F103ZET6. The debugging interface allows for the debugging of the test main control board by downloading the debugging program. PCB board debugging is a key step in ensuring that the circuit design functions normally, meets the performance standards, and is stable and reliable. It involves multiple dimensions such as parameter coverage function verification, electrical performance, signal quality, and power supply stability. It is a well-known technology in this field, and will not be elaborated on in this embodiment. The first voltage conversion circuit is a 5V to 3.3V circuit, used to power the test main control board; The second voltage conversion circuit includes a 5V to 3.3V circuit and a 5V to 1.8V circuit. The first control chip supplies power to the test sub-board after being connected to the corresponding second voltage conversion circuit through a voltage interface. The Start Test button works in conjunction with the Start Test indicator light and the Test Complete indicator light. When the Start Test button is clicked, the Start Test indicator light illuminates to indicate that the test has started; when the test is completed, the Test Complete indicator light illuminates to indicate that the test has finished. The FLASH chip model selection button and multiple indicator lights include: a voltage selection button, which works with the high voltage and low voltage indicator lights to select the operating voltage of the FLASH chip under test; and a capacity selection button, which works with multiple capacity indicator lights, such as... Figure 3The 256KB indicator light illuminates, indicating that the selected FLASH chip under test has a capacity of 256KB; the package selection button, in conjunction with multiple package indicator lights, such as... Figure 3 When the indicator light for the SOP8 package is lit, it means that the package of the FLASH chip under test is selected as SOP8. The model of the FLASH chip under test can be selected by using the selection button and the indicator light. There are 8 workstation indicator lights in total, which correspond to the status of 8 workstations on the monitoring and testing base plate, such as... Figure 3 When the indicator light at station 1 flashes, it indicates that testing is in progress at station 1; when the indicator light at station 1 changes from flashing to solid, it indicates that testing at station 1 is complete.

[0025] In addition, the test control board also includes a reset button to restore the test control board to its initial state; multiple temperature indicator lights, specifically including a low temperature indicator light, a normal temperature indicator light, and a high temperature indicator light, to correspond to the monitoring temperature of the test control board respectively; multiple spare buttons and multiple spare indicator lights to facilitate the subsequent expansion and addition of the test control board's functions.

[0026] The test main control board is electrically connected to the test baseboard through a communication interface, that is, to establish data exchange between the test main control board and the test baseboard regarding 458 communication. The communication circuit is a 458 communication circuit, which is a technology well known to those skilled in the art, and will not be elaborated on in this embodiment.

[0027] Please refer to the details. Figure 4 and Figure 5 The test base plate includes: The second control chip is an STM32F103CBT7. The debugging interface is used to download debugging programs to debug the test baseboard. This has already been explained in the section on debugging the test main control board, so it will not be repeated here. The JTAG serial port is used to download the control program for the second control chip and control the second control chip. The workstation status display interface works in conjunction with the workstation indicator lights on the main control board of the test, and sends corresponding commands through the work status display interface to make the workstation indicator lights flash or stay on. Multiple I / O ports are used to connect to the power supply of the test sub-board and to the package selection circuit of the test sub-board, respectively. The SPI interface connects to the FLASH chip under test on the test daughterboard. SPI is a high-speed, full-duplex, synchronous serial communication protocol used for high-speed data transmission between short-distance devices, improving the efficiency of functional testing of the FLASH chip under test.

[0028] In this embodiment, the test base plate has a total of 8 workstations, arranged symmetrically in two rows.

[0029] The test subboard contains: The test fixture includes multiple package selection resistors and corresponding package selection circuitry. The test fixture holds the FLASH chip under test and can be modular, adjustable, or matrix-designed to accommodate FLASH chips with varying pin counts. The multiple package selection resistors are pull-down resistors. The function of a pull-down resistor is to pull the signal line to ground when there is no drive signal, resulting in a stable low level. When the drive source outputs a high level, the pull-down resistor and the drive source form a voltage divider, but because the output impedance of the drive source is much lower than the pull-down resistor, the signal line remains stable at a high level. In other words, the package selection circuitry allows the pull-down resistors to be in a high-level, low-level, or high-impedance state. This embodiment includes three package selection resistors. The package selection circuitry configures these three pull-down resistors to define nine different FLASH chip models. Testing different FLASH chip models only requires replacing the corresponding test board.

[0030] In this embodiment, the test main control board and the test baseboard exchange data via 458 communication. The test baseboard and the test sub-board are connected (i.e., exchange data) via a European socket and a European plug. After the system is powered on, the model of the FLASH chip under test is configured using the package selection button, voltage selection button, and capacity selection button. Then, after the workstation indicator light is lit (indicating that the workstation is in normal condition and can be tested), press the start test button to start the test. When the work indicator light stops flashing, it indicates that the test of the current workstation is complete.

[0031] This embodiment can complete multi-station automated functional testing of FLASH chips with different pin counts, packages, capacities, and operating voltages using a single testing system. This reduces the difficulty and cycle of test development, significantly reduces the equipment occupancy rate of FLASH chip testing, and improves the efficiency of FLASH chip screening. Furthermore, the hardware and software program framework has high portability, and corresponding functional tests can be achieved by making simple modifications to other chips.

[0032] In some embodiments, the test main control board further includes: The first control chip is an STM32F103ZET6. A debugging interface is provided for downloading debugging programs to debug the test main control board. The first voltage conversion circuit is used to power the test main control board; The second voltage conversion circuit is connected to the first control chip through multiple voltage interfaces to supply power to the test sub-board. The Start Test button, together with the Start Test indicator and the Test Complete indicator, completes the test of the FLASH chip under test; The FLASH chip model selection button and corresponding indicator light are used to select the model of the FLASH chip under test. Workstation indicator lights are used to observe the status of each workstation on the test base plate.

[0033] In some embodiments, selecting the model of the FLASH chip under test is accomplished by using the selection button and corresponding indicator lights, including: The voltage selection button, in conjunction with the high voltage indicator and the low voltage indicator, allows for the selection of the operating voltage of the FLASH chip under test. The capacity selection button, in conjunction with multiple capacity indicator lights, allows for the selection of the capacity of the FLASH chip under test; The package selection button, in conjunction with multiple package indicator lights, allows you to select the package for the FLASH chip under test.

[0034] In some embodiments, the first voltage conversion circuit is a 5V to 3.3V circuit, and the second voltage conversion circuit includes a 5V to 3.3V circuit and a 5V to 1.8V circuit.

[0035] In some embodiments, the test main control board further includes: A reset button is used to restore the test main control board to its initial state; Multiple spare buttons are used as trigger keys for preset functions that can be configured later; Multiple temperature indicator lights are used to visualize the monitored temperature status of the test main control board.

[0036] In some embodiments, the test main control board is electrically connected to the test baseboard via a communication interface, including: The test main control board is connected to the communication circuit through the communication interface, and then electrically connected to the communication interface on the test baseboard to achieve electrical connection with the test baseboard.

[0037] In some embodiments, the test base plate further includes: The second control chip is an STM32F103CBT7. A debugging interface is provided for downloading debugging programs to debug the test baseboard. The JTAG serial port is used to download the control program of the second control chip and control the second control chip. The workstation status display interface, in conjunction with the workstation indicator lights on the main test control board, displays the status of each workstation on the test base plate; The first I / O port is connected to the power supply of the test sub-board; The second I / O port is connected to the package selection circuit of the test sub-board; The SPI interface is connected to the FLASH chip under test on the test sub-board.

[0038] In some embodiments, each test subboard includes three package selection resistors. The three package selection resistors are set by the package selection circuit to define nine different types of FLASH chips.

[0039] In some embodiments, the test base plate has 8 workstations, all of which are arranged symmetrically in two rows.

[0040] In some embodiments, functional testing of the FLASH chip under test includes: The FLASH chip under test is subjected to full-chip erase test, blank test, full-chip write data test and full-chip verification data test.

[0041] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computing software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0042] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0043] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A general-purpose FLASH chip functional testing system, characterized in that, include: Test the main control board, test the baseboard, and test the sub-board; The test main control board is configured to be electrically connected to the test baseboard via a communication interface; The test base plate is configured to have multiple workstations, each with a European-style socket, and each workstation is used to complete the functional test of a single FLASH chip under test. The test subboard is configured to include a test fixture and multiple package selection resistors. The test fixture is used to hold the FLASH chip under test. All package selection resistors are pull-down resistors. Different models of FLASH chips are defined by setting the package selection resistors. The test subboard is connected to the test baseboard by using a European plug to cooperate with the European socket of the test baseboard. The test control board downloads the test program via serial port to perform functional tests on the FLASH chip under test.

2. The general-purpose FLASH chip functional testing system according to claim 1, characterized in that, The test main control board also includes: The first control chip is an STM32F103ZET6. A debugging interface is provided for downloading debugging programs to debug the test main control board. The first voltage conversion circuit is used to power the test main control board; The second voltage conversion circuit is connected to the first control chip through multiple voltage interfaces to supply power to the test sub-board. The Start Test button, together with the Start Test indicator and the Test Complete indicator, completes the test of the FLASH chip under test; The FLASH chip model selection button and corresponding indicator light are used to select the model of the FLASH chip under test. Workstation indicator lights are used to observe the status of each workstation on the test base plate.

3. The general-purpose FLASH chip functional testing system according to claim 2, characterized in that, By using the selection button and corresponding indicator lights, the model selection of the FLASH chip under test can be completed, including: The voltage selection button, in conjunction with the high voltage indicator and the low voltage indicator, allows for the selection of the operating voltage of the FLASH chip under test. The capacity selection button, in conjunction with multiple capacity indicator lights, allows for the selection of the capacity of the FLASH chip under test; The package selection button, in conjunction with multiple package indicator lights, allows you to select the package for the FLASH chip under test.

4. The general-purpose FLASH chip functional testing system according to claim 2, characterized in that, The first voltage conversion circuit is a 5V to 3.3V circuit, and the second voltage conversion circuit includes a 5V to 3.3V circuit and a 5V to 1.8V circuit.

5. The general-purpose FLASH chip functional testing system according to claim 1, characterized in that, The test main control board also includes: A reset button is used to restore the test main control board to its initial state; Multiple spare buttons are used as trigger keys for preset functions that can be configured later; Multiple temperature indicator lights are used to visualize the monitored temperature status of the test main control board.

6. The general-purpose FLASH chip functional testing system according to claim 1, characterized in that, The test main control board is electrically connected to the test baseboard via a communication interface, including: The test main control board is connected to the communication circuit through the communication interface, and then electrically connected to the communication interface on the test baseboard to achieve electrical connection with the test baseboard.

7. The general-purpose FLASH chip functional testing system according to claim 2, characterized in that, The test base plate also includes: The second control chip is an STM32F103CBT7. A debugging interface is provided for downloading debugging programs to debug the test baseboard. The JTAG serial port is used to download the control program of the second control chip and control the second control chip. The workstation status display interface, in conjunction with the workstation indicator lights on the main test control board, displays the status of each workstation on the test base plate; The first I / O port is connected to the power supply of the test sub-board; The second I / O port is connected to the package selection circuit of the test sub-board; The SPI interface is connected to the FLASH chip under test on the test sub-board.

8. The general-purpose FLASH chip functional testing system according to claim 7, characterized in that, Each test subboard contains three package selection resistors. The package selection circuit sets the three package selection resistors to define nine different types of FLASH chips.

9. The general-purpose FLASH chip functional testing system according to claim 1, characterized in that, The test base plate has 8 workstations, all of which are arranged symmetrically in two rows.

10. A general-purpose FLASH chip functional testing system according to claim 1, characterized in that, Functional testing of the FLASH chip under test includes: The FLASH chip under test is subjected to full-chip erase test, blank test, full-chip write data test and full-chip verification data test.

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