An AXI interconnection module, method, electronic device, storage medium and product

Abstract

The application provides an AXI interconnection module, method, electronic equipment, storage medium and product, and relates to the technical field of computers.The AXI interconnection module comprises a sending arbitration module, which is used for receiving access transaction requests, performing arbitration, determining access transaction requests that need to be cached and sending the access transaction requests to a cache control module, and determining target access transaction requests and sending the target access transaction requests to corresponding target slave devices; a receiving arbitration module, which is used for receiving access transaction responses, performing arbitration, determining access transaction responses that need to be cached and sending the access transaction responses to the cache control module, and determining target access transaction responses and sending the target access transaction responses to corresponding source master devices; the cache control module, which is used for storing the access transaction requests that need to be cached and the access transaction responses that need to be cached to a cache area; and a response request, which is used for calling the target access transaction requests and the target access transaction responses from the cache area. The application can efficiently and orderly implement an AXI interconnection mechanism under a multi-master device / multi-slave device architecture.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly to an AXI interconnect module, method, electronic device, storage medium, and product. Background Technology

[0002] AXI4 (Advanced eXtensible Interface 4) is an important component of AMBA4 (Advanced Microcontroller Bus Architecture 4), used to enable high-speed communication between on-chip modules. The AXI4 protocol is a point-to-point transmission protocol, only allowing information transmission between two modules. To achieve AXI4 protocol transmission between multiple masters and multiple slaves, an AXI interconnect module is needed to route AXI transmission transactions between the devices.

[0003] AXI interconnect modules include various topologies such as single master / multiple slave devices, multiple master / single slave devices, and multiple master / multiple slave devices, with the multiple master / multiple slave device structure being the most complex. When performing AXI routing for multiple master / multiple slave devices, it is necessary to ensure transparent AXI transmission for various master-slave link combinations, while also taking into account several characteristics of AXI4, such as outstanding transactions, out-of-order delivery, and read interleave. This necessitates the design of complex caching structures and arbitration logic.

[0004] However, on-chip resources are limited, so the designed register transfer level (RTL) logic must minimize resource consumption while meeting functional requirements. Summary of the Invention

[0005] This application provides an AXI interconnect module, method, electronic device, storage medium, and product to at least solve the above-mentioned technical problems existing in the prior art.

[0006] According to a first aspect of this application, an AXI interconnect module is provided, the AXI interconnect module comprising: a transmitting arbitration module, a buffer control module, a buffer area, and a receiving arbitration module, wherein...

[0007] The sending arbitration module is used to receive access transaction requests initiated by each master device, arbitrate the access transaction requests, determine the access transaction requests that need to be cached and send them to the cache control module, and determine the target access transaction request and send it to the corresponding destination slave device.

[0008] The receiving arbitration module is used to receive access transaction responses returned by each slave device, arbitrate the access transaction responses, determine the access transaction responses that need to be cached and send them to the caching control module, and determine the target access transaction response and send it to the corresponding source master device.

[0009] The cache control module is connected to the sending arbitration module, the receiving arbitration module, and the cache area, respectively, and is used to store the access transaction request and the access transaction response that need to be cached in the cache area; and to retrieve the target access transaction request and the target access transaction response from the cache area in response to the requests of the sending arbitration module and the receiving arbitration module.

[0010] In one possible implementation, the arbitration sending module includes a first master device interface, a device mapping resolution module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface, wherein,

[0011] The first master device interface is used to connect to the AXI output channel interface of each master device and receive access transaction requests initiated by each master device;

[0012] The device mapping and parsing module is used to determine the destination slave device corresponding to the access transaction request;

[0013] The priority allocation module is used to determine the target priority value of the access transaction request;

[0014] The first cache interface module is used to obtain the status information of the cache area through the cache control module;

[0015] The first arbitration module is used to arbitrate and schedule access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the buffer, and to filter out the target access transaction requests.

[0016] The first slave device interface is used to connect to the AXI input channel interface of each slave device and send the target access transaction request to the corresponding destination slave device.

[0017] In one possible implementation, the priority allocation module is further configured to:

[0018] Determine the initial priority value for the access transaction request;

[0019] The access transaction request is triggered when the master and slave devices corresponding to the previous access transaction request are the same, and the access address ranges overlap.

[0020] If the initial priority value is greater than the current urgency of the preceding access transaction request, then the initial priority value of the access transaction request is determined to be the target priority value.

[0021] If the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then the current urgency of the preceding access transaction request is determined as the target priority value of the access transaction request.

[0022] In one possible implementation, the priority allocation module is further configured to:

[0023] The initial priority value is determined based on the emergency transaction flag, channel priority value, and quality of service signal value corresponding to the access transaction request.

[0024] In one possible implementation, the cache control module is further configured to:

[0025] Based on the data portion capacity of the access transaction request and a preset cacheable capacity threshold, a cache flag for the access transaction request is determined. The cache flag indicates whether the data portion of the access transaction request is allowed to enter the cache area.

[0026] In one embodiment, the cache area includes a general cache area and an emergency cache area, and the first arbitration module is further configured to:

[0027] If the access transaction request is a normal transaction, the instruction part of the access transaction request is stored in the normal buffer. If the normal buffer is full, it enters a waiting state as an instruction to be sent.

[0028] If the access transaction request is an urgent transaction, the instruction portion of the access transaction request is stored in the normal buffer. If the normal buffer is full, the instruction portion of the access transaction request is stored in the emergency buffer as an instruction to be sent.

[0029] In one possible implementation, the first arbitration module is further configured to:

[0030] Based on write instruction filtering rules and read instruction filtering rules, the instructions to be sent corresponding to each master device are filtered to obtain candidate sending instructions;

[0031] Based on the urgency value, the target sending command is determined from the candidate sending commands.

[0032] In one possible implementation, the first arbitration module is further configured to:

[0033] Based on the unique identifier of the target transmission command, the master device number, and the command ID, a transmission record entry is generated;

[0034] The transmission record entry is recorded in the transmission record queue of the destination slave device corresponding to the target transmission command.

[0035] In one possible implementation, the first arbitration module is further configured to:

[0036] If the cache tag indicates that the data portion of the access transaction request is allowed to be cached, then the data portion is stored in the cache area as data to be sent.

[0037] If the cache flag indicates that the data portion of the access transaction request is not allowed to be cached, then the data portion is temporarily stored in the AXI data channel of the master device as data to be sent.

[0038] In one possible implementation, the first arbitration module is further configured to:

[0039] Based on the transmission record entry of the target transmission instruction, the target transmission data is determined from the data to be transmitted in the buffer.

[0040] If there is no corresponding data to be sent in the buffer, then wait and obtain the target data to be sent from the write data channel of the corresponding master device.

[0041] In one possible implementation, the receiving arbitration module includes a second master device interface, a second slave device interface, a second arbitration module, and a second cache interface module, wherein;

[0042] The second slave device interface is used to receive the access transaction response returned by the slave device;

[0043] The second cache interface module receives the cache status information sent by the cache control module;

[0044] The second arbitration module is used to arbitrate and schedule access transaction responses based on the state information of the cache, and to filter out the target access transaction responses.

[0045] The second master device interface is used to send the target access transaction response to the corresponding source master device.

[0046] In one possible implementation, the second arbitration module is further configured to:

[0047] Based on the ID signal of the access transaction response, determine the master device number and instruction unique identifier corresponding to the access transaction response;

[0048] Based on the master device number and the instruction unique identifier, determine whether there is space in the cache area. If so, store the access transaction response in the cache area as data to be received through the cache control module.

[0049] In one possible implementation, the second arbitration module is further configured to:

[0050] In response to receiving data from an access transaction response, the target instruction in the cache is retrieved, wherein the target instruction is the earliest instruction stored in the cache.

[0051] If the target instruction and the data in the access transaction response have the same access type and the same master device ID, the target received data is obtained from the data to be received in the buffer based on the target instruction.

[0052] According to a second aspect of this application, an AXI interconnection method is provided, the method being applied to an AXI interconnection module, the AXI interconnection module comprising: a transmitting arbitration module, a buffer control module, a buffer area, and a receiving arbitration module, the method comprising:

[0053] The sending arbitration module receives access transaction requests initiated by each master device, arbitrates the access transaction requests, determines the access transaction requests that need to be cached and sends them to the caching control module, and determines the target access transaction request and sends it to the corresponding destination slave device.

[0054] The receiving arbitration module receives access transaction responses returned by each slave device, arbitrates the access transaction responses, determines the access transaction responses that need to be cached and sends them to the caching control module, and determines the target access transaction response and sends it to the corresponding source master device.

[0055] The cache control module stores the access transaction requests and responses that need to be cached into the cache area; and in response to the requests from the sending arbitration module and the receiving arbitration module, retrieves the target access transaction requests and target access transaction responses from the cache area.

[0056] In one possible implementation, the arbitration sending module includes a first master device interface, a device mapping resolution module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface. Correspondingly, the method further includes:

[0057] The first master device interface is connected to the AXI output channel interface of each master device to receive access transaction requests initiated by each master device.

[0058] The device mapping and resolution module determines the destination device corresponding to the access transaction request.

[0059] The priority allocation module determines the target priority value of the access transaction request.

[0060] The cache control module obtains the cache status information through the first cache interface module.

[0061] The first arbitration module arbitrates and schedules access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the buffer, and selects the target access transaction requests.

[0062] The first slave device interface is used to connect with the AXI input channel interface of each slave device to send the target access transaction request to the corresponding destination slave device.

[0063] In one possible implementation, determining the target priority value of the access transaction request includes:

[0064] Determine the initial priority value for the access transaction request;

[0065] The access transaction request is triggered when the master and slave devices corresponding to the previous access transaction request are the same, and the access address ranges overlap.

[0066] If the initial priority value is greater than the current urgency of the preceding access transaction request, then the initial priority value of the access transaction request is determined to be the target priority value.

[0067] If the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then the current urgency of the preceding access transaction request is determined as the target priority value of the access transaction request.

[0068] In one possible implementation, determining the initial priority value of the access transaction request includes:

[0069] The initial priority value is determined based on the emergency transaction flag, channel priority value, and quality of service signal value corresponding to the access transaction request.

[0070] According to a third aspect of this application, an electronic device is provided, comprising:

[0071] At least one processor; and,

[0072] A memory communicatively connected to the at least one processor; wherein,

[0073] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in this application.

[0074] According to a fourth aspect of this application, a non-transitory computer-readable storage medium is provided storing computer instructions for causing the computer to perform the methods described in this application.

[0075] According to a fifth aspect of this application, a computer program product is provided, comprising a computer program or instructions that, when executed by a processor, implement the method described in this application.

[0076] The AXI interconnect module, method, electronic device, storage medium, and product of this application construct an efficient multi-master / multi-slave AXI interconnect mechanism through the coordinated operation of a sending arbitration module, a buffer control module, a buffer area, and a receiving arbitration module. This mechanism not only fully complies with the AXI4 protocol specification but also ensures the correctness and orderliness of data transmission through arbitration scheduling, buffer management, and other technical means.

[0077] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0078] The above and other objects, features, and advantages of exemplary embodiments of this application will become readily apparent from the following detailed description taken in conjunction with the accompanying drawings. Several embodiments of this application are illustrated in the drawings by way of example and not limitation, in which:

[0079] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

[0080] Figure 1 A schematic diagram of the composition structure of an AXI interconnect module according to an embodiment of this application is shown;

[0081] Figure 2 A schematic diagram of the composition structure of an arbitration transmission module according to an embodiment of this application is shown;

[0082] Figure 3 A schematic diagram illustrating the implementation flow of the method for accessing the cache portion of transaction instructions according to an embodiment of this application is shown;

[0083] Figure 4 A schematic diagram illustrating the implementation flow of the method for sending the access transaction instruction portion according to an embodiment of this application is shown;

[0084] Figure 5 The diagram illustrates the implementation flow of the write access transaction data caching method according to an embodiment of this application;

[0085] Figure 6 A schematic diagram illustrating the implementation flow of the write access transaction data portion sending method according to an embodiment of this application is shown;

[0086] Figure 7 A schematic diagram of the composition structure of an arbitration receiving module according to an embodiment of this application is shown;

[0087] Figure 8 A schematic diagram illustrating the implementation flow of the method for accessing the cached portion of transaction response data according to an embodiment of this application is shown;

[0088] Figure 9 A schematic diagram illustrating the implementation flow of the method for sending the access transaction response data portion according to an embodiment of this application is shown;

[0089] Figure 10 A schematic diagram illustrating the implementation flow of an AXI interconnection method according to an embodiment of this application is shown;

[0090] Figure 11 A schematic diagram of the composition structure of an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0091] To make the objectives, features, and advantages of this application more apparent and understandable, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0092] In a multi-master / multi-slave AXI interconnect topology, each master device and slave device maintain independent communication relationships. The AXI interconnect module routes access transactions initiated by the master device to the target slave device according to preset rules, and sends the response transactions returned by the slave device back to the corresponding source master device.

[0093] According to the first aspect of this application, an AXI interconnect module is proposed for use in an AXI interconnect topology with multiple master / slave devices. For example... Figure 1 As shown, the AXI interconnect module includes a sending arbitration module, a buffer control module, a buffer area, and a receiving arbitration module.

[0094] The arbitration module is used to receive access transaction requests initiated by each master device, arbitrate the access transaction requests, determine the access transaction requests that need to be cached and send them to the cache control module, and determine the target access transaction request and send it to the corresponding destination slave device.

[0095] Specifically, the arbitration module sends data to multiple master devices (such as...). Figure 1 Connect the AXI output channel interface of Master1-MasterN and multiple slave devices (such as...) Figure 1The AXI input channel interface is connected to Slave1-SlaveM. The master device refers to a functional module capable of actively initiating data access requests, such as the CPU, GPU, and DMA controller. These modules send read and write access commands to other devices according to their needs. The arbitration module receives access transaction requests initiated by each master device; these requests contain both command and data components.

[0096] Next, the arbitration module prioritizes and arbitrates conflicts among various access transaction requests. Based on preset rules (such as transaction urgency, channel priority, etc.), combined with the storage status of the cache and the readiness of the slave devices, it determines whether the access transaction request needs to be cached and the specific caching operation. Then, it selects the most suitable access transaction request to send, i.e., the target access transaction request. The target access transaction request contains the target data and the target sending command, which the arbitration module sends to the target slave device through the corresponding slave device interface. The target slave device is the passively responding device to which the access transaction request is directed, such as a memory or peripheral controller. These devices will perform corresponding read and write operations based on the received request and return the result access transaction response.

[0097] The arbitration module receives access transaction responses returned by each slave device, arbitrates the access transaction responses, determines the access transaction responses that need to be cached and sends them to the cache control module, and determines the target access transaction response and sends it to the corresponding source master device.

[0098] Specifically, the arbitration receiving module and multiple master devices (such as...) Figure 1 The AXI input channel interface connection of Master1-MasterN and multiple slave devices (such as Master1-MasterN) is supported. Figure 1 The AXI output channel interface of Slave1-SlaveM is connected. When the slave device receives an access transaction request transmitted by the arbitration module, it will perform corresponding operations according to the request type (read request or write request): if it is a read request, it will read data from the specified address; if it is a write request, it will write the transmitted data to the target address. After completing the operation, the corresponding access transaction response will be generated.

[0099] These access transaction responses are transmitted from the device's AXI output channel to the corresponding interface of the receiving arbitration module. Upon receiving the response, the receiving arbitration module combines the cache's storage status (e.g., remaining capacity, existing response storage status) with preset caching rules (e.g., response data size, transaction priority) to determine whether the access transaction response needs caching and the specific caching operation. Simultaneously, it considers the master device's readiness status (e.g., whether the AXI input channel is idle) and the response association order (e.g., responses from the same master device with the same ID must be returned in the original request order) to filter out the most suitable target access transaction response for sending. Finally, the receiving arbitration module returns the target access transaction response to the initiating master device through the target master device's AXI input channel, completing the entire transaction response loop.

[0100] The cache control module is connected to the sending arbitration module, the receiving arbitration module, and the cache area respectively. It is used to store the access transaction requests and access transaction responses that need to be cached into the cache area; and to retrieve the target access transaction requests and target access transaction responses from the cache area in response to the requests from the sending arbitration module and the receiving arbitration module.

[0101] Specifically, the cache control module receives cached access transaction requests from the arbitration module and categorizes them into corresponding storage areas in the cache according to preset caching rules (such as transaction priority, data size, and whether it is an Urgent transaction). Simultaneously, it receives cached access transaction responses forwarded by the arbitration module and stores them according to their association with the original transaction.

[0102] On the other hand, when the sending arbitration module needs to retrieve the target access transaction request, the cache control module locates and retrieves the corresponding request data from the cache based on the specified transaction identifier, such as the master device number or instruction unique identifier (TAG value), and feeds it back to the sending arbitration module. When the receiving arbitration module needs the target access transaction response, it also retrieves the corresponding response data from the cache based on the matching conditions of its requirements and feeds it back, while simultaneously updating the storage status of the relevant transactions in the cache.

[0103] The AXI interconnect module of this application constructs an efficient multi-master, multi-slave AXI interconnect mechanism through the coordinated operation of the sending arbitration module, the buffer control module, the buffer area, and the receiving arbitration module. This mechanism not only fully complies with the AXI4 protocol specification, but also ensures the correctness and orderliness of data transmission through techniques such as priority scheduling, dynamic buffer management, and response matching.

[0104] In another possible embodiment of this application, such as Figure 2As shown, the arbitration sending module includes a first master device interface, a device mapping and parsing module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface.

[0105] The first master device interface is used to connect to the AXI output channel interfaces of each master device and receive access transaction requests initiated by each master device. The AXI output channels include write address channels, write data channels, and read address channels.

[0106] The device mapping and resolution module is used to determine the destination slave device corresponding to the access transaction request. Specifically, the device mapping and resolution module is connected to the first master device interface and receives the access transaction request passed in from the first master device interface. It analyzes the access transaction request according to predefined mapping rules to determine that the access transaction request needs to access the destination slave device. Mapping rules may include address range-based rules, such as a fixed address range being exclusive to a specific slave device, or sideband information-based rules, such as matching the corresponding slave device through specific sideband signal identifiers.

[0107] The priority allocation module is used to determine the target priority value of access transaction requests. The priority value is non-negative; the lower the value, the higher the priority, and the earlier the corresponding access transaction is sent. Specifically, the priority allocation module receives the access transaction request transmitted by the device mapping and parsing module, extracts the channel priority value, service quality signal value, and urgent transaction flag carried in the request, and determines the target priority value as the basis for arbitration scheduling.

[0108] The first cache interface module is used to obtain the status information of the cache area through the cache control module. Specifically, the first cache interface module establishes communication with the cache control module to obtain the status information of the cache area in real time, such as the cache area occupancy status, and synchronizes it to the first arbitration module.

[0109] The first arbitration module is used to arbitrate and schedule access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the cache, and to filter out the target access transaction requests. Specifically, this module first classifies and determines the access transaction requests based on the above information: according to preset caching rules, it distinguishes between access transaction requests that need to be cached and those that do not need to be cached, and passes the former to the cache control module for cache management. Subsequently, by combining the current status of the destination slave device (such as channel idle time), the target priority value of the transaction, and the storage status of the cache, it determines the most suitable target access transaction request to send from the pending access transaction requests (including those that are cached and those that do not need to be cached). And it sends it to the corresponding destination slave device through the first slave device interface.

[0110] In another embodiment of this application, the priority allocation module is further configured to: determine the initial priority value of the access transaction request; in response to the fact that the master device and slave device corresponding to the access transaction request and the preceding access transaction request are the same and the access address ranges overlap, if the initial priority value is greater than the current urgency of the preceding access transaction request, then the initial priority value of the access transaction request is determined to be the target priority value; if the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then the current urgency of the preceding access transaction request is determined to be the target priority value of the access transaction request.

[0111] First, the initial priority value is determined based on the urgent transaction flag, channel priority value, and quality of service (QoS) signal value corresponding to the access transaction request. Furthermore, since the execution order of access transactions initiated by the same master device to the same access address of the same slave device cannot be changed by the reordering function of the AXI interconnect module (otherwise, logical errors such as read-before-write may occur, resulting in inconsistencies between the read and write content and expectations), it is necessary to associate the target priority value of the access transaction request with the preceding access transactions already existing in the cache.

[0112] Specifically, it is necessary to first locate the last write access transaction in the cache that has the same master device number and slave device number as the current access transaction request, and whose access address range overlaps. Then, obtain the current urgency value (not the initial priority value) of the preceding access transaction. Finally, determine the target priority value using the following formula (1):

[0113] (1)

[0114] Where P is the target priority value; E is the urgency of the preceding access transaction. This is the initial priority value; if... If the value is greater than E, then the target priority value is determined to be... Otherwise, the target priority value is set to E.

[0115] Each access transaction is assigned an urgency value to mark its dynamic priority, which is used by the subsequent arbitration logic to determine the sending order of access transactions. Therefore, when an access transaction is stored in the cache, the priority value calculated above is used as the initial urgency value and stored in the cache entry corresponding to that access transaction.

[0116] The solution in this embodiment avoids read / write logic errors caused by reordering by constraining the priority relationship of transactions with overlapping addresses on the same master-slave device. While improving the efficiency of multi-device interconnection, it ensures the consistency and correctness of data access, thus balancing system performance and logical reliability.

[0117] In another embodiment of this application, the priority allocation module is further configured to determine an initial priority value based on the urgent transaction flag (Urgent signal value), channel priority value, and QoS signal value corresponding to the access transaction request.

[0118] Specifically, the initial priority value can be determined using the following formula (2):

[0119] (2)

[0120] in, The initial priority value is represented by U; the Urgent signal value is 1 when the access transaction is not urgent, otherwise it is 0; the channel priority value is represented by H, which is a non-negative value. The lower the value, the higher the channel priority; Q represents the inverse value of the QoS signal, obtained by inverting the QoS signal, and the value range is [0, 15]; α and β are non-negative parameters. When α is 0, it means that the channel priority is not considered. When β is 0, it means that the QoS signal is not considered. The larger the value of α and β, the higher the proportion of the corresponding channel priority and QoS signal priority; the function of 1 is to include non-zero initial priority values ​​for non-urgent transactions, while the initial priority value of urgent transactions is zero because U is 0, so that the initial urgency value of non-urgent transactions is always greater than or equal to 1, and the initial urgency value of urgent transactions is always 0, ensuring that urgent transactions always have the highest priority.

[0121] This embodiment determines the initial priority value by combining emergency transaction markers, channel priority values, and QoS signal values, which can accurately distinguish the urgency and importance of access transactions. This ensures that urgent transactions are processed first, avoiding blockage of critical tasks, while also rationally scheduling regular transactions based on channel priority and QoS requirements, reducing resource contention conflicts. Simultaneously, it balances the processing priorities of different types of transactions, improving the overall response efficiency and resource utilization of the AXI interconnect module in multi-master, multi-slave device scenarios, and ensuring efficient and stable system operation.

[0122] In another embodiment of this application, the cache control module is further configured to: determine a cache flag for the access transaction request based on the data portion capacity of the access transaction request and a preset cacheable capacity threshold, wherein the cache flag indicates whether the data portion of the access transaction request is allowed to enter the cache area.

[0123] AXI4 supports a maximum burst length of 256. If the data width is 128 bits (16 bytes), a single transaction requires 4kB of data, meaning that caching a single long transaction would occupy 4kB of on-chip resources. If the system has a large number of cached instructions and a large number of master devices, the caching demand of a large number of long transactions will quickly exhaust on-chip storage resources. In reality, short data transactions account for a higher proportion in actual use cases, and these are often critical transactions with extremely high real-time requirements (such as interrupted transactions). These transactions have small data volumes but require fast responses. If long transactions occupy a large amount of cache, causing short transactions to be unable to be cached and forced to wait, it will seriously affect the system's real-time performance.

[0124] Therefore, the solution in this embodiment proposes to determine whether to cache the data portion based on the capacity of the data portion, specifically:

[0125] First, a maximum cacheable capacity threshold is set for the data portion of the access transaction, such as 512 bytes. If the data portion capacity is less than or equal to this threshold, the cache mark for the access transaction request is determined to be allowed to be cached, meaning that the data portion is allowed to be temporarily stored in the cache area.

[0126] If the data portion exceeds the threshold, when caching the instruction portion of the transaction, the cache mark for the access transaction request is determined to be not allowed to be cached, that is, the data portion is not allowed to enter the cache area and stays directly in the AXI data channel of the master device.

[0127] This embodiment determines the cache flag based on the size of the access transaction request data portion and a preset cacheable threshold, thus achieving dynamic management of data caching. Specifically, large-volume transaction data is transmitted directly without caching, while small-sized data is stored in the cache. This reduces unnecessary cache usage and chip resource consumption, while improving the cache's efficiency in utilizing small data and preventing cache space from being squeezed out by large data. It optimizes resource allocation while ensuring transmission efficiency, making it particularly suitable for scenarios with limited on-chip resources.

[0128] In another embodiment of this application, the cache area includes a normal cache area and an emergency cache area. The first arbitration module is further configured to: if the access transaction request is a normal transaction, store the instruction part of the access transaction request in the normal cache area; if the normal cache area is full, enter a waiting state as an instruction to be sent; if the access transaction request is an emergency transaction, store the instruction part of the access transaction request in the normal cache area; if the normal cache area is full, store the instruction part of the access transaction request in the emergency cache area as an instruction to be sent.

[0129] In this embodiment, the first arbitration module sets up an access transaction instruction cache thread for each master device to handle the caching process of the instruction portion in the access transaction request, such as... Figure 3 As shown, the workflow of this thread is as follows:

[0130] When a new access transaction request arrives, a target priority value, a cache tag for the data portion, and a TAG are assigned to it. If the access transaction request is a normal transaction, its instruction portion is stored in the normal cache; if the normal cache is full, it enters a waiting state as an instruction to be sent. If it is an urgent transaction, its instruction portion is stored in the normal cache; if the normal cache is full, the instruction portion is stored in the Urgent cache as an instruction to be sent; if the urgent cache is also full, it waits for free space in the corresponding cache before storing it.

[0131] In this embodiment, the instruction portion of all access transaction requests is stored in a buffer, and the order of their positions in the buffer corresponds to the order in which they arrived. When the instruction portion is stored in the buffer, if caching of the data portion of the access transaction request is permitted, a data buffer is simultaneously allocated for this instruction, ensuring that there is sufficient data buffer space to store its data portion when caching of the instruction portion is permitted. After completion, the Master is notified that the instruction portion of the access transaction request has been received, i.e., the ready signal of the address channel is pulled high, and then the process returns, awaiting new access transaction requests.

[0132] It should be noted that A and B in the attached diagram only serve to connect different parts of the process, making it easier to clearly present the logical flow of the entire transaction processing process.

[0133] The solution in this embodiment ensures that urgent transactions can still be stored in the emergency cache when the ordinary cache is full, avoiding the loss or delay of important transactions due to insufficient cache space, and greatly improving the system's flexibility and efficiency in dealing with different transactions.

[0134] In another embodiment of this application, the first arbitration module is further configured to: filter the instructions to be sent corresponding to each master device based on the write instruction filtering rules and the read instruction filtering rules to obtain candidate sending instructions; and determine the target sending instruction from the candidate sending instructions based on the urgency value.

[0135] In this embodiment, the first arbitration module configures two access transaction instruction sending threads for each slave device. These threads handle the sending of the instruction portions of write and read access transactions respectively, and the instruction sending processes for write and read access transactions are essentially the same. Figure 4 As shown, the workflow of this thread is as follows:

[0136] First, it is determined whether the slave device has received the instruction portion of the previous access transaction request and whether the send record queue is not full. The send record queue here consists of a write send record queue and a read send record queue pre-configured for each slave device. These queues record the order in which instructions are sent to each slave device, and are updated independently. Each entry in the queue records the instruction identifier (TAG), master device number, and instruction ID. The TAG is used to distinguish instructions; the TAGs of all in-transit access transactions for each master device (including instructions stored in the cache and instructions not stored in the cache on the address channel) are unique, and there are no constraints on the TAGs of instructions from different master devices. The master device number is a unique number pre-defined to distinguish each master device; the instruction ID is the ID signal in the address channel.

[0137] If the above conditions are met—that is, the slave device has received all the instructions for the previous access transaction request and the send record queue is not full—then the master devices will process the instructions to be sent (including instructions in the buffer and instructions not stored in the buffer on the write address channel). If there is an instruction on the address channel, it is the last instruction to arrive, and its urgency is initially set to the target priority value. The access transaction requests to be sent from each master device to the current slave device are denoted as Cm (where m corresponds to the m-th master device), and candidate instructions to be sent are determined using appropriate filtering rules.

[0138] The write instruction filtering rule is as follows: among the preceding write instructions, there are no instructions whose data portion is not cached (to avoid deadlock caused by instruction reordering and caching strategies disrupting the execution order of instructions that need to be cached and those that do not). Among the instruction entries that meet this rule, the instructions whose destination slave device is this slave device are selected as candidate send instructions.

[0139] The read instruction filtering rules are as follows: among the preceding write instructions, there are no instructions whose address range overlaps with this instruction and have not yet been sent; among the preceding read instructions, there are no instructions whose data part needs to be cached and whose ID (i.e., the ID signal in the address channel) is the same as this instruction (to avoid deadlock caused by incorrect execution order of read instructions with the same ID but different data cache states due to instruction reordering and caching strategies). Among the instruction entries that meet these filtering rules, the instructions whose destination slave device is this slave device are selected as candidate send instructions.

[0140] Compare all candidate transmission commands and select the command with the lowest urgency value. If multiple commands exist, select the next Master's command (Cm) in a round-robin fashion. If the current Master does not have a Cm, continue the round-robin process. If none of the Master devices have a Cm, return to the step of filtering candidate transmission commands; otherwise, determine the final target transmission command.

[0141] In addition, for each instruction sent, if the access type of the instruction to be sent is the same as that of the instruction and the destination Slave device is this Slave device, the urgency value of the instruction is reduced by 1 if the urgency value is greater than 1, otherwise it remains unchanged.

[0142] The solution in this embodiment, on the one hand, rigorously filters the instructions to be sent by each master device based on write instruction filtering rules and read instruction filtering rules, ensuring the consistency of data access order and avoiding deadlocks. Simultaneously, it dynamically determines the target instruction to be sent from the candidate instructions based on urgency values, enabling priority processing of high-priority transactions. On the other hand, it allows the access transaction request instruction portion on the address channel to be directly sent to the corresponding slave device address channel while being stored in the cache, only synchronously updating the execution status flag in the cache, reducing the latency caused by intermediate cache operations. The combination of these two approaches ensures both the correctness and stability of system data access and significantly improves the flexibility and response speed of instruction sending, thereby comprehensively optimizing the overall communication efficiency of the AXI module.

[0143] In addition, two transmission record queues are set up for each slave device, recording the master device number, ID, and unique TAG in the cache for each transmitted instruction. This design can quickly locate the instruction corresponding to the data in the cache, improving lookup efficiency and ensuring that the response data accurately matches the original request, thereby improving the overall system performance and response speed.

[0144] In another embodiment of this application, the first arbitration module is further configured to combine the TAG value, master device number and instruction ID of the target sending instruction into a sending record entry and add it to the end of the sending record queue of the current slave device, which is either a read sending record queue or a write sending record queue.

[0145] In another embodiment of this application, the first arbitration module is further configured to: if the cache flag indicates that the data portion of the access transaction request is allowed to be cached, then store the data portion in the cache area as data to be sent; if the cache flag indicates that the data portion of the access transaction request is not allowed to be cached, then temporarily store the data portion in the AXI data channel of the master device as data to be sent.

[0146] In this embodiment, the first arbitration module configures a write access transaction data portion caching thread for each master device to handle the data portion caching and sending logic of write access transaction requests. (See reference...) Figure 5 The specific process is as follows:

[0147] First, the write command entry is switched. During the switch, the entry containing the incomplete data portion of the command is checked in the cache (i.e., the entry in the cache that records the command cache status and related information). If there is no incomplete data portion of the command in the cache, a new access transaction request is searched in the write address channel. If no new access transaction request is found, a new access transaction request is waited for. When new data arrives on the write data channel, the cache flag corresponding to the command is checked: if the cache flag indicates that the data portion of this access transaction request is allowed to be cached, the system waits for the data cache to have space to store the current data, and then stores the current data in the cache as data to be sent, and then waits for the data to be received by the destination Slave device; if the cache flag indicates that the data portion of this access transaction request is not allowed to be cached, the data portion is temporarily stored in the master device's AXI data channel as data to be sent, and then the master device is notified that the data has been received (i.e., the write data channel ready signal goes high). Finally, it is determined whether all the data corresponding to the current command has been received. If not, the system returns to the step of waiting for new data on the write data channel; if it has been received, the system returns to the step of switching the write command entry. Furthermore, since the AXI4 protocol does not support the wid signal, writing data will not result in the interweaving of data from different instructions. The writing order is consistent with the order of the instructions themselves. The data part corresponding to one instruction must be written before the data part of the next instruction is processed.

[0148] In another embodiment of this application, the first arbitration module is further configured to: determine the target data to be sent from the data to be sent in the data buffer based on the sending record entry of the target sending instruction; if there is no corresponding data to be sent in the data buffer, wait and obtain the target data to be sent from the write data channel of the corresponding master device.

[0149] In this embodiment, the first arbitration module configures a write access transaction data sending thread for each slave device to ensure that the sending order of the write access transaction data is consistent with the order of the write instructions sent by the slave device's write address channel. (See reference) Figure 6 The specific process is as follows:

[0150] Retrieve the next write send record entry from the Slave device's write send record queue (i.e., move the instruction record position pointer corresponding to the currently sent data down one position; this entry is the send record entry for the target send instruction). If the entry is valid, directly extract the Master device number and TAG from the entry; if the entry is invalid (e.g., the entry is empty or exceeds the queue range), wait for a new write access transaction instruction to enter the write address channel of the Slave device, and after the instruction enters, extract the corresponding Master device number and TAG as well.

[0151] Subsequently, the cache area corresponding to the master device is located based on the master device number. Then, based on the instruction's TAG value, the instruction entry associated with the currently transmitted data is matched from the master device's cache. Based on the cache markers and other information recorded in the instruction entry, the target transmission data is determined from the data to be transmitted in the data buffer. If there is no corresponding data to be transmitted in the data buffer (including two scenarios: one is that the access transaction data is not allowed to be stored in the data buffer, and the other is that it is allowed to be stored but the data has not yet been written), then the system waits for the corresponding master device's write data channel to transmit the data to be transmitted for the current instruction (if the data transmitted in the channel is not the current instruction data, it will be stored in the corresponding position in the data buffer first), and the target transmission data is retrieved after the data arrives.

[0152] Next, retrieve 1 beat of data and place it into the write data channel of the Slave device. Simultaneously, update the "data transmission progress" information in the corresponding instruction entry in the cache. Then, wait for the Slave device to receive the write data (i.e., wait for the write data channel's ready signal to go high). After the Slave device completes receiving the data, determine whether the current beat data is the last beat of the instruction (based on the wlast signal going high): if not, continue to retrieve the next beat data from the data cache or the corresponding Master device's write data channel and repeat the transmission process; if so, return to the Slave device's write transmission record queue, retrieve the next record, and start a new round of the process.

[0153] In addition, when there is no corresponding data in the data cache, the system will directly extract the data from the Master device's write data channel and transmit it to the Slave device's data channel, reducing communication latency through direct connection between the two. For write access transactions that do not allow cached data, after the data is sent, the instruction entries in its cache will be switched to the "allow cached data" state, which will be used to store the write response information of the transaction later.

[0154] In another possible embodiment of this application, such as Figure 7 As shown, the arbitration receiving module includes a second master device interface, a second slave device interface, a second arbitration module, and a second cache interface module. The second slave device interface connects to the AXI output channel interface of the slave device to receive the access transaction response returned by the slave device. The second cache interface module connects to the cache control module to receive the cache status information sent by the cache control module. The second arbitration module performs arbitration scheduling on the access transaction responses based on the cache status information to select the target access transaction response. The second master device interface connects to the AXI input channel interface of the master device to send the target access transaction response to the corresponding target master device.

[0155] The second slave device interface establishes connections with the AXI output channel interfaces of each slave device to receive access transaction responses from the slave devices. These AXI output channel interfaces include a write response channel and a read data channel, corresponding to the slave device's response information for write transactions and data and response information for read transactions, respectively. After receiving these access transaction responses, the second slave device interface performs preliminary processing of the response information according to a preset data format specification to ensure information integrity, and then transmits it uniformly to the second arbitration module.

[0156] The second cache interface module, acting as a bridge between the receiving arbitration module and the cache control module, receives cache status information from the cache control module in real time. This information includes key data such as the remaining capacity of the cache, the storage location of cached responses, and the validity of cache entries. This status information is then synchronously fed back to the second arbitration module. The second arbitration module uses this status information as the core basis, combined with AXI protocol rules and the original priority of access transactions, to arbitrate and schedule access transaction responses transmitted from the second slave device interface. First, it filters out target access transaction responses that meet the cache status (e.g., the cache has sufficient space to store the response or it needs to be returned first) and match the responses to be received by the master device. Simultaneously, if multiple responses are to be scheduled, the output order of the target responses is determined according to the original sending order and priority of the access transactions to avoid out-of-order responses causing processing errors on the master device.

[0157] Finally, the second master device interface is responsible for establishing connections with the AXI input channel interfaces of each master device. It should be noted that the AXI input channel interfaces of the master devices correspond to the AXI output channel interfaces of the slave devices, and also include write response channels and read data channels for receiving returned access transaction responses. After the second arbitration module determines the target access transaction response, the second master device interface will send the target response to the corresponding target master device according to the master device identifier (such as the master device number) recorded in the response information, completing the entire access transaction response return process.

[0158] In another embodiment of this application, the second arbitration module is further configured to: determine the master device number and instruction unique identifier corresponding to the access transaction response based on the ID signal of the access transaction response; determine whether there is space in the cache area based on the master device number and instruction unique identifier; if so, store the access transaction response in the cache area as data to be received through the cache control module.

[0159] In this embodiment, the second arbitration module configures a partial cache for the access transaction response data of each slave device, used for operations such as cache management of the slave device's access transaction responses. Figure 8 As shown, the execution flow of this thread is as follows:

[0160] If data exists in the response channel, the corresponding record is first determined based on the response channel's ID information and the sending record queue. Specifically, in the sending record queue, the record whose ID value matches the current ID value and was the earliest to enter the queue is selected, and the master device number and instruction unique identifier (i.e., TAG value) are extracted from it. Subsequently, the instruction entry whose TAG value matches the TAG value in the corresponding master device's cache is retrieved. This instruction entry is the unit in the cache that records the core information of the access transaction, including key content such as transaction type, data reception progress, and cache space requirements. Based on the cache space requirements recorded in the entry and the current remaining capacity of the cache, it can be determined whether the cache has sufficient storage space.

[0161] If the buffer has sufficient space, the access transaction response is stored in the buffer, making it data to be received. This ensures that caching is only performed when storage conditions are met, avoiding resource waste. If the buffer does not have sufficient space, the data is not cached temporarily. When the master device receives the instruction response data, the data is directly placed into the master device's response data channel, reducing waiting latency. After data processing is complete, the slave device is notified that the data has been received (i.e., the data channel's ready signal is pulled high). At the same time, it is determined whether the current instruction entry has completed all data reception: if it has, the current record is deleted from the sending record queue, ensuring the orderly connection of the entire response data processing flow.

[0162] In another embodiment of this application, the second arbitration module is further configured to: in response to receiving data of the access transaction response, obtain the target instruction in the cache, wherein the target instruction is the earliest instruction stored in the cache; if the target instruction and the access transaction response data have the same access type and the same master device ID, obtain the target received data from the data to be received in the cache based on the target instruction.

[0163] In this embodiment, the second arbitration module configures a thread for sending the access transaction response data portion for each slave device, used to process the access transaction response data of the slave devices in an orderly manner and return it to the master device. For example... Figure 9 As shown, the execution flow of this thread is as follows:

[0164] When data responding to an access transaction is received, the system first searches the cache for the earliest stored instruction among the instruction entries that have received response data, identifying it as the target instruction. Next, it checks the cache for other instruction entries of the same type and master device ID as the current data access. If such an instruction entry exists (meaning a previous access transaction with the same master device ID has not yet completed), the system returns to search for the target instruction again; otherwise, it retrieves the earliest arriving 1-beat data from the pending data in the cache based on the target instruction, uses it as the target received data, and deletes that data from the cache.

[0165] If the target instruction is not found in the cache, check the response channels of all slave devices to determine if there is response data sent to the corresponding master device. If so, use this data as the target to receive data; otherwise, return and continue waiting.

[0166] After acquiring the target data, it is placed into the corresponding response channel of the master device, and the information about the response data return progress in the corresponding instruction item in the cache is updated. Then, after waiting for the master device's response channel to finish receiving the current data, the progress information recorded in the cache is used to determine whether all the response data required for this access transaction has been sent.

[0167] If all data has been sent, the instruction entry and its corresponding data entry are deleted from the cache, marking the completion of the access transaction; if not, the process restarts. This mechanism ensures that access transactions with the same ID on the same master device return response data in the order they were sent, and also allows data to be retrieved and transmitted directly from the slave device's response channel when there is no data in the cache, reducing latency caused by intermediate steps.

[0168] A second aspect of this application provides an AXI interconnection method, which is applied to the aforementioned AXI interconnection module, such as... Figure 10 As shown, the method includes:

[0169] The sending arbitration module receives access transaction requests initiated by each master device, arbitrates the access transaction requests, determines the access transaction requests that need to be cached and sends them to the caching control module, and determines the target access transaction request and sends it to the corresponding destination slave device.

[0170] The receiving arbitration module receives access transaction responses returned by each slave device, arbitrates the access transaction responses, determines the access transaction responses that need to be cached and sends them to the caching control module, and determines the target access transaction response and sends it to the corresponding source master device.

[0171] The cache control module stores the access transaction requests and responses that need to be cached into the cache area; and in response to the requests from the sending arbitration module and the receiving arbitration module, retrieves the target access transaction requests and target access transaction responses from the cache area.

[0172] In another embodiment of this application, the arbitration sending module includes a first master device interface, a device mapping resolution module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface. Correspondingly, the method further includes:

[0173] It connects to the AXI output channel interface of each master device through the first master device interface and receives access transaction requests initiated by each master device.

[0174] The device mapping and resolution module determines the destination device corresponding to the access transaction request;

[0175] The priority allocation module determines the target priority value for access transaction requests.

[0176] The cache status information is obtained through the cache control module via the first cache interface module.

[0177] The first arbitration module arbitrates and schedules access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the buffer, and selects the target access transaction requests.

[0178] The first slave device interface is used to connect to the AXI input channel interface of each slave device, and the target access transaction request is sent to the corresponding destination slave device.

[0179] In another possible embodiment of this application, determining the target priority value of the access transaction request includes:

[0180] Determine the initial priority value for the access transaction request;

[0181] The response is when the master and slave devices corresponding to the access transaction request are the same as those of the previous access transaction request, and the access address ranges overlap;

[0182] If the initial priority value is greater than the current urgency of the preceding access transaction request, then the initial priority value of the access transaction request is determined to be the target priority value.

[0183] If the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then the current urgency of the preceding access transaction request is determined as the target priority value of the access transaction request.

[0184] In another possible embodiment of this application, determining the initial priority value of the access transaction request includes:

[0185] The initial priority value is determined based on the emergency transaction flag, channel priority value, and QoS signal value corresponding to the access transaction request.

[0186] According to embodiments of this application, this application also provides an electronic device and a readable storage medium.

[0187] Figure 11A schematic block diagram of an example electronic device that can be used to implement embodiments of this application is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the application described and / or claimed herein.

[0188] like Figure 11 As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 802 or a computer program loaded from storage unit 808 into random access memory (RAM) 803. RAM 803 may also store various programs and data required for the operation of device 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interface 805 is also connected to bus 804.

[0189] Multiple components in device 800 are connected to I / O interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0190] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as an AXI interconnect method. For example, in some embodiments, an AXI interconnect method can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on device 800 via ROM 802 and / or communication unit 809. When the computer program is loaded into RAM 803 and executed by the computing unit 801, one or more steps of an AXI interconnect method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform an AXI interconnect method by any other suitable means (e.g., by means of firmware).

[0191] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0192] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0193] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0194] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0195] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0196] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0197] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0198] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0199] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An AXI interconnect module, characterized in that, The AXI interconnect module includes: a sending arbitration module, a buffer control module, a buffer area, and a receiving arbitration module, wherein... The sending arbitration module is used to receive access transaction requests initiated by each master device, arbitrate the access transaction requests, determine the access transaction requests that need to be cached and send them to the cache control module, and determine the target access transaction request and send it to the corresponding destination slave device. The receiving arbitration module is used to receive access transaction responses returned by each slave device, arbitrate the access transaction responses, determine the access transaction responses that need to be cached and send them to the caching control module, and determine the target access transaction response and send it to the corresponding source master device. The cache control module is connected to the sending arbitration module, the receiving arbitration module, and the cache area respectively, and is used to store the access transaction request and the access transaction response that need to be cached in the cache area; and to retrieve the target access transaction request and the target access transaction response from the cache area in response to the requests of the sending arbitration module and the receiving arbitration module. The arbitration module includes a first master device interface, a device mapping and parsing module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface. The first master device interface connects to the AXI output channel interface of each master device to receive access transaction requests initiated by each master device. The device mapping and parsing module determines the destination slave device corresponding to the access transaction request. The priority allocation module determines the target priority value of the access transaction request. The first cache interface module obtains the status information of the cache area through the cache control module. The first arbitration module performs arbitration scheduling on the access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the cache area, filtering out the target access transaction request. The first slave device interface connects to the AXI input channel interface of each slave device to send the target access transaction request to the corresponding destination slave device. The priority allocation module is further configured to: determine the initial priority value of the access transaction request; in response to the access transaction request and the preceding access transaction request having the same master and slave devices and overlapping access address ranges; if the initial priority value is greater than the current urgency of the preceding access transaction request, then determine the initial priority value of the access transaction request as the target priority value; if the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then determine the current urgency of the preceding access transaction request as the target priority value of the access transaction request.

2. The AXI interconnect module according to claim 1, characterized in that, The priority allocation module is further configured to: The initial priority value is determined based on the emergency transaction flag, channel priority value, and quality of service signal value corresponding to the access transaction request.

3. The AXI interconnect module according to claim 2, characterized in that, The cache control module is also used for: Based on the data portion capacity of the access transaction request and a preset cacheable capacity threshold, a cache flag for the access transaction request is determined. The cache flag indicates whether the data portion of the access transaction request is allowed to enter the cache area.

4. The AXI interconnect module according to claim 3, characterized in that, The cache area includes a normal cache area and an emergency cache area, and the first arbitration module is further used for: If the access transaction request is a normal transaction, the instruction part of the access transaction request is stored in the normal buffer. If the normal buffer is full, it enters a waiting state as an instruction to be sent. If the access transaction request is an urgent transaction, the instruction portion of the access transaction request is stored in the normal buffer. If the normal buffer is full, the instruction portion of the access transaction request is stored in the emergency buffer as an instruction to be sent.

5. The AXI interconnect module according to claim 4, characterized in that, The first arbitration module is also used for: Based on write instruction filtering rules and read instruction filtering rules, the instructions to be sent corresponding to each master device are filtered to obtain candidate sending instructions; Based on the urgency value, the target sending command is determined from the candidate sending commands.

6. The AXI interconnect module according to claim 5, characterized in that, The first arbitration module is also used for: Based on the unique identifier of the target transmission command, the master device number, and the command ID, a transmission record entry is generated; The transmission record entry is recorded in the transmission record queue of the destination slave device corresponding to the target transmission command.

7. The AXI interconnect module according to claim 6, characterized in that, The first arbitration module is also used for: If the cache flag indicates that the data portion of the access transaction request is allowed to be cached, then the data portion is stored in the cache area as data to be sent. If the cache flag indicates that the data portion of the access transaction request is not allowed to be cached, then the data portion is temporarily stored in the AXI data channel of the master device as data to be sent.

8. The AXI interconnect module according to claim 7, characterized in that, The first arbitration module is also used for: Based on the transmission record entry of the target transmission instruction, the target transmission data is determined from the data to be transmitted in the buffer. If there is no corresponding data to be sent in the buffer, then wait and obtain the target data to be sent from the write data channel of the corresponding master device.

9. The AXI interconnect module according to claim 1, characterized in that, The receiving arbitration module includes a second master device interface, a second slave device interface, a second arbitration module, and a second cache interface module, wherein; The second slave device interface is used to receive the access transaction response returned by the slave device; The second cache interface module receives the cache status information sent by the cache control module; The second arbitration module is used to arbitrate and schedule access transaction responses based on the state information of the cache, and to filter out the target access transaction responses. The second master device interface is used to send the target access transaction response to the corresponding source master device.

10. The AXI interconnect module according to claim 9, characterized in that, The second arbitration module is also used for: Based on the ID signal of the access transaction response, determine the master device number and instruction unique identifier corresponding to the access transaction response; Based on the master device number and the instruction unique identifier, determine whether there is space in the cache area. If so, store the access transaction response in the cache area as data to be received through the cache control module.

11. The AXI interconnect module according to claim 10, characterized in that, The second arbitration module is also used for: In response to receiving data from an access transaction response, the target instruction in the cache is retrieved, wherein the target instruction is the earliest instruction stored in the cache. If the target instruction and the data in the access transaction response have the same access type and the same master device ID, the target received data is obtained from the data to be received in the buffer based on the target instruction.

12. An AXI interconnection method, characterized in that, The method is applied to an AXI interconnect module, the AXI interconnect module including: a transmitting arbitration module, a buffer control module, a buffer area, and a receiving arbitration module, the method including: The sending arbitration module receives access transaction requests initiated by each master device, arbitrates the access transaction requests, determines the access transaction requests that need to be cached and sends them to the caching control module, and determines the target access transaction request and sends it to the corresponding destination slave device. The receiving arbitration module receives access transaction responses returned by each slave device, arbitrates the access transaction responses, determines the access transaction responses that need to be cached and sends them to the caching control module, and determines the target access transaction response and sends it to the corresponding source master device. The cache control module stores the access transaction requests and responses that need to be cached into the cache area; and in response to the requests from the sending arbitration module and the receiving arbitration module, retrieves the target access transaction request and the target access transaction response from the cache area. The arbitration module includes a first master device interface, a device mapping resolution module, a priority allocation module, a first arbitration module, a first cache interface module, and a first slave device interface. Correspondingly, the method further includes: connecting the first master device interface to the AXI output channel interface of each master device to receive access transaction requests initiated by each master device; determining the destination slave device corresponding to the access transaction request through the device mapping resolution module; determining the target priority value of the access transaction request through the priority allocation module; obtaining the status information of the cache area through the first cache interface module and the cache control module; arbitrating and scheduling the access transaction requests based on the status information of the destination slave device, the target priority value, and the status information of the cache area through the first arbitration module to filter out target access transaction requests; and sending the target access transaction request to the corresponding destination slave device through the first slave device interface, which is used to connect to the AXI input channel interface of each slave device. The determination of the target priority value of the access transaction request includes: determining the initial priority value of the access transaction request; responding to the fact that the master device and slave device corresponding to the access transaction request are the same as those of the preceding access transaction request, and that the access address ranges overlap; if the initial priority value is greater than the current urgency of the preceding access transaction request, then the initial priority value of the access transaction request is determined to be the target priority value; if the initial priority value is less than or equal to the current urgency of the preceding access transaction request, then the current urgency of the preceding access transaction request is determined to be the target priority value of the access transaction request.

13. The method according to claim 12, characterized in that, The determination of the initial priority value for the access transaction request includes: The initial priority value is determined based on the emergency transaction flag, channel priority value, and quality of service signal value corresponding to the access transaction request.

14. An electronic device, characterized in that, include: At least one processor; as well as, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 12-13.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 12-13.

16. A computer program product comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by a processor, they implement the method of any one of claims 12-13.

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