Manufacturing method of three-dimensional system chip
By employing wafer-level reconstruction and bonding technology in 3D system-on-a-chip manufacturing, the problem of pad oxidation was solved, and efficient electrical interconnection of multi-layer chips was achieved, improving the reliability and integration density of the system-on-a-chip.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-10
- Publication Date
- 2026-03-10
AI Technical Summary
In existing 3D integrated circuit manufacturing processes, bonding pads are prone to oxidation during storage, leading to a decline in bonding quality and affecting the reliability of connections between devices.
By employing wafer-level reconstruction and bonding technology, interconnects and I/O interconnect electrodes are formed on the wafer, and interconnects are formed by metal growth, achieving precise bonding and electrical interconnection of multilayer chips.
It improves the structural flexibility and yield of system chips, simplifies the manufacturing process, and enhances the speed of electrical signal transmission and parallel processing capabilities between devices.
Smart Images
Figure CN121646387A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of wafer manufacturing technology, and more particularly to a method for manufacturing a three-dimensional system-on-a-chip. Background Technology
[0002] With the comprehensive development of semiconductor technology, the research focus of various companies, institutions and universities has gradually shifted to how to increase the number of components per unit area and improve microscopic precision. Traditional 2D planar integration technology has reached its density limit. In order to improve chip performance and integrate more transistors, three-dimensional stacking technology has emerged.
[0003] Three-dimensional integrated circuits are an extension of traditional two-dimensional integrated circuits from planar integration to vertical three-dimensional integration.
[0004] The advantages of three-dimensional integrated circuits are: the multi-layer device overlapping structure can increase the chip integration density many times over; the through-silicon via structure greatly improves the transmission speed of electrical signals; the multi-layer stacked structure makes it possible to process parallel signals; and the variety of integrated circuit design processes can diversify circuit functions.
[0005] The current mainstream 3D stacking manufacturing process adopts wafer-level bonding. First, the target device wafer is thinned, and temporary bonding is used to attach the device wafer to the carrier with intermediate material. After completing back-side thinning, back-side wiring, and pad fabrication, debonding process is used to separate the device wafer from the carrier. The thinned device wafer is then permanently bonded multiple times to complete the 3D stacking.
[0006] However, in the above method, there is usually a time interval between the preparation of clean microbump surfaces and bonding in the pad fabrication process. During this storage time, the surface of the pads is easily oxidized, which leads to a decrease in bonding quality. Summary of the Invention
[0007] To address the above technical problems, this invention provides a method for manufacturing a three-dimensional system-on-a-chip, comprising: Step S10: Provide a first wafer, the first wafer including a first die; Step S20: Provide a second core. Step S30: Fabricate interconnection adapters, which interconnect electrodes within the same first core and / or electrodes between different first cores to form I / O interconnect electrodes; Step S40: Bond the first wafer and the second die, wherein the I / O interconnect electrodes of the first wafer and the second die are opposite to each other; Step S50: Growing metal onto the I / O interconnect electrodes of the first wafer and the second wafer until an interconnect is formed.
[0008] The manufacturing method of the three-dimensional system chip of the present invention realizes the three-dimensional physical integration of multiple heterogeneous and heterogeneous dies through chip-level and wafer-level process steps such as wafer reconstruction of multiple dies, wafer bonding, and wafer-level metal interconnection, so as to complete the electrical interconnection between all dies required by the system chip. It has the advantages of high system chip structure flexibility, simple manufacturing process, high yield and good reliability. Attached Figure Description
[0009] Figure 1 This is a flowchart of the manufacturing method of the three-dimensional system chip of the present invention; Figures 2-7 This is a schematic diagram of the manufacturing method of the three-dimensional system chip of the present invention. Detailed Implementation
[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, so that the advantages and features of the present invention can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the scope of protection of the present invention. Obviously, the embodiments described in this invention are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0011] The method for manufacturing a three-dimensional system chip according to the present invention includes: Step S10: Provide a first wafer, the first wafer including a first die; Step S20: Provide a second core. Step S30: Fabricate interconnection adapters, which interconnect electrodes within the same first core and / or electrodes between different first cores to form I / O interconnect electrodes; Step S40: Bond the first wafer and the second die, wherein the I / O interconnect electrodes of the first wafer and the second die are opposite to each other; Step S50: Growing metal onto the I / O interconnect electrodes of the first wafer and the second wafer until an interconnect is formed.
[0012] In one embodiment, step S30 further includes: forming a bonding layer on the first wafer and the second die, wherein the bonding layer exposes a portion of an electrode or interconnect wire as an I / O interconnect electrode.
[0013] In the first embodiment, step S25 involves providing a second carrier and a second core, and then array-bonding the second core onto the second carrier to form a second wafer. Step S35: Fabricate interconnection adapters to interconnect electrodes within the same second core and / or electrodes between different second cores; Step S45: Form a plurality of trenches penetrating the first wafer or the second wafer, such that the I / O interconnect electrode of each of the first wafer and the second wafer is connected to at least one of the trenches.
[0014] In one embodiment, the first wafer formation step includes: Step S11: Provide a first carrier and a first core, and bond the first core in an array on the first carrier to form a first wafer; Step S12: Fabricate interconnection adapters to interconnect electrodes within the same first chip and / or electrodes between different first chips.
[0015] In one embodiment, after bonding the first core to the first substrate, the method further includes forming a dielectric layer surrounding the first core; The first substrate is thinned from the back.
[0016] In one embodiment, the step is to form a vertical through-body interconnect extending from the interconnect electrodes of the I / O of the first wafer and the second wafer to the surface of the first wafer or the second wafer until the trench is filled.
[0017] In one embodiment, the method further includes the step of forming through-silicon vias (TSVs) that interconnect from I / O interconnect electrodes to the surface of a first wafer or a second wafer. After the I / O interconnect electrodes of the first wafer and the second wafer are interconnected, the trench is filled with a dielectric.
[0018] In one embodiment, the electrode of the chip is a through-silicon via (TSV) electrode; the steps of fabricating interconnect adapters and forming I / O interconnect electrodes include: Deposit a metal layer covering the through-silicon vias onto the wafer surface; The metal layer is etched so that the required interconnect vias are interconnected through the metal layer. A dielectric layer is grown, and openings are formed in the dielectric layer in the areas where interconnection is required to serve as I / O interconnect electrodes.
[0019] In another embodiment, the electrodes of the chip are in the form of through-silicon vias; the steps of fabricating interconnect adapters and forming I / O interconnect electrodes include: A dielectric layer is grown on the wafer surface, and metal wire trenches are etched to form interconnecting vias within the same metal wire trench.
[0020] A metal layer is formed within the metal wire trench, a dielectric layer is grown, and openings are formed in the dielectric layer in the areas where interconnection is required, serving as I / O interconnect electrodes.
[0021] In one embodiment, the step of forming a plurality of trenches penetrating the first wafer or the second wafer includes: Thinning the first wafer from the back or thinning the second wafer from the back.
[0022] In one embodiment, bonding the second core to the second substrate includes the steps of: A dielectric layer is formed around the second core particle, and the dielectric layer covers the periphery of the second core particle.
[0023] In one embodiment, the vertical through-body interconnect is formed by injecting liquid or gaseous material to grow metal onto the I / O interconnect electrodes.
[0024] In one embodiment, the back-side thinning is achieved by heating, or by separating the second carrier and the second core.
[0025] In one embodiment, bonding the first wafer and the second die is performed by bonding the first wafer and the second die, and the bonding method includes electromagnetic bonding.
[0026] In one embodiment, the I / O interconnect electrode is hemispherical or planar.
[0027] In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a method for manufacturing a three-dimensional system-on-a-chip is provided, with reference to... Figure 1 As shown, Figure 1 The flowchart of this invention is shown below. Figures 2-7 , Figures 2-7 This is a schematic diagram of the manufacturing process according to an embodiment of this application.
[0028] Step S10: Provide a first wafer, which includes a first die 120.
[0029] In this embodiment, step S11 is included, providing a first carrier 110 and a first die 120, and array-bonding the first die 120 onto the first carrier 110 to form a first wafer. The first carrier 110 can be a wafer of a single-crystal semiconductor material, including silicon, germanium, GaAs, etc. The first die 120 is an unpackaged top die, that is, a single bare chip cut after manufacturing. In this embodiment, the first die 120 can be a bare chip with different functional devices.
[0030] Multiple first chips 120 with different functions and sizes can be bonded onto the first substrate 110. In this embodiment, the electrode 122 can be as follows: Figure 2The electrode pads shown can also be through-silicon vias (TSVs). In this embodiment, TSVs are preferred, as this eliminates the need for electrode pad fabrication during wafer manufacturing, while retaining the TSVs. This integrates the electrode pad fabrication process into the interconnect fabrication process of the present invention. Specifically, a bonding layer can be formed on the first carrier 110. The bonding layer material can be a dielectric material, such as SiO2 or dry film. A bonding layer can also be formed on the back side of the first die 120, and the bonding layer material can be a dielectric material, such as SiO2 or dry film. Multiple first dies 120 are arranged in an array on the first carrier 110 according to their connection relationships and correspondence with second dies on the second wafer. Through optical alignment and bonding between the bonding layers on the first die 120 and the bonding layers on the first carrier, precise bonding is achieved between the first die and the first carrier. Figure 3 As shown, multiple first chips 120 are neatly and regularly attached to the bonding layer, with the front I / O interconnect electrodes 122 exposed. After the first chips 120 are bonded to the first carrier 110, a dielectric layer 130 is formed surrounding the first chips 120.
[0031] like Figure 4 As shown, after bonding, the process continues with thinning the first substrate 110 from the back side. In other embodiments, the first substrate 110 can also be removed by releasing the bonding layer to form a reconstructed first wafer. For example, heating can be used to reduce the adhesion between the bonding layer's dielectric dry film and the first substrate 110, thereby causing the first substrate to detach and be completely removed. Alternatively, chemical mechanical polishing can be used to thin the first substrate, removing all or part of its thickness.
[0032] In other embodiments, a pre-manufactured first wafer, including the bare die, may be provided directly without reconfiguration.
[0033] In other embodiments, the bonding and filling dielectric layer 130 steps can also involve injection molding and curing a liquid dielectric around each first core 120. In this embodiment, the injection molding material is the same as the bonding layer material. Specifically, the aforementioned structure is placed in a mold, and then liquid photoresist material is injected. The injected liquid material surrounds the first core 120 and is then cured to form a reconstructed first wafer. In this way, the first core 120 is surrounded by the cured dielectric layer, thus forming a reconstructed first wafer, which facilitates the operation of the arm and protects the safety of the first core during processing. This step is mainly to integrate first cores with different functions onto one wafer, facilitating subsequent integration with the second wafer. If the cores have the same function and are formed using the same process, they only need to be manufactured on the first wafer, and reconstruction is not required.
[0034] Step S20: Provide a second core.
[0035] In this embodiment, specifically, step 25 is included, providing a second carrier and a second core, and array-bonding the second core 311 onto the second carrier to form a second wafer 310.
[0036] Specifically, the reconstruction process of the second core and the second carrier wafer can be referred to step S10. The reconstruction process of the first wafer will not be repeated here. The difference is that in other embodiments, the second core can also be a bare core directly manufactured and cut, and the wafer reconstruction is not required.
[0037] Step S30: Fabricate interconnecting adapters to interconnect electrodes within the same first core and / or electrodes between different first cores.
[0038] For details, please refer to [link / reference]. Figure 4 A metal layer can be formed on the first wafer, and then the metal layer that retains the connecting electrodes can be etched to form interconnects and I / O interconnects.
[0039] Specifically, in one embodiment, the electrode of the chip is a through-silicon via (TSV) electrode; the steps of fabricating interconnect adapters and forming I / O interconnect electrodes include: Deposit a metal layer covering the through-silicon vias onto the wafer surface; The metal layer is etched so that the required interconnect vias are interconnected through the metal layer. A dielectric layer is grown, and openings are formed in the dielectric layer in the areas where interconnection is required to serve as I / O interconnect electrodes.
[0040] In another embodiment, the electrodes of the chip are in the form of through-silicon vias; the steps of fabricating interconnect adapters and forming I / O interconnect electrodes include: A dielectric layer is grown on the wafer surface, and metal wire trenches are etched to form interconnecting vias within the same metal wire trench.
[0041] A metal layer is formed within the metal wire trench, a dielectric layer is grown, and openings are formed in the dielectric layer in the areas where interconnection is required, serving as I / O interconnect electrodes.
[0042] In the two embodiments described above, the steps of growing a dielectric layer on a metal layer and etching the dielectric layer to form an opening in the area where interconnection is required can also be omitted. Instead, the subsequent steps of forming a bonding layer and etching the opening can be used to form an exposed area as an I / O interconnect electrode.
[0043] In this embodiment, since a reconstructed second wafer is used, step S35 is included, which involves fabricating interconnect wires to interconnect electrodes within the same second die and / or electrodes between different second dies. The implementation method of step S35 is the same as that of step S30 and will not be repeated here.
[0044] A bonding layer is formed on the first wafer and the second die, and the bonding layer exposes a portion of the electrode or interconnect adapter line as an I / O interconnect electrode.
[0045] Specifically, it is possible, such as Figure 5 As shown, bonding layers are first formed on the front sides of the first wafer and the second wafer. The bonding layer material can be a dielectric material, such as SiO2 or dry film. Multiple first cores on the first wafer are arranged in an array according to their connection relationships and their correspondence with second cores on the second wafer. During bonding, the bonding layer can be formed only in the dielectric layer region between the cores, thus ensuring better connectivity between the cores.
[0046] Alternatively, a SiO2 bonding layer can be formed on the first wafer first, and then a portion of the bonding layer can be etched away to expose the I / O interconnect electrodes 122 on the front side of the first wafer. Alternatively, the bonding layer can be etched away to expose only the areas requiring interconnection, serving as the I / O interconnect electrodes. The same method can be used to form the bonding layer on the second wafer.
[0047] In another embodiment, a bonding layer may not be formed, and the I / O interconnect electrode is hemispherical.
[0048] In another embodiment, the I / O interconnect electrodes of the first wafer are hemispherical, and the I / O interconnect electrodes of the second die are planar.
[0049] In another embodiment, the I / O interconnect electrodes of the first wafer are planar, and the I / O interconnect electrodes of the second die are hemispherical.
[0050] Step S40: The first wafer and the second die are bonded using a bonding layer, wherein the I / O interconnect electrodes of the first wafer and the second die are opposite to each other.
[0051] Specifically, such as Figure 5 As shown, the first wafer and the second wafer 310 are precisely bonded by bonding the bonding layers on the first wafer after optical alignment.
[0052] In this embodiment, both the first wafer and the second wafer are wafers reconstructed using dielectric materials. For example... Figure 6 As shown, it also includes step S45, forming a plurality of trenches penetrating the first wafer or the second wafer, such that the I / O interconnect electrode of each of the first wafer and the second wafer is connected to at least one of the trenches.
[0053] Specifically, before forming trench 410, the process includes: back thinning of the second wafer structure using chemical mechanical polishing (CMP) from the back side, i.e., the side without exposed I / O interconnect electrodes. Then, etching is performed from the back side of the second wafer structure, i.e., the side without exposed I / O interconnect electrodes. A patterned layer can be formed first using photolithography, and then the trench penetrating the second wafer structure can be etched. Alternatively, the trench can also be formed on the back side of the first wafer.
[0054] In step S50, metal is deposited onto the I / O interconnect electrodes of the first wafer and the second wafer until an interconnect is formed. In this embodiment, step S50 continues until the trench is filled, forming a vertical through-hole interconnect 500 extending from the I / O interconnect electrodes of the first wafer and the second wafer to the surface of the first wafer or the second wafer.
[0055] Specifically, such as Figure 7 As shown, metal ions are transferred to the I / O interconnect electrodes of the first and second cores using a selective deposition method. The conductive material is deposited using any one or a combination of chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar methods. For example, in this embodiment, a chemical vapor deposition method is used. A strong magnet is used to firmly fix the first wafer structure and the conductive copper substrate together, and then an adhesive medium is used to temporarily bond them together. Next, CO2 is pumped into the electroplating chamber, and the pressure is increased until it reaches a level sufficient to enter a supercritical state (1070 psi). Magnetic stirring and mixing are then initiated for 30 minutes to obtain a more stable supercritical emulsion. After the metal in the slitting tank fills the surface of the first wafer structure, the pressure in the electroplating chamber is released and brought back to atmospheric pressure. Then, the conductive copper substrate is separated, ultimately forming a self-aligned micro-interconnect solder joint, i.e., forming a vertical through-body interconnect while filling microvoids with metal.
[0056] In another embodiment, because the I / O interconnect electrodes are hemispherical, it is more advantageous for the liquid plating material to flow in the gaps of the I / O interconnect electrodes, forming a more uniform interconnect, and the planarization requirements for the I / O interconnect electrodes are also lower.
[0057] In another embodiment, the growth of the metal layer can be stopped after the I / O interconnect electrodes of the first and second wafers are interconnected. Then, the back side of the second wafer structure is injection molded to seal all trenches and voids, making its back side substantially planar. Next, the back side of the second wafer or the second wafer structure is thinned again to expose the TSV.
[0058] Subsequently, back-side rewiring conductors 510, solder pads and / or solder balls (tin) 520 are formed to connect to these TSVs or vertical through-body interconnects as I / O inlets for the entire system chip.
[0059] Each I / O interconnect is made of Al, Cu, Ti, and their alloys, with a thickness of 0.1–15 μm (typical) and a horizontal dimension of 0.5–100 μm. The vertical through-hole interconnect is made of Cu, Ta, W, and multiple alloys, with a typical diameter of 1–20 μm and a length of 5–200 μm.
[0060] Vertical through-body interconnects are made of metal alloys such as Ni, Cu, Cr, and Ag. Dimensions (horizontal) range from 1 to 100 μm, and thicknesses range from 1 to 50 μm.
[0061] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.
Claims
1. A method of manufacturing a three-dimensional system on chip, characterized by, Comprising: Step S10, providing a first wafer, the first wafer comprising first dies therein; Step S20, providing second dies; Step S30, fabricating interconnects connecting electrodes within the same first die and / or electrodes between different first dies and forming I / O interconnects; Step S40, bonding the first wafer and the second dies with the I / O interconnects of the first wafer and the second dies facing each other; Step S50, growing metal to the I / O interconnects of the first wafer and the second wafer until forming interconnects.
2. The method of manufacturing a three-dimensional system on chip according to claim 1, wherein, Step S30 further comprises forming a bonding layer on the first wafer and the second dies, the bonding layer exposing portions of the electrodes or the interconnects as the I / O interconnects.
3. The manufacturing method of a three-dimensional system on chip according to claim 2, wherein, Further comprising: Step S25, providing a second wafer and second dies, the second dies being array bonded on the second wafer to form a second wafer; Step S35, fabricating interconnects connecting electrodes within the same second die and / or electrodes between different second dies; Step S45, forming a plurality of trenches through the first wafer or the second wafer such that each of the I / O interconnects of the first wafer and the second wafer is in communication with at least one of the trenches.
4. The method of claim 3, wherein: The first wafer forming step comprises: Step S11, providing a first wafer and first dies, the first dies being array bonded on the first wafer to form a first wafer; Step S12, fabricating interconnects connecting electrodes within the same first die and / or electrodes between different first dies.
5. The method of claim 4, wherein: After the first dies are bonded to the first wafer, further comprising forming a dielectric layer surrounding the first dies; The first wafer is thinned from the back side.
6. The method of claim 5, wherein: Further comprising the step of forming vertical through interconnects extending from the I / O interconnects of the first wafer and the second wafer all the way to the surface of the first wafer or the second wafer until the trenches are filled.
7. The method of claim 5, wherein: Further comprising the step of forming through silicon vias interconnecting from the I / O interconnects to the surface of the first wafer or the second wafer; After the I / O interconnects of the first wafer and the second wafer are formed, the trenches are filled with a dielectric material.
8. The method of manufacturing a three-dimensional system on chip according to claim 1, wherein, The electrodes of the dies are in the form of through silicon vias; the step of fabricating interconnects connecting the electrodes within the same die and / or electrodes between different dies and forming I / O interconnects comprises: Depositing a metal layer on the surface of the wafer covering the through silicon vias; Etching the metal layer to leave the through silicon vias to be interconnected through the metal layer; Growing a dielectric layer and etching the dielectric layer to form openings as the I / O interconnects in the areas where interconnection is needed.
9. The method of manufacturing a three-dimensional system on chip according to claim 1, wherein, The electrodes of the dies are in the form of through silicon vias; the step of fabricating interconnects connecting the electrodes within the same die and / or electrodes between different dies and forming I / O interconnects comprises: Growing a dielectric layer on the surface of the wafer and etching to form metal line trenches such that the through silicon vias to be interconnected are within the same metal line trench. A metal layer is formed in the metal line trench, a dielectric layer is grown, and the dielectric layer is etched to form an opening as an I / O interconnection electrode at the area where interconnection is needed.
10. The method of manufacturing a 3D system on chip according to claim 9, wherein, The step of forming a plurality of trenches through the first wafer or the second wafer comprises: The first wafer is thinned from the back side or the second wafer is thinned from the back side.
11. The method of claim 10, wherein the first wafer and the second die are bonded by electromagnetic bonding. The step of bonding the second die to the second carrier comprises the steps of: A dielectric layer is formed around the second die, and the dielectric layer covers the periphery of the second die.
12. The method of claim 11, wherein the step of forming the vertical through-body interconnects comprises growing a metal on the I / O interconnection electrode using an injected liquid or gaseous material. The back side thinning is performed by heating, or the second carrier and the second die are separated.
13. The method of manufacturing a 3D system on chip according to claim 12, wherein, The first wafer and the second die are bonded by electromagnetic bonding.
14. The method of manufacturing a three-dimensional system on a chip according to claim 1, wherein, The I / O interconnection electrode is hemispherical or planar.
15. The method of manufacturing a 3D system on chip according to claim 14, wherein,