Integrated circuit chip structure and fabrication method

Abstract

This invention discloses an integrated integrated circuit chip structure and its fabrication method. The invention relates to the field of thermal design and thermal control technology for integrated circuit chips, addressing the problem of weak heat transfer capabilities at high heat flux density points in existing integrated circuit chips. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during integrated circuit chip fabrication, rather than being fabricated separately after chip fabrication. This enables the fabrication of heat dissipation structures for multiple integrated circuit chips, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate, reducing thermal resistance during heat loss and improving heat dissipation capacity.

Description

Technical Field

[0001] This invention relates to the field of thermal design and thermal control technology for integrated circuit chips, and particularly to the structure and fabrication method of integrated integrated circuit chips. Background Technology

[0002] Currently, semiconductor devices are continuously evolving towards higher functionality, smaller size, and higher integration. Chip feature sizes are shrinking, operating frequencies are increasing, computing speeds are significantly accelerating, and power density is constantly rising. This increase in power density creates high heat flux density points within the chip. If the heat at these high heat flux density points cannot be transported away in time, the accumulated heat will cause the chip temperature to rise sharply, limiting the device's operating temperature limit, restricting its electrical performance, and potentially accelerating device degradation or even leading to device failure, thus hindering the application of devices and systems. Therefore, heat transfer at high heat flux density points in integrated circuit chips is a current research hotspot.

[0003] Therefore, there is a need to provide an integrated circuit chip structure and fabrication method that can be directly cooled. Summary of the Invention

[0004] The purpose of this invention is to provide an integrated integrated circuit chip structure and a fabrication method to solve the problem of weak heat transfer capability at high heat flux density points in existing integrated circuit chips.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] In a first aspect, the present invention provides an integrated integrated circuit chip structure, comprising:

[0007] A semiconductor substrate, wherein an integrated circuit device region and a microchannel structure are disposed on the semiconductor substrate;

[0008] A cover plate having a liquid separation structure and liquid inlet and outlet ports;

[0009] The packaging structure of an integrated circuit chip includes a protective shell; the protective shell is used to protect the integrated integrated circuit chip; the integrated integrated circuit chip is formed by bonding a semiconductor substrate wafer and a cover plate and then dicing; the microfluidic structure is fabricated on the semiconductor substrate wafer before the integrated integrated circuit chip is formed and is embedded in the semiconductor substrate wafer.

[0010] Secondly, the present invention provides a method for fabricating an integrated integrated circuit chip structure, used to fabricate the aforementioned integrated integrated circuit chip structure, the method comprising:

[0011] An integrated circuit device region and a microchannel structure are fabricated on a semiconductor substrate wafer; the microchannel structure is embedded within the semiconductor substrate wafer.

[0012] A liquid separation structure and inlet / outlet ports are fabricated on the cover plate;

[0013] The semiconductor substrate wafer and the cover plate are bonded together to obtain a bonding structure;

[0014] The bonding structure is diced to form an integrated circuit chip having the microchannel structure, the liquid separation structure, and the inlet and outlet ports;

[0015] The integrated integrated circuit chip is packaged; the integrated integrated circuit chip includes a semiconductor substrate, a cover plate, and a packaging structure for the integrated circuit chip, the packaging structure having a protective shell; the protective shell is used to protect the integrated integrated circuit chip.

[0016] This invention provides an integrated integrated circuit chip structure and fabrication method. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during the integrated circuit chip fabrication process, rather than being fabricated separately after chip fabrication. By embedding the microfluidic channels into the semiconductor substrate wafer, a heat dissipation structure for multiple integrated circuit chips is achieved, reducing the cost required for chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium through conduction via the substrate, reducing thermal resistance during heat dissipation and improving heat dissipation capacity. A liquid-separation structure guides the flow of the cooling medium, shortening its flow path and improving its heat exchange efficiency, achieving highly efficient heat dissipation. Attached Figure Description

[0017] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0018] Figure 1 A schematic diagram of the overall structure of the integrated integrated circuit chip provided by the present invention;

[0019] Figure 2 A schematic diagram of the inlet / outlet thread design structure in the integrated integrated circuit chip structure provided by the present invention;

[0020] Figure 3 A schematic diagram of the external liquid inlet / outlet connection structure in the integrated integrated circuit chip structure provided by the present invention;

[0021] Figure 4 This is a schematic diagram of the integrated integrated circuit chip structure fabrication method provided by the present invention;

[0022] Figure 5 This is a schematic diagram illustrating the fabrication process on a semiconductor substrate wafer.

[0023] Figure 6 This is a schematic diagram illustrating the manufacturing process on the cover plate.

[0024] Figure 7 This is a schematic diagram of the bonding process between a semiconductor substrate wafer and a cover plate.

[0025] Figure 8 A schematic diagram illustrating the process of dicing the bonded structure to form an integrated circuit chip.

[0026] Figure 9 This is a schematic diagram of the structure for packaging an integrated circuit chip.

[0027] Reference numerals: 1-Semiconductor substrate, 2-Cover plate, 3-Packaging structure of integrated circuit chip, 4-Integrated circuit device area, 5-Microchannel structure, 6-Inlet fluid passage, 7-Outlet fluid passage, 8-Packaging shell, 9-Bottom filler material, 10-Electrical connection structure, 11-Inlet of liquid distribution structure, 12-Outlet of liquid distribution structure, 13-Inlet reserved in the packaging shell, 14-Outlet reserved in the packaging shell, 15-Electrical pin on the packaging shell, 16-Threaded structure of the inlet, 17-Threaded structure of the outlet, 18-Connecting nozzle structure at the inlet, 19-Connecting nozzle structure at the outlet. Detailed Implementation

[0028] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0029] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0031] In existing technologies, common heat dissipation methods for integrated circuit chips include air cooling and indirect liquid cooling. In these methods, air-cooled or liquid-cooled heat dissipation devices are attached to the packaged integrated circuit chip casing using thermal interface materials. Heat generated by the chip needs to be conducted through multiple thermal interfaces and then dissipated through natural convection or solid-liquid heat transfer. The heat dissipation path is: high heat flux density point on the chip – thermal interface material – packaging structure – thermal interface material – heat dissipation structure. Thermal interface materials increase the thermal resistance of the chip, limiting its heat transfer efficiency and reducing its heat dissipation capacity. Therefore, currently used integrated circuit chip heat dissipation methods cannot adequately meet the heat dissipation requirements of high heat flux density points on integrated circuit chips.

[0032] Meanwhile, current chip thermal management and heat dissipation structure designs are all carried out after packaging is complete. For example, microchannels are only fabricated on the formed chip after it has been formed on the wafer, causing great inconvenience to users. After the chip is manufactured, its rated power and maximum heat generation under operating conditions are known. If a standard direct heat dissipation solution and method could be provided for fixed chip products, it would not only improve heat dissipation efficiency, but also provide end users with a standard thermal management interface. Furthermore, current integrated circuit chips are produced in batches, requiring a convenient method to meet their heat dissipation needs and reduce heat dissipation costs.

[0033] Therefore, there is a need for a heat dissipation solution that effectively reduces the thermal resistance of integrated circuit chips, improves the heat transfer capability at high heat flux density points of integrated circuit chips, and is highly usable and easy to implement.

[0034] This solution provides an integrated integrated circuit chip structure and fabrication method. During chip fabrication, a microfluidic structure 5 is fabricated on the back side of a semiconductor substrate wafer with integrated circuit devices on the front side by etching. A cover plate with inlet / outlet ports is then bonded to the microfluidic structure 5 to achieve its enclosure. Finally, the chip is packaged to achieve a directly cooled integrated circuit chip. The method involves first fabricating the devices on the front side of the semiconductor substrate wafer using a CMOS process, and then fabricating micro-structured channels on the back side using a compatible process. Next, a cover plate 2 with inlet / outlet ports and a liquid distribution structure is fabricated. The semiconductor substrate wafer and cover plate 2 are then connected, and the wafer is diced to form an integrated integrated circuit chip with the microfluidic structure 5, liquid distribution structure, and inlet / outlet ports. The chip is then packaged, with inlet / outlet ports pre-installed on the package shell, corresponding to the inlet / outlet ports of the microfluidic channels. This creates an integrated circuit chip capable of direct cooling, allowing heat from high heat flux density points on the chip to be carried away through the microfluidic channels, reducing heat accumulation and ensuring the device can operate within its temperature tolerance range, thus extending the chip's operating limits.

[0035] Next, the solutions provided in the embodiments of this specification will be described in conjunction with the accompanying drawings:

[0036] Figure 1 This is a schematic diagram of the overall structure of the integrated circuit chip provided by the present invention. Figure 1 As shown, the structure may include:

[0037] A semiconductor substrate 1 may be provided with an integrated circuit device region 4 and a microfluidic structure 5; the microfluidic structure 5 is embedded in the semiconductor substrate wafer.

[0038] The cover plate 2 has a liquid distribution structure and liquid inlet / outlet ports; the integrated circuit chip packaging structure 3 has a protective shell; the protective shell is used to protect the integrated integrated circuit chip. The integrated integrated circuit chip is formed by bonding the semiconductor substrate wafer and the cover plate 2 and then dicing; the microfluidic structure 5 is fabricated on the semiconductor substrate wafer before the integrated integrated circuit chip is formed and is embedded in the semiconductor substrate wafer.

[0039] The integrated circuit chip packaging structure 3 can have a protective shell to protect the integrated circuit chip and improve the chip's reliability. It also has an electrical connection structure 10 to bring out the chip's electrical pins, and has inlet and outlet ports to allow the cooling medium to flow in and out.

[0040] The above Figure 1The structure comprises an integrated circuit chip consisting of a semiconductor substrate 1 and a cover plate 2. The semiconductor substrate 1 has corresponding integrated circuit device areas and microfluidic structures 5. The cover plate 2 has a liquid distribution structure and inlet / outlet ports, allowing the cooling medium to be guided into the microfluidic structure 5, circulated within the microchannels, and then discharged through the inlet / outlet ports. Simultaneously, the liquid distribution structure shortens the flow path of the cooling medium. The number of microfluidic structures is consistent with the number of integrated circuit device areas 4. It should be noted that the cover plate can be a semiconductor wafer or other materials. In this solution, the material of the cover plate is not specifically limited; as long as the liquid distribution structure and the inlet / outlet ports are present, the cover plate falls within the scope of protection of this solution.

[0041] Integrated circuit chips with electrical and heat dissipation functions are fabricated on semiconductor substrate wafers and then packaged. By combining integrated circuit fabrication technology and microfluidic fabrication technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during the integrated circuit chip fabrication process, rather than being fabricated separately after chip fabrication. By embedding the microfluidic channels into the semiconductor substrate wafer, a heat dissipation structure for multiple integrated circuit chips is achieved, reducing the cost of chip heat dissipation. A cover plate guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium through conduction via the substrate. This reduces the thermal resistance during heat dissipation and improves heat dissipation capacity. A liquid-separation structure guides the flow of the cooling medium, shortening its flow path and improving its heat exchange efficiency, achieving highly efficient heat dissipation.

[0042] based on Figure 1 The structure in the code can also include the following specific implementation structures:

[0043] The cover plate 2 is provided with an inlet fluid passage 6 and an outlet fluid passage 7. The liquid distribution structure has an inlet 11 and an outlet 12. The cooling medium entering from the inlet 11 is distributed through the inlet fluid passage 6, then flows through the sub-channels in the microchannel, and then directly collects liquid through the outlet fluid passage 7. Finally, it flows out through the outlet 12. Compared with no liquid distribution structure, the cooling medium changes from flowing along the length of the channel to flowing along the width of the channel, shortening the flow path of the cooling medium and improving the heat exchange efficiency.

[0044] The space between the semiconductor substrate 1 and the package housing is filled with the underfill material 9.

[0045] The integrated integrated circuit chip structure may further include: a package shell 8, the package shell 8 having an internal cavity and a liquid inlet / outlet, the liquid inlet / outlet on the package shell 8 being connected to the liquid inlet / outlet of the integrated integrated circuit chip for the inlet and outlet of the cooling working fluid; both the integrated circuit device area 4 and the bottom of the package shell 8 are provided with electrical pins for leading out the electrical pins of the integrated circuit chip, and the electrical pins in the integrated circuit device area 4 being connected to the electrical pins at the bottom of the package shell 8.

[0046] Furthermore, the liquid inlet and outlet of the encapsulation housing 8 are provided with threaded structures and connecting nozzle structures, which can be combined with... Figure 2 as well as Figure 3 Explanation: Figure 2 A schematic diagram of the inlet / outlet thread design structure in the integrated circuit chip structure provided by the present invention. Figure 3 A schematic diagram of the external connection structure of the liquid inlet and outlet in the integrated integrated circuit chip structure provided by the present invention.

[0047] like Figure 2 As shown, reference numeral 13 is the liquid inlet reserved in the packaging shell, reference numeral 14 is the liquid outlet reserved in the packaging shell, reference numeral 16 is the threaded structure of the liquid inlet, and reference numeral 17 is the threaded structure of the liquid outlet. The threaded structure and the connecting nozzle structure are used to provide a thermal management interface for connecting to an external liquid supply structure.

[0048] like Figure 3 As shown, reference numeral 18 is the connection nozzle structure at the liquid inlet of the encapsulation shell, and reference numeral 19 is the connection nozzle structure at the liquid outlet of the encapsulation shell.

[0049] The above method facilitates connection to external liquid supply structures, provides users with a standard thermal management interface, and improves chip usability.

[0050] In existing technologies, microchannel etching is performed after chip fabrication is completed. However, in this solution, the cooling structure is fabricated during chip fabrication. The fabrication of microchannels is incorporated into the chip fabrication process. Specifically, the integrated circuit periodic region and microchannels can be fabricated on a semiconductor substrate wafer. A liquid distribution structure and inlet / outlet ports are provided on the cover plate 2. Then, the semiconductor substrate wafer and the cover plate are bonded together and packaged.

[0051] More specifically, both the semiconductor substrate 1 and the cover plate 2 have a first surface and a second surface;

[0052] The integrated circuit device region 4 is disposed on the first surface of the semiconductor substrate 1, and there are multiple integrated circuit device regions 4; the microchannel structure 5 is disposed on the second surface of the semiconductor substrate 1;

[0053] The liquid distribution structure can be a microchannel, which is located on the first side of the cover plate 2, and the inlet and outlet are located on the second side of the cover plate 2. The inlet and outlet are connected to the microchannel, and the number of inlets and outlets and the number of microchannels are consistent with the number of microchannel structures 5. The cooling medium entering from the inlet on the cover plate 2 is distributed through the inlet fluid passage 6 in the cover plate 2, then flows through the sub-channels in the microchannel structure 5, and is collected through the outlet fluid passage 7 in the cover plate 2. Finally, it flows out through the outlet on the cover plate 2 to ensure that the cooling medium flows along the width of the channel.

[0054] It should be noted that the "first side" described in this specification can correspond to the "front side" and the "second side" can correspond to the "back side". In practical applications, in order to avoid ambiguity in the determination of the front and back sides, this specification uses the description of "first side" and "second side" to clearly indicate that there are two opposing sides on both the semiconductor substrate 1 and the cover plate 2.

[0055] Regarding the integrated integrated circuit chip structure in the above embodiments, the specific fabrication method can be implemented using the following embodiments:

[0056] Figure 4 This is a schematic diagram of the integrated integrated circuit chip structure fabrication method provided by the present invention. Figure 4 As shown, the process corresponding to the integrated integrated circuit chip structure fabrication method may include the following steps:

[0057] Step 410: Fabricate an integrated circuit device region and a microchannel structure on a semiconductor substrate wafer; the microchannel structure is embedded in the semiconductor substrate wafer.

[0058] Step 420: Create the liquid separation structure and inlet / outlet ports on the cover plate.

[0059] Step 430: Bond the semiconductor substrate wafer and the cover plate to obtain a bonding structure.

[0060] Step 440: Divide the bonding structure to form an integrated integrated circuit chip having the microchannel structure, liquid separation structure and liquid inlet / outlet.

[0061] Step 450: Package the integrated integrated circuit chip; the integrated integrated circuit chip includes a semiconductor substrate, a cover plate, and a packaging structure for the integrated circuit chip, the packaging structure having a protective shell; the protective shell is used to protect the integrated integrated circuit chip.

[0062] Figure 4The method described herein involves fabricating and packaging an integrated circuit chip with both electrical and heat dissipation functions on a semiconductor substrate wafer. By embedding microfluidic channels within the semiconductor substrate wafer, a heat dissipation structure for multiple integrated circuit chips is created. A cover plate 2 then guides the cooling medium into the microfluidic channels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium via conduction through the substrate. This reduces thermal resistance during heat dissipation and improves heat dissipation capacity. Furthermore, a liquid-separation structure guides the flow of the cooling medium, shortening its flow path and improving its heat exchange efficiency, thus enhancing heat dissipation and achieving highly efficient heat dissipation.

[0063] based on Figure 4 In addition to the method described herein, this specification also provides some specific implementation methods of this method, which will be described below.

[0064] Optionally, a packaging shell 8 is provided to provide liquid inlet and liquid outlet for the microchannels in the integrated integrated circuit chip; the liquid inlet and liquid outlet on the packaging shell 8 are connected to the liquid inlet and liquid outlet of the integrated integrated circuit chip.

[0065] Optionally, the method may further include:

[0066] Threaded structures and connecting nozzle structures are fabricated at the liquid inlet and liquid outlet of the encapsulation shell 8; including a liquid inlet threaded structure 16, a liquid outlet threaded structure 17, a liquid inlet connecting nozzle structure 18, and a liquid outlet connecting nozzle structure 19. The threaded structures and the connecting nozzle structures are used to provide thermal management interfaces for connecting to an external liquid supply structure.

[0067] Optionally, when fabricating the microchannel structure 5 on the semiconductor substrate wafer, any one of the following methods may be used: deep silicon etching, plasma etching, reactive ion etching, laser etching, and chemical etching.

[0068] More specifically, the above Figure 4 The actual preparation process corresponding to the preparation process in the text can be combined with... Figure 5-9 Explanation:

[0069] Figure 5 This is a schematic diagram illustrating the fabrication process on a semiconductor substrate wafer. (Example) Figure 5 As shown, an integrated circuit device region 4 is fabricated on the first surface of a semiconductor material wafer, and then microchannels are fabricated on the second surface of the semiconductor substrate wafer. For a semiconductor substrate wafer with opposite first and second surfaces, several integrated circuit device regions 4 are fabricated on the first surface of the semiconductor substrate wafer, and microchannel structures of several depths are fabricated on the second surface of the semiconductor substrate wafer. The number of microchannel structures is consistent with the number of integrated circuit device regions 4.

[0070] Figure 6This is a schematic diagram illustrating the manufacturing process on the cover plate. Figure 6 As shown, for a cover plate with a first side and a second side, the first side of the cover plate is made with microchannels of several depths for liquid separation. The number of microchannels is the same as the number of microchannel structures. The second side of the cover plate is made with several inlet and outlet ports. The number of inlet and outlet ports is the same as the number of microchannels. The inlet and outlet ports have a certain depth to allow the inlet and outlet ports to communicate with the microchannels.

[0071] Figure 7 This is a schematic diagram illustrating the bonding process between a semiconductor substrate wafer and a cover plate. Figure 7 As shown, bonding the semiconductor material wafer and the cover plate involves bonding the second side of the semiconductor substrate wafer to the first side of the cover plate 2. Since the number of microchannels and microfluidic structures are the same, the number of inlets and outlets is the same as the number of microchannels, and the number of microfluidic structures is the same as the number of integrated circuit device regions 4, the bonding of the cover plate 2 and the semiconductor substrate wafer does not affect the function of the overall cooling structure.

[0072] Figure 8 This diagram illustrates the process of dicing the bonded structure to form an integrated circuit chip. Figure 8 As shown, the chips are diced to form an integrated integrated circuit chip with microchannel structure 5, liquid separation structure and inlet / outlet ports.

[0073] Figure 9 This is a schematic diagram of the structure for packaging an integrated circuit chip. (Example) Figure 9 As shown, the integrated integrated circuit chip is packaged so that the electrical pins of the integrated integrated circuit device area 4 are connected to the reserved electrical pins on the package shell 8, the liquid inlet of the integrated integrated circuit chip is connected to the reserved liquid inlet 13 on the package shell, and the liquid outlet of the integrated integrated circuit chip is connected to the reserved liquid outlet 14 on the package shell.

[0074] Several designs for the encapsulation housing 8, such as Figures 2-3 The example shown is merely an illustration. Various other forms of encapsulation housings 8 that can protect integrated circuit chips and provide inlet and outlet ports for microchannels in integrated circuit chips are also within the scope of protection of this invention.

[0075] Based on the above embodiments, the present invention also includes some specific optional implementation methods:

[0076] The semiconductor substrate 1 of the integrated circuit chip may include silicon, silicon carbide, diamond, etc. The cover plate 2 may be made of semiconductor materials such as silicon, diamond, silicon carbide, glass, PMMA (acrylic; polymethyl methacrylate), FR4 (epoxy glass cloth laminate), etc. The encapsulation shell 8 may be made of materials such as epoxy resin, ceramic, aluminum, aluminum-iron alloy, etc.

[0077] Methods for fabricating the liquid distribution structure and inlet / outlet ports in cover plate 2 may include DRIE (deep silicon etching), plasma etching, reactive ion etching, laser etching, chemical etching, 3D printing, machining, etc.

[0078] Methods for achieving bonding can include silicon-silicon bonding, anodic bonding, gold-silicon bonding, gold-gold bonding, gold-tin bonding, gold-indium bonding, thermocompression bonding, polymer wafer bonding, etc.

[0079] Methods for dicing bonded wafers can include mechanical dicing, laser dicing, water jet dicing, etc.

[0080] Methods for packaging integrated circuit chips can include DIP (Dual In-line Package), QFN (Quad Flat Package), SOP (Small Outline Package), PLCC (Plastic WireChip Package), BGA (Ball Grid Array Package), etc.

[0081] It should be noted that the solutions in the above embodiments are only one or more embodiments of the present invention and do not limit the scope of protection of the present invention. By fabricating microchannels on the back side of the semiconductor substrate wafer of the integrated circuit chip during the integrated circuit chip processing, and then connecting a cover plate with a liquid distribution structure and inlet / outlet ports, and then dicing, an integrated circuit chip with microchannel structure, liquid distribution structure and inlet / outlet ports that can be directly cooled is formed. An integrated integrated circuit chip with electrical and heat dissipation functions is fabricated on the semiconductor substrate wafer and packaged. By combining the integrated circuit processing technology and the microchannel processing technology, the microchannels are directly fabricated on the semiconductor substrate wafer during the integrated circuit chip processing, instead of being fabricated separately after the chip is completed. By embedding the microchannels into the semiconductor substrate wafer, the heat dissipation structure of multiple integrated circuit chips is realized, reducing the cost required for chip heat dissipation. The cooling medium is led to the microchannels through the cover plate, so that the heat of the high heat flux density points of the chip is directly exchanged with the cooling medium through the conduction of the substrate, reducing the thermal resistance in the process of heat loss of the chip and improving the heat dissipation capacity. By guiding the flow of the cooling medium through a liquid-liquid separation structure, the flow path of the cooling medium is shortened, the heat exchange efficiency of the cooling medium is improved, and efficient heat dissipation is achieved.

[0082] In the embodiments of this invention, microchannels are embedded in a semiconductor substrate wafer to fabricate a heat dissipation structure for multiple integrated circuit chips. Then, a cover plate guides the cooling medium into the microchannels, allowing heat from high heat flux density points on the chip to directly exchange with the cooling medium after conduction through the substrate. This reduces thermal resistance during heat dissipation and improves heat dissipation capacity. A liquid-separation structure guides the flow of the cooling medium, shortening its flow path and improving its heat exchange efficiency, thus enhancing heat dissipation and achieving highly efficient heat dissipation. Furthermore, the chip packaging design provides users with a standard thermal management interface, improving chip usability and meeting the heat dissipation requirements of high heat flux density points on integrated circuit chips.

[0083] The solution of the present invention has the following advantages:

[0084] 1) An integrated circuit chip with electrical and heat dissipation functions is fabricated on a semiconductor substrate wafer and packaged. By combining integrated circuit processing technology and microfluidic processing technology, microfluidic channels are directly fabricated on the semiconductor substrate wafer during the integrated circuit chip fabrication process, instead of fabricating microfluidic channels separately after the chip is completed. By embedding microfluidic channels into the semiconductor substrate wafer, the heat dissipation structure of multiple integrated circuit chips is realized, reducing the cost required for chip heat dissipation.

[0085] 2) By manufacturing integrated circuit chips with electrical and heat dissipation functions and packaging them, the ease of use of integrated circuit chips is improved.

[0086] 3) By combining the method of directly fabricating microchannels on the back side of the semiconductor substrate wafer of the integrated circuit chip and designing a liquid distribution structure to shorten the flow path of the cooling medium, heat exchange efficiency is improved and the heat dissipation capacity of the integrated circuit chip is increased.

[0087] 4) By designing the chip's packaging, a standard thermal management interface can be provided to users, thereby improving the chip's usability.

[0088] In practical applications, the preparation method in the above embodiments can be implemented using a preparation apparatus and equipment, wherein the preparation equipment may further include a memory. The memory stores computer execution instructions for implementing the present invention, and its execution is controlled by a processor. The processor executes the computer execution instructions stored in the memory, thereby implementing the preparation method provided in the embodiments of the present invention.

[0089] The memory can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via communication lines. The memory can also be integrated with the processor.

[0090] Optionally, the computer execution instructions in the embodiments of the present invention may also be referred to as application code, and the embodiments of the present invention do not specifically limit this.

[0091] Those skilled in the art will readily recognize that, based on the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein, the present invention can be implemented in hardware or a combination of hardware and computer software. Whether a function is implemented in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention.

[0092] The processor described in this specification may also function as a memory. The memory stores computer execution instructions for carrying out the present invention, and its execution is controlled by the processor. The processor executes the computer execution instructions stored in the memory, thereby implementing the method provided in the embodiments of the present invention.

[0093] The memory can be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, random access memory (RAM) or other types of dynamic storage devices capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed discs, laser discs, optical discs, universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited to these. The memory can exist independently and be connected to the processor via communication lines. The memory can also be integrated with the processor.

[0094] The methods disclosed in the above embodiments of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above methods can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present invention can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0095] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present invention are performed entirely or partially. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal, a user equipment, or other programmable device. The computer program or instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. For example, the computer program or instructions can be transferred from one website, computer, server, or data center to another website, computer, server, or data center via wired or wireless means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a digital video disc (DVD); or it can be a semiconductor medium, such as a solid-state drive (SSD).

[0096] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit can implement several functions listed in the claims. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0097] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A method of fabricating an integrated circuit chip structure, comprising: A method for preparing an integrated circuit chip structure, the method comprising: ​ fabricating an integrated circuit device region and a microfluidic structure on a semiconductor substrate wafer; embedding the microfluidic structure into the semiconductor substrate wafer; fabricating a distribution structure and fluid inlet / outlet ports on a cover plate; bonding the semiconductor substrate wafer and the cover plate to obtain a bonded structure; singulating the bonded structure to form an integrated circuit chip having the microfluidic structure, the distribution structure, and the fluid inlet / outlet ports; 2. The method of claim 1, wherein the method further comprises: packaging the integrated circuit chip; the integrated circuit chip comprising a semiconductor substrate, a cover plate, and a packaging structure of the integrated circuit chip, the packaging structure having a protective shell; the protective shell being configured to protect the integrated circuit chip. The method further comprises:

3. The method for fabricating an integrated circuit chip structure according to claim 2, characterized in that, providing the microfluidic structure in the integrated circuit chip with a packaging shell in the form of fluid inlet and outlet ports; the fluid inlet and outlet ports on the packaging shell being connected to the fluid inlet and outlet ports of the integrated circuit chip. The method further comprises:

4. The method of claim 1, wherein the method further comprises: fabricating a threaded structure and a connection nozzle structure at the fluid inlet and outlet ports of the packaging shell; the threaded structure and the connection nozzle structure being configured to provide a thermal management interface for connecting to an external fluid supply structure. In fabricating the microfluidic structure on the semiconductor substrate wafer, any one of deep silicon etching, plasma etching, reactive ion etching, laser etching, and chemical etching is used. ​

Images