A cross-cluster high-reliability data interaction method based on an inter-core loose coupling architecture

Abstract

The application provides a cross-cluster high-reliability data interaction method based on an inter-core loose coupling architecture, and relates to the technical field of integrated circuits, and comprises the following steps: realizing data intercommunication of a computing processor cluster and a communication processor cluster based on an AHB2AHB bridge; uniformly allocating address spaces of the computing processor cluster and the communication processor cluster, so that the address spaces of the computing processor cluster and the communication processor cluster do not contain overlapping parts; when cross-cluster data access is performed based on the AHB2AHB bridge, the AHB2AHB bridge performs address remapping based on the address spaces of the two processor clusters; and cross-cluster data interaction is performed based on the remapped addresses. The application realizes data interaction between the computing processor cluster and the communication processor cluster through the AHB2AHB bridge, and further realizes uniform mapping of the address spaces of the processor cluster and the communication processor cluster through the uniform allocation of addresses and the address remapping mechanism, thereby improving the efficiency and reliability of the inter-cluster communication of the computing processor cluster and the communication processor cluster.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture. BACKGROUND

[0002] At present, in the inter-core loosely coupled architecture based on function clustering, when designing a multi-core SoC with multiple types of interface communication protocols, the processor cores are divided into different processor clusters according to functions, forming a computing processor cluster oriented to high-performance computing and a communication processor cluster oriented to the control and response of communication peripherals.

[0003] However, when sharing and accessing data between the computing processor cluster and the communication processor cluster, due to the lack of an effective data interaction mechanism, the reliability of data interaction between the clusters is low.

[0004] Therefore, there is an urgent need for a cross-cluster high-reliability data interaction method suitable for an inter-core loosely coupled architecture. SUMMARY

[0005] The present application aims to provide a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture to improve the above problems. In order to achieve the above purpose, the technical solution adopted by the present application is as follows:

[0006] The present application provides a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture, comprising:

[0007] The data intercommunication between the computing processor cluster and the communication processor cluster is realized based on an AHB2AHB bridge, and the interconnection structure within the computing processor cluster and the communication processor cluster is realized based on a crossbar switch of the AHB protocol;

[0008] The address spaces of the computing processor cluster and the communication processor cluster are allocated to obtain the address spaces of the computing processor cluster and the communication processor cluster, and the address spaces of the computing processor cluster and the communication processor cluster do not contain overlapping address spaces;

[0009] When cross-cluster data access is performed based on the AHB2AHB bridge, the AHB2AHB bridge performs address remapping based on the address spaces of the computing processor cluster and the communication processor cluster to obtain a remapping address;

[0010] The data interaction between the computing processor cluster and the communication processor cluster is performed based on the remapping address.

[0011] As a preferred scheme of the present application, the starting address of the address space of the computing processor cluster is 0.

[0012] As a preferred scheme of the present application, the method further comprises:

[0013] The on-chip unallocated address space is taken as a reserved area, and the reserved area is obtained, which is invalid when accessed by a host of the computing processor cluster or the communication processor cluster.

[0014] As a preferred scheme of the present application, the method further comprises:

[0015] When any slave of the communication processor cluster and the computing processor cluster is simultaneously accessed by a plurality of first hosts, a preset arbitration module outputs a plurality of control signals based on access request information of each first host, the access request information including priority and timing of the access request, and one control signal corresponding to one first host.

[0016] Access control of the plurality of first hosts is performed based on the plurality of control signals, the control signals including a first control signal and at least one second control signal, the first control signal being used to instruct the first host to access the slave, and the second control signal being used to instruct the first host to wait.

[0017] As a preferred scheme of the present application, the method further comprises:

[0018] When the first slave interface of the AHB2AHB bridge receives a first command of the computing processor cluster, the AHB2AHB bridge transmits the first command to the host interface of the communication processor cluster through the first host interface.

[0019] When the second slave interface of the AHB2AHB bridge receives a second command of the communication processor cluster, the AHB2AHB bridge transmits the second command to the host interface of the communication processor cluster through the second host interface.

[0020] As a preferred scheme of the present application, the remapping address includes a first remapping address and a second remapping address, the first remapping address being an address of the first slave interface of the AHB2AHB bridge, and the first remapping address being the same as the address space of the computing processor cluster, and the second remapping address being an address of the second slave interface of the AHB2AHB bridge, and the second remapping address being the same as the address space of the communication processor cluster.

[0021] As a preferred scheme of the present application, after the AHB2AHB bridge realizes data intercommunication between the computing processor cluster and the communication processor cluster, the present application further comprises:

[0022] The first slave interface or the second slave interface of the AHB2AHB bridge, after receiving a third control signal, synchronizes the third control signal based on a secondary synchronization unit of the AHB2AHB bridge, to obtain a synchronized third control signal, the third control signal being a transmission control signal output by the computing processor cluster or the communication processor cluster, and the synchronized signal being used to start data transmission between the computing processor cluster and the communication processor cluster within a preset clock domain.

[0023] The present application has the following beneficial effects:

[0024] The present application realizes data interaction between the computing processor cluster and the communication processor cluster through the AHB2AHB bridge, and further realizes address uniform mapping between the processor cluster and the communication processor cluster through a unified address allocation and address remapping mechanism, thereby improving the efficiency and reliability of inter-cluster communication between the computing processor cluster and the communication processor cluster.

[0025] Other features and advantages of the present application will be illustrated in the following description, and some of them will become apparent from the description, or will be understood by those skilled in the art through implementation of the embodiments of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the present application, and therefore should not be considered as limiting the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0027] Figure 1 A flowchart of a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture according to an embodiment of the present application;

[0028] Figure 2 A data interaction flowchart based on address remapping of a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture according to an embodiment of the present application;

[0029] Figure 3 A flowchart of mutual exclusion access of multiple hosts to the same slave of a cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture according to an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0031] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0032] Embodiment 1

[0033] The embodiment provides a cross-cluster high-reliability data interaction method based on an inter-core loose coupling architecture.

[0034] As shown in Figure 1 , the figure shows that the method includes:

[0035] The AHB2AHB bridge is used to realize data intercommunication between the computing processor cluster and the communication processor cluster, and the interconnection structure in the computing processor cluster and the communication processor cluster is realized based on a crossbar switch of an AHB protocol;

[0036] The address spaces of the computing processor cluster and the communication processor cluster are allocated to obtain the address spaces of the computing processor cluster and the communication processor cluster, and the address spaces of the computing processor cluster and the communication processor cluster do not contain overlapping address spaces;

[0037] When the AHB2AHB bridge is used for cross-cluster data access, the AHB2AHB bridge performs address remapping based on the address spaces of the computing processor cluster and the communication processor cluster to obtain a remapping address;

[0038] The computing processor cluster and the communication processor cluster perform data interaction based on the remapping address.

[0039] It can be understood that the computing processor cluster and the communication processor cluster in the embodiment, i.e. the computing subsystem and the communication subsystem, both use an AHB-based crossbar as the core interconnection structure within the cluster. Therefore, the embodiment uses an AHB2AHB protocol conversion bridge to realize the inter-cluster interconnection between the computing subsystem and the communication subsystem. On this basis, the data interaction between the computing subsystem and the communication subsystem is further realized.

[0040] For a single cluster, normal access of the master to the slave can be satisfied by using uniform addressing within the cluster. However, if only independent addressing is used within each cluster, problems will occur in inter-cluster access: the same slave may correspond to different addresses in the view of the master in different clusters. This inconsistency in addresses will cause the application layer to be unable to identify whether it is the same resource, thereby generating access ambiguity, causing unexpected access or even system errors, and thus reducing the overall reliability.

[0041] Therefore, the embodiment uses a global uniform addressing mechanism to uniformly allocate and map the addresses of all slaves on the chip. Through this mechanism, the masters of the computing processor cluster and the communication processor cluster both use consistent global addresses when accessing the same slave, thereby constructing a unique system address view. This scheme not only avoids address ambiguity, guarantees the correctness and reliability of inter-cluster data interaction, but also provides a single transparent address space for the application layer, simplifies software development and porting, and provides a unified permission management basis for the memory protection unit, thereby improving the security and stability of the system. Under this mechanism, the embodiment guarantees that the address spaces of the computing subsystem and the communication subsystem do not overlap and do not interfere with each other, and the allocation of the global system addresses on the chip is as shown in the following table:

[0042]

[0043] Among them, FLASH, EMIF and SRAM belong to the slaves in the computing subsystem, two peripheral clusters are integrated into the communication subsystem through an APB shared bus bridge, and the remaining unused address space is reserved. When the master accesses this type of address, it is invalid. TCM is a tightly coupled storage of the processor core in the computing processor cluster and the communication processor cluster. When the processor accesses the TCM corresponding to the core, it can be directly accessed, and when other masters (including other cores within the cluster or cross-cluster masters) access, it needs to pass through the crossbar link. The design purpose of TCM is to ensure high-speed and low-latency access of the processor to instructions and data, while supporting inter-core communication and DMA data transfer.

[0044] If the TCM is not globally uniformly addressed, the same TCM can correspond to different addresses in the address space of different hosts, which can easily lead to ambiguity or illegal access in cross-cluster access, increase the complexity of software in address conversion and management, and further affect the stability and reliability of the system. Therefore, in the embodiment, the TCM in each processor cluster is included in the global uniform addressing system, and a unique address is allocated to the TCM, so as to ensure that the same TCM is accessed by a consistent global address in any host, realize the consistency and correctness of cross-cluster access, and improve the overall stability and security of the system.

[0045] Two peripheral clusters are integrated into the communication subsystem based on the APB shared bus bridge. The remaining unused address space is reserved, and the host access to such addresses is invalid.

[0046] After the on-chip uniform addressing is performed, in order to enable the computing subsystem and the communication subsystem to interact data through shared memory, the embodiment realizes the global address uniform mapping through the address remapping mechanism of the AHB2AHB bridge, simplifies the data interaction process, reduces the complex address conversion logic, and makes the cross-subsystem data access more direct.

[0047] As a preferred scheme of the embodiment, the starting address of the address space of the computing processor cluster is 0.

[0048] It can be understood that, since the storage of the computing processor cluster needs to store instructions and the like, when the on-chip uniform addressing is performed, the addressing of the computing processor cluster is performed first, that is, the computing processor cluster starts from 0 to perform the addressing.

[0049] As a preferred scheme of the embodiment, after the address spaces of the computing processor cluster and the communication processor cluster are allocated, the method further includes:

[0050] The unallocated address space on the chip is taken as a reserved area, and the reserved area is obtained, and the reserved area is invalid when accessed by the host of the computing processor cluster or the communication processor cluster.

[0051] It can be understood that, in the embodiment, two reserved areas are included: one is located inside the computing processor cluster, and is used to isolate the undefined or unallocated address inside the cluster, and returns an invalid response when the host inside the cluster accesses the area, and at the same time, reserves space for future system expansion, function upgrade or addition of a control interface; the other is located between the address boundary of the computing processor cluster and the communication processor cluster, forms a cross-cluster logical isolation layer, and is used to prevent disordered access of the cross-cluster host to other cluster resources, and provides a protection band for the cross-cluster access, which is beneficial to permission check and exception handling.

[0052] As a preferred scheme of the present application, the data intercommunication between the computing processor cluster and the communication processor cluster based on the AHB2AHB bridge comprises:

[0053] When the first slave interface of the AHB2AHB bridge receives the first command of the computing processor cluster, the AHB2AHB bridge transmits the first command to the master interface of the communication processor cluster through the first master interface;

[0054] When the second slave interface of the AHB2AHB bridge receives the second command of the communication processor cluster, the AHB2AHB bridge transmits the second command to the master interface of the communication processor cluster through the second master interface.

[0055] It can be understood that, as shown in Figure 2 the AHB2AHB bridge is as shown in Figure 2 The structure converts the command issued by the master interface of the computing subsystem into the command of the master interface on the communication subsystem through the slave interface of the AHB2AHB, so as to realize the cross-subsystem access of the master of the computing subsystem to the slave of the communication subsystem, and vice versa, so as to realize the data intercommunication between the two subsystems.

[0056] As a preferred scheme of the present application, after the data intercommunication between the computing processor cluster and the communication processor cluster based on the AHB2AHB bridge, the method further comprises:

[0057] After the first slave interface or the second slave interface of the AHB2AHB bridge receives a third control signal, the second synchronization unit of the AHB2AHB bridge synchronizes the third control signal to obtain a synchronized third control signal, the third control signal being a transmission control signal output by the computing processor cluster or the communication processor cluster, and the synchronized signal being used to start the data transmission between the computing processor cluster and the communication processor cluster within a preset clock domain.

[0058] It can be understood that the computing subsystem adopts a high clock frequency to meet its high-performance computing requirement, while the communication subsystem reduces the clock frequency as much as possible to realize dynamic power optimization on the basis of meeting the functional requirement, thereby resulting in the difference in clock frequency between the two subsystems, and the AHB2AHB bridge needs to synchronize between different clock domains. The cross-subsystem data interaction process is initiated by the access of the master to the cross-cluster slave interface. After the cross-cluster slave interface receives the transmission control signal from the master of the subsystem, in order to realize the cross-clock-domain transmission, the request control signal needs to be synchronized through the second synchronization unit to eliminate the timing problem caused by the inconsistency of clock domains. The synchronized signal is transmitted to the cross-cluster master interface, which is responsible for starting the data transmission within the target clock domain.

[0059] When a burst write transfer occurs between the source subsystem and the target subsystem, the cross-cluster master interface reads data from the write data FIFO according to the synchronized request signal and transmits the data to the target subsystem. When a burst read transfer occurs, the cross-cluster master interface writes data into the read data FIFO, and the cross-cluster slave interface subsequently reads data from the FIFO. When a single read-write transfer occurs, the cross-cluster master interface directly receives data. In this process, the secondary synchronization unit ensures the timing synchronization of the request signal. After the data transfer is completed, the cross-cluster master interface sends a response signal to inform the cross-cluster slave interface that the data transfer has ended, and the response signal must be synchronized by the secondary synchronization unit. To efficiently process burst transfer data, the system is designed with a write data FIFO and a read data FIFO to store write data and read data, respectively, to avoid conflicts between read and write operations. The write operation and the read operation are performed independently, but through the exchange of data in the FIFO queue, the synchronization of data transfer is ensured.

[0060] As a preferred scheme of the present application, the remapping address includes a first remapping address and a second remapping address, the first remapping address is the address of the first slave interface of the AHB2AHB bridge, and the first remapping address is the same as the address space of the computing processor cluster, and the second remapping address is the address of the second slave interface of the AHB2AHB bridge, and the second remapping address is the same as the address space of the communication processor cluster.

[0061] It can be understood that, as shown in Figure 2 To achieve cross-cluster data access, the embodiment implements unified address mapping of the whole chip through the address remapping mechanism of the AHB2AHB bridge, that is, the address of the slave of the AHB2AHB of the computing subsystem is mapped to the address of the communication peripheral cluster, and the address of the AHB2AHB of the communication subsystem is mapped to the address of the on-chip storage. The command issued by the master interface of the computing subsystem is converted through the slave interface of the AHB2AHB bridge into a command recognizable by the master interface of the communication subsystem, realizing the access of the master of the computing subsystem to the slave of the communication subsystem. Conversely, when the master in the communication subsystem accesses the slave in the computing subsystem, the same mapping and conversion mechanism is used, that is, after address remapping, the communication processor cluster can be regarded as a slave of the computing processor cluster, and vice versa, the computing processor cluster can be regarded as a slave of the communication processor cluster. In this way, through this address remapping, the system can realize efficient data interaction between the two subsystems.

[0062] As a preferred scheme of the present application, it also includes:

[0063] When any slave in the communication processor cluster and the computing processor cluster is accessed by multiple first hosts simultaneously, a preset arbitration module outputs multiple control signals based on access request information of each first host, the access request information including priority and timing of the access request, one control signal corresponding to one first host;

[0064] Access control of the multiple first hosts is performed based on the multiple control signals, the control signals including a first control signal and at least one second control signal, the first control signal being used to instruct the first host to access the slave, and the second control signal being used to instruct the first host to wait.

[0065] It can be understood that, since the cross-cluster access and the crossbar structure within the cluster both support parallel communication between multiple hosts and slaves, multiple hosts can simultaneously initiate access requests to the same slave, which, if not handled properly, can cause data transmission errors, access conflicts, and system operation abnormalities, etc. Figure 3 As shown in FIG. 1, in the case of multiple hosts of the crossbar interconnection bus accessing the same slave, it is necessary to ensure that only one host can access the slave at any time. This process is managed by an arbitration unit, and its core task is to determine which host can obtain access permission according to factors such as priority and timing of the access request, so as to avoid multiple hosts accessing the same resource simultaneously. The arbitration mechanism can take a priority-based or polling-based approach depending on the application scenario.

[0066] In the arbitration process, the crossbar will only allow the request of one host to pass according to the control signal of the arbitration unit, while other hosts need to wait until the current host completes the access and releases the resource. In this way, the same slave can be prevented from being accessed by multiple hosts at the same time, further improving the reliability of cross-cluster data interaction.

[0067] The above only describes preferred embodiments of the present application and is not intended to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

[0068] The above only describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the present application, which shall be included in the protection scope of the present application.

Claims

1. A cross-cluster high-reliability data interaction method based on an inter-core loosely coupled architecture, characterized in that, The method comprises the following steps: Implementing data intercommunication between a computing processor cluster and a communication processor cluster based on an AHB2AHB bridge, the interconnection structure within the computing processor cluster and the communication processor cluster being implemented based on a crossbar switch of AHB protocol; Allocating address spaces of the computing processor cluster and the communication processor cluster, obtaining the address spaces of the computing processor cluster and the communication processor cluster, and the address spaces of the computing processor cluster and the communication processor cluster not containing overlapping address spaces; When cross-cluster data access is performed based on the AHB2AHB bridge, the AHB2AHB bridge performs address remapping based on the address spaces of the computing processor cluster and the communication processor cluster, obtaining remapping addresses; Performing data interaction between the computing processor cluster and the communication processor cluster based on the remapping addresses.

2. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 1, characterized in that, The starting address of the address space of the computing processor cluster is 0.

3. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 1, characterized in that After the address spaces of the computing processor cluster and the communication processor cluster are allocated, the method further comprises the following steps: Taking the on-chip unallocated address space as a reserved area, obtaining the reserved area, and the reserved area being invalid when accessed by a host of the computing processor cluster or the communication processor cluster.

4. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 1, characterized in that, The method further comprises the following steps: When any slave of the communication processor cluster and the computing processor cluster is simultaneously accessed by a plurality of first hosts, a preset arbitration module outputs a plurality of control signals based on access request information of each first host, the access request information including priority and timing of the access request, and one control signal corresponding to one first host; Performing access control of the plurality of first hosts based on the plurality of control signals, the control signals including a first control signal and at least one second control signal, the first control signal being used for instructing the first host to access the slave, and the second control signal being used for instructing the first host to wait.

5. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 1, characterized in that The step of implementing data intercommunication between the computing processor cluster and the communication processor cluster based on the AHB2AHB bridge comprises the following steps: When a first command of the computing processor cluster is received by a first slave interface of the AHB2AHB bridge, the AHB2AHB bridge transmits the first command to a host interface of the communication processor cluster through a first host interface; When a second command of the communication processor cluster is received by a second slave interface of the AHB2AHB bridge, the AHB2AHB bridge transmits the second command to the host interface of the communication processor cluster through a second host interface.

6. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 5, characterized in that The remapping addresses include a first remapping address and a second remapping address, the first remapping address being an address of the first slave interface of the AHB2AHB bridge, and the first remapping address being the same as the address space of the computing processor cluster, and the second remapping address being an address of the second slave interface of the AHB2AHB bridge, and the second remapping address being the same as the address space of the communication processor cluster.

7. The cross-cluster high-reliability data interaction method based on the inter-core loosely coupled architecture according to claim 5, characterized in that After the step of implementing data intercommunication between the computing processor cluster and the communication processor cluster based on the AHB2AHB bridge, the method further comprises the following steps: The first slave interface or the second slave interface of the AHB2AHB bridge performs synchronization processing on the third control signal based on a secondary synchronization unit of the AHB2AHB bridge after receiving the third control signal, to obtain a synchronized third control signal, the third control signal being a transmission control signal output by the computing processor cluster or the communication processor cluster, and the synchronized signal being used to start data transmission between the computing processor cluster and the communication processor cluster in a preset clock domain.

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