Equivalent resistance calculation method, calculation equipment and computer readable storage medium

Abstract

The invention discloses an equivalent resistance calculation method, an equivalent resistance calculation device and a computer readable storage medium. The equivalent resistance calculation method comprises the steps of obtaining a minimum resistance path from a power supply pin of a target unit circuit to a nearest power supply bump; determining a target circuit region in the power network based on the minimum resistance path; and calculating the equivalent resistance from the power supply pin of the target unit circuit to all the power supply bumps according to the target circuit region. Thus, the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump is obtained, and then the equivalent resistance from the power supply pin of the target unit circuit to all the power supply bumps is calculated based on the target circuit region in the power supply network determined by the minimum resistance path, so that the time required for calculation is greatly reduced, and the calculation efficiency is improved. And the calculation efficiency of the equivalent resistance of the power supply pin of the unit circuit is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to an equivalent resistance calculation method, computing device, and computer-readable storage medium. Background Technology

[0002] In power integrity analysis, assessing the robustness of a power network is crucial, particularly ensuring that each unit circuit of the power network receives a stable and sufficient supply voltage. One common technique is to calculate the equivalent resistance from the power pins of a unit circuit to all power bumps to check the robustness of the power network. However, this method requires global power network information, resulting in long calculation times and low computational efficiency. Summary of the Invention

[0003] The purpose of this application is to provide an equivalent resistance calculation method, a computing device, and a computer-readable storage medium to at least solve the problems in the related art.

[0004] To achieve the above objectives: In a first aspect, embodiments of this application provide a method for calculating equivalent resistance, the method comprising: Find the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump; The target circuit region in the power network is determined based on the minimum resistance path. Calculate the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the target circuit region.

[0005] In one embodiment, obtaining the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump includes: Parasitic parameters are extracted from the power network to obtain the resistance between the power pins of the target unit circuit and each power bump in the power network. Construct a mapping network with power pins and power bumps as nodes and resistors as weights of edges; Based on the mapping network, the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump is found. In one embodiment, determining the target circuit region in the power network based on the minimum resistance path includes: Obtain the maximum and minimum coordinate values ​​of the minimum resistance path in the first coordinate axis direction and the second coordinate axis direction in the preset coordinate system, respectively; The target circuit region in the power network is determined based on the maximum and minimum coordinate values.

[0006] In one embodiment, determining the target circuit region in the power network based on the maximum coordinate value and the minimum coordinate value includes: Obtain the rectangular region surrounding the path of minimum resistance, determined by the maximum and minimum coordinate values; The target circuit region in the power network is determined based on the rectangular region.

[0007] In one embodiment, determining the target circuit region in the power network based on the rectangular region includes: The rectangular region is defined as the target circuit region in the power network.

[0008] In one embodiment, determining the target circuit region in the power network based on the rectangular region includes: At least one side of the rectangular region is expanded outward, and the corresponding area is determined as the target circuit region in the power network.

[0009] In one embodiment, expanding at least one side of the rectangular region to determine the corresponding area as the target circuit region in the power network includes: The rectangular area is expanded by a preset multiple, and the expanded area is used as the target circuit area.

[0010] In one embodiment, calculating the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the target circuit region includes: A test outflow current is applied to the components, power bumps, and power pins of the target unit circuit within the target circuit area; Solve the linear equations constructed based on the target circuit region to obtain the voltages corresponding to the power supply pins of the target unit circuit; Calculate the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the voltage and the test outflow current.

[0011] Secondly, embodiments of this application provide a computing device, including: a processor and a memory storing a computer program, wherein when the processor runs the computer program, the equivalent resistance calculation method described in the first aspect is implemented.

[0012] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the equivalent resistance calculation method described in the first aspect.

[0013] The equivalent resistance calculation method, computing device, and computer-readable storage medium provided in this application obtain the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump, and then calculate the equivalent resistance from the power supply pin of the target unit circuit to all power supply bumps based on the target circuit region in the power network determined by the minimum resistance path. This eliminates the need for calculation based on the global power network, greatly reducing the calculation time and improving the calculation efficiency of the equivalent resistance of the power supply pin of the unit circuit. Attached Figure Description

[0014] Figure 1 This is a flowchart illustrating the equivalent resistance calculation method provided in an embodiment of this application.

[0015] Figure 2 This is a schematic diagram of the region in an embodiment of this application.

[0016] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0017] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0018] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0019] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0020] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0021] It should be noted that step designations such as S101 and S102 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S102 first and then S101, etc., but these should all be within the protection scope of this application.

[0022] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0023] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0024] See Figure 1 This application provides an equivalent resistance calculation method, which can be executed by an equivalent resistance calculation device provided in this application. The equivalent resistance calculation device can be implemented in software and / or hardware, such as a computer, server, or other computing device. The equivalent resistance calculation method provided in this embodiment includes: Step S101: Obtain the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump.

[0025] In this context, the target cell circuit refers to the cell circuit in the power network whose equivalent resistance is to be calculated. The nearest power bump is the power bump with the shortest distance to the power pin of the target cell circuit. The minimum resistance path is the path with the lowest resistance; there may be multiple paths from the power pin of the target cell circuit to the nearest power bump, and the resistance of each path may be different.

[0026] In one embodiment, obtaining the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump includes: Parasitic parameters are extracted from the power network to obtain the resistance between the power pins of the target unit circuit and each power bump in the power network. Construct a mapping network with power pins and power bumps as nodes and resistors as weights of edges; The mapping network is used to find the minimum resistance path from the power supply pin of the target cell circuit to the nearest power supply bump.

[0027] Parasitic parameters include electrical characteristics such as resistance and capacitance between conductors in the power network. In this embodiment, parasitic parameter extraction tools (such as Cadence QRC, Synopsys StarRC, GloryBolt / EX, etc.) can be used to extract parasitic parameters from the power network. After extracting the parasitic parameters, the power network can be represented as a large-scale resistance network, which includes all metal layers, vias, power bumps, and the interconnection resistance values ​​between them. Therefore, by extracting parasitic parameters from the power network, the resistance between the power pins and power bumps of the target unit circuit in the power network can be obtained. Knowing the resistance between the power pins and power bumps of the target unit circuit, a mapping network can be constructed with power pins and power bumps as nodes and resistances as edge weights. This mapping network can be represented in the form of a graph, etc.

[0028] Among them, based on the mapping network, point-to-point shortest path algorithms such as Dijkstra's algorithm and A-Star algorithm can be used to find the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump, starting from the power supply pin of the target unit circuit.

[0029] In this way, the minimum resistance path from the power supply pin of the unit circuit to the nearest power supply bump can be found quickly and accurately, further reducing the calculation time required and further improving the calculation efficiency of the equivalent resistance of the power supply pin of the unit circuit.

[0030] Step S102: Determine the target circuit region in the power network based on the path of minimum resistance.

[0031] Specifically, by determining the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump, the part of the power supply network most relevant to the power supply pin of the target unit circuit can be identified, i.e., the target circuit region in the power supply network, also known as the lead-in region. The target circuit region can be the area covered by the minimum resistance path in the power supply network, or it can be an area that is appropriately expanded from the area covered by the minimum resistance path.

[0032] In one embodiment, determining the target circuit region in the power network based on the minimum resistance path includes: Obtain the coordinates of the maximum and minimum values ​​of the path with the minimum resistance in the first coordinate axis direction of the preset coordinate system, and the coordinates of the maximum and minimum values ​​of the path with the minimum resistance in the second coordinate axis direction. The target circuit region in the power network is determined based on the coordinate points corresponding to the maximum and minimum values, respectively.

[0033] Since the path can be considered as being composed of multiple points, and each point has corresponding coordinate values ​​in a preset coordinate system, the coordinates of each point forming the path of minimum resistance can be determined based on the maximum and minimum values ​​along the first and second coordinate axes in the preset coordinate system, as well as the coordinates of the maximum and minimum values ​​along the second coordinate axis. Here, the preset coordinate system can specifically be a two-dimensional planar coordinate system, etc.

[0034] Since the shape of the resistance path is usually not a straight line, but a curve composed of multiple line segments, after obtaining the coordinate points corresponding to the maximum and minimum values ​​of the minimum resistance path in the first coordinate axis direction and the second coordinate axis direction, respectively, the distribution of the minimum resistance path can be known, and then the target circuit area in the power network can be determined based on the coordinate points corresponding to the maximum and minimum values.

[0035] In one embodiment, determining the target circuit region in the power network based on the coordinate points corresponding to the maximum and minimum values ​​respectively includes: Obtain the rectangular region enclosing the path of minimum resistance, determined by the coordinates corresponding to the maximum and minimum values, respectively. The target circuit region in the power network is determined based on the rectangular region.

[0036] In this system, multiple coordinate points can be determined in the power network based on the coordinate points corresponding to the maximum and minimum values ​​along the first and second coordinate axes of the minimum resistance path in a preset coordinate system. Since the minimum resistance path is a curve composed of multiple line segments, the coordinate points corresponding to the maximum and minimum values ​​can be considered as vertices of a rectangle. Therefore, based on the coordinate points corresponding to the maximum and minimum values, a rectangular region enclosing the minimum resistance path can be determined. This rectangular region is the area that passes through or includes the coordinate points corresponding to the maximum and minimum values.

[0037] In one embodiment, determining the target circuit region in the power network based on the rectangular region includes: The rectangular region is defined as the target circuit region in the power network.

[0038] Specifically, the rectangular region enclosing the path of minimum resistance, determined by the coordinate points corresponding to the maximum and minimum values, can be directly defined as the target circuit region in the power supply network. For example, assuming the coordinate points corresponding to the maximum and minimum values ​​of the path of minimum resistance in the first coordinate axis direction of a preset coordinate system are A and B, and the coordinate points corresponding to the maximum and minimum values ​​in the second coordinate axis direction are C and D, then the rectangular region composed of A, B, C, and D can be defined as the target circuit region in the power supply network.

[0039] In one embodiment, determining the target circuit region in the power network based on the rectangular region includes: Expand at least one side of the rectangular region to determine the corresponding area as the target circuit region in the power network.

[0040] To improve the accuracy of equivalent resistance calculation, at least one side of the rectangular region can be expanded outwards, i.e., the area of ​​the rectangular region can be increased. The expanded region is then determined as the target circuit region in the power supply network. For example, assuming the rectangular region is rectangle ABCD, and AB and CD are opposite sides of the rectangle, side AB can be shifted 5 cm away from side CD to determine the newly obtained region as the target circuit region in the power supply network.

[0041] In one embodiment, at least one side of the rectangular region is expanded outward to determine the corresponding area as the target circuit region in the power network, including: The rectangular area is expanded by a preset multiple, and the expanded area is used as the target circuit area.

[0042] The preset multiplier can be set according to actual needs, such as 0.2 or 0.5 times. By expanding the rectangular area according to the preset multiplier, and using the expanded area as the target circuit area, the information contained in the target circuit area can be increased, thereby improving the calculation accuracy.

[0043] Step S103: Calculate the equivalent resistance from the power supply pins of the target unit circuit to all power supply bumps based on the target circuit region.

[0044] Specifically, a test outflow current is applied to the components, power bumps, and power pins of the target unit circuit within the target circuit region; the linear equation constructed based on the target circuit region is solved to obtain the voltage of the power pin of the target unit circuit; and the equivalent resistance from the power pin of the target unit circuit to all power bumps is calculated based on the voltage and the test outflow current.

[0045] The target circuit region can be represented as a linear resistor network, allowing the construction of linear equations based on this region. By solving these equations, the voltages of the components and power bumps within the target circuit region can be obtained. Based on these voltages, the voltages of the power pins of the target unit circuit can be calculated. Furthermore, using Ohm's law, the equivalent resistance from the power pins of the target unit circuit to all power bumps can be calculated based on the voltages of the power pins and the measured outflow current.

[0046] Here, the calculated equivalent resistance can also be compared with design standards. For example, if the equivalent resistance is too high, it may indicate that some parts of the power network have high resistance, or that the power distribution is uneven in some areas. Furthermore, when the equivalent resistance value is too high, it may be necessary to re-optimize the power network. For example, the equivalent resistance from the power pins to the power bumps can be reduced by adding more metal layers or optimizing the placement of power blocks.

[0047] In summary, the equivalent resistance calculation method provided in the above embodiments obtains the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump, and then calculates the equivalent resistance from the power supply pin of the target unit circuit to all power supply bumps based on the target circuit region in the power network determined by the minimum resistance path. This eliminates the need for calculation based on the global power network, greatly reducing the calculation time and improving the calculation efficiency of the equivalent resistance of the power supply pin of the unit circuit.

[0048] The equivalent resistance calculation method provided in this embodiment will be illustrated below with a specific example. In this example, a clock buffer cell in a selected chip is used as the target cell circuit to calculate its equivalent resistance. The position of this cell can be represented as two-dimensional coordinates (156.85u, 251.35u).

[0049] First, parasitic parameters are extracted from the power network using a parasitic parameter extraction tool to obtain the circuit netlist. Parasitic parameters mainly include the electrical characteristics such as resistance and capacitance between conductors in the power network.

[0050] Next, a graph is created based on the circuit netlist, where the nodes represent the power pins and bumps of the cell, and the edge weights represent the extracted resistance values. Then, using Dijkstra's algorithm or similar methods, the minimum resistance path to each power bump is found, starting from the power pin of the cell.

[0051] Then, based on the shapes of all the metal wires in the path of minimum resistance, the converging rectangular region is determined, such as... Figure 2 The solid-line box in the image is shown. Then, based on the user's settings, the buffer area is increased by 20% to expand the rectangular area to ((112.680, 221.070)(157.462, 251.393)), and the resulting area is used as the import area, as shown below. Figure 2 As shown in the dashed box in the image.

[0052] Next, apply a test outflow current source, typically 1A, to the components, resistors, power blocks of the power network within the input region ((112.680, 221.070)(157.462, 251.393)) and to the power pins of that unit.

[0053] Finally, the equivalent resistance is calculated. For the sub-circuit corresponding to the input region, a linear equation is constructed, and then the linear square matrix R*I=V is solved. This yields the voltage value V(n) of all nodes in the sub-circuit. After obtaining the voltage V(pin) of the power supply pin of the unit circuit, Ohm's law, R=V(pin) / I, is used to calculate the equivalent resistance from the power supply pin to all power supply bumps of the unit circuit.

[0054] In summary, by employing lightweight graph-based computation, prioritizing the calculation of the minimum resistance path from the power supply pins to the power supply bumps of the unit circuit guides the introduction region of the power network, thereby inspiring the minimum computational region for the equivalent resistance. In this way, by identifying critical resistance paths and constructing the circuit model only within these path ranges, the size of the global power mesh is significantly reduced, thus avoiding the need to solve matrices with hundreds of billions of nodes in large-scale digital chips. This improves the computational efficiency of the equivalent resistance corresponding to the power supply pins of the unit circuit. Based on the same inventive concept as the foregoing embodiments, this embodiment of the invention provides a computing device, such as... Figure 3 As shown, the computing device includes: a processor 310 and a memory 311 storing computer programs; wherein, Figure 3 The processor 310 shown in the diagram does not indicate that there is only one processor 310, but only indicates the positional relationship of the processor 310 relative to other devices. In practical applications, there can be one or more processors 310; similarly, Figure 3 The memory 311 shown in the diagram has the same meaning, that is, it is only used to indicate the positional relationship of memory 311 relative to other devices. In practical applications, there can be one or more memories 311. When the processor 310 runs the computer program, it implements the equivalent resistance calculation method applied to the above-mentioned computing device.

[0055] The computing device may also include at least one network interface 312. Various components in the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to implement communication between these components. In addition to a data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 3 The general designated all buses as Bus System 313.

[0056] The memory 311 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); magnetic surface memory can be disk storage or magnetic tape storage. Volatile memory can be random access memory (RAM), used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0057] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a computer-readable storage medium storing a computer program. The computer-readable storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc. When the computer program stored in the computer-readable storage medium is run by a processor, it implements the above-described equivalent resistance calculation method. For the specific steps implemented when the computer program is executed by the processor, please refer to [link to relevant documentation]. Figure 1 The description of the illustrated embodiments will not be repeated here.

[0058] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0059] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0060] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for calculating equivalent resistance, characterized in that, The method includes: Find the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump; The target circuit region in the power network is determined based on the minimum resistance path. Calculate the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the target circuit region.

2. The method according to claim 1, characterized in that, The step of obtaining the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump includes: Parasitic parameters are extracted from the power network to obtain the resistance between the power pins of the target unit circuit and each power bump in the power network. Construct a mapping network with power pins and power bumps as nodes and resistors as weights of edges; Based on the mapping network, the minimum resistance path from the power supply pin of the target unit circuit to the nearest power supply bump is found.

3. The method according to claim 1 or 2, characterized in that, Determining the target circuit region in the power network based on the minimum resistance path includes: Obtain the coordinates of the maximum and minimum values ​​of the minimum resistance path in the first coordinate axis direction of the preset coordinate system, and the coordinates of the maximum and minimum values ​​in the second coordinate axis direction. The target circuit region in the power network is determined based on the coordinate points corresponding to the maximum and minimum values, respectively.

4. The method according to claim 3, characterized in that, Determining the target circuit region in the power network based on the coordinate points corresponding to the maximum and minimum values ​​respectively includes: Obtain the rectangular region enclosing the path of minimum resistance, determined by the coordinate points corresponding to the maximum and minimum values, respectively; The target circuit region in the power network is determined based on the rectangular region.

5. The method according to claim 4, characterized in that, Determining the target circuit region in the power network based on the rectangular region includes: The rectangular region is defined as the target circuit region in the power network.

6. The method according to claim 4, characterized in that, Determining the target circuit region in the power network based on the rectangular region includes: At least one side of the rectangular region is expanded outward, and the corresponding area is determined as the target circuit region in the power network.

7. The method according to claim 6, characterized in that, The step of expanding at least one side of the rectangular region to determine the corresponding area as the target circuit region in the power network includes: The rectangular area is expanded by a preset multiple, and the expanded area is used as the target circuit area.

8. The method according to claim 1, characterized in that, The step of calculating the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the target circuit region includes: A test outflow current is applied to the components, power bumps, and power pins of the target unit circuit within the target circuit area; Solve the linear equations constructed based on the target circuit region to obtain the voltages corresponding to the power supply pins of the target unit circuit; Calculate the equivalent resistance from the power supply pins to all power supply bumps of the target unit circuit based on the voltage and the test outflow current.

9. A computing device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the equivalent resistance calculation method as described in any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program that, when executed by a processor, implements the equivalent resistance calculation method as described in any one of claims 1 to 8.

Images