Chip simulation method and device, electronic equipment, storage medium and program product

Abstract

This disclosure provides a chip simulation method and apparatus, electronic device, storage medium, and program product, relating to the field of chip technology, specifically to the field of chip simulation technology. The method includes: determining an initial simulation test case set corresponding to the chip under test; determining functional block description information corresponding to the simulation test cases in the initial simulation test case set; wherein the functional block description information at least indicates the functional blocks used to run the simulation test cases, and the functional blocks are obtained based on the functional and / or physical distribution of components on the chip under test; deduplicating simulation test cases with overlapping functional block description information in the initial simulation test case set to obtain a simplified simulation test case set; and performing simulation verification on the chip under test based on the simplified simulation test cases in the simplified simulation test case set. This solution can significantly improve chip simulation efficiency, thereby helping to shorten the chip design cycle and reduce chip design costs.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, specifically to the field of chip simulation technology, and in particular to a chip simulation method and apparatus, electronic device, storage medium, and program product. Background Technology

[0002] Simulation verification is a crucial step in chip design and development. Currently, for small-scale chips, all simulation verification work can be completed within the chip design cycle. However, for ultra-large-scale chip scenarios, the speed required to complete the vast majority of simulation verifications is far slower than the pace of chip design, resulting in low simulation efficiency and impacting chip design progress. Therefore, effectively improving chip simulation efficiency has become an urgent technical challenge. Summary of the Invention

[0003] This disclosure provides a chip emulation method, a chip emulation device, an electronic device, a computer-readable storage medium, and a computer program product.

[0004] In a first aspect, embodiments of this disclosure propose a chip simulation method, comprising: determining an initial simulation test case set corresponding to the chip under test; determining functional block description information corresponding to the simulation test cases in the initial simulation test case set; wherein the functional block description information is at least used to indicate the functional blocks used to run the simulation test cases, and the functional blocks are obtained based on the components on the chip under test according to functional distribution and / or physical distribution; performing deduplication processing on the simulation test cases with overlapping functional block description information in the initial simulation test case set to obtain a simplified simulation test case set; and performing simulation verification on the chip under test based on the simplified simulation test cases in the simplified simulation test case set.

[0005] In some optional implementations of the embodiments of this disclosure, the simulation cases with overlapping function block description information in the initial simulation case set are deduplicated to obtain a simplified simulation case set, including: determining multiple first simulation cases from the initial simulation case set based on the function block description information, wherein the multiple first simulation cases have the same function block description information; and deduplicating the multiple first simulation cases to obtain a simplified simulation case set.

[0006] In some optional implementations of the embodiments of this disclosure, the above-mentioned function block description information is further used to indicate the runtime sequence corresponding to the function block used by the simulation test case; wherein, the above-mentioned deduplication processing of multiple first simulation test cases to obtain a simplified simulation test case set includes: selecting multiple second simulation test cases with the same runtime sequence from multiple first simulation test cases; and deduplicating multiple second simulation test cases to obtain a simplified simulation test case set.

[0007] In some optional implementations of the embodiments of this disclosure, the aforementioned function block description information is further used to indicate the load parameters corresponding to the function blocks used in running the simulation test cases; and the aforementioned deduplication processing of simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set includes: for the simulation test cases in the initial simulation test case set, determining a matrix for indicating the usage of function blocks in each simulation test case based on the function block description information corresponding to each simulation test case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; and deduplicating simulation test cases with overlapping elements in the matrix in the initial simulation test case set to obtain a simplified simulation test case set.

[0008] In some optional implementations of the embodiments of this disclosure, the above-mentioned deduplication of simulation test cases with overlapping elements in the matrix of the initial simulation test case set to obtain a simplified simulation test case set includes: dividing the matrix corresponding to each simulation test case in the initial simulation test case set into at least one sub-matrix according to at least one module under test associated with each simulation test case of the chip under test, wherein the functional blocks are divided according to the functional distribution of the components on the module under test of the chip under test; comparing two different simulation test cases with the elements in the sub-matrix corresponding to the same module under test, and deduplicating the sub-matrixes with the same elements.

[0009] In some optional implementations of the embodiments of this disclosure, the chip simulation method may further include: classifying the simulation cases in the initial simulation case set according to the simulation type to obtain an initial simulation case set corresponding to the simulation type; wherein the simulation type includes at least one of testability design simulation, functional design simulation, and low-power design simulation; and performing deduplication processing on the simulation cases in the initial simulation case set where the elements of the matrix overlap to obtain a simplified simulation case set, including: performing deduplication processing on the simulation cases where the elements of the matrix overlap within the initial simulation case set of the same simulation type and between the initial simulation case sets of different simulation types.

[0010] In some optional implementations of the embodiments of this disclosure, the above-mentioned simulation verification of the chip under test based on the simplified simulation test cases in the simplified simulation test case set includes: determining the test load corresponding to each simplified simulation test case based on the module under test associated with each simplified simulation test case of the chip under test; selecting candidate simulation test cases whose test load is greater than a first load threshold from the simplified simulation test case set based on the test load corresponding to each simplified simulation test case; determining the target module under test in the chip under test for re-partitioning the functional blocks based on the selected candidate simulation test cases; and performing simulation verification of the chip under test based on the result of re-partitioning the functional blocks of the target module under test; wherein the test load of the simulation test cases determined based on the result of re-partitioning the functional blocks of the target module under test is less than or equal to the first load threshold.

[0011] In some optional implementations of the embodiments of this disclosure, the above-mentioned function block description information is further used to indicate the load parameters corresponding to the function blocks used to run the simulation test cases; and the above-mentioned determination of the test load corresponding to each simplified simulation test case based on the test module associated with each simplified simulation test case of the chip under test includes: determining the test load corresponding to each simplified simulation test case based on the load parameters corresponding to the function blocks used to run each simplified simulation test case in the test module.

[0012] In some optional implementations of the embodiments of this disclosure, the above-mentioned determination of the target module under test for re-division of the chip under test based on the selected candidate simulation test cases includes: determining the test load corresponding to the module under test associated with the candidate simulation test cases based on the load parameters of the function blocks used to run the candidate simulation test cases in the module under test associated with the candidate simulation test cases; and determining the module under test associated with the candidate simulation test cases whose test load is greater than the second load threshold as the target module under test.

[0013] In some optional implementations of the embodiments of this disclosure, the above-mentioned load parameters are determined based on at least one of the following: the area ratio of the functional block relative to the chip under test; the number of components contained in the functional block.

[0014] In some optional implementations of the embodiments of this disclosure, the process of re-dividing the target module under test into functional blocks includes: determining the smallest component in the target module under test; based on the smallest component, filtering target components that match the simulation type associated with the target module under test; and re-dividing the target module under test into functional blocks based on the smallest component and the target components.

[0015] In some optional implementations of the embodiments of this disclosure, the above-mentioned simulation verification of the chip under test based on the result of re-dividing the target module under test into functional blocks includes: updating the test load corresponding to the simulation test cases associated with the target module under test based on the result of re-dividing the target module under test into functional blocks; determining the overall test load corresponding to the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test; and using the test resources allocated to the chip under test based on the overall test load to perform simulation verification of the chip under test.

[0016] In some optional implementations of the embodiments of this disclosure, the above-mentioned determination of the overall test load corresponding to the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test includes: determining the category test load corresponding to the simulation type associated with the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test and the simulation type to which the simulation test cases belong; and determining the overall test load based on the category test load corresponding to the simulation type associated with the chip under test.

[0017] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional block includes one or more of the following: input / output functional block, input boundary register functional block, output boundary register functional block, control functional block, pass-through functional block, internal logic functional block, and low-power functional block.

[0018] Secondly, embodiments of this disclosure propose a chip simulation apparatus, comprising: a simulation test case set determination unit, a description information determination unit, a processing unit, and a simulation unit. The simulation test case set determination unit is configured to determine an initial simulation test case set corresponding to the chip under test; the description information determination unit is configured to determine functional block description information corresponding to the simulation test cases in the initial simulation test case set; wherein the functional block description information at least indicates the functional blocks used to run the simulation test cases, and the functional blocks are obtained based on the functional distribution and / or physical distribution of components on the chip under test; the processing unit is configured to perform deduplication processing on the simulation test cases with overlapping functional block description information in the initial simulation test case set to obtain a simplified simulation test case set; the simulation unit is configured to perform simulation verification on the chip under test based on the simplified simulation test cases in the simplified simulation test case set.

[0019] In some optional implementations of the embodiments of this disclosure, the above-mentioned processing unit may be further configured to: determine a plurality of first simulation cases from the initial simulation case set based on the function block description information, wherein the plurality of first simulation cases have the same function block description information; and perform deduplication processing on the plurality of first simulation cases to obtain a simplified simulation case set.

[0020] In some optional implementations of the embodiments of this disclosure, the above-mentioned function block description information is also used to indicate the runtime sequence corresponding to the function block used to run the simulation test case; wherein, the above-mentioned processing unit can be further configured to: filter out a plurality of second simulation test cases with the same runtime sequence from a plurality of first simulation test cases; perform deduplication processing on the plurality of second simulation test cases to obtain a simplified simulation test case set.

[0021] In some optional implementations of the embodiments of this disclosure, the aforementioned function block description information is further used to indicate the load parameters corresponding to the function blocks used in running the simulation test cases; and the processing unit can be further configured to: for the simulation test cases in the initial simulation test case set, determine a matrix for indicating the usage of function blocks in each simulation test case based on the function block description information corresponding to each simulation test case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; and perform deduplication processing on the simulation test cases in the initial simulation test case set whose elements overlap, to obtain a simplified simulation test case set.

[0022] In some optional implementations of the embodiments of this disclosure, the above-mentioned processing unit may be further configured to: divide the matrix corresponding to each simulation test case in the initial simulation test case set into at least one sub-matrix according to at least one module under test associated with each simulation test case of the chip under test, wherein the functional blocks are obtained by dividing the components on the module under test of the chip under test according to their functional distribution; compare two different simulation test cases with the elements in the sub-matrix corresponding to the same module under test, and remove duplicates from the sub-matrixes with the same elements.

[0023] In some optional implementations of the embodiments of this disclosure, the chip simulation apparatus may further include a classification unit configured to classify simulation cases in the initial simulation case set according to the simulation type, thereby obtaining an initial simulation case set corresponding to the simulation type; wherein the simulation type includes at least one of testability design simulation, functional design simulation, and low-power design simulation; and the processing unit may further be configured to: perform deduplication processing on simulation cases whose matrix elements overlap within the initial simulation case set of the same simulation type and between the initial simulation case sets of different simulation types.

[0024] In some optional implementations of the embodiments of this disclosure, the simulation unit may be further configured to: determine the test load corresponding to each simplified simulation test case based on the module under test associated with each simplified simulation test case of the chip under test; select candidate simulation test cases whose test load is greater than a first load threshold from the set of simplified simulation test cases based on the test load corresponding to each simplified simulation test case; determine the target module under test in the chip under test for re-partitioning the functional blocks based on the selected candidate simulation test cases; and perform simulation verification on the chip under test based on the result of re-partitioning the functional blocks of the target module under test; wherein the test load of the simulation test cases determined based on the result of re-partitioning the functional blocks of the target module under test is less than or equal to the first load threshold.

[0025] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional description information is also used to indicate the load parameters corresponding to the functional blocks used to run the simulation test cases; wherein, the above-mentioned simulation unit can be further configured to: determine the test load corresponding to each simplified simulation test case based on the load parameters corresponding to the functional blocks used to run each simplified simulation test case in the module under test.

[0026] In some optional implementations of the embodiments of this disclosure, the simulation unit may be further configured to: determine the test load corresponding to the module under test associated with the candidate simulation test case based on the load parameters corresponding to the function block used to run the candidate simulation test case in the module under test associated with the candidate simulation test case; and determine the module under test associated with the candidate simulation test case whose test load is greater than the second load threshold as the target module under test.

[0027] In some optional implementations of the embodiments of this disclosure, the above-mentioned load parameters are determined based on at least one of the following: the area ratio of the functional block relative to the chip under test; the number of components contained in the functional block.

[0028] In some optional implementations of the embodiments of this disclosure, the simulation unit may be further configured to: determine the smallest component in the target module under test; based on the smallest component, filter target components that match the simulation type associated with the target module under test; and re-divide the target module under test into functional blocks based on the smallest component and the target components.

[0029] In some optional implementations of the embodiments of this disclosure, the simulation unit may be further configured to: update the test load corresponding to the simulation test cases associated with the target module under test based on the result of re-dividing the target module under test into functional blocks; determine the overall test load corresponding to the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test; and use the test resources allocated to the chip under test based on the overall test load to perform simulation verification on the chip under test.

[0030] In some optional implementations of the embodiments of this disclosure, the simulation unit may be further configured to: determine the classification test load corresponding to the simulation type associated with the chip under test based on the updated test load corresponding to the simulation test case associated with the target module under test and the simulation type to which the simulation test case belongs; and determine the overall test load based on the classification test load corresponding to the simulation type associated with the chip under test.

[0031] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional block includes one or more of the following: input / output functional block, input boundary register functional block, output boundary register functional block, control functional block, pass-through functional block, internal logic functional block, and low-power functional block.

[0032] Thirdly, embodiments of this disclosure provide an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the chip emulation method described in any of the implementations of the first aspect above.

[0033] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer to implement the chip emulation method described in any of the implementations in the first aspect when executed.

[0034] Fifthly, embodiments of this disclosure provide a computer program product including a computer program that, when executed by a processor, can implement the chip emulation method as described in any implementation of the first aspect.

[0035] According to the chip simulation scheme provided in this disclosure, an initial simulation test case set can be determined for the chip under test (DUT), and the function block description information corresponding to each simulation test case, indicating the function block used to run the corresponding simulation test case, can be determined. Furthermore, the function block granularity description information on the DUT can be used to accurately optimize the simulation test cases in the initial simulation test case set, removing redundant simulation test cases to obtain a simplified simulation test case set. Thus, by optimizing the initial configuration or design simulation test cases for the DUT and performing simulation verification based on this simplified simulation test case set, simulation resource consumption can be reduced, thereby significantly improving chip simulation verification efficiency, which in turn helps to shorten the chip design cycle and reduce chip design costs.

[0036] In addition, based on the functional description information of each simulation test case associated with each module under test in the chip under test, the corresponding test load can be determined for different types of functional blocks in each module under test. Furthermore, by evaluating the relationship between the test load corresponding to each type of functional block and the pre-set load threshold, it can be determined whether the module under test needs to be divided into smaller granular functional blocks. This allows for further optimization of the simulation load by optimizing the combination of circuits used for simulation verification, thereby further improving simulation efficiency.

[0037] Classifying the initial simulation test case set corresponding to the chip under test based on simulation type can improve the flexibility to apply different simulation requirements.

[0038] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0039] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0040] Figure 1 This is a schematic diagram of the module division of a chip provided in an embodiment of this disclosure;

[0041] Figure 2 This invention provides an exemplary application scenario diagram for embodiments of the present disclosure.

[0042] Figure 3 A flowchart of a chip simulation method provided in this disclosure embodiment;

[0043] Figure 4 A flowchart of another chip simulation method provided in this disclosure embodiment;

[0044] Figure 5 This is a schematic diagram illustrating the functional block division of any module under test in a chip in an application scenario, as provided by an embodiment of this disclosure.

[0045] Figure 6 A schematic diagram illustrating the functional block subdivision of a module under test in a chip, provided for embodiments of this disclosure;

[0046] Figure 7 In order to be in Figure 6 A retained schematic diagram of the functional blocks used for simulation, implemented based on the above.

[0047] Figure 8 A structural block diagram of a chip emulation device provided in this disclosure embodiment;

[0048] Figure 9 This is a schematic diagram of the structure of an electronic device suitable for performing a chip emulation method, provided as an embodiment of the present disclosure. Detailed Implementation

[0049] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0050] In the chip development and design process, chips are generally divided into functional design and design-testable (DTM) components. Functional design describes the various performance characteristics the chip can support and implement, while DTM verifies and locates functional and manufacturing defects. Simulation verification is a crucial step in this process. Currently, when chips are small-scale, all simulation verification work can be completed within the chip design cycle. However, for very large-scale and 3D / 2.5D integrated circuit scenarios, the speed required to complete the vast majority of simulation verifications is far slower than the pace of chip design, resulting in low simulation efficiency. This impacts the chip design schedule and, consequently, the chip's timeline to market.

[0051] Different simulation schemes can be used for functional design verification and design-testable verification. Due to the different methodologies of functional design and design-testable verification, related technologies generally handle simulation verification for each separately. Specifically, different methods can be used to improve simulation efficiency during verification. For example, the multi-threading capabilities of the simulation tool itself can be used for speed-up, hardware acceleration methods can be applied for optimization, or the chip can be divided into different modules or regions for block testing. However, these methods typically have the following problems:

[0052] (1) Using the multi-threading of Electronic Design Automation (EDA) tools and their own logic to speed up simulation increases the consumption of simulation resources. Furthermore, multi-threaded verification of a large number of parallel designs cannot meet the actual chip design requirements. At the same time, it requires a large number of tool licenses and server resources, resulting in high costs.

[0053] (2) Using hardware acceleration also faces the problem of limited hardware acceleration resources, cannot perform full chip compilation, cannot meet the simulation verification needs of a large number of different functions, and is also more expensive.

[0054] (3) By dividing the chip into different modules or regions, unnecessary modules can be removed during simulation, such as... Figure 1 As shown, the chip can be divided into module 1, module 2, module 3, module 4, etc. (for example, according to the actual implementation in the chip design). During simulation, the circuits in the module under test (i.e., the circuits under test, such as...) can be retained. Figure 1 Module 1 shown), and other unnecessary modules (such as Figure 1 The circuits in modules 2-4 shown are replaced with extracted circuits (also known as cut-out circuits). However, as the integration density of chip design increases, there will be many related logics between the modules of the chip. The number of modules after division is still large, and the improvement in simulation efficiency is limited.

[0055] Therefore, how to effectively improve chip simulation efficiency has become an urgent technical problem to be solved.

[0056] Figure 2 This diagram illustrates an exemplary application scenario for an embodiment of this disclosure. For example... Figure 2The application scenarios illustrated may include a simulation device 201 and a simulation platform 202 communicatively coupled to the simulation device 201. The simulation platform 202 can be configured to execute various simulation processes for a chip; for example, it can be configured to execute a chip simulation method according to embodiments of this disclosure. By executing the chip simulation method of embodiments of this disclosure, simulation can be accelerated based on functional information in the chip, thereby improving chip simulation efficiency and thus helping to shorten the chip design cycle.

[0057] The simulation device 201 may include at least one or more processors for processing data and one or more memories for storing data. The simulation platform 202 may include a chip component 203 for simulation within the platform. Exemplarily, the chip component 203 may be a virtual component built within the simulation platform 202 or a real component outside the simulation platform 202, which may be mapped to the simulation platform 202 through some form of virtualization. The chip component 203 may include any type of semiconductor device used for chip simulation and may be implemented in hardware, software, firmware, or a combination thereof, for example, as a physical semiconductor device or apparatus, or as a virtual component on the software platform 202, etc. Furthermore, the above application scenario may also include a backend device 204 communicatively coupled to the simulation device 201 for, for example, receiving port data and / or providing data about module timing information. Exemplarily, the backend device 204 may be a manually controlled terminal or server and may have a configuration similar to that of the simulation device 201.

[0058] Figure 2 The application scenario described herein is merely one example of implementing the embodiments of this disclosure and is not restrictive. The simulation device 201 and / or the backend device 204 can be a terminal or server, or other device capable of performing simulation. When the simulation device 201 and / or the backend device 204 is a terminal, it can be a tablet computer, a laptop computer, a desktop computer, etc., without limitation. When the simulation device 201 and / or the backend device 204 is a server, it can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, and can also be a cloud server providing basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0059] Please refer to Figure 3 , Figure 3 This is a flowchart illustrating a chip simulation method provided in this disclosure, which can be applied to the above-described embodiments. Figure 2In the application scenario described in the corresponding embodiment, process 300 includes the following steps:

[0060] Step 301: Determine the initial simulation test case set corresponding to the chip under test.

[0061] This step aims to collect and confirm the simulation test cases (such as the simulation test cases currently to be simulated) involved in the chip under test to be simulated and verified, that is, to determine the initial simulation test case set corresponding to the chip under test. This initial simulation test case set may include multiple simulation test cases. The simulation test cases are standardized test cases or test sets for chip verification designs. Their core function is to verify the conformity and robustness of specific functional blocks in the chip under test by simulating signal input, timing relationships, and load conditions in real-world scenarios. In the embodiments of this disclosure, the specific data structure form of the simulation test cases is not limited.

[0062] Furthermore, in the embodiments of this disclosure, the number of simulation test cases in the initial simulation test case set is not limited, and is set according to actual needs. The chip under test can be any type of semiconductor device used for simulation, and can be used in fields such as consumer electronics, communication systems, photovoltaic power generation, lighting, and high-power power conversion. The chip under test can be implemented in hardware, software, firmware, or a combination thereof. For example, it can be used as a physical semiconductor device or apparatus, or as a virtual component on a software platform, etc.

[0063] Step 302: Determine the function block description information corresponding to the simulation cases in the initial simulation case set.

[0064] The function block description information is used to indicate at least the function blocks used to run the simulation test case. The function blocks are divided based on the components on the chip under test according to their functional distribution and / or physical distribution.

[0065] In this embodiment of the disclosure, based on the collected and confirmed initial simulation test case set, the corresponding functional block description information can be determined for each simulation test case in the initial simulation test case set. In some optional implementations of this embodiment, the functional block description information corresponding to each simulation test case can at least be used to indicate or describe the functional blocks on the chip under test used or involved in the process of running the corresponding simulation test case. The functional blocks on the chip under test can refer to one or more regions used to constitute the chip under test, obtained by dividing the components on the chip under test according to functional distribution and / or physical distribution. In this way, the required functional blocks (or circuits) can be retained according to specific simulation requirements, thereby improving chip simulation efficiency. Each functional block may include at least components for running simulation test cases and logic related to each component. The components on the chip under test may refer to basic cells or standard cells used in chip design. For example, they may include, but are not limited to, gate-level units such as AND gates and OR gates, flip-flops, buffers, multiplexers, etc. for implementing digital logic functions, various memory units for storing data, power switches, level converters, etc. for power distribution, voltage regulation and power consumption optimization, interfaces for connecting the chip to the outside world, special units designed for specific needs such as scan chains, and vias, shielding lines, etc. for placement, routing and physical verification. The functional distribution can be determined according to the actual functional requirements in the chip design, and the physical distribution can be determined according to the physical placement or arrangement method adopted in the chip design.

[0066] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional blocks may include, but are not limited to, one or more of the following types of functional blocks: input / output functional blocks, input boundary register functional blocks, output boundary register functional blocks, control functional blocks, pass-through functional blocks, internal logic functional blocks, and low-power functional blocks.

[0067] Step 303: Deduplicate the simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set.

[0068] This step aims to optimize the simulation cases in the initial simulation case set based on the functional block description information corresponding to each simulation case in step 302 above, thereby reducing simulation resource consumption while meeting simulation requirements. In some optional implementations of this disclosure, simulation cases with overlapping functional block description information in the initial simulation case set can be deduplicated to obtain an optimized simulation case set, i.e., a simplified simulation case set. Here, simulation cases with overlapping functional block description information can refer to simulation cases whose functional block description information is completely (i.e., identical) or partially overlapping.

[0069] Step 304: Based on the simplified simulation test cases in the simplified simulation test case set, perform simulation verification on the chip under test.

[0070] In this step, simulation verification of the chip under test can be achieved by performing simulation verification on simplified simulation test cases from the simplified simulation test case set. During the execution of the corresponding simulation test cases, key information can be extracted based on the functional blocks to be used, depending on the specific simulation requirements. In this embodiment, information extraction can be applied to the netlist level or the register-transfer level (RTL) level, so as to efficiently perform simulation verification in various scenarios and thus achieve more efficient chip simulation.

[0071] According to the chip simulation method provided in this disclosure, an initial simulation test case set can be determined for the chip under test, and the function block description information corresponding to each simulation test case, indicating the function block used to run the corresponding simulation test case, can be determined. Furthermore, the function block-level description information on the chip under test can be used to accurately optimize the simulation test cases in the initial simulation test case set, removing redundant simulation test cases to obtain a simplified simulation test case set. Thus, by optimizing the initial configuration or design simulation test cases for the chip under test and performing simulation verification based on this simplified simulation test case set, simulation resource consumption can be reduced, thereby significantly improving chip simulation verification efficiency, which in turn helps to shorten the chip design cycle and reduce chip design costs.

[0072] Please refer to Figure 4 , Figure 4 This is a flowchart of another chip simulation method provided in this disclosure embodiment, which can be applied to the above-described... Figure 2 In the application scenario described in the corresponding embodiment, process 400 includes the following steps:

[0073] Step 401: Determine the initial simulation test case set corresponding to the chip under test.

[0074] Step 402: Determine the function block description information corresponding to the simulation cases in the initial simulation case set.

[0075] The function block description information is used to indicate at least the function blocks used to run the simulation test case. The function blocks are divided based on the components on the chip under test according to their functional distribution and / or physical distribution.

[0076] Step 403: Deduplicate the simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set.

[0077] Steps 401-403 are related to the above. Figure 3 Steps 301-303 in any of the embodiments based on this implementation are consistent. For identical parts, please refer to the corresponding parts of any of the above embodiments; they will not be repeated here. Furthermore, step 304 in any of the above embodiments is... Figure 4 In the corresponding embodiments, steps 404-407 can be specifically implemented as follows.

[0078] Step 404: Based on the modules under test associated with each simplified simulation test case of the chip under test, determine the test load corresponding to each simplified simulation test case.

[0079] In some optional implementations of this disclosure, functional blocks can be obtained by dividing the components on the module under test (DUT) of the chip under test according to their functional distribution. For example, each DUT module in the chip under test (e.g., Figure 1 Module 1) shown is a functional block division at the granular level to accelerate simulation based on the functional information in the module under test, thereby improving the flexibility of simulation processing. Each module under test can be divided based on the physical distribution of components on the chip under test. Furthermore, functionally dividing each module under test in the chip under test based on its functional distribution reduces the occupation of server hard disk space and processor resources in large-scale or ultra-large-scale chip simulation verification scenarios compared to simply retaining all the necessary modules, thus further improving simulation efficiency. In some optional implementations of this disclosure, the initial component granularity of the functional block division of each module under test included in the chip under test can be the same or different.

[0080] For example, by dividing any module under test in a chip into functional blocks in an application scenario, the following can be obtained: Figure 5 The input / output function blocks shown Input boundary register function block Output Boundary Register Function Block Control function block Penetration Function Block Internal logic function blocks and low-power function blocks For example, It can be the corresponding area for the input and output of functional signals or a sub-module of the module under test. This can be the region corresponding to the register on the input port side or a sub-module of the module under test. This can be the region corresponding to the register on the output port side or a sub-module of the module under test. It can be the area corresponding to the control circuit such as power supply and clock, or a sub-module of the module under test. It can be a region or a sub-module of the module under test corresponding to the flow path of the penetrating or through-path signal. This can be a region or sub-module of the module under test corresponding to a circuit structure used to implement a specific function (which can be related to...). Figure 5 The internal logic 1~n corresponds to), and It can be a region corresponding to a low-power circuit or a sub-module of the module under test.

[0081] In some optional implementations of the embodiments of this disclosure, each simplified simulation test case in the simplified simulation test case set can be associated with one or more modules under test in the chip under test (DUT). Correspondingly, each DUT in the DUT can be associated with one or more simplified simulation test cases in the simplified simulation test case set. In this embodiment, when running each simplified simulation test case in the simplified simulation test case set, function blocks on one or more DUT modules in the DUT can be used. The type and number of function blocks used by each DUT module can be determined according to specific simulation requirements, such as the specific simulation type, and are not specifically limited here. Thus, the test load corresponding to each simulation test case can be accurately determined based on the DUT modules associated with each simulation test case.

[0082] In some optional implementations of the embodiments of this disclosure, the function block description information corresponding to each simulation test case indicates the function block used to run the simulation test case, which is a function block in one or more modules under test associated with each simulation test case. It should be noted that each simulation test case in the initial simulation test case set and each simplified simulation test case in the simplified simulation test case set of the embodiments of this disclosure can be considered as chip-level and associated with one or more modules under test in the chip under test, that is, also associated with the corresponding function blocks in the one or more modules under test. Of course, each simulation test case in the embodiments of this disclosure can also be set as module-level or subsystem-level, where the subsystem can be composed of one or more modules in the chip under test.

[0083] Step 405: Based on the test load corresponding to each simplified simulation test case, select candidate simulation test cases whose test load is greater than the first load threshold from the simplified simulation test case set.

[0084] Step 406: Based on the selected candidate simulation test cases, determine the target module to be re-partitioned in the chip under test.

[0085] In this embodiment, after determining the test load corresponding to each simplified simulation test case based on the module under test associated with each simplified simulation test case in the simplified simulation test case set, candidate simulation test cases with larger loads can be screened based on the test loads corresponding to each simplified simulation test case. That is, simulation test cases with test loads exceeding a preset first load threshold are screened, so as to determine the target module under test in the chip under test that needs to be re-divided into functional blocks based on the screened candidate simulation test cases.

[0086] In some optional implementations of the embodiments of this disclosure, the number of candidate simulation test cases selected from the simplified simulation test case set may be one or more. The specific value of the first load threshold may be set or adjusted according to specific simulation requirements, and is not specifically limited here. The target module under test belongs to the chip under test and is associated with the selected candidate simulation test cases, and the number of target modules under test may be one or more.

[0087] Step 407: Based on the result of re-dividing the functional blocks of the target module under test, perform simulation verification on the chip under test.

[0088] Among them, the test load of the simulation test cases determined based on the result of re-dividing the target module under test into functional blocks is less than or equal to the first load threshold.

[0089] In this embodiment, after re-dividing the target module under test into functional blocks, the test load corresponding to the simulation test cases using the re-divided target module under test during simulation runtime can be re-determined based on the result of the re-dividing. For example, the test load corresponding to the simulation test cases can be re-determined based on the modules under test associated with the simulation test cases, including the target module under test. It is then determined whether the re-determined test load corresponding to the simulation test cases is less than or equal to the first load threshold. If so, the above step and related processes are repeated until the test load of the simulation test cases determined based on the result of re-dividing the target module under test into functional blocks is less than or equal to the first load threshold. In other words, by re-dividing the target module under test into functional blocks, the test load corresponding to the simulation test cases of the re-divided target module under test can be effectively reduced, i.e., reduced to below the first load threshold.

[0090] In some optional implementations of the embodiments of this disclosure, re-dividing the target module under test into functional blocks can be understood as dividing the target module under test into functional blocks with smaller granularity, so as to further optimize the simulation load by optimizing the circuit used for simulation verification, thereby further improving the simulation efficiency.

[0091] In some optional implementations of the embodiments of this disclosure, step 407 can be implemented as follows: based on the result of re-dividing the target module under test into functional blocks, run the corresponding simulation test cases to obtain the simulation verification result of the chip under test. In this embodiment, during the simulation verification of the chip under test based on a simplified simulation test case set, i.e., running the corresponding simulation test cases, key information can be extracted based on smaller granularity functional blocks obtained by re-dividing the target module under test into functional blocks. Then, the corresponding simulation test cases can be run based on the module after re-dividing the functional blocks. In this embodiment of the disclosure, this can be applied to information extraction at the netlist level or at the RTL level to efficiently perform simulation verification in various different scenarios, thereby improving the simulation verification speed. Furthermore, by utilizing simplified simulation test cases and optimized functional load, resource consumption can be reduced.

[0092] According to the chip simulation method provided in this disclosure, after optimizing the initial simulation test case set corresponding to the chip under test (DUT) and removing redundant simulation test cases from the initial set to obtain a simplified simulation test case set, simulation efficiency can be improved at the granularity of the module under test (DUT) in the DUT based on the test load of each simplified simulation test case. That is, the test load corresponding to each simplified simulation test case can be determined based on one or more DUT modules associated with each simplified simulation test case in the DUT chip. Furthermore, when candidate simulation test cases with excessively high test loads (i.e., consuming significant simulation resources) are identified, the target DUT module requiring re-partitioning of functional blocks needs to be determined based on the selected candidate simulation test cases. This effectively reduces the test load corresponding to the simulation test cases of the re-partitioned target DUT module. Thus, based on the redundancy removal optimization of the initial simulation test case set for the DUT chip, further optimization of the simulation load can be achieved by optimizing the circuit used for simulation verification, thereby effectively improving simulation efficiency and shortening the chip design cycle.

[0093] In some optional implementations of the embodiments of this disclosure, the one or more modules under test associated with each simplified simulation test case in the above-mentioned simplified simulation test case set may also include, in addition to the target modules under test that can be further subdivided into functional blocks, modules under test that do not require further subdivision into functional blocks. In this part of the modules under test, only the functional blocks corresponding to specific logic can be retained, that is, the modules under test are not all retained, so as to meet the simulation requirements of the chip under test. The specific logic may include multi-power domain management logic, pass-through logic, input and output logic, etc. For example, for the module under test corresponding to the extraction circuit in the chip under test, only the input and output logic used to meet the simulation requirements of the chip under test can be retained.

[0094] In some optional implementations of the embodiments of this disclosure, in the above... Figure 4 Based on the corresponding embodiments, the functional description information corresponding to the simulation test case in any of the above embodiments can also be used to indicate the load parameters corresponding to the functional blocks used to run the simulation test case, so as to accurately evaluate the resources and / or time required for simulation.

[0095] Further, step 404 in the above embodiment can be executed as follows: based on the load parameters corresponding to the function blocks in the module under test used to run each simplified simulation test case, determine the test load corresponding to each simplified simulation test case.

[0096] In this embodiment, the test load corresponding to each simplified simulation test case in the simplified simulation test case set can be accurately determined based on the function block description information corresponding to each simulation test case. In some optional implementations of this disclosure, based on the load parameters corresponding to the function blocks used to run each simplified simulation test case in the simplified simulation test case set in each module under test of the chip under test, the test load corresponding to each module under test associated with each simplified simulation test case in the simplified simulation test case set can be determined. Furthermore, the test load corresponding to the corresponding simulation test case can be determined based on the test load corresponding to each module under test.

[0097] It should be noted that in some alternative implementations of the embodiments of this disclosure, the test load corresponding to the simulation test case can also be directly determined based on the type of function block used to run each simulation test case, the corresponding load parameters, and the number of function blocks of the corresponding type. The types of function blocks include, but are not limited to, one or more of the following: input / output function blocks, input boundary register function blocks, output boundary register function blocks, control function blocks, pass-through function blocks, internal logic function blocks, and low-power function blocks.

[0098] For example, if a simulation test case is associated with module 1 and module 2 in the chip under test, wherein module 1 is divided into functional blocks , , , , , and The module under test 2 is divided into functional blocks. , , , , , and Running this simulation test case requires the use of the function block in module 1 under test. , , and and the function blocks in module 2 under test , , and Furthermore, it can be based on functional blocks. , , and By considering the corresponding load parameters, the test load for the module under test (DUT) 1 in this simulation test case can be determined, as well as the test load based on the function block. , , and By using the corresponding load parameters, the test load of the module under test 2 when used in the simulation test case can be determined. Furthermore, the test load of the simulation test case can be determined based on the test loads of the module under test 1 and the module under test 2 respectively.

[0099] Furthermore, in some optional implementations of the embodiments of this disclosure, the load parameters corresponding to each functional block are determined based on at least one of the following: the area ratio of the functional block relative to the chip under test; and the number of components contained in the functional block. The area ratio of the functional block relative to the chip under test can be understood as follows: after dividing the functional blocks at the granularity of the chip under test or at the granularity of the modules under test within the chip under test, the area occupied by each functional block can be further determined. Thus, the ratio of the area occupied by each functional block to the area of ​​the chip under test can be calculated, and the calculation result can be assigned as the load parameter corresponding to each functional block. Alternatively, the number of components contained in or covered by a functional block can be directly assigned as its corresponding load parameter.

[0100] Continuing with the above Figure 5 The corresponding embodiments are used as examples for illustration. The function block description information corresponding to each simulation test case in any of the above embodiments can at least be used to indicate the function block used to run the simulation test case and the load parameters corresponding to the function block. In some optional implementations of the embodiments of this disclosure, the module under test in the chip under test can be associated with one or more simulation test cases. Then, the current simulation usage of the module under test can be described by the following expression: = ,in, - The value of can be an integer greater than or equal to 0, representing the total number of functional blocks of each type used in the module under test when running simulation test cases in the corresponding simulation test case set. The functional blocks used can be obtained by dividing the module under test. - This can be the cumulative number (or number of times) that each type of functional block in the module under test is used by all current simulation test cases, i.e., the different types of functional blocks in the module under test. , , , , , and The sum of the quantities used. The load parameter for each functional block in each module under test can refer to the area ratio of each functional block in each module under test relative to the chip under test.

[0101] In some optional implementations of the embodiments of this disclosure, the target module under test may include all modules under test associated with candidate simulation cases whose test load is greater than the first load threshold selected from the simplified simulation case set. This allows for a simple and efficient determination of the target module under test that needs to be further subdivided.

[0102] In some alternative implementations of the embodiments of this disclosure, the test modules associated with the candidate simulation test cases selected above can be further screened to narrow down the range of test modules for functional block subdivision, thereby further improving the efficiency of determining the target test module. In this case, step 406 in any of the above embodiments can be implemented as follows: based on the load parameters corresponding to the functional blocks used to run the candidate simulation test cases in the test modules associated with the candidate simulation test cases, the test load corresponding to the test modules associated with the candidate simulation test cases is determined; the test modules associated with candidate simulation test cases whose test loads are greater than a second load threshold are determined as target test modules. That is, in this embodiment, the test loads corresponding to each test module associated with each candidate simulation test case can be determined, and test modules whose test loads exceed a second load threshold can be determined as target test modules for functional block subdivision. The specific value of the second load threshold can be set or adjusted according to specific simulation requirements and is not specifically limited here.

[0103] For example, taking the association of candidate simulation test cases with the aforementioned module under test 1 and module under test 2 as an example, the functional description information corresponding to each type of functional block in module under test 1 when applied to the simulation of the candidate simulation test case can be represented as follows: That is, when running this simulation test case, the function block in module 1 under test needs to be used. , , and And the functional description information corresponding to each type of functional block in the module under test 2 when applied to the candidate simulation test case can be represented as ( This means that running this simulation test case requires using the function blocks in module 1 under test. , , and In the above function description information, 1 indicates that the corresponding function block is used, and 0 indicates that the corresponding function block is not used. Furthermore, It can be assigned the area ratio between the corresponding functional block and the chip under test. , , as well as , , and And so on, the test load corresponding to module 1 under test can be the value assigned to it. , , and The summation result shows that the test load corresponding to module 2 under test can be the value assigned to it. , , and Furthermore, the test load corresponding to the above candidate simulation cases can be the sum of the test loads corresponding to the two modules under test.

[0104] In some optional implementations of the embodiments of this disclosure, the process of re-dividing the target module under test into functional blocks in any of the above embodiments may include the following: determining the smallest component in the target module under test; based on the smallest component, filtering target components that match the simulation type associated with the target module under test; and re-dividing the target module under test into functional blocks based on the smallest component and the target components.

[0105] In this embodiment, the retention of relevant logic and penetration signals can be performed at the granularity of the smallest component (basic unit or standard unit, i.e., the smallest segment) in the target module under test that constitutes the test load exceeding the set second load threshold. For example, the relevant logic and penetration signals can be retained. Figure 6 The module 3 in the chip under test shown is taken as the target module under test, which includes minimum components 1~i. Further, the minimum component in this target module under test can be taken as the minimum reserved unit (exemplarily, such as...). Figure 7 As shown, target components that match simulation test cases of the corresponding simulation type associated with the target module under test are retained by searching upwards or downwards (or filtering / tracking) to achieve circuit extraction and circuit optimization, thereby meeting simulation requirements and accelerating simulation.

[0106] For example, such as Figure 7As shown, by using synthesis tools (software tools for converting high-level design descriptions into low-level gate-level netlists) or other logic parsing tools (or scripts) that output according to simulation requirements, the input / output control logic of the smallest retained unit can be searched upwards or downwards for the fan-in and fan-out logic of the currently retained unit. For example, based on physical placement information and multi-power domain management information, the control drive logic, input control logic, and output control logic related to the second-level or third-level sub-modules can be searched upwards level by level for circuit retention, and unnecessary logic can be removed. Here, unit fan-in refers to the number of input signals or connection sources received by the unit, which can be used to reflect the degree of dependence or input complexity of the unit. Unit fan-out refers to the number of target signals or connections output by the unit, which can be used to reflect the scope of dependence or output complexity of the unit. Therefore, starting from the smallest constituent unit in the target module under test, the components required to achieve the corresponding simulation requirements can be retained to achieve the purpose of functional block subdivision, thereby optimizing the simulation load and realizing the re-division of the functional blocks of the module under test while meeting simulation requirements.

[0107] This allows for the use of the most streamlined combination of function blocks when running the corresponding simulation test cases, reducing the simulation load and further improving simulation efficiency. The simulation type associated with the target module under test can include, but is not limited to, one or more of the following: design for testability simulation, functional design simulation, and low-power design simulation.

[0108] In some optional implementations of the embodiments of this disclosure, step 406 in any of the above embodiments may be implemented as follows: based on the result of re-dividing the target module under test into functional blocks, update the test load corresponding to the simulation test cases associated with the target module under test; based on the updated test load corresponding to the simulation test cases associated with the target module under test, determine the overall test load corresponding to the chip under test; and use the test resources allocated to the chip under test based on the overall test load to perform simulation verification on the chip under test.

[0109] In this embodiment, after the functional blocks of the target module under test (DUT) are subdivided, the test load corresponding to the simulation test cases associated with the DUT can be updated based on the re-divided functional blocks of the target DUT for its associated simulation test cases. The test load corresponding to the simulation test cases associated with the re-divided target DUT can be the sum of the test loads of all DUTs associated with the simulation test cases (including the re-divided target DUT). Furthermore, if the simulation test cases associated with the target DUT meet the test load requirement (i.e., are less than or equal to the aforementioned first load threshold), the overall test load corresponding to the chip under test can be determined based on the updated test load of these simulation test cases. The overall test load corresponding to the chip under test can be the sum of the test loads of all current simulation test cases (including the simulation test cases associated with the re-divided target DUT). This overall test load can effectively guide the allocation of test resources for simulation verification. The test resources for simulation verification may include, but are not limited to, simulation equipment and data storage space (Memory).

[0110] In some optional implementations of the embodiments of this disclosure, the process of determining the overall test load of the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test may include the following: determining the category test load corresponding to the simulation type associated with the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test and the simulation type to which the simulation test cases belong; and determining the overall test load based on the category test load corresponding to the simulation type associated with the chip under test.

[0111] In this embodiment, the updated test load corresponding to the simulation test cases associated with the target module under test can be updated to the test load corresponding to the simulation test case set. Then, based on the test load corresponding to the simulation test cases in the updated simulation test case set and the simulation type to which the simulation test cases belong, the classification test load corresponding to each simulation type associated with the chip under test can be determined. Then, the sum of the classification test loads corresponding to all simulation types can be determined as the overall test load corresponding to the chip under test.

[0112] In some optional implementations of the embodiments of this disclosure, the allocation of test resources for simulation verification can be effectively guided based on the test load corresponding to each simulation type associated with the chip under test and / or the overall test load corresponding to the chip under test.

[0113] Thus, by using functional blocks divided according to functional distribution in this embodiment of the present disclosure to evaluate and obtain the allocation amount of resource consumption, that is, by quantifying the above-mentioned test load, simulation resource evaluation can be realized, so as to further optimize the resource allocation in the chip simulation process according to the amount of resource consumption.

[0114] In some optional implementations of this disclosure, test resources for simulation verification can be allocated to the chip under test based on the test load corresponding to each simulation type associated with the chip under test and / or the overall test load corresponding to the chip under test, combined with the simulation priority determined based on simulation requirements. The simulation priority can correspond to different simulation types.

[0115] Continuing with the above Figure 5 The corresponding implementation example will be used for illustration, through Indicates design-testability simulation, Indicates functional design simulation and For low-power design simulation, the simulation test cases associated with the above-mentioned chip under test are determined according to the simulation type. When classifying, you can use Representing simulation test cases This attribute can be used to indicate the simulation type corresponding to the simulation use case. For example, and The value can be 0 or 1, for example, It can represent simulation test cases. For functional testing and without low-power configuration; further, it can be utilized Implement simulation test cases The classification corresponds to different simulation types, for example, with simulation type The corresponding simulation test case set can be represented as , and simulation type The corresponding simulation test case set can be represented as and simulation type The corresponding simulation test case set can be represented as ,in, , and These represent simulation test cases. It should be noted that in the embodiments of this disclosure, simulation test cases of different simulation types are associated with one or more modules under test in the chip under test. When running simulation test cases of the corresponding simulation type, it is necessary to use the functional blocks in the associated module under test. For example, functional design simulation may involve through-logic (which may correspond to through-logic functional blocks), input / output logic (which may correspond to input / output functional blocks), etc.

[0116] Optionally, when any one of the modules under test in the chip under test is used to implement simulation verification of different simulation types, the test load of the module under test under simulation test cases of different simulation types can be expressed as:

[0117] , n can take the value of an integer;

[0118] , The value of m is an integer;

[0119] , l q can take the value of an integer.

[0120] Optionally, the test load corresponding to each simulation test case of each simulation type associated with each module under test can be determined based on the test load corresponding to the test test cases of each simulation type of the chip under test. Further, based on the test load corresponding to the simulation test cases of each simulation type of the chip under test, the categorized test load corresponding to each simulation type of the chip under test can be determined, and based on the categorized test load corresponding to each simulation type of the chip under test, the overall test load corresponding to the chip under test can be determined. Optionally, the cumulative test load of the module under test under all simulation test cases of each simulation type of the chip under test can be expressed as:

[0121] ;

[0122] ;

[0123] ;

[0124] Where n can represent the number of simulation test cases of the design testability simulation type of the functional blocks in the module under test used by the chip under test during operation, m can represent the number of simulation test cases of the low power design simulation type of the functional blocks in the module under test used by the chip under test during operation, and q can represent the number of simulation test cases of the functional design simulation type of the functional blocks in the module under test used by the chip under test during operation. The values ​​of n, m and q can be the same or different, and no specific limitation is made here. They can be set according to the actual situation.

[0125] Thus, through the embodiments of this disclosure, the quantification of any of the above test loads can be achieved according to the size of different functional blocks, and it can be determined whether the current functional block division of the module under test needs to be further subdivided so as to generate different samples for simulation; and the above test loads can be recalculated after subdivision to evaluate whether further subdivision is needed until the test loads corresponding to the subdivided functional blocks meet the corresponding threshold requirements.

[0126] In some optional implementations of the embodiments of this disclosure, based on any of the above embodiments, step 303 or step 403 can be specifically executed as follows:

[0127] Based on the function block description information, multiple first simulation cases are determined from the initial simulation case set. Among them, multiple first simulation cases have the same function block description information. The multiple first simulation cases are deduplicated to obtain a simplified simulation case set.

[0128] In this embodiment, simulation cases that use the same function blocks at runtime, i.e., whose corresponding function block description information completely overlap, can be selected from the initial simulation case set as multiple first simulation cases to be optimized for redundancy removal. Furthermore, deduplication can be performed based on the selected multiple first simulation cases to achieve efficient and accurate optimization of the initial simulation case set.

[0129] In some optional implementations of the embodiments of this disclosure, in order to further improve the optimization efficiency of the initial simulation test case set, only one of the first simulation test cases with the same functional blocks used by the multiple runtimes can be retained.

[0130] In some optional implementations of the embodiments of this disclosure, the function block description information in any of the above embodiments can also be used to indicate the runtime sequence corresponding to the function block used to run the simulation test case, so as to meet the corresponding simulation requirements and realize simulation verification.

[0131] In some alternative implementations of the embodiments of this disclosure, the step of deduplicating multiple first simulation use cases to obtain a simplified simulation use case set can be specifically performed as follows: selecting multiple second simulation use cases with the same runtime sequence from multiple first simulation use cases; deduplicating multiple second simulation use cases to obtain a simplified simulation use case set.

[0132] In this embodiment, when optimizing simulation test cases based on multiple first simulation test cases that use the same functional blocks during runtime, the overlap of runtime sequences between simulation test cases can be further considered. Multiple second simulation test cases with the same runtime sequence can be selected, and redundancy-removing optimization can be performed on these second simulation test cases. In this way, efficient and accurate optimization of the initial simulation test case set can be achieved while ensuring that the final simplified simulation test case set used for simulating and verifying the chip under test comprehensively covers the simulation requirements as much as possible.

[0133] In some optional implementations of the embodiments of this disclosure, regarding the steps of deduplicating multiple first simulation test cases to obtain a simplified simulation test case set, or the steps of deduplicating multiple second simulation test cases to obtain a simplified simulation test case set, considering that the functional block description information corresponding to the simulation test cases can also be used for the load parameters corresponding to the functional blocks used to run the simulation test cases, when performing redundancy optimization based on the multiple first simulation test cases or multiple second simulation test cases, multiple first or second simulation test cases with the same load parameters corresponding to the functional blocks used to run the simulation test cases can be deduplicated. Optionally, only one of the multiple first or second simulation test cases with the same load parameters corresponding to the functional blocks used to run the simulation test cases can be retained.

[0134] In some optional implementations of the embodiments of this disclosure, based on any of the above embodiments, step 303 or step 403 may be specifically executed as follows: For the simulation cases in the initial simulation case set, based on the function block description information corresponding to each simulation case, a matrix is ​​determined to indicate the usage of the function blocks of each simulation case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; the simulation cases with overlapping elements in the matrix of the initial simulation case set are deduplicated to obtain a simplified simulation case set.

[0135] In this embodiment, the elements in the matrix used to indicate the functional usage of each simulation test case can be determined based on the load parameters corresponding to the function blocks. Specifically, the load parameters corresponding to the function blocks used by the simulation test cases can be indicated by the function block description information. The determination of the elements in the matrix can be understood as follows: the element is determined by multiplying the value of the load parameter corresponding to the function block with the value of the identifier indicating whether the simulation test case uses the function block (e.g., 0 or 1). In other words, the functional block usage indicated by the elements in this matrix can at least include whether the corresponding function block is used and the load parameters corresponding to the used function block. Thus, by quantifying the functional block usage of the simulation test cases and comparing the forms of the elements in the matrices corresponding to different simulation test cases, it is possible to intuitively and accurately determine whether there is overlap between the functional block description information corresponding to the simulation test cases.

[0136] In some optional implementations of the embodiments of this disclosure, the above-mentioned deduplication of simulation test cases with overlapping elements in the matrix of the initial simulation test case set to obtain a simplified simulation test case set includes: dividing the matrix corresponding to each simulation test case in the initial simulation test case set into at least one sub-matrix according to at least one module under test associated with each simulation test case of the chip under test, wherein the functional blocks are divided according to the functional distribution of the components on the module under test of the chip under test; comparing two different simulation test cases with the elements in the sub-matrix corresponding to the same module under test, and deduplicating the sub-matrixes with the same elements.

[0137] In this embodiment, in order to further improve the deduplication efficiency of simulation test cases, the elements in the matrix corresponding to each simulation test case that need to be deduplicated can be filtered according to the test modules associated with each simulation test case. Optionally, the elements in the matrix corresponding to each simulation test case can be divided into corresponding sub-matrices according to one or more test modules associated with them. Then, when performing deduplication comparison, it is only necessary to compare the elements in the corresponding sub-matrices of the simulation test cases corresponding to the same test module.

[0138] In some optional implementations of the embodiments of this disclosure, the correspondence between the module under test and the sub-matrix can also be indicated by the above-mentioned functional block description information, so as to enable accurate element comparison between matrices corresponding to different simulation test cases.

[0139] In some optional implementations of the embodiments of this disclosure, in the above... Figure 3 or Figure 4 Based on the corresponding embodiments, the chip simulation method in any of the above embodiments may further include the following: classifying the simulation cases in the initial simulation case set according to the simulation type to obtain an initial simulation case set corresponding to the simulation type; wherein, the simulation type includes at least one of testability design simulation, functional design simulation, and low-power design simulation. Thus, classifying the simulation cases according to the simulation type helps improve the efficiency of simulation case deduplication and the allocation efficiency of simulation resources. The results of low-power design simulation can describe the power consumption characteristics of circuit elements under different operating conditions. For example, low-power design simulation can achieve static power consumption analysis, dynamic power consumption analysis, and power consumption assessment of the circuit during switching activities.

[0140] In this embodiment, the simulation test cases in the simulation test case set corresponding to the chip under test can each correspond to a specific simulation type to flexibly adapt to simulation requirements. The simulation types corresponding to this initial simulation test case set can include, but are not limited to, one or more of design for testability simulation, functional design simulation, and low-power design simulation. Based on this, the simulation test cases can be classified according to all simulation types corresponding to the initial simulation test case set to obtain an initial simulation test case set corresponding to the respective simulation type.

[0141] In the embodiments of this disclosure, by classifying the initial simulation test case set corresponding to the chip under test, the flexibility to apply different simulation requirements can be further improved. For example, in some simulation scenarios, when there is only a simulation requirement for a part of the above simulation type, the simulation test case set corresponding to the corresponding simulation type can be called flexibly and efficiently.

[0142] In some optional implementations of the embodiments of this disclosure, step 303 or step 403 can be implemented as follows: within the initial simulation example set of the same simulation type and between the initial simulation example sets of different simulation types, simulation example sets with overlapping elements of the matrix are deduplicated.

[0143] In this embodiment, based on the classification of simulation cases in the initial simulation case set according to simulation type, when performing redundancy optimization on the simulation cases in the initial simulation case set, simulation cases with overlapping elements in the matrix can be screened within each corresponding simulation type's initial simulation case set and between initial simulation case sets of different simulation types. It should be noted that whether to perform deduplication screening within each initial simulation case subset first or between different initial simulation case sets first can be determined based on specific simulation requirements, and no specific limitation is made here.

[0144] In some optional implementations of the embodiments of this disclosure, the step of determining multiple first simulation use cases from the initial simulation use case set based on function block description information can be specifically executed as follows: within the initial simulation use case set of the same simulation type and between initial simulation use case sets of different simulation types, multiple first simulation use cases using the same function blocks are determined based on the function blocks used by the running simulation use cases indicated by the function block description information. That is, in this embodiment, having the same function block description information among multiple first simulation use cases may include using the same function blocks.

[0145] The chip simulation scheme disclosed herein is applicable to at least functional design simulation verification, design-for-test (DT) simulation verification, and low-power design simulation verification. It can automatically retain wiring-related signals based on the wiring structure in the physical implementation to achieve functional block granularity partitioning of the module under test (DUT) in the chip under test. Furthermore, it provides a flexible simulation configuration scheme to retain the required circuitry according to the actual needs of the simulated functional points, thereby improving chip verification efficiency and significantly shortening the chip design cycle. Simultaneously, it simplifies the requirements for multi-threading and hardware acceleration resources in related technologies, providing higher parallelism.

[0146] Further reference Figure 8 As an implementation of the methods shown in the above figures, this disclosure provides an embodiment of a chip simulation device, which corresponds to the above method embodiment.

[0147] like Figure 8 As shown, the chip simulation device 800 of this embodiment may include: a simulation use case set determination unit 801, a description information determination unit 802, a processing unit 803, and a simulation unit 804.

[0148] The simulation test case set determination unit 801 is configured to determine an initial simulation test case set corresponding to the chip under test; the description information determination unit 802 is configured to determine the function block description information corresponding to the simulation test cases in the initial simulation test case set; wherein the function block description information is used to indicate at least the function blocks used to run the simulation test cases, and the function blocks are obtained based on the components on the chip under test according to the functional distribution and / or physical distribution; the processing unit 803 is configured to perform deduplication processing on the simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set; and the simulation unit 804 is configured to perform simulation verification on the chip under test based on the simplified simulation test cases in the simplified simulation test case set.

[0149] In this embodiment of the disclosure, the specific processing of the simulation use case set determination unit 801, the description information determination unit 802, the processing unit 803, and the simulation unit 804 in the chip simulation device 800, and the resulting technical effects, can be referred to respectively. Figure 3 The relevant descriptions of steps 301-304 in the corresponding embodiments will not be repeated here.

[0150] In some optional implementations of the embodiments of this disclosure, the processing unit 803 may be further configured to: determine a plurality of first simulation cases from the initial simulation case set based on the function block description information, wherein the plurality of first simulation cases have the same function block description information; and perform deduplication processing on the plurality of first simulation cases to obtain a simplified simulation case set.

[0151] In some optional implementations of the embodiments of this disclosure, the above-mentioned function block description information is also used to indicate the runtime sequence corresponding to the function block used to run the simulation test case; wherein, the above-mentioned processing unit 803 can be further configured to: filter out a plurality of second simulation test cases with the same runtime sequence from a plurality of first simulation test cases; perform deduplication processing on the plurality of second simulation test cases to obtain a simplified simulation test case set.

[0152] In some optional implementations of the embodiments of this disclosure, the aforementioned function block description information is further used to indicate the load parameters corresponding to the function blocks used in running the simulation test cases; and the processing unit 803 can be further configured to: for the simulation test cases in the initial simulation test case set, determine a matrix for indicating the usage of function blocks in each simulation test case based on the function block description information corresponding to each simulation test case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; and perform deduplication processing on the simulation test cases in the initial simulation test case set whose elements overlap, to obtain a simplified simulation test case set.

[0153] In some optional implementations of the embodiments of this disclosure, the processing unit 803 may be further configured to: divide the matrix corresponding to each simulation test case in the initial simulation test case set into at least one sub-matrix according to at least one module under test associated with each simulation test case of the chip under test, wherein the functional blocks are obtained by dividing the components on the module under test of the chip under test according to their functional distribution; compare two different simulation test cases with the elements in the sub-matrix corresponding to the same module under test, and remove duplicates from the sub-matrixes with the same elements.

[0154] In some optional implementations of the embodiments of this disclosure, the chip simulation apparatus 800 may further include a classification unit (not shown in the figure), configured to classify the simulation cases in the initial simulation case set according to the simulation type to obtain an initial simulation case set corresponding to the simulation type; wherein, the simulation type includes at least one of testability design simulation, functional design simulation and low power design simulation; and the processing unit 803 may be further configured to: perform deduplication processing on simulation cases whose matrix elements overlap within the initial simulation case set of the same simulation type and between the initial simulation case sets of different simulation types.

[0155] In some optional implementations of the embodiments of this disclosure, the simulation unit 804 may be further configured to: determine the test load corresponding to each simplified simulation test case based on the module under test associated with each simplified simulation test case of the chip under test; select candidate simulation test cases whose test load is greater than a first load threshold from the set of simplified simulation test cases based on the test load corresponding to each simplified simulation test case; determine the target module under test in the chip under test for re-partitioning the functional blocks based on the selected candidate simulation test cases; and perform simulation verification on the chip under test based on the result of re-partitioning the functional blocks of the target module under test; wherein the test load of the simulation test cases updated based on the result of re-partitioning the functional blocks of the target module under test is less than or equal to the first load threshold.

[0156] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional description information is also used to indicate the load parameters corresponding to the functional blocks used to run the simulation test cases; wherein, the above-mentioned simulation unit 804 can be further configured to: determine the test load corresponding to each simplified simulation test case based on the load parameters corresponding to the functional blocks used to run each simplified simulation test case in the module under test.

[0157] In some optional implementations of the embodiments of this disclosure, the simulation unit 804 may be further configured to: determine the test load corresponding to the module under test associated with the candidate simulation test case based on the load parameters corresponding to the function block used to run the candidate simulation test case in the module under test associated with the candidate simulation test case; and determine the module under test associated with the candidate simulation test case whose test load is greater than the second load threshold as the target module under test.

[0158] In some optional implementations of the embodiments of this disclosure, the above-mentioned load parameters are determined based on at least one of the following: the area ratio of the functional block relative to the chip under test; the number of components contained in the functional block.

[0159] In some optional implementations of the embodiments of this disclosure, the simulation unit 804 may be further configured to: determine the smallest component in the target module under test; based on the smallest component, filter target components that match the simulation type associated with the target module under test; and re-divide the target module under test into functional blocks based on the smallest component and the target components.

[0160] In some optional implementations of the embodiments of this disclosure, the simulation unit 804 may be further configured to: update the test load corresponding to the simulation test cases associated with the target module under test based on the result of re-dividing the target module under test into functional blocks; determine the overall test load corresponding to the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test; and perform simulation verification on the chip under test using the test resources allocated to the chip under test based on the overall test load.

[0161] The simulation unit 804 can be further configured to: determine the classification test load corresponding to the simulation type associated with the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test and the simulation type to which the simulation test cases belong; and determine the overall test load based on the classification test load corresponding to the simulation type associated with the chip under test.

[0162] In some optional implementations of the embodiments of this disclosure, the above-mentioned functional block includes one or more of the following: input / output functional block, input boundary register functional block, output boundary register functional block, control functional block, pass-through functional block, internal logic functional block, and low-power functional block.

[0163] This embodiment exists as a device embodiment corresponding to the above method embodiment. It can determine the initial simulation test case set corresponding to the chip under test (DUT), and determine the function block description information corresponding to each simulation test case, indicating the function block used to run the corresponding simulation test case. Furthermore, the function block-level description information on the DUT can be used to accurately optimize the simulation test cases in the initial simulation test case set, removing redundant simulation test cases to obtain a simplified simulation test case set. Thus, by optimizing the initial configuration or design simulation test cases for the DUT and performing simulation verification based on this simplified simulation test case set, simulation resource consumption can be reduced, thereby significantly improving chip simulation verification efficiency, which in turn helps to shorten the chip design cycle and reduce chip design costs.

[0164] According to embodiments of the present disclosure, the present disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the chip emulation method described in any of the above embodiments when executed.

[0165] According to embodiments of this disclosure, this disclosure also provides a non-transitory computer-readable storage medium storing computer instructions that enable a computer to implement the chip emulation method described in any of the above embodiments when executed.

[0166] According to embodiments of this disclosure, this disclosure also provides a computer program product, which includes a computer program that, when executed by a processor, can implement the chip emulation method described in any of the above embodiments.

[0167] Figure 9A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device 900 includes one or more processors 901, a communication interface 902, and a memory 903. The processors 901, communication interface 902, and memory 903 are interconnected via a bus 904. Optionally, the electronic device 900 may further include an input / output interface 905, which is connected to input / output devices for receiving user-set parameters, etc. The electronic device 900 can be used to implement some or all of the functions of the device embodiments or system embodiments of the present disclosure described above; the processor 901 can also be used to implement some or all of the operation steps of the method embodiments of the present disclosure described above. For example, the specific implementation of various operations performed by the electronic device 900 can be referred to the specific details in the above embodiments, such as the processor 901 being used to execute some or all of the steps or operations in the above method embodiments. For example, in this embodiment of the present disclosure, the electronic device 900 can be used to implement some or all of the functions of one or more components in the above-described device embodiments. In addition, the communication interface 902 can be used specifically for communication functions necessary to implement the functions of these devices and components, and the processor 901 can be used specifically for processing functions necessary to implement the functions of these devices and components.

[0168] It should be understood that, Figure 9 The electronic device 900 may include one or more processors 901, and the multiple processors 901 may collaboratively provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or an arbitrary connection mode; or the multiple processors 901 may form a processor sequence or a processor array; or the multiple processors 901 may be divided into a main processor and an auxiliary processor; or the multiple processors 901 may have different architectures, such as adopting a heterogeneous computing architecture. Furthermore, Figure 9 The structural and functional descriptions of the electronic device 900 shown are exemplary and non-limiting. In some exemplary embodiments, the electronic device 900 may include... Figure 9 The diagram shows more or fewer components, or combinations of some components, or splitting of some components, or different arrangements of components.

[0169] The processor 901 can have various specific implementations. For example, the processor 901 may include one or more combinations of a central processing unit (CPU), a graphics processing unit (GPU), a neural network processing unit (NPU), a tensor processing unit (TPU), or a data processing unit (DPU), etc., and this disclosure does not impose specific limitations. The processor 901 can also be a single-core processor or a multi-core processor. The processor 901 can be a combination of a CPU and hardware chips. The aforementioned hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The aforementioned PLDs can be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof. The processor 901 can also be implemented solely using logic devices with built-in processing logic, such as FPGAs or digital signal processors (DSPs). The communication interface 902 can be a wired interface or a wireless interface, used to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface can be a cellular network interface or a wireless LAN interface, etc.

[0170] Memory 903 can be non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Memory 903 can also be volatile memory, which can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 903 can also be used to store program code and data, so that the processor 901 can call the program code stored in the memory 903 to execute some or all of the operation steps in the above method embodiments, or to execute the corresponding functions in the above device embodiments. Furthermore, the electronic device 900 may include, compared to... Figure 9 The number of components displayed may be more or less, or there may be different component configurations.

[0171] The 904 bus can be a Peripheral Component Interconnect Express (PCIe) bus, or an Extended Industry Standard Architecture (EISA) bus, a Unified Bus (Ubus or UB), a Compute Express Link (CXL) bus, a Cache Coherent Interconnect for Accelerators (CCIX) bus, etc. The 904 bus can be divided into address bus, data bus, control bus, etc. In addition to the data bus, the 904 bus can also include a power bus, a control bus, and a status signal bus. However, for clarity, Figure 9 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0172] The methods and devices provided in this disclosure are based on the same inventive concept. Since the principles by which the methods and devices solve problems are similar, embodiments, implementation methods, examples, or methods of implementation can be referred to mutually, and repeated details will not be repeated. This disclosure also provides a system comprising multiple computing devices, the structure of each computing device of which can refer to the structure of the computing devices described above. The functions or operations achievable by this system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be repeated here.

[0173] According to the technical solution of this disclosure, an initial simulation test case set can be determined for the chip under test (DUT), and the function block description information corresponding to each simulation test case, indicating the function block used to run the corresponding simulation test case, can be determined. Furthermore, the function block-level description information on the DUT can be used to accurately optimize the simulation test cases in the initial simulation test case set, removing redundant simulation test cases to obtain a simplified simulation test case set. Thus, by optimizing the initial configuration or design simulation test cases for the DUT and performing simulation verification based on this simplified simulation test case set, simulation resource consumption can be reduced, thereby significantly improving chip simulation verification efficiency, which in turn helps to shorten the chip design cycle and reduce chip design costs.

[0174] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. This disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Embodiments of this disclosure can be implemented wholly or partially by software, hardware, firmware, or any other combination. When implemented in software, the above embodiments can be implemented wholly or partially as a computer program product. This application can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code. A computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, all or part of the flow or function according to embodiments of this disclosure is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that a computer can access, or a data storage device such as a server or data center that contains one or more sets of available media. Available media can be magnetic media (such as floppy disks, hard disks, and magnetic tapes), optical media, or semiconductor media. Semiconductor media can be solid-state drives, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other suitable form of storage medium.

[0175] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. Each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart. Figure 1 One or more processes and / or boxes Figure 1 The computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1One or more processes and / or boxes Figure 1 The functions specified in one or more boxes. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable apparatus for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0176] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. The steps in the methods of the embodiments of this disclosure can be adjusted in order, combined, or deleted according to actual needs; the modules in the systems of the embodiments of this disclosure can be divided, combined, or deleted according to actual needs. If these modifications and variations of the embodiments of this disclosure fall within the scope of this disclosure and its equivalents, then this disclosure also intends to include these modifications and variations.

Claims

1. A chip simulation method, characterized in that, include: Determine the initial set of simulation test cases corresponding to the chip under test; Determine the function block description information corresponding to the simulation test cases in the initial simulation test case set; wherein, the function block description information is used at least to indicate the function blocks used to run the simulation test cases, and the function blocks are obtained based on the division of components on the chip under test according to functional distribution and / or physical distribution; According to the simulation type, the simulation cases in the initial simulation case set are classified to obtain the initial simulation case set corresponding to the simulation type; wherein, the simulation type includes at least one of testability design simulation, functional design simulation and low power design simulation; The process of deduplicating simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set includes: when the function block description information is also used to indicate the load parameters corresponding to the function blocks used to run the simulation test cases, for the simulation test cases in the initial simulation test case set, based on the function block description information corresponding to each simulation test case, determining a matrix to indicate the function block usage of each simulation test case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; and deduplicating simulation test cases with overlapping elements in the matrix within the initial simulation test case set of the same simulation type and between the initial simulation test case sets of different simulation types to obtain the simplified simulation test case set. The chip under test is simulated and verified based on the simplified simulation test cases in the simplified simulation test case set.

2. The method according to claim 1, characterized in that, The process of deduplicating simulation test cases with overlapping function block description information in the initial simulation test case set to obtain a simplified simulation test case set includes: Based on the functional block description information, multiple first simulation cases are determined from the initial simulation case set, wherein the multiple first simulation cases have the same functional block description information; The multiple first simulation test cases are deduplicated to obtain the simplified simulation test case set.

3. The method according to claim 2, characterized in that, The function block description information is also used to indicate the runtime sequence corresponding to the function block used in running the simulation test case. The step of deduplicating the plurality of first simulation test cases to obtain the simplified simulation test case set includes: Select multiple second simulation cases with the same runtime sequence from the plurality of first simulation cases; The multiple second simulation test cases are deduplicated to obtain the simplified simulation test case set.

4. The method according to claim 1, characterized in that, The method further includes: The matrix corresponding to each simulation case in the initial simulation case set is divided into at least one sub-matrix according to at least one module under test associated with each simulation case of the chip under test. The functional blocks are obtained based on the functional distribution of the components on the module under test of the chip under test. Two different simulation test cases are compared with the elements in the submatrix corresponding to the same module under test, and the submatrixes with the same elements are deduplicated.

5. The method according to claim 1, characterized in that, The simulation verification of the chip under test based on the simplified simulation test cases in the simplified simulation test case set includes: Based on the chip under test and the modules under test associated with each of the simplified simulation test cases, the test load corresponding to each of the simplified simulation test cases is determined. Based on the test load corresponding to each of the simplified simulation test cases, candidate simulation test cases whose test load is greater than the first load threshold are selected from the simplified simulation test case set. Based on the selected candidate simulation cases, the target module to be tested in the chip under test for re-partitioning the functional blocks is determined. Based on the result of re-dividing the target module under test into functional blocks, the chip under test is simulated and verified; wherein, the test load of the simulation test cases determined based on the result of re-dividing the target module under test into functional blocks is less than or equal to the first load threshold.

6. The method according to claim 5, characterized in that, The determination of the test load corresponding to each simplified simulation test case based on the chip under test and the module under test associated with each of the simplified simulation test cases includes: Based on the load parameters corresponding to the function blocks in the module under test used to run each of the simplified simulation test cases, the test load corresponding to each of the simplified simulation test cases is determined.

7. The method according to claim 6, characterized in that, Based on the selected candidate simulation cases, the target module to be re-partitioned in the chip under test for functional block re-division is determined, including: Based on the load parameters of the function blocks used to run the candidate simulation test cases in the module under test associated with the candidate simulation test cases, the test load corresponding to the module under test associated with the candidate simulation test cases is determined. The module under test associated with the candidate simulation test case whose test load exceeds the second load threshold is identified as the target module under test.

8. The method according to claim 1, characterized in that, The load parameters are determined based on at least one of the following: The area ratio of the functional block relative to the chip under test; The number of components contained in a function block.

9. The method according to claim 5, characterized in that, The process of re-dividing the target module under test into functional blocks includes: Identify the smallest component in the target module under test; Based on the minimum component, target components that match the simulation type associated with the target module under test are selected; Based on the minimum component and the target component, the target module under test is re-divided into functional blocks.

10. The method according to claim 5, characterized in that, The simulation verification of the chip under test based on the result of re-dividing the functional blocks of the target module under test includes: Based on the result of re-dividing the target module under test into functional blocks, update the test load corresponding to the simulation test cases associated with the target module under test; Based on the updated test load corresponding to the simulation test cases associated with the target module under test, the overall test load corresponding to the chip under test is determined. The chip under test is simulated and verified using the test resources allocated to the chip under test based on the overall test load.

11. The method according to claim 10, characterized in that, The determination of the overall test load corresponding to the chip under test based on the updated test load corresponding to the simulation test cases associated with the target module under test includes: Based on the updated test load corresponding to the simulation test cases associated with the target module under test and the simulation type to which the simulation test cases belong, the classification test load corresponding to the simulation type associated with the chip under test is determined. The overall test load is determined based on the classification test load corresponding to the simulation type associated with the chip under test.

12. The method according to claim 1, characterized in that, The functional block includes one or more of the following: Input / output function blocks, input boundary register function blocks, output boundary register function blocks, control function blocks, pass-through function blocks, internal logic function blocks, and low-power function blocks.

13. A chip emulation device, characterized in that, include: The simulation test case set determination unit is configured to determine the initial simulation test case set corresponding to the chip under test; The description information determination unit is configured to determine the function block description information corresponding to the simulation test cases in the initial simulation test case set; wherein the function block description information is at least used to indicate the function blocks used to run the simulation test cases, and the function blocks are obtained based on the division of components on the chip under test according to functional distribution and / or physical distribution; The processing unit is configured to perform deduplication processing on the simulation test cases with overlapping functional block description information in the initial simulation test case set to obtain a simplified simulation test case set. The simulation unit is configured to perform simulation verification on the chip under test based on the simplified simulation test cases in the simplified simulation test case set. The classification unit is configured to classify the simulation cases in the initial simulation case set according to the simulation type to obtain an initial simulation case set corresponding to the simulation type; wherein the simulation type includes at least one of testability design simulation, functional design simulation and low power design simulation. The processing unit is configured to: when the function block description information is also used to indicate the load parameters corresponding to the function blocks used in running simulation test cases, for the simulation test cases in the initial simulation test case set, determine a matrix for indicating the usage of function blocks for each simulation test case based on the function block description information corresponding to each simulation test case, wherein the elements in the matrix are determined based on the load parameters corresponding to the function blocks; and perform deduplication processing on simulation test cases with overlapping elements in the matrix within the initial simulation test case set of the same simulation type and between the initial simulation test case sets of different simulation types to obtain the simplified simulation test case set.

14. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the chip emulation method according to any one of claims 1-12.

15. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the chip simulation method according to any one of claims 1-12.

16. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the chip simulation method according to any one of claims 1-12.

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