Low-power simulation method, device, equipment, storage medium and program product

Abstract

The disclosure provides a low-power simulation method, device, equipment, storage medium and program product, and relates to the technical field of integrated circuits. The method comprises the following steps: determining an initial synthesis model of a register transfer level corresponding to a chip to be simulated; determining a target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model; generating a target gate-level netlist corresponding to a power supply loop in low-power simulation according to an initial gate-level netlist corresponding to the chip to be simulated; and performing low-power simulation including the power supply loop on the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator. The method greatly accelerates the low-power simulation convergence time and improves the simulation efficiency.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, specifically to a low-power simulation method, apparatus, electronic device, computer-readable storage medium, and computer program product. Background Technology

[0002] For large-scale System-on-Chips (SoCs), power consumption has become a key parameter for chip competitiveness. To reduce chip power consumption, various low-power design schemes have been introduced into SoC design. To verify the correctness of these low-power schemes, dedicated low-power simulation verification is required. Summary of the Invention

[0003] This disclosure provides a low-power simulation method, apparatus, electronic device, and computer-readable storage medium.

[0004] In a first aspect, embodiments of this disclosure propose a low-power simulation method, comprising: determining an initial synthesis model of the register-transfer level corresponding to the chip to be simulated; determining a target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model; generating a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated; and performing low-power simulation, including the power supply loop, on the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator.

[0005] In some embodiments, the target synthesizable model includes a second memory synthesizable sub-model. Determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: determining a first memory synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated based on the initial synthesis model; and generating a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first memory synthesizable sub-model.

[0006] In some embodiments, generating a second memory synthesizable submodel corresponding to the power supply loop in the low-power simulation based on the first memory synthesizable submodel includes: adding the power supply port and ground port corresponding to the power supply loop in the low-power simulation to a first memory list to generate a second memory list, wherein the first memory list is the memory list of the first memory synthesizable submodel; and generating a second memory synthesizable submodel corresponding to the power supply loop in the low-power simulation based on the second memory list.

[0007] In some embodiments, the target synthesizable model includes a second pin interface synthesizable sub-model; determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: determining a first pin interface synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated based on the initial synthesis model; and generating a second pin interface synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first pin interface synthesizable sub-model.

[0008] In some embodiments, the first pin interface may synthesize sub-models including pin access device models, input / output buffer models, and / or general input / output models.

[0009] In some embodiments, the target synthesizable model includes a behavioral-level synthesizable sub-model; determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: determining the non-synthesizable model of the register transfer level corresponding to the chip to be simulated based on the initial synthesis model; wherein the non-synthesizable model includes a phase-locked loop simulation model and a physical layer simulation model; converting the non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behavioral-level synthesizable sub-model.

[0010] In some embodiments, converting a non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behaviorally synthesizable sub-model includes: in response to the non-synthesizable model having the same function as a preset function, converting the non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behaviorally synthesizable sub-model; in response to the non-synthesizable model having a different function from a preset function, generating a virtual module based on the non-synthesizable model, the virtual module containing port information corresponding to the non-synthesizable model. In some embodiments, the method further includes: determining an initial synthesizable model based on an initial synthesis model; compiling the initial synthesizable model to obtain an initial data version file; and determining an initial gate-level netlist based on the gate-level netlist information recorded in the initial data version file.

[0011] In some embodiments, generating a second memory synthesizable submodel corresponding to the power supply loop in low-power simulation based on a first memory synthesizable submodel includes: debugging test cases to be tested corresponding to the chip to be simulated based on an initial data version file to obtain a first test result corresponding to the first memory synthesizable submodel; updating the first memory synthesizable submodel based on the error in the first test result in response to the existence of an error in the first test result; and generating a second memory synthesizable submodel corresponding to the power supply loop in low-power simulation based on the updated first memory synthesizable submodel.

[0012] In some embodiments, the first test result includes a first test case that has passed debugging in the test cases to be tested; generating a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated includes: compiling the initial gate-level netlist corresponding to the chip to be simulated, and testing the compiled initial gate-level netlist using the first test case to obtain a second test result; in response to an error in the second test result, updating the compiled initial gate-level netlist based on the error in the second test result to obtain an updated gate-level netlist; and generating the target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the updated gate-level netlist.

[0013] In some embodiments, based on a preset hardware simulation accelerator, low-power simulation including power supply loops is performed on the target synthesizable model and the target gate-level netlist, including: compiling the target synthesizable model and the target gate-level netlist based on the preset hardware simulation accelerator to obtain a target data version file; and performing low-power simulation on power-on and / or power-off of the power supply based on the target data version file.

[0014] In some embodiments, low-power simulation of power-on and / or power-off based on a target data version file includes: triggering a first interrupt in the firmware in response to a firmware-initiated low-power simulation request instruction; controlling a hardware simulation accelerator to perform a first power-on power assignment operation based on the received first interrupt; wherein the power-on power assignment operation is used to place the power supply in a power-on state or a power-off state; controlling the hardware simulation accelerator to perform a second power-on power assignment operation opposite to the first power-on power assignment operation when a first preset condition is met; and controlling the hardware simulation accelerator to deactivate the first interrupt in the firmware when a second preset condition is met.

[0015] In some embodiments, triggering a first interrupt in the firmware includes writing first data to a reserved register in the firmware to trigger the first interrupt.

[0016] In some embodiments, clearing the first interrupt in the firmware includes: controlling the hardware emulation accelerator to write second data to a reserved register to clear the first interrupt by triggering a second interrupt.

[0017] Secondly, embodiments of this disclosure also provide a low-power simulation apparatus, comprising: a first determining module, configured to determine an initial synthesis model of a register-transfer level corresponding to a chip to be simulated; a second determining module, configured to determine a target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model; a generating module, configured to generate a target gate-level netlist corresponding to a power supply loop in the low-power simulation based on an initial gate-level netlist corresponding to the chip to be simulated; and a simulation module, configured to perform low-power simulation, including the power supply loop, on the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator.

[0018] Thirdly, embodiments of this disclosure provide an electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the low-power simulation method described in any implementation of the first aspect.

[0019] Fourthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium storing computer instructions that enable a computer to implement the low-power simulation method described in any implementation of the first aspect.

[0020] Fifthly, embodiments of this disclosure provide a computer program product, including a computer program that, when executed by a processor, implements the steps of the low-power simulation method as described in any implementation of the first aspect.

[0021] The low-power simulation method provided in this disclosure, on the one hand, generates a target synthesizable model corresponding to the power supply loop in the low-power simulation based on an initial synthesis model of the register-transfer level corresponding to the chip to be simulated; on the other hand, it generates a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on an initial gate-level netlist corresponding to the chip to be simulated. After associating both the target synthesizable model and the target gate-level netlist with the power supply loop in the low-power simulation, a hardware simulation accelerator is then used to perform low-power simulation of the target synthesizable model and the target gate-level netlist, including the power supply loop. This disclosure, through the above steps, can achieve low-power simulation of the power supply loop based on a hardware simulation accelerator. Compared with software simulation embodiments, this significantly accelerates the convergence time of the low-power simulation of the power supply loop and reduces the risk of chip tape-out. Attached Figure Description

[0022] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0023] Figure 1 This is a schematic diagram of a low-power simulation method provided in an embodiment of the present disclosure;

[0024] Figure 2 A flowchart of a low-power simulation method provided in this disclosure embodiment;

[0025] Figure 3 A schematic diagram of a simulation provided for an embodiment of this disclosure;

[0026] Figure 4 A flowchart illustrating yet another low-power simulation method provided in this disclosure embodiment;

[0027] Figure 5 A flowchart illustrating yet another low-power simulation method provided in this disclosure embodiment;

[0028] Figure 6 This is a schematic diagram illustrating the simulation of power-on and power-off according to an embodiment of the present disclosure;

[0029] Figure 7 A structural block diagram of a low-power simulation device provided in this disclosure embodiment;

[0030] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0031] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding; these should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description. It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other.

[0032] In chip verification, thorough low-power simulation verification is typically required before chip tape-out. Depending on the stage of the front-end design, low-power simulation verification is usually divided into two stages: RTL (Register Transfer Level) + UPF (Unified Power Format) verification and PG (Power and Ground) verification.

[0033] RTL+UPF verification refers to the verification process based on RTL design and UPF power consumption description. Specifically, RTL design describes the chip's functional behavior, while UPF describes its power consumption behavior. The UPF file contains key information such as power domain, power PG connection, low-power cell rule, and power state. This information helps define and manage the chip's power domain, ensuring effective power consumption management under different operating states. By combining the UPF file with the RTL design, the chip's power consumption performance under different power states can be simulated and analyzed, thereby optimizing the design, reducing power consumption, and improving efficiency. This verification method plays a crucial role in the chip design flow, ensuring that the design's power consumption characteristics meet design requirements.

[0034] PG verification refers to the verification of the power and ground networks in a chip design to ensure that the power and ground connections are correct and that there are no floating nodes or other connection problems. This verification is crucial for ensuring the stability and reliability of the chip.

[0035] Figure 1 This is a schematic diagram of a low-power simulation method provided in an embodiment of this disclosure.

[0036] like Figure 1 As shown, based on the implementation time stage, low-power simulation can be divided into two stages: RTL+UPF simulation stage and PG gate-level netlist simulation stage.

[0037] In the RTL+UPF simulation phase, the power network information of the UPF is mainly used for simulation. The UPF file describes a virtual power network, which mainly includes functions such as power switches, isolation, level shifters, and retention registers (RR). Through RTL+UPF simulation, power-on and power-off flow issues can be identified in the RTL stage. At the same time, logic synthesis tools are used to convert the RTL+UPF code into a gate-level netlist.

[0038] In the PG gate-level netlist simulation phase, the gate-level netlist and UPF are converted into a specific physical implementation through Place & Route (P&R). Power and ground are added to the gate-level netlist to obtain the PG gate-level netlist, and the PG gate-level netlist simulation is performed.

[0039] During the PG gate-level netlist simulation phase, the large size of the PG gate-level netlist, the typically lengthy power-on / off processes involving services, and the fact that cells and memory in the simulated gate-level netlist become types with power and ground connections significantly impact the simulation speed. Therefore, using this software simulation method for low-power verification results in slow simulation speed, and due to the large logic scale, the software simulation cannot complete the execution of subsystem or system scenario use cases, leading to potential tape-out risks.

[0040] Based on the problems existing in the above-mentioned solutions, this disclosure provides another low-power simulation solution.

[0041] Figure 2 This is a flowchart illustrating a low-power simulation method provided in this disclosure. This method can be applied to devices such as processors, chip verification tools, simulation tools, or other hardware devices, and this disclosure does not limit its application. Flow 200 includes the following steps:

[0042] Step 201: Determine the initial synthesis model of the register transfer stage corresponding to the chip to be simulated.

[0043] The initial synthesis model refers to a synthesis model that corresponds to the register transfer stage of the chip to be simulated and is independent of the power supply circuit. Optionally, the initial synthesis model may include synthesizable models, such as synthesizable models related to memory, clock and reset, or interface protocols, etc.; it may also include non-synthesizable models, which are not limited in this disclosure.

[0044] In the field of chip verification, a synthesizable model is code written in a hardware description language (such as Verilog or VHDL) that describes the logic function and structure of a circuit. It can be converted into a gate-level netlist by synthesis tools for subsequent hardware implementation.

[0045] In some embodiments, the initial synthesis model can be obtained directly based on pre-set parameters or generated from code based on the chip under test; this disclosure does not limit this.

[0046] Step 202: Based on the initial synthesis model, determine the target synthesizable model corresponding to the chip to be simulated.

[0047] The target synthesizable model specifies all synthesizable models relevant to low-power simulation of the chip under test.

[0048] When performing low-power simulations related to the power supply circuit, it is necessary to associate the initial synthesis model with the power supply signals and grounding signals of the power supply circuit in the low-power simulation, thereby generating a target synthesizable model corresponding to the power supply circuit in the low-power simulation. This ensures that low-power simulations including the power supply circuit can be achieved when simulating the target synthesizable model.

[0049] Step 203: Generate the target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated.

[0050] The initial gate-level netlist corresponding to the chip to be simulated refers to a general gate-level netlist that is independent of the power supply loop in the low-power simulation. When performing low-power simulation of the power supply loop, it is necessary to associate this initial gate-level netlist with the power supply loop in the low-power simulation to generate a target gate-level netlist corresponding to the power supply loop in the low-power simulation. This ensures that low-power simulation including the power supply loop can be achieved when simulating the target gate-level netlist.

[0051] Step 204: Based on the preset hardware simulation accelerator, perform low-power simulation of the target synthesizable model and the target gate-level netlist, including the power supply loop.

[0052] After preparing the target synthesizable model and the target gate-level netlist, hardware simulation can be performed using a hardware simulation accelerator.

[0053] The default hardware accelerator can be Synopsys ZeBu and Siemens Veloce or other hardware emulation accelerators, and this disclosure does not limit it.

[0054] In some embodiments, the preset hardware simulation accelerator is Palladium. Palladium is a hardware simulation accelerator used in large-scale chip development, primarily for chip functional verification and system prototype verification. Since PG low-power simulation is a specific combination of netlist simulation and low-power verification, the Palladium tool is generally not incorporated into the low-power simulation workflow. This disclosure proposes a new workflow using the Palladium tool for PG low-power specific verification, compared to... Figure 1 The corresponding software simulation methods can greatly improve simulation speed.

[0055] The low-power simulation method provided in this disclosure, on the one hand, generates a target synthesizable model corresponding to the power supply loop in the low-power simulation based on an initial synthesis model of the register-transfer level corresponding to the chip to be simulated; on the other hand, it generates a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on an initial gate-level netlist corresponding to the chip to be simulated. After associating both the target synthesizable model and the target gate-level netlist with the power supply loop in the low-power simulation, a hardware simulation accelerator is then used to perform low-power simulation of the target synthesizable model and the target gate-level netlist, including the power supply loop. This disclosure, through the above steps, can achieve low-power simulation of the power supply loop based on a hardware simulation accelerator, compared to... Figure 1 The corresponding software simulation implementation greatly accelerates the low-power simulation convergence time of the power supply circuit and reduces the risk of chip tape-out.

[0056] In some embodiments, the target synthesizable model includes a second memory synthesizable sub-model. Step 201: Determine the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model, including: determining a first memory synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated based on the initial synthesis model; and generating a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first memory synthesizable sub-model.

[0057] The first synthesizable sub-model of memory in the Register Transfer Level (RTL) refers to the RTL-level description of the logical function and structure of memory (such as SRAM, ROM, register files, etc.). This description must meet the requirements of synthesis tools (such as Synopsys Design Compiler, Cadence Genus) and be correctly converted into physical memory cells (such as standard SRAM macrocells) in the target technology library. The first synthesizable sub-model of memory is typically used to initialize memory modules, ensuring that the initial state of the memory in the hardware is consistent with the design requirements.

[0058] In some embodiments, the first memory synthesizable sub-model can be obtained directly based on pre-set parameters or generated by code based on the chip under test; this disclosure does not limit this.

[0059] The first synthesizable sub-model of memory only includes memory modules related to the chip under test. When performing low-power simulation related to the power supply circuit, it is necessary to associate the first synthesizable sub-model of memory with the power supply signal and ground signal of the power supply circuit in the low-power simulation, so as to generate a second synthesizable sub-model of memory corresponding to the power supply circuit in the low-power simulation, so as to ensure that low-power simulation including the power supply circuit can be achieved when simulating the target synthesizable model.

[0060] In some embodiments, a second memory synthesizable submodel corresponding to the power supply loop in the low-power simulation is generated based on the first memory synthesizable submodel. Specifically, this includes: adding the power supply port and ground port corresponding to the power supply loop in the low-power simulation to the first memory list to generate a second memory list; and generating a second memory synthesizable submodel corresponding to the power supply loop in the low-power simulation based on the second memory list.

[0061] The first memory list is the memory list of the first synthesizable submodel. It includes a memory initialization data file, typically stored in text format, containing memory initialization data, address mappings, and other information. During synthesis, the first synthesizable submodel reads data from the first memory list to initialize the memory module.

[0062] A second memory list is obtained by adding power and ground ports corresponding to the power supply loop in the low-power simulation to the first memory list. This second memory list contains information related to the power and ground signals in the power supply loop. By identifying the port information of the power and ground terminals in the second memory list, a synthesizable sub-model of the second memory, written in a hardware description language, can be generated based on the second memory list and associated with the power and ground signals in the power supply loop.

[0063] In some embodiments, a script can be used to identify the power and ground ports based on the names in a second memory list. Of course, other methods can also be used to identify the power and ground ports in the second memory list, and this disclosure does not limit this approach.

[0064] In some embodiments, the target synthesizable model includes a second pin interface synthesizable sub-model. Step 202: Determine the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model, including: determining a first pin interface synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated based on the initial synthesis model; and generating a second pin interface synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first pin interface synthesizable sub-model.

[0065] Specifically, in low-power simulations related to the power supply circuit, in addition to associating the synthesizable memory model with the power and ground signals in the power supply circuit, the behavior and function of the pins also need to be associated with the power and ground signals in the power supply circuit to verify the correctness of the signals and functions related to the power supply circuit.

[0066] In some embodiments, the first pin interface may synthesize sub-models including a PinAccess Device Model (PAD Model), an Input / Output Buffer Model (IOBUF Model), and / or a General Purpose Input / Output Model (GPIOModel).

[0067] The PAD Model describes the electrical characteristics and connection methods of the chip pins. It defines the behavior of the pins in different operating modes, ensuring correct pin connections and functionality. The PAD Model is used in the chip's physical design and verification phases to ensure correct pin connections and functionality.

[0068] An IOBUF Model is a module used in FPGA or ASIC designs to implement bidirectional I / O functionality. It can be configured as an input, output, or tri-state mode. The IOBUF Model ensures correct signal transmission and supports input / output control.

[0069] A GPIO Model describes the behavior of general-purpose input / output pins, allowing users to configure pin functions via software, such as input, output, or interrupt modes. GPIO Modes provide a flexible I / O interface, supporting various functional configurations.

[0070] In some embodiments, generating a second pin interface synthesizable submodel corresponding to the power supply loop in low-power simulation based on the first pin interface synthesizable submodel includes: replacing the first pin interface synthesizable submodel with a second pin interface synthesizable submodel carrying port information of power supply and ground terminals. This disclosure embodiment generates a second pin interface synthesizable submodel corresponding to the power supply loop in low-power simulation by replacing the PADModel with a PG Model, replacing IOBUF with a Model supporting PG synthesis, and replacing the GPIO Model with a PG version. This ensures that the target synthesizable model determined based on the second memory synthesizable submodel and the second pin interface synthesizable submodel is associated with the power supply and ground in the power supply loop, thereby more accurately achieving low-power simulation related to power supply and ground when simulating the target synthesizable model.

[0071] In some embodiments, generating a second pin interface synthesizable submodel corresponding to the power supply loop in the low-power simulation based on the first pin interface synthesizable submodel further includes: adding the port information of the power supply port and ground port corresponding to the power supply loop in the low-power simulation to the first pin interface synthesizable submodel to generate the second pin interface synthesizable submodel corresponding to the power supply loop in the low-power simulation. Of course, other methods can also be used to generate the second pin interface synthesizable submodel corresponding to the power supply loop in the low-power simulation based on the first pin interface synthesizable submodel, and this disclosure does not limit this method.

[0072] In some embodiments, the target synthesizable model includes a behavioral-level synthesizable sub-model. Step 202: Based on the initial synthesis model, determine the target synthesizable model corresponding to the chip to be simulated, including: based on the initial synthesis model, determine the non-synthesizable model of the register transfer level corresponding to the chip to be simulated; wherein, the non-synthesizable model includes a phase-locked loop simulation model and a physical layer simulation model; convert the non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behavioral-level synthesizable sub-model.

[0073] Non-synthesizable models refer to code or modules that cannot be converted into actual hardware circuits (gate-level netlists) using logic synthesis tools (such as Synopsys Design Compiler and Cadence Genus). These models are typically used for simulation, functional verification, or performance evaluation, but are not suitable for final chip implementation. When performing chip simulation verification, non-synthesizable models (also known as code) describing the chip's physical units are generally only suitable for simulator verification platforms on servers, and not for simulation accelerator verification platforms such as simulation accelerators. The characteristics of non-synthesizable models include abstract behavioral logic, simulation-specific syntax, dynamic or untestable structures, etc.

[0074] In some embodiments, the non-synthesizable model includes a phase-locked loop simulation model and a physical layer simulation model.

[0075] A PLL (Phase-Locked Loop) is a feedback control circuit used to generate an output signal that is synchronized with the phase and frequency of the input signal. PLLs are commonly used in applications such as clock generation, frequency synthesis, and clock recovery. A PLL simulation model is a model used to simulate the behavior of a PLL in a simulation environment, typically used to verify whether the PLL design meets timing and performance requirements.

[0076] The PHY (Physical Layer) is the lowest layer in the OSI network model, responsible for handling signal transmission and reception related to the physical medium. The PHY layer typically includes functions such as signal encoding, decoding, clock recovery, and signal driving.

[0077] A PHY simulation model is a model used to simulate the behavior of a PHY in a simulation environment. It is typically used to verify whether a PHY design meets communication protocols and performance requirements.

[0078] When it is necessary to verify a chip through an analog accelerator verification platform, it is usually necessary to modify the chip's underlying standard cell code (i.e., non-synthesizable model). The non-synthesizable logic in the underlying standard cell code will cause the netlist circuit function after chip synthesis to be inconsistent with the theoretical simulation function of the underlying standard cell code, making it impossible to verify the structure of the physical cell and resulting in insufficient chip verification.

[0079] In some embodiments, a non-synthesizable model is transformed into a synthesizable model with the same behavioral logic to obtain a behaviorally synthesizable sub-model. Specifically, this may include: determining the transformation rule corresponding to the model type in the non-synthesizable model; and transforming the non-synthesizable model into a synthesizable model with the same behavioral logic based on the transformation rule to obtain a behaviorally synthesizable sub-model.

[0080] Specifically, the model types in the non-synthesizable model can be classified based on the functionality of the corresponding physical units or on code logic; this disclosure does not impose any restrictions on this. The conversion rules corresponding to the model types can be set based on the different code description rules of the behavioral models of the physical units in the non-synthesizable model and the synthesizable model. For example, the functionality implemented by the physical units can be determined based on the physical unit documentation of the chip to be verified. These physical units can then be classified, and the functionality of each type of physical unit can be analyzed to identify the similarities and differences in the behavioral models of different cases of the same type of physical units within the synthesizable model. Based on this, the conversion rules for converting the behavioral models of each type of physical unit into synthesizable models can be determined. Of course, these conversion rules can also be pre-set based on the model type; this disclosure does not impose any restrictions on this.

[0081] This disclosure converts the non-synthesizable model of the physical units of the chip under test into a behaviorally synthesizable sub-model that meets the conditions of the target verification platform. Then, based on the target synthesizable model, the chip under test is simulated and verified using a hardware-accelerated simulation platform to obtain simulation verification results. This enables simulation verification of the chip under test using hardware-accelerated simulation platforms such as Emulator without modifying the original design code. Since the behavioral logic of the synthesizable model and the behavioral model is consistent, the consistency between the gate-level netlist circuit function of the synthesized chip and the theoretical simulation function of the behavioral-level code can be maintained, thus not affecting the verification of the physical unit structure of the chip under test and contributing to the sufficiency of chip simulation verification.

[0082] In some embodiments, transforming a non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behaviorally synthesizable sub-model includes: in response to the non-synthesizable model having the same function as a preset function, transforming the non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behaviorally synthesizable sub-model; in response to the non-synthesizable model having a different function from the preset function, generating a virtual module based on the non-synthesizable model, the virtual module containing port information corresponding to the non-synthesizable model.

[0083] Specifically, non-synthesizable models include multiple sub-models. Some non-synthesizable models may only be used for testing platforms. For example, reference models are used to generate expected results, and stimulus generation models are used to generate complex test confidence. The functions of these modules do not need to be implemented in hardware; they are only used as auxiliary tools for verification.

[0084] In this embodiment, it is first necessary to determine whether the function to be implemented by the non-synthesizable model is consistent with the preset function that needs to be implemented in hardware. If it is confirmed that the function of the model is the hardware function that needs to be finally implemented, then the non-synthesizable model needs to be transformed into a corresponding behavioral-level synthesizable sub-model, which can then be integrated into a larger design and sent to the synthesis tool. If it is determined that the model is just a pure verification component and does not contain any implementable hardware functions, then a virtual module (or shell module) can be created for the non-synthesizable model.

[0085] The virtual module only includes port declarations; that is, the module name, inputs, outputs, bit width, etc., of the virtual module must be completely consistent with the original model to ensure correct connection with other modules. Furthermore, the virtual module has no internal logic; its output is usually set to a constant (e.g., 0, 'bz high impedance state) or remains in an undriven state ('bx undetermined state), and sometimes simple print statements may be added. The display function is used for debugging, etc.

[0086] The purpose of virtual modules is to serve as placeholders during top-level integration, ensuring correct net connections and avoiding compilation errors. During final synthesis, the synthesis tool only processes synthesizable behavioral-level synthesizable sub-models.

[0087] Figure 3 This is a schematic diagram of a simulation provided for an embodiment of this disclosure. (As shown...) Figure 3As shown, before performing low-power simulation of the target synthesizable model and target gate-level netlist based on the preset hardware simulation accelerator in step 204 above, three synthesizable models need to be prepared: a second pin interface synthesizable sub-model related to the power supply loop, a second memory synthesizable sub-model related to the power supply loop, and a behavioral synthesizable sub-model. This will yield the target synthesizable model and the target gate-level netlist related to the power supply loop, thereby enabling the simulation verification of the power supply loop in low power consumption when performing simulation based on the preset hardware simulation accelerator.

[0088] Figure 4 A flowchart of yet another low-power simulation method provided in this disclosure embodiment.

[0089] like Figure 4 As shown, in some embodiments, in simulation flow 400, the simulation method includes not only steps 201-204 of simulation flow 200, but also:

[0090] Step 401: Based on the initial synthesis model, determine the initial synthesizable model.

[0091] Specifically, the initial synthesizable model refers to a synthesizable model that is independent of the power supply loop. In addition to the first memory synthesizable sub-model, the initial synthesizable model also includes other necessary synthesizable sub-models for simulation verification, such as synthesizable sub-models related to pin interfaces and behavioral-level sub-models that transform non-synthesizable models into synthesizable ones.

[0092] Step 402: Compile the initial synthesizable model to obtain the initial data version file.

[0093] Specifically, the initial data version file refers to the intermediate code file generated by compiling the primary synthesizable model. This intermediate code file includes simple-level gate-level netlist information generated by converting RTL code using synthesis tools. This simple-level gate-level netlist information is generated during the front-end design phase and is mainly used to verify whether the logical functionality of the design is correct. It does not contain test logic and is used for preliminary logic verification and timing analysis, forming the basis for subsequent physical design.

[0094] Step 403: Determine the initial gate-level netlist based on the gate-level netlist information recorded in the initial data version file.

[0095] Specifically, based on a simple gate-level netlist, to detect manufacturing defects, test logic (such as scan chains, built-in self-tests, etc.) is inserted to generate a more complex gate-level netlist, resulting in a primary gate-level netlist. This primary gate-level netlist is a Design for Testability netlist (DFT netlist) and is independent of the power supply loop. This primary gate-level netlist not only verifies the logical functionality of the design but also verifies the correctness of the test logic, thereby improving the chip's testability and ensuring that the manufactured chip can pass tests.

[0096] Figure 5 A flowchart of another low-power simulation method provided in an embodiment of this disclosure.

[0097] like Figure 5 As shown, process 500 and Figure 4 The only difference between the corresponding process 400 and the process 400 is that... Figure 5 right Figure 4 The step of generating the second memory synthesizable sub-model in step 202 has been further defined, while the other steps are the same. The other steps will not be repeated here.

[0098] In some embodiments, step 202, generating a second memory synthesizable model corresponding to the power supply loop in the low-power simulation based on the first memory synthesizable submodel, includes the following steps:

[0099] Step 501: Debug the test cases corresponding to the chip to be simulated based on the initial data version file to obtain the first test results corresponding to the first synthesizable sub-model of memory.

[0100] Specifically, after compiling the RTL-level Emulator simulation platform, the test cases to be tested corresponding to the chip to be simulated are debugged on the SOC. The test cases to be tested may only include basic test cases related to the basic functions of the simulation platform, which are used to verify whether there are errors in the first memory synthesizable sub-model determined in step 201, so as to ensure the accuracy when performing subsequent operations based on the first memory synthesizable sub-model.

[0101] If an error is found in the first test result, it indicates that there is an error in the first memory synthesizable model. Then, continue to execute the following steps 502 to 503.

[0102] Step 502: Update the first memory synthesizable sub-model based on the errors in the first test results.

[0103] Specifically, the first synthesizable submodel of memory can be updated based on the error type in the first test result. For example, if the error type in the first test result indicates that the first synthesizable submodel of memory includes content unrelated to the first synthesizable submodel of memory, the corresponding content causing the error can be deleted to obtain the updated first synthesizable submodel of memory. As another example, if the error type in the first test result indicates that a memory submodel has a name inconsistency error, the name of the memory submodel can be corrected according to the preceding and following logic, and so on. The error types in the first test result can also include syntax errors, logic errors, memory mapping errors, address errors, etc., which are not limited in this disclosure.

[0104] Step 503: Based on the updated first memory synthesizable sub-model, generate a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation.

[0105] Optionally, after obtaining the updated first memory synthesizable sub-model, steps 401, 402, and 501 can be executed again based on the updated first memory synthesizable sub-model to perform the above compilation and test case debugging steps on the updated first memory synthesizable sub-model, so as to further determine the accuracy of the updated first memory synthesizable model, thereby ensuring the accuracy of the power supply circuit simulation in the subsequent low-power simulation.

[0106] Returning to step 501, if there are no errors in the first test result, it means that there are no errors in the first memory synthesizable model, then continue to execute step 504 (that is, directly execute step 202 in process 400).

[0107] Step 504: Based on the first synthesizable sub-model, generate a second synthesizable sub-model corresponding to the power supply circuit in the low-power simulation.

[0108] This embodiment of the disclosure compiles the first synthesizable submodel of memory and debugs the test cases corresponding to the chip to be simulated on the SOC. It can determine whether there are errors in the first synthesizable submodel of memory based on the test results, and update the first synthesizable submodel of memory if there are errors in the test results. This ensures that the first synthesizable submodel used to generate the second synthesizable submodel of memory is error-free, thereby ensuring the accuracy of subsequent simulation of the power supply circuit in low power consumption.

[0109] In some embodiments, the first test result includes the first test case that has passed debugging in the test cases to be tested; step 204: Based on the initial gate-level netlist corresponding to the chip to be simulated, generate a target gate-level netlist corresponding to the power supply loop in the low-power simulation, including:

[0110] The initial gate-level netlist corresponding to the chip to be simulated is compiled, and the first test case is used to test the compiled initial gate-level netlist to obtain the second test result; in response to the existence of errors in the second test result, the compiled initial gate-level netlist is updated based on the errors in the second test result to obtain the updated gate-level netlist; based on the updated gate-level netlist, the target gate-level netlist corresponding to the power supply loop in the low-power simulation is generated.

[0111] Specifically, as mentioned above Figure 4 In the corresponding embodiment, the initial synthesizable model is compiled to obtain a simple gate-level netlist in the initial data version file. The initial gate-level netlist is a more complex gate-level netlist generated based on this simple netlist. Therefore, in Figure 5 In the corresponding embodiment, in step 501, when debugging the test cases to be tested corresponding to the chip to be simulated based on the initial data version file, the primary gate-level netlist is not verified, and the accuracy of the primary gate-level netlist cannot be guaranteed.

[0112] Therefore, in this embodiment, the initial gate-level netlist is further compiled and debugged to verify its accuracy. Similar to the processing of the first memory sub-model described above, after testing the compiled initial gate-level netlist using the first test case and obtaining the second test result, if an error exists in the second test result, it indicates that an error exists in the obtained initial gate-level netlist. Based on the error type in the second test result, the initial gate-level netlist is updated to obtain the updated gate-level netlist. Then, a target gate-level netlist corresponding to the power supply loop in the low-power simulation is generated based on the updated gate-level netlist. The error types in the second test result include test control logic errors, scan connection configuration errors, etc. This disclosure does not limit the error types in the second test result.

[0113] If there are no errors in the second test results, it means that there are also no errors in the initial gate-level netlist. Therefore, the target gate-level netlist corresponding to the power supply circuit in the low-power simulation can be directly generated based on the initial gate-level netlist.

[0114] This embodiment of the disclosure, by compiling the initial gate-level netlist and debugging it using test cases, can ensure the accuracy of the initial gate-level netlist used to generate the target gate-level netlist corresponding to the power supply loop in the low-power simulation, thereby ensuring the accuracy of the generated target gate-level netlist and further ensuring the accuracy of the subsequent simulation results for the low-power simulation.

[0115] In some embodiments, step 205, performing low-power simulation of the target synthesizable model and the target gate-level netlist, including power supply loops, based on a preset hardware simulation accelerator, includes: compiling the target synthesizable model and the target gate-level netlist to obtain a target data version file based on the preset hardware simulation accelerator; and performing low-power simulation of power-on and / or power-off based on the target data version file.

[0116] Specifically, parameters related to the power supply and ground in the power supply circuit are added to the compilation script to obtain the modified compilation script; based on the preset hardware simulation accelerator, the target synthesizable model and the target gate-level netlist are compiled according to the modified compilation script to obtain the target data version file.

[0117] The target data version file refers to the intermediate code file related to the power supply circuit obtained through compilation. After compilation and synthesis, simulation begins based on the generated target data version file. Following the power-on and power-off procedures of the PMU (Power Management Unit) module, the SoC subsystem is simulated using the power-on procedure → execution of normal test cases → power-off procedure, thus completing the low-power simulation of power supply power-on and / or power-off. The power-on operation can be controlled via VDD / VSS pins on the chip.

[0118] In some embodiments, low-power simulation of power-on and / or power-off based on a target data version file includes: triggering a first interrupt in the firmware in response to a firmware-initiated low-power simulation request instruction; controlling a hardware simulation accelerator to perform a first power-on power assignment operation based on the received first interrupt; wherein the power-on power assignment operation is used to place the power supply in a power-on state or a power-off state; controlling the hardware simulation accelerator to perform a second power-on power assignment operation opposite to the first power-on power assignment operation when a first preset condition is met; and controlling the hardware simulation accelerator to deactivate the first interrupt in the firmware when a second preset condition is met.

[0119] Specifically, firmware is a program that sits between hardware and software. It is "burned" into the hardware device and is responsible for controlling the basic functions of the hardware; it is a special type of software. The relationship between firmware and power-on / off operations is a close collaboration where the firmware initiates requests, the hardware emulator actually executes them, and synchronization is achieved through an interrupt mechanism.

[0120] The firmware contains power-down / power-on process control code, which controls the execution conditions for power-down / power-on and the order in which various power domains are turned off or on. However, the firmware cannot directly control the power network in the Emulator environment.

[0121] The hardware emulator is the main entity responsible for executing physical power supply operations. The emulator simulates the entire hardware logic of the SoC, including the registers of the power management unit, but it typically does not directly simulate real current-voltage (VDD) power-on / off waveforms and distributed networks. Upon receiving a low-power emulation request from the firmware, the hardware emulator is responsible for simulating the effects of power-on and power-off in the simulation environment, such as forcibly setting a signal in a power domain to 0 (power-off) or restoring it (power-on).

[0122] The specific process of performing low-power simulation is as follows: When the firmware reaches the power-on / power-off procedure, it triggers a first interrupt signal sent to the Emulator. After triggering the interrupt, the firmware immediately enters a busy-wait loop or a low-power state, pausing the execution of subsequent code and waiting for the Emulator to complete the actual operation. The monitoring program on the Emulator side captures the first interrupt sent by the firmware. The Emulator then performs the corresponding power-on operation. For example, the Emulator first performs the corresponding power-off operation: saving the state of all registers / memory in the target power domain to a backup area of ​​the simulation environment, and then forcibly setting all signals in that domain to 0 (or X state) to simulate the power-off effect. After the power-off operation is completed, the corresponding power-on operation is performed: restoring the state of all registers / memory in that power domain from the backup area, releasing the forced values ​​of the signals, allowing the simulation to continue normally, simulating the power-on and recovery state. When the Emulator completes the power-on / power-off operation, it releases the first interrupt that previously blocked the firmware (or triggers a completion interrupt). The firmware detects that the first interrupt has been released (or receives a completion interrupt) in the loop, exits the waiting loop, and continues to execute the subsequent code of the power-off / power-on procedure. The power-down process likely leads to actual hibernation; the power-on process may involve checking system status and restoring the current state.

[0123] The first preset condition refers to the condition that triggers the second power switch electrical assignment operation. In other words, the first preset condition is used to indicate the completion of the first power switch electrical assignment operation. Specifically, after the first power switch electrical assignment operation is performed, the power supply is in the state corresponding to the first power switch electrical assignment operation. The relevant program is executed in this state. Once the relevant program is completed, and no further operation is needed in the state corresponding to the first power switch electrical assignment operation, the condition for the second power switch electrical assignment operation is triggered to restore the power supply from the state corresponding to the first power switch electrical assignment operation to its original state (i.e., the state corresponding to the second power switch electrical assignment operation). Similarly, the second preset condition is used to indicate the completion of the second power switch electrical assignment operation.

[0124] In some embodiments, triggering a first interrupt in the firmware includes writing first data to a reserved register in the firmware to trigger the first interrupt. Correspondingly, deactivating the first interrupt in the firmware includes controlling a hardware emulation accelerator to write second data to a reserved register to deactivate the first interrupt by triggering a second interrupt.

[0125] Specifically, when the firmware reaches the power-down procedure, it can trigger an interrupt signal sent to the emulator by writing a value to a pre-defined reserved register (either a simulation-specific register or via a specific sequence). This register / mechanism is specifically designed for simulation verification. After the emulator completes the power-up / power-down operation, it can also use the same register / mechanism to release the first interrupt that previously blocked the firmware (or trigger a completion interrupt). Thus, when the firmware detects that the first interrupt has been released (or receives a completion interrupt) in the loop, it exits the waiting loop and continues executing the subsequent code of the power-down / power-up procedure.

[0126] Figure 6 This is a schematic diagram illustrating the simulation of power-on and power-off in an embodiment of this disclosure.

[0127] In some embodiments, low-power simulation of power-on and / or power-off is performed based on a target data version file, including the following steps:

[0128] Step 601: In response to receiving a low-power emulation instruction, write the first data to the reserved register in the firmware to trigger the first interrupt.

[0129] Specifically, during the process of powering down / up on the SoC, the power supply VDD needs to be switched on and off in the firmware, and the hardware emulation accelerator does not directly support this operation.

[0130] The firmware runs using the first language code, and the two language codes cannot run simultaneously. Therefore, upon receiving a low-power emulation instruction, writing the first data into a reserved register in the firmware using the second language code will trigger a first interrupt, interrupting the first language code that was running in the firmware. Optionally, the first language code can be C language, and the second language code can be a TDF scripting language.

[0131] Step 602: Control the hardware simulation accelerator to perform a first power switch assignment operation based on the received first interrupt, wherein the power switch assignment operation is used to put the power supply into a power-on state or a power-off state.

[0132] Specifically, such as Figure 6As shown, the hardware simulation accelerator is waiting for interrupt 1 to be triggered. After the hardware simulation accelerator receives the first interrupt, it starts the first power switch assignment operation to simulate the power-on and / or power-off of the power supply.

[0133] Step 603: When the preset conditions are met, control the hardware simulation accelerator to perform the second power switch electrical assignment operation.

[0134] Specifically, the first power switch assignment operation and the second power switch assignment operation are opposite operations. That is, if the first power switch assignment operation is a power-on operation, then the second power switch assignment operation is a power-off operation. Conversely, if the first power switch assignment operation is a power-off operation, then the second power switch assignment operation is a power-on operation.

[0135] The preset conditions refer to the conditions that trigger the second power switch electrical assignment operation. Specifically, after the first power switch electrical assignment operation is performed, the power supply is in the state corresponding to the first power switch electrical assignment operation. The relevant program is executed in the state corresponding to the first power switch electrical assignment operation. When the relevant program is completed, and no further operation is required in the state corresponding to the first power switch electrical assignment operation, the conditions for the second power switch electrical assignment operation are triggered to restore the power supply from the state corresponding to the first power switch electrical assignment operation to its original state (i.e., the state corresponding to the second power switch electrical assignment operation).

[0136] Step 604: Control the hardware simulation accelerator to write second data into the reserved register to trigger the second interrupt, so as to complete the low-power simulation of the chip under test.

[0137] Specifically, after the power supply is restored from the state corresponding to the first power switch assignment operation to its original state (i.e., the state corresponding to the second power switch assignment operation), that is, after the low-power simulation of the chip under test is completed, the hardware simulation accelerator writes the second data into the reserved register in the firmware, which triggers the second interrupt. When the firmware detects this second interrupt, it can continue to execute the subsequent program.

[0138] This disclosure employs an indirect handshake mechanism to facilitate interaction between the hardware emulation accelerator and the software firmware. This addresses the issue that the hardware emulation accelerator does not directly support power switching operations during the SoC power-down / power-on process, thereby enabling low-power simulation, including power supply circuitry, based on the hardware emulation accelerator provided in this disclosure.

[0139] In some embodiments, after performing low-power simulation on the power-on and / or power-off of the power supply to confirm that the test cases of the chip under test are executed correctly, the waveform can be used to further confirm whether the power-on and power-off operation process meets expectations, so as to reduce the risk of subsequent chip tape-out.

[0140] The low-power simulation method proposed in this disclosure utilizes a hardware simulation accelerator to accelerate the simulation of the PG low-power of the chip under test. This method greatly accelerates the simulation convergence time of PG low-power by innovating the traditional software simulation process, thereby reducing the risk of chip tape-out.

[0141] Based on the same inventive concept as the above simulation method, this disclosure also provides a low-power simulation device.

[0142] Figure 7 This is a structural block diagram of a low-power simulation device provided in an embodiment of the present disclosure.

[0143] Further reference Figure 7 As an implementation of the methods shown in the above figures, this device embodiment is similar to... Figure 2 Corresponding to the method embodiments shown, this device can be specifically applied to various electronic devices.

[0144] like Figure 7 As shown, the low-power simulation device 700 of this embodiment may include: a first determining module 701, a second determining module 702, a generating module 703, and a simulation module 704.

[0145] The first determining module 701 is used to determine the initial synthesis model of the register-transfer level corresponding to the chip to be simulated. The second determining module 702 is used to determine the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model. The generating module 703 is used to generate the target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated. The simulation module 704 is used to perform low-power simulation, including the power supply loop, on the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator.

[0146] In this embodiment, the specific processing of the first determining module 701, the second determining module 702, the generating module 703, and the simulation module 704 in the low-power simulation device 700, and the resulting technical effects, can be found in reference to [reference needed]. Figure 2 The relevant descriptions of steps 201-204 in the corresponding embodiments will not be repeated here.

[0147] The low-power simulation apparatus 700 provided in this disclosure comprises two parts: firstly, a second determining module 702 generates a target synthesizable model corresponding to the power supply loop in the low-power simulation based on the initial synthesis model of the register-transfer level corresponding to the chip to be simulated, determined by the first determining module 701; secondly, a generating module 703 generates a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated. The simulation module 704, after associating both the target synthesizable model and the target gate-level netlist with the power supply loop in the low-power simulation, then uses a hardware simulation accelerator to perform low-power simulation of the target synthesizable model and the target gate-level netlist, including the power supply loop. The low-power simulation apparatus of this disclosure can realize low-power simulation of the power supply loop based on a hardware simulation accelerator, greatly accelerating the simulation convergence time of the power supply loop and reducing the risk of chip fabrication.

[0148] In some embodiments, the target synthesizable model includes a second memory synthesizable sub-model, and the second determining module 702 is specifically used to generate a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first memory synthesizable sub-model, wherein the power supply circuit includes a power supply terminal and a ground terminal.

[0149] In some embodiments, the second determining module 702 is further configured to add the power supply port and ground port corresponding to the power supply circuit in the low-power simulation to the first memory list to generate a second memory list, wherein the first memory list is the memory list of the first memory synthesizable sub-model; and generate a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the second memory list.

[0150] In some embodiments, the target synthesizable model includes a second pin interface synthesizable sub-model, and the second determining module 702 is further configured to determine a first pin interface synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated based on the initial synthesis model; and generate a second pin interface synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the first pin interface synthesizable sub-model.

[0151] In some embodiments, the first pin interface may synthesize sub-models including pin access device models, input / output buffer models, and / or general input / output models.

[0152] In some embodiments, the target synthesizable model includes a behavioral-level synthesizable sub-model, and the second determining module 702 is further configured to determine the non-synthesizable model of the register transfer level corresponding to the chip to be simulated based on the initial synthesis model; wherein, the non-synthesizable model includes a phase-locked loop simulation model and a physical layer simulation model; the non-synthesizable model is converted into a synthesizable model with the same behavioral logic to obtain a behavioral-level synthesizable sub-model.

[0153] In some embodiments, the second determining module 702 is further configured to, in response to the fact that the function corresponding to the non-synthesizable model is the same as the preset function, convert the non-synthesizable model into a synthesizable model with the same behavioral logic to obtain a behavioral-level synthesizable sub-model; and in response to the fact that the function corresponding to the non-synthesizable model is different from the preset function, generate a virtual module based on the non-synthesizable model, wherein the virtual module contains port information corresponding to the non-synthesizable model.

[0154] In some embodiments, the low-power simulation device 700 includes not only a first determining module 701, a second determining module 702, a generating module 703, and a simulation module 704, but also a third determining module, a compiling module, and a fourth determining module. The third determining module is used to determine an initial synthesizable model based on the initial synthesis model; the compiling module is used to compile the initial synthesizable model to obtain an initial data version file; and the fourth determining module is used to determine an initial gate-level netlist based on the gate-level netlist information recorded in the initial data version file.

[0155] In some embodiments, the first determining module 701 is further configured to debug the test cases to be tested corresponding to the chip to be simulated based on the initial data version file, and obtain a first test result corresponding to the first memory synthesizable sub-model; in response to the existence of an error in the first test result, update the first memory synthesizable sub-model based on the error in the first test result; and generate a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation based on the updated first memory synthesizable sub-model.

[0156] The first test result includes the first test case that has passed debugging among the test cases to be tested.

[0157] In some embodiments, the generation module 703 is specifically used to compile an initial gate-level netlist corresponding to the chip to be simulated, and to test the compiled initial gate-level netlist using a first test case to obtain a second test result; in response to an error in the second test result, to update the compiled initial gate-level netlist based on the error in the second test result to obtain an updated gate-level netlist; and to generate a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the updated gate-level netlist.

[0158] In some embodiments, the simulation module 704 is specifically used to compile the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator to obtain a target data version file; and to perform low-power simulation of power-on and / or power-off based on the target data version file.

[0159] In some embodiments, the simulation module 704 is specifically configured to respond to a firmware-initiated low-power simulation request instruction, trigger a first interrupt in the firmware; control the hardware simulation accelerator to perform a first power switch assignment operation based on the received first interrupt; wherein the power switch assignment operation is used to place the power supply in a power-on state or a power-off state; control the hardware simulation accelerator to perform a second power switch assignment operation opposite to the first power switch assignment operation when a first preset condition is met; and control the hardware simulation accelerator to deactivate the first interrupt in the firmware when a second preset condition is met.

[0160] In some embodiments, the simulation module 704 is specifically configured to write first data into a reserved register in the firmware to trigger a first interrupt; and control the hardware simulation accelerator to write second data into the reserved register to cancel the first interrupt by triggering a second interrupt.

[0161] In some embodiments, the simulation module 704 is specifically configured to, in response to receiving a low-power simulation instruction, write first data to a reserved register in the firmware to trigger a first interrupt; control the hardware simulation accelerator to perform a first power switch assignment operation according to the received first interrupt, wherein the power switch assignment operation is used to place the power supply in a power-on state or a power-off state; control the hardware simulation accelerator to perform a second power switch assignment operation when a preset condition is met; and control the hardware simulation accelerator to write second data to a reserved register to trigger a second interrupt, so as to complete the low-power simulation of the chip under test.

[0162] The specific implementation details and technical effects of the low-power simulation device embodiments provided in this disclosure are the same as the implementation details and technical effects of the low-power simulation method embodiments described above, and will not be repeated here.

[0163] This embodiment exists as a device embodiment corresponding to the above method embodiment. The low-power simulation device provided in this embodiment includes, on one hand, a second determining module 702 generating a target synthesizable model corresponding to the power supply loop in the low-power simulation based on the initial synthesis model of the register transfer level corresponding to the chip to be simulated determined by the first determining module 701; on the other hand, a generating module 703 generating a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated. After associating both the target synthesizable model and the target gate-level netlist with the power supply loop in the low-power simulation, the simulation module 704 then uses a hardware simulation accelerator to perform low-power simulation of the target synthesizable model and the target gate-level netlist, including the power supply loop. The low-power simulation device disclosed above can realize low-power simulation of the power supply loop based on a hardware simulation accelerator, greatly accelerating the simulation convergence time of the low-power supply loop and reducing the risk of chip fabrication.

[0164] Furthermore, in the low-power simulation device 700 provided in this disclosure, the first determining module 701 and the generating module 703 also obtain corresponding test results by debugging the test cases to be tested corresponding to the chip to be simulated; and when there are errors in the test results, update the first memory synthesizable sub-model and the primary gate-level netlist to ensure the accuracy of the first memory synthesizable sub-model and the primary gate-level netlist, thereby ensuring the accuracy of the final target synthesizable model and the target gate-level netlist, and thus achieving the accuracy of low-power simulation.

[0165] According to embodiments of this disclosure, this disclosure also provides an electronic device, the electronic device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to implement the low-power simulation method described in any of the above embodiments when executed.

[0166] Figure 8 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 8 As shown, the electronic device 800 of this embodiment includes a processor 801 and a memory 802; wherein, the memory 802 is used to store computer execution instructions; the processor 801 is used to execute the computer execution instructions stored in the memory to implement the various steps performed by the electronic device in the above embodiment. For details, please refer to the relevant descriptions in the foregoing method embodiments. For example, the electronic device 800 can be a general-purpose processor, a graphics processing device, a neural network computing device, or a graph neural network computing device.

[0167] In some embodiments, the memory 802 can be either standalone or integrated with the processor 801.

[0168] When the memory 802 is set up independently, the electronic device also includes a bus 803 for connecting the memory 802 and the processor 801.

[0169] It should be understood that the processor 801 described above can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), etc. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this invention can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0170] The memory 802 may include high-speed RAM memory, and may also include non-volatile memory NVM, such as at least one disk storage device, and may also be a USB flash drive, portable hard drive, read-only memory, disk or optical disc, etc.

[0171] Bus 803 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, the buses shown in the accompanying drawings are not limited to a single bus or a single type of bus.

[0172] This disclosure also provides a computer storage medium storing computer execution instructions, which, when executed by a processor, implement the steps of the low-power simulation method of any of the above method embodiments.

[0173] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the low-power simulation method according to any of the above embodiments.

[0174] In the several embodiments provided by this invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0175] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to implement the solution of this embodiment according to actual needs.

[0176] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each module can exist physically separately, or two or more modules can be integrated into one unit. The unit composed of the above modules can be implemented in hardware or in the form of hardware plus software functional units.

[0177] The integrated modules described above, implemented as software functional modules, can be stored in a computer-readable storage medium. These software functional modules, stored in a storage medium, include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute partial steps of the methods in the various embodiments of this application.

[0178] The aforementioned storage medium can be implemented from any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk. The storage medium can be any available medium accessible to general-purpose or special-purpose computers.

[0179] An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium can be an integral part of the processor. Both the processor and the storage medium can reside in an Application Specific Integrated Circuit (ASIC). Alternatively, the processor and storage medium can exist as discrete components in an electronic device or host device.

[0180] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0181] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0182] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this disclosure can be achieved, and this is not limited herein.

[0183] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A low-power simulation method, characterized in that, The method includes: Determine the initial synthesis model of the register-transfer stage corresponding to the chip to be simulated; wherein, the initial synthesis model includes an initial synthesizable model and / or an initial non-synthesizable model, and the initial synthesis model is independent of the power supply loop; The initial synthesis model is correlated with the power supply signal and ground signal of the power supply circuit in the low-power simulation to obtain the target synthesizable model corresponding to the chip to be simulated. Based on the initial gate-level netlist corresponding to the chip to be simulated, generate the target gate-level netlist corresponding to the power supply loop in the low-power simulation. Based on a pre-set hardware simulation accelerator, a low-power simulation, including a power supply loop, is performed on the target synthesizable model and the target gate-level netlist; wherein, the power supply loop includes a power supply terminal and a ground terminal.

2. The method according to claim 1, characterized in that, The target synthesizable model includes a second in-memory synthesizable sub-model. The step of determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: Based on the initial synthesis model, determine the first memory synthesizable sub-model of the register transfer stage corresponding to the chip to be simulated; Based on the first memory synthesizable sub-model, a second memory synthesizable sub-model corresponding to the power supply circuit in the low-power simulation is generated.

3. The method according to claim 2, characterized in that, The step of generating a second memory synthesizable submodel corresponding to the power supply circuit in the low-power simulation based on the first memory synthesizable submodel includes: Add the power supply port and ground port corresponding to the power supply circuit in the low-power simulation to the first memory list to generate the second memory list; wherein, the first memory list is the memory list of the first memory synthesizable submodel; Based on the second memory list, a second synthesizable sub-model of memory corresponding to the power supply circuit in the low-power simulation is generated.

4. The method according to any one of claims 1-3, characterized in that, The target synthesizable model includes a second pin interface synthesizable sub-model; The step of determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: Based on the initial synthesis model, determine the synthesizable sub-model of the first pin interface of the register transfer stage corresponding to the chip to be simulated; Based on the first pin interface synthesizable sub-model, a second pin interface synthesizable sub-model corresponding to the power supply circuit in the low-power simulation is generated.

5. The method according to claim 4, characterized in that, The first pin interface can synthesize sub-models including pin access device models, input / output buffer models, and / or general input / output models.

6. The method according to claim 4, characterized in that, The target synthesizable model includes a behavior-level synthesizable sub-model; The step of determining the target synthesizable model corresponding to the chip to be simulated based on the initial synthesis model includes: Based on the initial synthesis model, the non-synthesizable model of the register transfer stage corresponding to the chip to be simulated is determined; wherein, the non-synthesizable model includes a phase-locked loop simulation model and a physical layer simulation model; The non-synthesizable model is transformed into a synthesizable model with the same behavioral logic, resulting in a behavioral-level synthesizable sub-model.

7. The method according to claim 6, characterized in that, The process of transforming the non-synthesizable model into a synthesizable model with the same behavioral logic, resulting in a behaviorally synthesizable sub-model, includes: In response to the fact that the function corresponding to the non-synthesizable model is the same as the preset function, the non-synthesizable model is transformed into a synthesizable model with the same behavioral logic, thus obtaining a behavioral-level synthesizable sub-model. In response to the fact that the function corresponding to the non-synthesizable model is different from the preset function, a virtual module is generated based on the non-synthesizable model, and the virtual module contains port information corresponding to the non-synthesizable model.

8. The method according to claim 2, characterized in that, The method further includes: Based on the initial synthesis model, determine the initial synthesizable model; The initial synthesizable model is compiled to obtain an initial data version file; The initial gate-level netlist is determined based on the gate-level netlist information recorded in the initial data version file.

9. The method according to claim 8, characterized in that, The step of generating a second memory synthesizable submodel corresponding to the power supply circuit in the low-power simulation based on the first memory synthesizable submodel includes: Based on the initial data version file, debug the test cases to be tested corresponding to the chip to be simulated, and obtain the first test result corresponding to the first memory synthesizable sub-model; In response to an error in the first test result, the first memory synthesizable sub-model is updated based on the error in the first test result; Based on the updated first memory synthesizable submodel, a second memory synthesizable submodel corresponding to the power supply loop in the low-power simulation is generated.

10. The method according to claim 9, characterized in that, The first test result includes the first test case that has passed debugging among the test cases to be tested; The step of generating a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated includes: The initial gate-level netlist corresponding to the chip to be simulated is compiled, and the first test case is used to test the compiled initial gate-level netlist to obtain the second test result; In response to an error in the second test result, the initial gate-level netlist compiled by the compiler is updated based on the error in the second test result to obtain the updated gate-level netlist; Based on the updated gate-level netlist, a target gate-level netlist corresponding to the power supply loop in the low-power simulation is generated.

11. The method according to claim 1, characterized in that, The preset hardware simulation accelerator performs low-power simulation, including power supply loops, on the target synthesizable model and the target gate-level netlist, including: Based on a preset hardware simulation accelerator, the target synthesizable model and the target gate-level netlist are compiled to obtain the target data version file; Low-power simulations are performed on power-on and / or power-off of the power supply based on the target data version file.

12. The method according to claim 11, characterized in that, The low-power simulation of power-on and / or power-off based on the target data version file includes: In response to the firmware initiating a low-power emulation request command, the first interrupt of the firmware is triggered; The hardware simulation accelerator is controlled to perform a first power switch assignment operation based on the received first interrupt; wherein the power switch assignment operation is used to put the power supply into a power-on state or a power-off state. When the hardware simulation accelerator meets the first preset condition, it performs a second power switch electrical assignment operation that is the opposite of the first power switch electrical assignment operation. When the hardware emulation accelerator meets the second preset condition, it releases the first interrupt in the firmware.

13. The method according to claim 12, characterized in that, The first interrupt of the trigger firmware includes: Write first data into the reserved register in the firmware to trigger the first interrupt; Deactivating the first interrupt in the firmware includes: The hardware emulation accelerator is controlled to write second data into the reserved register in order to cancel the first interrupt by triggering a second interrupt.

14. A low-power simulation device, characterized in that, The device includes: The first determining module is used to determine the initial synthesis model of the register transfer stage corresponding to the chip to be simulated; wherein, the initial synthesis model includes an initial synthesizable model and / or an initial non-synthesizable model, and the initial synthesis model is independent of the power supply loop; The second determining module is used to associate the initial synthesis model with the power supply signal and ground signal of the power supply circuit in the low power simulation to obtain the target synthesizable model corresponding to the chip to be simulated. The generation module is used to generate a target gate-level netlist corresponding to the power supply loop in the low-power simulation based on the initial gate-level netlist corresponding to the chip to be simulated. The simulation module is used to perform low-power simulation, including power supply loops, on the target synthesizable model and the target gate-level netlist based on a preset hardware simulation accelerator.

15. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the low-power simulation method according to any one of claims 1-13.

16. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to execute the low-power simulation method according to any one of claims 1-13.

17. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the low-power simulation method according to any one of claims 1-13.

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