A low-power ATPG method, apparatus, chip, chip module, and terminal device

Abstract

This invention discloses a low-power ATPG method, apparatus, chip, chip module, and terminal device. The low-power ATPG method involves minimizing inverter insertion / deletion in the scan chain data path without altering the functional path. This maximizes the shutdown of the chip's integrated clock gating after Shift-0 vector loading, significantly reducing capture-to-flip rate and shift-to-flip rate. This method modifies only the scan chain data structure without affecting the functional path timing, offering advantages such as minimal hardware overhead, significantly reduced power consumption, fewer vectors, and high automation. It can be widely applied in low-power testing processes for various chips, chip modules, terminals, and base stations.

Description

Technical Field

[0001] This invention relates to the field of design for testability (DFT) of integrated circuits, and more particularly to a method, apparatus, chip, chip module and terminal device for scanning chain analysis and circuit modification to reduce dynamic power consumption of chips during the scanning test phase. Background Technology

[0002] As process technology evolves and chip size increases, a large number of registers flip on the same clock edge during scan testing, which can easily generate a significant voltage drop (IR Drop) on the power network, leading to test failure or reduced reliability in severe cases. The voltage drop phenomenon can be divided into two categories according to the test stage in which it occurs: Shift-IR Drop and Capture-IR Drop.

[0003] The Capture-IR Drop occurs during the Capture phase: the scan chain remains stationary, the system clock initiates a valid edge trigger, and the combinational logic under test captures the response back to the scan register. During this phase, a large number of combinational logic circuits flip simultaneously, concentrating instantaneous current in a localized area. If numerous integrated clock gating (ICG) circuits are enabled, the local clock network also flips synchronously, easily leading to discrepancies between the captured value and the simulation expectation, resulting in a "simulation-measurement mismatch." The ATPG tool reports "Capture failure" or "At-speed fail." Such misjudgments can incorrectly label the chip under test as defective. Therefore, one of the core objectives of low-power ATPG is to reduce the Capture-toggle (capture toggle rate, i.e., the register toggle rate during the capture phase).

[0004] Currently, the industry standard for reducing power consumption during the capture stage is to limit the register toggle rate when the ATPG generates test vectors (patterns). The general principle of ATPG is to reduce the capture toggle rate of the design by using an integrated clock gating (ICG) in the control design circuit. For example... Figure 1 As shown, existing technology reduces the capture-to-flip rate by controlling the enable (EN) terminal of the integrated clock gating unit via ATPG to shut down the local clock. This approach requires additional control registers, control AND gate logic, etc., which leads to the following drawbacks:

[0005] a) Increase chip area and wiring resources;

[0006] b) The control path may be located on the critical path of a function, affecting the timing of the function.

[0007] c) The ATPG tool needs to repeatedly calculate the switch combination each time a vector is generated, which leads to increased running time and an expansion of the number of vectors.

[0008] In the prior art, invention patent CN115469214A discloses a low-power scan test circuit based on segmented control of the scan chain. It reduces capture / shift power consumption through a gated clock module and introduces a "control chain" to assign values ​​to the gated signals, thereby achieving low power consumption. However, this application requires adding a "control chain" and additional ports SCI / SCO. Furthermore, the modification point is in the clock network, which inevitably affects functional timing. Thus, in order to save test power consumption, functional performance, area, accuracy, and reliability may be sacrificed.

[0009] For example, invention patent CN103091620B discloses an optimization method for capture power consumption in scanning tests. It uses a decoder to constrain the enable terminal of the CG unit to reduce capture power consumption; at the same time, the power consumption constraint unit is driven by the scan register. This application is similar to existing common solutions, and also requires a combination of decoder + AND gate + boundary scan register, so it still has the drawbacks of large chip area / port overhead.

[0010] The article "Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits" (DOI: 10.1109 / ITC50571.2021.00045, P319–P323), published by Yi Sun, Hui Jiang, et al. at IEEE ITC 2021, proposes a DFT-based solution to reduce IR-drop caused by excessive power consumption during testing. This solution involves dividing the scan chain into segments and inserting "embedded enable capture bits (EECB)" between segments. The EECB value is automatically generated by standard ATPG tools and determines whether the segment actually captures data during the capture cycle. Specifically, it reduces power consumption by adding special registers within the scan chain using "embedded enable capture bits" to control the integrated clock gating and AND gates (EECB). This paper requires adding special registers serially into the chain, altering the chain structure and affecting the functional path due to the insertion position at the EN terminal of the integrated clock gating. Summary of the Invention

[0011] A brief overview of embodiments of the invention is provided below to provide a basic understanding of certain aspects of the invention. It should be understood that this overview is not an exhaustive summary of the invention. It is not intended to identify key or essential parts of the invention, nor is it intended to limit the scope of the invention. Its purpose is merely to present certain concepts in a simplified form as a prelude to the more detailed description that follows.

[0012] To address the aforementioned technical problems, the present invention provides a low-power ATPG method that employs a circuit optimization scheme that modifies only the scan chain (Shift path) without affecting the function path. This allows the ATPG tool to significantly reduce the capture-toggle rate and shift-toggle rate with minimal hardware modifications, thereby reducing voltage drop, shortening test time, and lowering test power consumption.

[0013] Specifically, according to the first aspect of this application, a low-power ATPG method is provided, comprising:

[0014] Step 1: Obtain the status table of all scan chain registers in the Shift-0 state from the scan chain status report file generated by the ATPG tool; the Shift-0 state is when all scan chain inputs are 0.

[0015] Step 2: Based on the status table of all scan chain registers in the Shift-0 state and the design netlist, obtain the list of integrated clock gates that are in the enabled state;

[0016] Step 3: Based on the list of integrated clock gates in the enabled state, obtain the list of drive registers for each integrated clock gate through circuit analysis; the list of drive registers is a list of directly or indirectly controlled registers of the EN signal of each integrated clock gate in the enabled state.

[0017] Step 4: Based on the list of drive registers for each integrated clock gate and the Shift-0 value, obtain the key registers and their expected toggles;

[0018] Step 5: Generate a scan chain modification script based on the order of the key registers in the scan chain. The scan chain modification script is used to insert or delete inverters in the scan chain data path without changing the functional path.

[0019] Step 6: Back-annotate the scan chain modification script to the design netlist and complete the physical implementation. Finally, deliver it to the ATPG tool to generate low-power test vectors without affecting the functional path timing.

[0020] Furthermore, step 4 involves using a minimum flip search of N to obtain the key registers and their expected flip values. N is a preset positive integer, N≥1. The minimum flip search of N involves performing a minimum flip search on each register in the list one by one, two by two, ... N times. Simultaneously, it employs a multi-threaded parallel approach, dividing the integrated clock gating list into several analysis groups to accelerate the search.

[0021] Furthermore, the scan chain modification script in step 5 is generated based on the bit sequence number of the key register in the scan chain. This script is configured to insert or remove inverters before the Shift-in of the corresponding register, so that the register presents the desired flip value after the Shift-0 vector is loaded, thereby disabling the corresponding integrated clock gate (making the clock enable pin EN of the corresponding integrated clock gate inactive). In addition, the inserted inverters only operate in scan mode and have no timing or area impact on the functional path.

[0022] Furthermore, the scan chain modification script in step 5 includes:

[0023] For a single-bit register, insert an inverter at its preceding data input.

[0024] For multi-bit registers, an inverter is inserted at the data input terminal of the first-bit register, and a compensation inverter is inserted at the data input terminal of the next-level register to keep the subsequent data unchanged.

[0025] Furthermore, in step 6, the scan chain modification script automatically back-annotates the design netlist and is used in the placement and routing process.

[0026] According to a second aspect of this application, a low-power ATPG device is provided, comprising:

[0027] The scan chain register status table acquisition unit is used to acquire the status tables of all scan chain registers in the Shift-0 state based on the scan chain status report file generated by the ATPG tool.

[0028] The integrated clock gating list acquisition unit is used to obtain the list of integrated clock gating devices that are in the enabled state based on the status table of all scan chain registers and the design netlist in the Shift-0 state.

[0029] The drive register list acquisition unit is used to obtain the drive register list of each integrated clock gate based on the list of integrated clock gates that are in the enabled state through circuit analysis.

[0030] The critical register and its expected flip value acquisition unit is used to obtain the critical register and its expected flip value based on the list of drive registers of each integrated clock gate and the Shift-0 value;

[0031] The scan chain modification script generation unit is used to generate a scan chain modification script according to the order of the key registers in the scan chain. The scan chain modification script is used to insert or delete inverters in the scan chain data path without changing the functional path.

[0032] The low-power test vector generation unit is used to back-annotate the scan chain modification script to the design netlist and complete the physical implementation, and finally deliver it to the ATPG tool to generate low-power test vectors without affecting the functional path timing.

[0033] According to a third aspect of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the low-power ATPG method described above.

[0034] According to the fourth aspect of this application, a chip is provided, wherein the scan chain structure is formed by modifying the low-power ATPG method described above, and is used for low-power scan testing; wherein the scan chain data path includes an inverter dedicated to the scan mode, and the functional path maintains the original timing unchanged.

[0035] According to a fifth aspect of this application, a chip module is provided, comprising the aforementioned chip.

[0036] According to a sixth aspect of this application, a terminal device is provided, comprising the aforementioned chip module.

[0037] According to a seventh aspect of this application, a base station device is provided, comprising the aforementioned chip or the aforementioned chip module.

[0038] This invention, through the aforementioned scheme, achieves zero new register additions in hardware, modifying only the scan chain data structure by inserting inverters, thus having zero impact on the functional path. In software, it employs a closed-loop process of "shift-0 state → inverter insertion → zero functional interference," generating a chain-level inverter insertion scan chain modification script through a heuristic search of the minimum number of flipped registers one by one…one by N. This script is then back-annotated to the design netlist and physically implemented, finally delivering the results to the ATPG tool to generate low-power test vectors. This scheme, modifying only the scan chain data structure without affecting the functional path timing, offers advantages such as minimal hardware overhead, significantly reduced power consumption, fewer vectors, and a high degree of automation. It can be widely applied in low-power testing processes for various chips, chip modules, terminals, and base stations. Attached Figure Description

[0039] The present invention can be better understood by referring to the description given below in conjunction with the accompanying drawings, in which the same or similar reference numerals are used throughout the drawings to denote the same or similar parts. These drawings, together with the following detailed description, are incorporated in and form part of this specification, and are used to further illustrate preferred embodiments of the invention and explain the principles and advantages of the invention. In the drawings:

[0040] Figure 1 A schematic diagram illustrating the introduction of control logic into the functional path of existing technologies;

[0041] Figure 2 This is a schematic diagram of the low-power ATPG method in this embodiment;

[0042] Figure 3 This is a schematic diagram illustrating the acquisition of the Shift-0 register state in step 1 of this embodiment;

[0043] Figure 4 This is a schematic diagram illustrating the generation of the enabled ICG list in step 2 of this embodiment;

[0044] Figure 5 This is a schematic diagram illustrating the tracing of the ICG driver register in step 3 of this embodiment;

[0045] Figure 6 This is a schematic diagram of the analysis grouping and parallelization in step 4 of this embodiment;

[0046] Figure 7 This is an example of modifying register values ​​one by one and two by two in this embodiment;

[0047] Figure 8 This is an example of the N-by-N restriction strategy in this embodiment;

[0048] Figure 9 This is an example of inserting a script into the inverter of a single-bit register in this embodiment;

[0049] Figure 10 This is an example of inserting a script into the inverter of the multi-bit register in this embodiment;

[0050] Figure 11 This is a schematic diagram of the modified ICG shutdown path timing in this embodiment. Detailed Implementation

[0051] Embodiments of the present invention will now be described with reference to the accompanying drawings. Elements and features described in one drawing or embodiment of the invention may be combined with elements and features shown in one or more other drawings or embodiments. It should be noted that, for clarity, representations and descriptions of components and processes unrelated to the present invention and known to those skilled in the art have been omitted from the drawings and description.

[0052] In the description of this invention, it should be understood that the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0053] The following are explanations of the terms used in this invention: IR Drop: Voltage drop; Scan: Chip scan test; DFT: Design For Test; Shift: Shift, Scan test uses Shift to move data from port data into internal registers for control and moves internal register data to ports for observation; Capture: Capture, Scan test uses Capture to sample data between different registers to determine whether the register combinational logic operation value meets expectations; ATPG: Automatic Test Pattern Generation, Automatically generates chip scan test vectors; ICG: Integrate Clock Gater (hereinafter referred to as ICG); Load: Load, in this article refers to the loading of scan chain data; Load toggle rate: Data loading toggle rate; Response: Return, in this article refers to the return of scan chain data; Response toggle rate: Data return toggle rate.

[0054] This invention provides a low-power ATPG method, apparatus, and chip that inserts inverters into only the scan chain without altering any functional timing paths. By acquiring the register values ​​of the scan chain in the shift-0 state, the ICG that needs to be disabled is located; then, a heuristic search is used to determine the key register with the fewest flips; finally, an inverter insertion script is automatically generated based on the chain order, simultaneously reducing the capture flip rate, shift flip rate, and pattern count, with zero impact on area and timing. This zero-functionality, low-cost, low-power ATPG solution is applicable to various chips, chip modules, terminals, and base station products.

[0055] Example 1

[0056] This embodiment provides a low-power ATPG method, the flowchart of which is as follows: Figure 2 As shown, it includes:

[0057] Step 1: Process the scan chain status report file generated by the ATPG tool, analyze and obtain all register values ​​corresponding to a scan chain input of 0, and output "Scan Chain Register Status Values". For example... Figure 3 As shown, when all inputs in the scan chain are 0, the status values ​​of all registers in the scan chain are analyzed.

[0058] Step 2: Analyze the on / off state of ICGs in the design and output a "list of ICGs that are on". For example... Figure 4 As shown, all registers in the scan chain drive a large number of ICGs. The design goal is to disable the ICGs in the design as much as possible when the scan chain shifts to 0. The list of ICGs that are in the enabled state is obtained by using the register status values ​​of all registers when the scan chain shifts to 0 obtained in step 1.

[0059] Step 3: Analyze the designed ICG circuit structure and output the "List of ICG-related driver registers in the enabled state". Analyze all ICGs obtained in Step 2 to obtain the list of enabled states, and through circuit analysis, obtain the register list of the corresponding ICG-related drivers for each enabled state, such as... Figure 5 As shown, the ICG-related driver registers are registers A, B, C, D, and E.

[0060] Step 4: Analyze the circuit structure to obtain the key driver registers that can disable the ICG, and output a "List of Key Driver Registers for Disabling the ICG". For example... Figure 4 As shown, when registers A, B, C, D, E, etc. are in the state of 0, 0, 1, 0, 0, the ICG is in the open state. In fact, the circuit only needs to control register C to be in the state of 0, and the ICG will be in the closed state.

[0061] like Figure 6 As shown, the design is broken down into N analysis groups, each containing multiple ICG analysis circuits. The smallest analysis unit within each group is analyzed sequentially. Step 4 requires independent analysis for each ICG. By splitting the analysis groups, the analysis process can be run in multiple threads, accelerating the analysis time.

[0062] In step 4, the analysis objective of each smallest unit of the analysis circuit is to find the method with the fewest number of toggled registers. First, the register value at shift 0 of the scan chain is marked into the relevant register. The register values ​​are modified one by one, two by two, three by three, etc., until the EN value of ICG is captured as 0. The state value of the modified register at this point is recorded. For example... Figure 7 As shown, it can be observed that when the register values ​​are modified one by one and the value of register B is changed from 0 to 1, the EN value of ICG becomes 0, and the information "the expected value of register B is 1" can be stored. This step of the analysis script can specify the analysis limit value (the value of N for each N) to reduce the analysis time.

[0063] For example: Figure 7 As shown, if the sequential analysis fails to reduce the EN value of ICG to 0, a sequential two-by-two analysis will be initiated. The analysis will continue until the EN value of ICG becomes 0, at which point the current analysis will exit, or until the N value limit for sequential N is reached, at which point the analysis will exit. Figure 8 The illustration will output "Register I expected value is 1" and "Register L expected value is 1".

[0064] In step 4, a multi-threaded parallel approach is used to divide the ICG list into several analysis groups to accelerate the search.

[0065] Step 5: Analyze the scan chain and the expected modification values ​​of key registers on the scan chain, obtain the minimum scan chain modification scheme, and output the scan chain modification script.

[0066] By capturing the connection order of the desired key registers on the scan chain, the following text information that needs to be modified for scan chains 1 to N is mapped:

[0067] Scan chain 1: 10, 11, 12, 30, 50, 51, 52, 53;

[0068] Scan chain 2: 1, 2, 3, 4, 5, 6, 7, 8, 9, 10;

[0069] … …

[0070] Scan chain N: 30, 31, 32, 33, 100, 101, 102.

[0071] like Figure 9 Example: For the analysis of the above scan chain 1 (the above digital representation scan chain starts from shift in and calculates the Nth register), only the inverters before shift in the 10th register, the 13th register, the 30th register, the 31st register, the 50th register, and the 54th register need to be inserted.

[0072] Should Figure 9 The analysis example only illustrates the analysis method for single-bit registers. This invention is also applicable to the analysis of multi-bit registers, such as... Figure 10 Example: Suppose that the 10th, 11th, 12th and 13th bits of scan chain 1 are merged 4-bit multi-bit registers. If the analysis determines that the values ​​of the sub-registers inside the multi-bit registers need to be modified, an inverter will be inserted at the shift in of the multi-bit register and an inverter will be inserted at the shift in of the next level register of the multi-bit register.

[0073] like Figure 11 The analysis in step 5 demonstrates how the actual effect of the ICG's on state changing to off state occurs: Registers C, I, and L need to be modified. Since registers C, I, and L are connected consecutively on the scan chain, this analysis step will determine that an inverter needs to be inserted before the shift in register C to ensure that the values ​​of registers C, I, and L will change compared to their original values. In order to maintain the value after register L at the initial scan chain shift 0, an inverter is inserted before the shift in register after register L.

[0074] This invention improves the efficiency of the ATPG tool by optimizing the corresponding circuitry based on its working principle. Furthermore, modifications are made only to the scan shift channel, ensuring minimal impact on the functional path and minimizing modification points through circuit structure analysis.

[0075] This invention modifies the scan chain analysis scheme to ensure that as many ICGs as possible are in the off state during shift 0. The low-power embedded compression logic utilizes the number of scan chains controlled during shift 0 to control the load toggle rate. The ATPG controls the capture toggle rate by controlling the switching of ICGs. Since the ICG control registers are distributed throughout the scan chain, this invention primarily targets the low-power ATPG characteristics of embedded compression logic, aiming to control the logic toggle information of the scan chain as much as possible during shift 0, keeping relevant ICGs in the off state to reduce the capture toggle rate. Simultaneously, the scan chain shift toggle rate is divided into the data load toggle rate and the data return toggle rate. Since the scan chain response occurs after capture, reducing the capture toggle rate helps reduce changes in values ​​on the scan chain, thereby helping to reduce the data return toggle rate.

[0076] Example 2

[0077] This embodiment provides a low-power ATPG device, including...

[0078] The scan chain register status table acquisition unit is used to acquire the status tables of all scan chain registers in the Shift-0 state based on the scan chain status report file generated by the ATPG tool.

[0079] The ICG list acquisition unit is used to obtain the list of ICGs that are in the enabled state based on the status table of all scan chain registers and the design netlist in the Shift-0 state.

[0080] The driver register list acquisition unit is used to obtain the driver register list of each ICG based on the list of ICGs in the enabled state through circuit analysis.

[0081] The key register and its expected flip value acquisition unit uses an N-bit minimum flip search strategy to modify the register values ​​in the driver register list, so that the corresponding ICG is turned off, and records the key register and its expected value; the N-bit strategy is to flip the register values ​​one bit at a time, two bits at a time... N bits at a time until the combination that can turn off the ICG by finding the minimum number of flip bits is found.

[0082] The scan chain modification script generation unit is used to generate a scan chain modification script according to the order of the key registers in the scan chain. The scan chain modification script is used to insert or delete inverters in the scan chain data path without changing the functional path.

[0083] The low-power test vector generation unit is used to back-annotate the scan chain modification script to the gate-level netlist and complete the placement and routing, and finally deliver it to the ATPG tool to generate low-power test vectors without affecting the timing of the functional path.

[0084] Example 3

[0085] This embodiment provides a chip whose scan chain is modified according to the method of Embodiment 1 and used for low-power scan testing.

[0086] Example 4

[0087] This embodiment provides a chip module that includes the chip of embodiment 3.

[0088] Example 5

[0089] This embodiment provides a terminal device or base station device, which includes the chip of embodiment 3 or the chip module of embodiment 4.

[0090] Example 6

[0091] This embodiment provides a computer-readable storage medium storing a program for performing the method of Embodiment 1.

[0092] This invention achieves a significant reduction in the ATPG search space with minimal hardware modifications, protecting functional timing while directly reducing test power consumption and test time. Experiments show that, under the same low-power ATPG settings, the number of test vectors after using this solution is significantly reduced compared to before, making it convenient to use and easy to promote.

[0093] The method of this invention is not limited to being executed in the chronological order described in the specification, but can also be executed in other chronological orders, in parallel, or independently. Therefore, the execution order of the method described in this specification does not constitute a limitation on the technical scope of this invention.

[0094] Although the invention has been disclosed above through the description of specific embodiments, it should be understood that all the embodiments and examples described above are exemplary and not restrictive. Those skilled in the art can design various modifications, improvements, or equivalents to the invention within the spirit and scope of the appended claims. These modifications, improvements, or equivalents should also be considered to be included within the protection scope of the invention.

Claims

1. A low-power ATPG method, characterized in that: include: Step 1: Obtain the status table of all scan chain registers in the Shift-0 state from the scan chain status report file generated by the ATPG tool; the Shift-0 state is when all scan chain inputs are 0. Step 2: Based on the status table of all scan chain registers in the Shift-0 state and the design netlist, obtain the list of integrated clock gates that are in the enabled state; Step 3: Based on the list of integrated clock gates in the enabled state, obtain the list of drive registers for each integrated clock gate through circuit analysis; the list of drive registers is a list of directly or indirectly controlled registers of the EN signal of each integrated clock gate in the enabled state. Step 4: Based on the list of drive registers for each integrated clock gate and the Shift-0 value, use N-step minimum toggle search to obtain the key registers for disabling the integrated clock gate and their expected toggle values; N is a preset positive integer, N≥1; Step 5: Generate a scan chain modification script based on the order of the key registers in the scan chain. This script is used to insert or delete inverters in the scan chain data path without changing the functional path. The scan chain modification script includes: For a single-bit register, insert an inverter at its preceding data input. For multi-bit registers, an inverter is inserted at the data input terminal of the first-bit register and a compensation inverter is inserted at the data input terminal of the next-level register to keep the subsequent data unchanged. Step 6: Back-annotate the scan chain modification script to the design netlist and complete the physical implementation. Finally, deliver it to the ATPG tool to generate low-power test vectors without affecting the functional path timing.

2. The low-power ATPG method according to claim 1, characterized in that: The scan chain modification script in step 5 is generated based on the bit number of the key register in the scan chain. The scan chain modification script is configured to insert or delete an inverter before the Shift-in of the corresponding register, so that the register presents the desired flip value after the Shift-0 vector is loaded, thereby turning off the corresponding integrated clock gate.

3. A low-power ATPG device, characterized in that: include: The scan chain register status table acquisition unit is used to acquire the status tables of all scan chain registers in the Shift-0 state based on the scan chain status report file generated by the ATPG tool. The integrated clock gating list acquisition unit is used to obtain the list of integrated clock gating devices that are in the enabled state based on the status table of all scan chain registers and the design netlist in the Shift-0 state. The drive register list acquisition unit is used to obtain the drive register list of each integrated clock gate based on the list of integrated clock gates that are in the enabled state through circuit analysis. The key register and its expected flip value acquisition unit is used to obtain the key register for disabling the integrated clock gate and its expected flip value by using N-step minimum flip search based on the list of drive registers of each integrated clock gate and the Shift-0 value. N is a preset positive integer, N≥1; A scan chain modification script generation unit is used to generate a scan chain modification script based on the order of key registers in the scan chain. The scan chain modification script is used to insert or delete inverters in the scan chain data path without changing the functional path. The scan chain modification script includes: For a single-bit register, insert an inverter at its preceding data input. For multi-bit registers, an inverter is inserted at the data input terminal of the first-bit register and a compensation inverter is inserted at the data input terminal of the next-level register to keep the subsequent data unchanged. The low-power test vector generation unit is used to back-annotate the scan chain modification script to the design netlist and complete the physical implementation, and finally deliver it to the ATPG tool to generate low-power test vectors without affecting the functional path timing.

4. A computer-readable storage medium, characterized in that: It stores a computer program that, when executed by a processor, implements the steps of the low-power ATPG method according to any one of claims 1-2.

5. A chip, characterized in that: Its scan chain structure is formed by modifying the low-power ATPG method according to any one of claims 1-2, and is used for low-power scan testing; wherein the scan chain data path includes an inverter for scan mode, and the functional path maintains the original timing unchanged.

6. A chip module, characterized in that: It includes the chip as described in claim 5.

7. A terminal device, characterized in that: It includes the chip as described in claim 5 or the chip module as described in claim 6.

8. A base station device, characterized in that: It includes the chip as described in claim 5 or the chip module as described in claim 6.

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