Chip integration method, apparatus, device, and storage medium

Abstract

The application relates to the chip technical field, in particular to a chip integration method, device, equipment and storage medium, which can improve the flexibility and efficiency of chip integration. The method comprises the following steps: in response to a first instruction, acquiring hierarchical structure data for integrating a first chip; based on the hierarchical structure data, acquiring a hierarchical path of a first module and a hierarchical path of a first target module; traversing the hierarchical path of the first module and the hierarchical path of the first target module, determining a first common parent module of the first module and the first target module; and based on the first common parent module, moving the first module to the next layer of the first target module. The first instruction is used to indicate that the first module in the first chip is moved from the current layer to the next layer of the first target module; and the hierarchical structure data is used to indicate the hierarchical relationship among a plurality of modules included in the first chip.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a chip integration method, apparatus, device and storage medium. Background Technology

[0002] As the integration level of system-on-a-chip (SoC) continues to increase, the number and complexity of internal modules also increase significantly. Chip design typically requires organizing and connecting multiple functional modules according to a certain hierarchical structure to achieve the chip's functions.

[0003] In existing technologies, chip integration mainly relies on manual methods to write code and instantiate modules one by one, and then connect signal lines one by one according to requirements. Once the chip structure is adjusted, such as by changing the module hierarchy, merging or splitting modules, a lot of manual operations need to be performed again, resulting in low integration efficiency and easy introduction of errors.

[0004] In existing technologies, when faced with changes in chip design, it is often necessary to re-integrate from scratch, resulting in wasted resources and extended development cycles, making it difficult to meet the requirements of efficient and maintainable chip design. Summary of the Invention

[0005] This application provides a chip integration method, apparatus, device, and storage medium. The technical solution adopted in this application is as follows:

[0006] In a first aspect, a chip integration method is provided, comprising: in response to a first instruction, acquiring hierarchical structure data for integrating a first chip; based on the hierarchical structure data, acquiring a hierarchical path of a first module and a hierarchical path of a first target module; traversing the hierarchical paths of the first module and the first target module to determine a first common parent module of the first module and the first target module; and based on the first common parent module, moving the first module to the next level of the first target module. The first instruction is used to instruct the first module in the first chip to be moved from its current level to the next level of the first target module; the hierarchical structure data is used to indicate the hierarchical relationship between multiple modules included in the first chip.

[0007] Based on the aforementioned technical means, firstly, by receiving instructions and extracting hierarchical structure data, the need for module hierarchy changes can be dynamically identified; secondly, by obtaining the hierarchical path between the first module and the first target module and determining their common parent module, the module hierarchy adjustment process has a clear contextual relationship; finally, the module position is changed based on the common parent module, avoiding the inefficiency and errors caused by manually reconstructing connections in traditional methods. Compared to the existing technology of manually reconstructing connections layer by layer, this significantly improves the flexibility and efficiency of chip integration.

[0008] In one possible implementation of the first aspect, the first module is connected to the first common parent module through an intermediate module; based on the first common parent module, moving the first module to the next level of the first target module includes: disconnecting the connection between the first module and its current parent module, and moving the first module to the next level of the first common parent module; disconnecting the connection between the first module and the first common parent module, and moving the first module to the next level of the first target module.

[0009] Based on the aforementioned technical methods, by disconnecting and rebuilding connections in stages, it is ensured that the original connection structure is not damaged during the hierarchical migration of modules, while also guaranteeing the accuracy of the final hierarchical structure adjustment. This method reduces the disturbance to the overall connection network during hierarchical changes and improves the robustness of module movement operations.

[0010] In one possible implementation of the first aspect, disconnecting the connection between the first module and its current parent module, and moving the first module to the next level of the first common parent module, includes: executing a first loop until the first module is moved to the next level of the first common parent module; the first loop is: disconnecting the connection between the first module and its current parent module, and moving the first module up one level along the hierarchical path of the first module.

[0011] Based on the above technical means, by gradually moving upwards in a cyclical manner to approach the common parent module, the hierarchical adjustment can be completed without changing the entire connection relationship at once, reducing the instability risk that may be caused by excessive hierarchical jumps, while enhancing the controllability and reversibility of module movement operations.

[0012] In one possible implementation of the first aspect, the first target module is connected to the first common parent module through an intermediate module; disconnecting the connection between the first module and the first common parent module and moving the first module to the next level of the first target module includes: executing a second loop until the first module is moved to the next level of the first target module; the second loop is: disconnecting the connection between the first module and the current parent module of the first module and moving the first module down one level along the hierarchical path of the first target module; in the case of the first execution of the second loop, the current parent module of the first module is the first common parent module.

[0013] Based on the aforementioned technical methods, the hierarchical adjustment from the common parent module to the target module is completed through a cyclical downward movement, ensuring that the module can still be accurately placed in the designated position even in the presence of intermediate modules. This approach simplifies the module movement logic in complex hierarchical structures and improves the degree of automation.

[0014] In one possible implementation of the first aspect, this application can also realize the pass-through requirement based on the hierarchical structure data of the first chip. Specifically: in response to the second instruction, based on the hierarchical structure data, the hierarchical path of the second module and the hierarchical path of the second target module are obtained; based on the hierarchical path of the second module and the hierarchical path of the second target module, a second common parent module of the second module and the second target module is determined; based on the second common parent module, the signal of the second module is passed through the pass-through module to reach the second target module. The second instruction is used to instruct the signal of the second module to pass through the pass-through module to reach the second target module.

[0015] Based on the aforementioned technical methods, when signal pass-through is required between modules, the existing hierarchical structure information is used to automatically update the connection relationships, effectively supporting signal pass-through requirements and improving the adaptability of chip integration. By identifying the common parent module of two modules, the connection relationships that need to be modified can be accurately located, avoiding the accidental deletion of other irrelevant connections, thereby ensuring the stability of the chip design. This hierarchical path analysis-based method makes signal pass-through implementation more efficient and reliable.

[0016] In one possible implementation of the first aspect, based on the second common parent module, the signal of the second module is transmitted through the pass-through module to the second target module, including: removing the first signal channel in the integrated code of the second common parent module; the first signal channel is used to transmit the signal of the second module to the second target module; establishing a second signal channel in the integrated code of the second common parent module; the second signal channel is used to transmit the signal of the second module to the second target module through the pass-through module.

[0017] Based on the above technical means, by accurately accessing the integrated code of the second common parent module and modifying the signal channels in the integrated code, the connection relationship between modules is locally updated without reconstructing the entire chip structure, thus improving integration efficiency.

[0018] In one possible implementation of the first aspect, removing the first signal channel from the integrated code of the second common parent module includes: removing the code in the code of the second common parent module used to define the connection relationship between the first output port and the first input port, wherein the first output port is a port in the third module used to output signals from the second module, and the third module is a module located at the next level below the second common parent module in the hierarchical path of the second module; the first input port is a port in the fourth module used to receive signals from the second module; and the fourth module is a module located at the next level below the second common parent module in the hierarchical path of the second target module.

[0019] Based on the above technical means, the connection relationship between ports is removed in the integrated code of the second common parent module, laying the foundation for realizing signal pass-through.

[0020] In one possible implementation of the first aspect, a second signal channel is established in the integrated code of the second common parent module, including: adding code in the integrated code of the second common parent module to define the connection relationship between the first output port and the input port of the transparent transmission module; and adding code in the integrated code of the second common parent module to define the connection relationship between the output port of the transparent transmission module and the second target module.

[0021] Based on the above technical means, the connection relationship between ports is redefined in the integrated code of the second common parent module, so that the signal can be successfully transmitted through the transparent transmission module.

[0022] Secondly, a chip integration device is provided, the device comprising:

[0023] The first acquisition module is used to acquire hierarchical structure data for integrating the first chip; the hierarchical structure data is used to indicate the hierarchical relationship between the multiple modules included in the first chip.

[0024] The second acquisition module is used to acquire the hierarchical path of the first module and the hierarchical path of the first target module based on the hierarchical structure data.

[0025] The module is determined by traversing the hierarchical path of the first module and the hierarchical path of the first target module to determine the first common parent module of the first module and the first target module.

[0026] A move module is used to move the first module to the next level of the first target module based on the first common parent module.

[0027] Thirdly, a chip integration device is provided, the device comprising:

[0028] One or more processors;

[0029] A memory for storing one or more programs, which, when executed by one or more processors, cause the device to implement the chip integration method as shown in the first aspect and any one thereof.

[0030] Fourthly, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a computer's processor, causes the computer to perform the chip integration method as described in the first aspect and any one thereof. Attached Figure Description

[0031] Figure 1 This is a schematic flowchart of a chip integration method provided in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of the hierarchical structure data of a chip provided in an embodiment of this application;

[0033] Figure 3 This is a schematic flowchart of another chip integration method provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of another type of chip hierarchical structure data provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of the integrated code of a chip provided in an embodiment of this application;

[0036] Figure 6 This is a flowchart illustrating another chip integration method provided in the embodiments of this application;

[0037] Figure 7 This is a schematic diagram illustrating a module hierarchy adjustment provided in an embodiment of this application;

[0038] Figure 8 This is a schematic diagram of a signal redirection provided in an embodiment of this application;

[0039] Figure 9 This is a schematic diagram of the structure of a chip integration device provided in an embodiment of this application;

[0040] Figure 10 This is a schematic diagram of the structure of a chip integration device provided in an embodiment of this application. Detailed Implementation

[0041] As chip size continues to increase, the interconnections between modules and chip integration become increasingly complex. During chip design, multiple factors can influence the hierarchical relationships between modules, including changes in architectural requirements, the ease of backend implementation, and the division of power consumption modules.

[0042] In the field of chip design, conventional chip integration methods typically rely on manually coding and instantiating each module one by one, and then connecting signal lines one by one as needed. This traditional method is not only time-consuming, but also becomes problematic in large-scale system-on-chip (SoC) design processes. When faced with requirements for adjusting chip module hierarchy, merging or splitting modules, or hardening modules when the chip area is large, any of these situations can render all previous integration work futile, requiring a restart. This is not only time-consuming but also prone to errors.

[0043] Therefore, this application provides a chip integration method that, when there is a need to adjust the hierarchy of modules, can perform hierarchical changes to modules based on the chip's hierarchical structure data. This eliminates the need to start integration from scratch, making it efficient and less prone to errors.

[0044] The following describes a chip integration method provided by an embodiment of this application, in conjunction with the accompanying drawings and embodiments. Figure 1 This is a schematic flowchart of a chip integration method provided in an embodiment of this application, as shown below. Figure 1 As shown, the method may include:

[0045] S101, in response to the first instruction, acquires hierarchical structure data for integrating the first chip.

[0046] The first instruction is used to instruct the first module in the first chip to be moved from the current level to the next level of the first target module. The first module is the module to be moved. Moving one module to the next level of another module can be understood as: embedding or integrating one module into another module, or making one module a direct submodule of another module.

[0047] The chip integration method provided in this embodiment can be executed by an electronic device, including but not limited to computers, mobile terminals, etc. The electronic device includes chip integration software, which assists developers in chip design and integration. For example, it performs chip module integration operations according to the developer's instructions, wherein the integration operations include, but are not limited to, module movement, connection, and verification. The chip integration software may include an instruction input box for accepting instructions from the developer. In some embodiments, responding to a first instruction specifically means responding to the developer inputting a first instruction in the instruction input box of the chip integration software.

[0048] In some embodiments, before executing S101, the hierarchical structure data of the first chip and the integrated code or design code of the first chip can be loaded first. For example, the hierarchical structure data of the first chip can be obtained from a preset location. That is, the hierarchical structure data of the first chip can be pre-stored in the electronic device.

[0049] The hierarchical structure data of the first chip is used to indicate the hierarchical relationship between the multiple modules included in the first chip. For example, the hierarchical structure data records the position of each module in the first chip, as well as the parent-child relationship, i.e., the hierarchical relationship, between modules. The hierarchical structure data is usually represented by a tree structure, where each node represents a module, and the connections between nodes represent the hierarchical relationship between modules.

[0050] For example, Figure 2 This is a schematic diagram of the hierarchical structure data of a chip provided in an embodiment of this application. Figure 2Each circle in the diagram represents a module, and the arrows indicate parent-child relationships between modules, meaning one module instantiates another. The top-level module has three sub-modules, such as `aa`, `bb`, and `cc`, meaning `aa`, `bb`, and `cc` are at the next level below the top-level module. The `aa` module has two sub-modules, such as `a1` and `a2`, meaning `a1` and `a2` are at the next level below `aa`. The `aa` module can be considered the common parent module of `a1` and `a2`. The `a1` module includes the `a1_1` module, meaning `a1_1` is at the next level below `a1`, and `a1` can be considered the parent module of `a1_1`. The `bb` module has three sub-modules, such as `b1`, `b2`, and `b3`. The `b2` module includes `b2_1` and `b2_2`. The `cc` module has three sub-modules, such as `c1`, `c2`, and `c3`. Module c3 includes module c3_1, meaning module c3_1 is at the next level below module c3. Module c3 can be called the parent module of module c3_1.

[0051] S102, based on the hierarchical structure data, obtain the hierarchical path of the first module and the hierarchical path of the first target module.

[0052] A module's hierarchical path refers to the set of all intermediate modules traversed from the top-level module to the next module. Figure 2 Taking the hierarchical data structure shown as an example, the hierarchical path of module b1 can be represented as top / bb / b1, which can be understood as: there is an instance named bb under the top-level module, and inside the bb instance there is an instance named b1. Another example is that the hierarchical path of module c3_1 can be represented as top / cc / c3 / c3_1. Yet another example is that the hierarchical path of module aa can be represented as top / aa.

[0053] The hierarchical path is used to determine the position of the module within the first chip and provides a basis for subsequent module movement. In this embodiment, the hierarchical paths of the first module and the first target module are extracted separately. For example, the first module and the first target module can be identified based on the user's first instruction, and their hierarchical paths can be extracted separately.

[0054] The following example uses module b1 as the first module and module aa as the first target module. It provides a specific implementation method for obtaining the hierarchical paths of the first module and the first target module based on hierarchical data structure.

[0055] For example, in response to a first instruction, the computer identifies the first module and the first target module based on the module identifier carried by the first instruction. The computer searches for module b1 in the hierarchical data structure. Upon finding module b1, it traces upwards from module b1 to the top module, recording the names of all modules encountered during the tracing process in sequence, forming the hierarchical path of module b1. Similarly, the computer searches for module aa in the hierarchical data structure. After finding module aa, it traces upwards from module aa to the top module, recording the names of all modules encountered during the tracing process in sequence, forming the hierarchical path of module aa.

[0056] After obtaining the hierarchical path of the first module and the hierarchical path of the first target module, S103 can be executed to determine the first common parent module of the two modules.

[0057] S103, traverse the hierarchical path of the first module and the hierarchical path of the first target module to determine the first common parent module of the first module and the first target module.

[0058] A common parent module refers to the nearest common parent module of two modules along their hierarchical path. The following section will combine... Figure 2 Let's introduce them. Taking modules b1 and aa as examples, their first common parent module is the top module. Taking modules b2_1 and b2_2 as examples, their first common parent module is the b2 module. Taking modules b2_2 and b3 as examples, their first common parent module is the bb module. Taking modules a1-1 and c3_1 as examples, their first common parent module is the top module.

[0059] In some embodiments, the first common parent module of the first module and the first target module is determined by traversing the hierarchical path of the first module and the first target module. For example, the hierarchical path of the first module and the first target module is traversed upwards layer by layer until the first common parent module is found, which is the first common parent module.

[0060] S104, based on the first common parent module, move the first module to the next level of the first target module.

[0061] After obtaining the first module and the first target module, the first module can be moved to the next level of the first target module based on the first common parent module.

[0062] In some embodiments, the first module is moved to the next level below the first target module by modifying the integration code of the first common parent module and the first target module. The module's integration code describes the functions and hardware structure of the sub-modules included in the module, including but not limited to the input and output ports, internal logic, and interface logic of the sub-modules. Exemplarily, the first module is moved to the next level below the first target module by modifying the code related to the first module in the integration code of the first common parent module and the first target module. The integration code may be, for example, register transfer level (RTL) code. The code related to the first module includes, but is not limited to, code for instantiating the first module and code for defining signal connections with the first module. This allows for only local modifications, improving integration efficiency and avoiding errors.

[0063] The chip integration method provided in this application dynamically adjusts the module hierarchy relationship through hierarchical structure data, thereby achieving flexible and efficient chip integration operations and improving the flexibility of chip integration.

[0064] In some embodiments, when the first module is connected to the first common parent module through at least one intermediate module, the first module can be moved to the next level of the first target module by the following method.

[0065] The first step is to disconnect the connection between the first module and its current parent module, and then move the first module to the next level of the first common parent module.

[0066] For example, firstly, the integrated code of the current parent module of the first module is modified to disconnect the connection between the first module and its current parent module. For instance, based on the hierarchical structure data of the first chip, the hierarchical path of the current parent module of the first module is obtained, and the integrated code of the current parent module of the first module is located in the integrated code of the first chip based on this hierarchical path. In the integrated code of the current parent module of the first module, the code related to the first module is found and removed. The code related to the first module includes, but is not limited to, the code used to instantiate the first module and the code used to define the signal connection with the first module. For instance, the code used to instantiate the first module in the integrated code of the current parent module of the first module is removed, and the code used to define the signal connection with the first module is also removed. Afterwards, the integrated code of the first common parent module is modified to move the first module to the next level of the first common parent module. For instance, based on the hierarchical structure data of the first chip, the hierarchical path of the first common parent module is obtained, and the integrated code of the first common parent module containing the first module and its current parent module is found in the integrated code of the first chip based on this hierarchical path. Modify the integration code of the first common parent module, such as instantiating the first module directly within the first common parent module, and update the signal connections to ensure that the first module can correctly receive input signals and send output signals.

[0067] Combination Figure 2 Taking module b1 as the first module and module top as the first common parent module as an example, the following steps are given: First, based on the hierarchical structure data of the first chip, the hierarchical path of module bb is obtained. Based on this hierarchical path, the integrated code of module bb, the current parent module of module b1, is found in the integrated code of the first chip. The integrated code of module bb is modified to disconnect the connection between module b1 and module bb. For example, code related to module bb is removed, such as code used to instantiate module b1 and code used to define signal connections with module b1. Next, based on the hierarchical structure data of the first chip, the hierarchical path of module top is obtained, and the integrated code of module top is found in the integrated code of the first chip. The integrated code of module top is modified to instantiate module b1 within module top and update the signal connections. In this way, module b1 can be moved to the next level of module top.

[0068] The second step is to disconnect the connection between the first module and the first common parent module, and move the first module to the next level of the first target module.

[0069] For example, based on the hierarchical structure data of the first chip, the integrated code of the first common parent module is located. The code related to the first module is found in the integrated code of the first common parent module and removed. For example, the code used to instantiate the first module and the code used to define signal connections with the first module are removed. Next, based on the hierarchical structure data of the first chip, the integrated code of the first target module is located and modified, such as by directly instantiating the first module within the first target module and updating the signal connections.

[0070] Combination Figure 2 Taking module b1 as the first module, module top as the first common parent module, and module a1 as the first target module as an example, the following steps are given: First, based on the hierarchical structure data of the first chip, the integrated code of module top is located. The integrated code of module top is modified to disconnect module b1 from module top. For example, the code used to instantiate module b1 and the code used to define signal connections with module b1 are removed from the integrated code of module top. Next, based on the hierarchical structure data of the first chip, the integrated code of module a1 is located. The integrated code of module a1 is modified to instantiate module b1 within module a1 and update the signal connections. In this way, module b1 can be moved to the next level of module a1.

[0071] The hierarchical adjustment of the first module within the first chip is completed through steps one and two. This step-by-step design, consisting of steps one and two, not only improves flexibility but also enhances controllability over complex module structures, helping to handle frequent design changes in the chip design flow. It offers benefits such as reduced complexity, increased predictability, enhanced traceability, and easier verification and testing. For example, after each update of connectivity relationships, verification can be performed to ensure that each update is correct and does not introduce errors.

[0072] In some embodiments, when the first module is directly connected to the first common parent module, the above method can be simplified to: disconnecting the connection between the first module and the first common parent module, and moving the first module to the next layer of the first target module.

[0073] In some embodiments, when the first module is connected to the first common parent module through at least one intermediate module, the first module can be moved layer by layer multiple times to gradually move the first module to the lower layer of the first common parent module. For example, a first loop is executed until the first module is moved to the next layer below the first common parent module. The first loop involves: disconnecting the connection between the first module and its current parent module, and moving the first module one layer up along its hierarchical path. For example, the first loop may specifically involve: locating the integrated code of the current parent module of the first module based on the hierarchical structure data of the first chip, removing code related to the first module from the integrated code of the current parent module of the first module; and locating the integrated code of the parent module of the current parent module of the first module based on the hierarchical structure data of the first chip, adding code related to the first module to the integrated code of the parent module of the current parent module of the first module.

[0074] The first loop is a repetitive operation mechanism. Its purpose is to adjust the first module's hierarchy once per loop until the first module reaches the next level of its common parent module. In this embodiment, each loop includes two core actions: disconnecting the first module from its current parent module and moving the first module up one level, i.e., promoting it to a higher position in the hierarchical structure. The first loop ensures that the movement of the first module is gradual and controllable, avoiding errors or irreversible consequences that might result from a one-time change. Furthermore, the first loop allows for flexible handling of complex hierarchical changes. When multiple first modules need to adjust their hierarchy simultaneously, the first loop can run independently for each module, ensuring the independence and non-interference of the adjustment process. This not only improves the stability of the adjustment process but also enhances development efficiency.

[0075] In some embodiments, it can be first determined whether the first module is already at the next level of the first common parent module. If the first module is not at the next level of the first common parent module, then the first loop is executed.

[0076] The following example uses module b1 as the first module and the top module as the first shared module, combined with... Figure 2 Here's an example. For instance, during the first execution of the first loop, the connection between module b1 and its current parent module (e.g., module bb) is broken. Then, module b1 is moved up one level, establishing a connection between it and the parent module of the current parent module (e.g., module top). After one iteration, if module b1 is now one level below module top, the loop stops.

[0077] The first module is module b2, and the first shared module is module top, combined with... Figure 2Here's an example. For instance, during the first execution of the first loop, the connection between module b2 and its current parent module (e.g., module bb) is broken. Then, module b2 is moved up one level, establishing a connection between b2 and the parent module's parent module (e.g., module top). After one loop, module b2 is located one level below module top, so the loop stops. When moving b2, b2, its submodules, and their submodules are moved as a whole. In other words, this application moves modules hierarchically, treating the module and all its submodules (including their submodules) as a single unit. This ensures that the module's internal structure and connections remain unchanged.

[0078] In some embodiments, when the first target module is connected to the first common parent module through at least one intermediate module, the first module can be moved multiple times level by level to gradually move the first module to the lower level of the first target module. For example, a second loop is executed until the first module is moved to the next level below the first target module. The second loop involves: disconnecting the connection between the first module and its current parent module, and moving the first module down one level along the hierarchical path of the first target module. In the first execution of the second loop, the current parent module of the first module is the first common parent module. For example, the second loop may specifically involve: locating the integrated code of the current parent module of the first module based on the hierarchical structure data of the first chip, removing code related to the first module from the integrated code of the current parent module of the first module; locating the integrated code of the child module of the current parent module of the first module based on the hierarchical structure data of the first chip, and adding code related to the first module to the integrated code of the child module of the current parent module of the first module.

[0079] The second loop is an iterative process used to progressively adjust the module hierarchy. By disconnecting the first module from its current parent module in each loop and moving the first module to the next level, the hierarchical structure is updated gradually. This second loop mechanism ensures that the first module moves along a predetermined path without requiring a complete modification of the entire hierarchy, thus reducing the probability of errors during integration.

[0080] The current parent module of the first module refers to the superior module to which the first module directly belongs at any given moment. In the initial state, i.e., during the first execution of the second loop, the current parent module of the first module is the first common parent module. As the second loop executes, the current parent module of the first module will continuously change until it becomes the first target module.

[0081] The following example uses module b1 as the first module and module a1 as the first target module, combined with... Figure 2Provide a specific implementation for moving module b1 to the next level below module a1.

[0082] First, based on the hierarchical structure data of the first chip, the hierarchical path of module b1 (e.g., top / bb / b1) and the hierarchical path of module a1 (e.g., top / aa / a1) are obtained. Based on the hierarchical paths of modules b1 and a1, the first common parent module of both modules is determined to be the top module. Next, module b1 is moved level by level according to its hierarchical path to the level below the top module. The first loop is executed once, disconnecting module b1 from module bb and moving module bb to the level below the top module. Module b1 is then moved level by level according to the hierarchical path of module a1 to the level below the a1 module. For example, the second loop is executed once, disconnecting module b1 from its current parent module (e.g., the top module) and moving module b1 down one level, for example, establishing a connection between module b1 and module aa, with module b1 located at the level below module aa. Execute the second loop twice, disconnect the connection between module b1 and the current parent module such as module aa, move module b1 down one level, or establish a connection between module b1 and module a1, and place module b1 at the next level of module a1.

[0083] In some embodiments, the chip integration method provided in this application, when there is a feedthrough requirement, redirects the signal direction based on the hierarchical structure of the first chip to meet the feedthrough requirement. Here, the feedthrough requirement is a specific inter-module connection requirement, where the signal of a module needs to be directly transmitted from one module to another without any intermediate processing or logical transformation. In other words, it requires the signal of one module to pass through an intermediate module, such as a feedthrough module, to reach another module. The following describes... Figure 3 To introduce, Figure 3 This is a flowchart illustrating another chip integration method provided in an embodiment of this application, as shown below. Figure 3 As shown, the method includes:

[0084] S301, in response to the second instruction, obtains the hierarchical path of the second module and the hierarchical path of the second target module based on the hierarchical structure data.

[0085] The second instruction instructs the signal from the second module to pass through the pass-through module to the second target module. The second module is the source module, i.e., the signal initiating module; the second target module is the destination module, i.e., the signal receiving module. In other words, the second instruction instructs the signal generated by the second module to be directly transmitted to the second target module through the pass-through module. The pass-through module can act as an intermediary or bridge for signal transmission between modules. In some embodiments, responding to the second instruction can specifically be responding to the developer inputting the second instruction in the instruction input box of the chip integration software.

[0086] In response to the second instruction, the second module and the second target module can be parsed out based on the second instruction, and the hierarchical paths of the second module and the second target module can be obtained based on the hierarchical data structure of the first chip. This avoids the complexity of manually searching for module paths, thereby improving integration efficiency, reducing human error, and ultimately supporting the frequent architectural adjustment needs during chip design.

[0087] The method for obtaining the hierarchical path of the second module and the hierarchical path of the second target module is the same as the method for obtaining the hierarchical path of the first module and the hierarchical path of the first target module. Please refer to the previous introduction, and it will not be repeated here.

[0088] It should be understood that the second module can be the first module mentioned above or other modules of the first chip; this application does not specifically limit this. This application does not restrict the execution order. In some embodiments, the following can be executed first: Figure 2 Execute the method shown below Figure 3 The method shown. In some other embodiments, it may be performed first. Figure 3 Execute the method shown below Figure 2 The method shown. In some embodiments, Figure 2 The method shown and Figure 3 The methods shown can be executed individually.

[0089] S302, based on the hierarchical path of the second module and the hierarchical path of the second target module, determine the second common parent module of the second module and the second target module.

[0090] As described above, a common parent module refers to the nearest common parent module of two modules on their hierarchical path. The second common parent module is the nearest common parent module of the second module and the second target module on their hierarchical path.

[0091] In some embodiments, the second common parent module of the second module and the second target module is determined by traversing the hierarchical path of the second module and the second target module. For example, the hierarchical path of the second module and the second target module is traversed upwards layer by layer until the first common parent module is found, which is the second common parent module.

[0092] S303, based on the second common parent module, transmits the signal of the second module through the transparent transmission module to the second target module.

[0093] After obtaining the first module and the first target module, the signal of the second module can be transmitted through the transparent transmission module to the second target module based on the second common parent module.

[0094] In some embodiments, by modifying the integration code of the first common parent module, the signal of the second module is routed through the pass-through module to the second target module. This requires only local modifications, improving integration efficiency and avoiding errors.

[0095] In this embodiment of the application, in response to the second instruction, the transparent transmission requirement can be realized based on the hierarchical structure data, which can avoid recoding and manual wiring, thereby enabling a rapid response to the structural adjustment requirements in chip design, and thus significantly improving integration efficiency and design flexibility.

[0096] In some embodiments, signal pass-through can be achieved in the following manner.

[0097] The first step is to remove the first signal channel from the integrated code of the second common parent module, whereby the first signal channel is used to transmit signals from the second module to the second target module.

[0098] In some embodiments, the first signal channel may be code within the integrated code of the second common parent module used to define the connection relationship between the first output port and the first input port. The first output port is a port in the third module used to output signals from the second target module, and the third module is a module located at the next level below the second common parent module in the hierarchical path of the second module. The first input port is a port in the fourth module used to receive signals from the second target module. The fourth module is also a module located at the next level below the second common parent module in the hierarchical path of the second target module. In other words, the first signal channel may be code within the integrated code of the second common parent module used to define the connection relationship between the output port of the third module and the input port of the fourth module. Specifically, the first signal channel is responsible for outputting signals from the second module from the third module and transmitting them to the input port of the fourth module.

[0099] For example, based on the hierarchical structure data of the first chip, the integrated code of the second common parent module is located. Within the integrated code of the second common parent module, the first signal channel used to transmit signals from the second module to the second target module is found and removed. For instance, the code defining the connection between the first output port and the first input port is found and removed within the integrated code of the second common parent module. This disconnects the output port of the third module from the input port of the fourth module. Consequently, signals transmitted from the second module and output through the third module are truncated in the second common parent module and cannot propagate further.

[0100] The second step is to establish a second signal channel in the integrated code of the second common parent module. The second signal channel is used to transmit the signals of the second module to the second target module through the transparent transmission module.

[0101] In some embodiments, the integration code of the second common parent module adds a signal channel for transmitting signals from the third module to the pass-through module, and adds a signal channel for transmitting signals from the pass-through module to the second target module. These two signal channels constitute the second signal channel. For example, the integration code of the second common parent module adds code for defining the connection relationship between the first output port and the input port of the pass-through module. The integration code of the second common parent module also adds code for defining the connection relationship between the output port of the pass-through module and the input port of the second target module.

[0102] For example, in the integration code of the second common parent module, two new signal channels are added, and signal channels such as signal channel A and signal channel B are defined. For instance, signal channel A is defined as carrying signals from the output of the second module to the input of the pass-through module, and signal channel B is defined as carrying signals from the output of the pass-through module to the input of the second target module. The output connection of the third module is modified by connecting the output port of the third module, which is used to output signals to the second module, to signal channel A, so that its output signal is directed to the pass-through module instead of the old path. The input connection of the second target module is modified by connecting the input port of the second target module to signal channel B, so that its input signal source becomes the pass-through module E.

[0103] For example, combining Figure 4 Taking module b1 as the second module and module c1 as the second target module as an example. Before modification: the signal from module b1 first flows into module aa, then through the second common parent module top, and finally into module cc. The pass-through requirement is: the signal from module b1 first flows into module aa, then through module bb, and finally to module cc. The specific implementation is: based on the hierarchical paths of modules b1 and cc, the second common parent module is determined to be module top. In the integration code of module top, the signal channel between the output port of module aa used to output signals from module b1 and the input port of module cc used to receive signals from module b1 is removed. In the integration code of module top, a new signal channel is added between the output port of module aa used to output signals from module b1 and the input port of the pass-through module bb. In the integration code of module top, a new signal channel is added between the output port of module bb and the input port of module cc used to receive input signals from module b1. The input port and output port of module bb are used to transmit signals from module b1. In some embodiments, the integration code of the bb module can be modified first to add input and output ports for outputting signals from the b1 module.

[0104] In this application embodiment, "removal" can be understood as no longer using, or commented as not being used.

[0105] The following describes the chip integration method provided in the embodiments of this application, using specific scenarios.

[0106] As chip size increases, the connections between modules become more complex, and the integration of the chip's top layer becomes increasingly massive. Furthermore, during chip design, factors such as changes in architectural requirements, the difficulty of backend implementation, and the partitioning of power consumption modules all influence the hierarchical relationships between chip modules. The hard partitioning method and the pass-through implementation method are also important factors. To address these issues and improve the flexibility and efficiency of chip design, this application provides a module integration method based on binary trees and linked lists.

[0107] Traditional chip module integration methods are very time-consuming from start to finish. During large-scale SoC design, the following situations may arise: due to structural changes, the chip modules may require hierarchical adjustments; there may be new requirements for merging or disassembling modules; when the chip area is large, there may be a need to divide it into smaller modules and harden them. If any of these requirements exist, all previously completed chip integration work will be rendered useless, requiring re-integration, which consumes a significant amount of time and manpower and is prone to errors.

[0108] To address the aforementioned technical problems, this application proposes a method that establishes hierarchical structure data for each module during chip integration. This allows for flexible adjustments based on the previously established hierarchical structure data when module hierarchies change or signal connection relationships (such as pass-through) change, facilitating easier modifications rather than requiring a complete overhaul every time requirements change. The method proposed in this application enables the elevation and repositioning of module hierarchies, repackaging or splitting of modules, and rapid implementation of pass-through, thereby significantly improving the efficiency and accuracy of chip design.

[0109] The advantages achieved through this application are as follows: Developers can directly move modules up or down in hierarchy without recoding. Developers can directly repackage or split software modules without rewriting code; during chip integration, developers can directly achieve transparent reconnection by adjusting the circuit design without rewriting code.

[0110] The key points this application seeks to protect are: 1. Using data structures such as binary trees, i.e., hierarchical data structures, to store the connection relationships between modules. 2. Modifying the relationships between modules, through hierarchical data structures similar to linked lists, to achieve changes in hierarchy and pass-through methods.

[0111] Traditional top-level integration solutions ultimately achieve the following: Figure 5 As shown in the example, the integration of various modules can be completed. This application not only accomplishes the following: Figure 5 The effect shown is achieved by additionally extracting and recording the relationships between these modules during implementation. These relationships are recorded using programming languages ​​such as Python, C, C++, and command-line languages ​​(Tcl), with `top` as the tree node. Modules at each level within `top` (e.g., modules aa, bb, cc) are recorded as first-level leaves. Similarly, the next level, aa_1, aa_2, etc., are also recorded as a binary tree table. If the chip module structure changes, such as changes in hierarchy or the need for pass-through, the relationships recorded in this binary tree can be used to directly implement hierarchical advancement / demotion and pass-through.

[0112] The following provides a specific implementation method and details how to achieve efficient integration and dynamic adjustment of chip modules using binary tree and linked list data structures. This chip integration method is as follows: Figure 6 As shown, it includes:

[0113] S601: Based on the structural relationship of the chip plan, complete the code writing of each module, realize the connection between modules, and use a high-level language to record the hierarchical relationship between modules.

[0114] S602: When there is a need to change the hierarchy of modules, modify the hierarchical relationship of modules based on the hierarchical structure data.

[0115] like Figure 7 As shown, if you need to move b1 from the bb module to the aa module, perform the following operations:

[0116] like Figure 7 As shown in (b), disconnect the original connection between module b1 and module bb as disconnect=>top / bbconnection b1, and establish a connection between module b1 and module top as connect=>top connection b1. Remove the original connection between module b1 and module bb as disconnect=>top / bb connection b1.

[0117] like Figure 7 As shown in (c), disconnect the connection between module b1 and module top as disconnect => topconnection b1. Establish the connection between module b1 and module aa as connect => top / aa connection b1. Remove the connection between module b1 and module top as delete => top connection b1.

[0118] S603: When there is a signal pass-through requirement with modules, signal pass-through is achieved based on hierarchical data structure.

[0119] For example, such as Figure 8 As shown in (a), if there is a signal connection between module b1 and module cc, the path of the signal connection between module b1 and module cc is: Top / aa / b1<=>top / aa<=>top / cc.

[0120] When the chip requires pass-through, such as Figure 8 As shown in (b), the signal of b1 is required to pass through the specified bb module to reach the cc module. At this point, with the help of the relationship tree information, there is no need to reconnect; the target connection can be achieved simply by performing the following operations: Disconnect the original connection: top / aa / b1<=>top / aa disconnect top / cc, such as disconnecting the connection between the aa module and the cc module in the top module; Establish a new connection: top / aa / b1<=>top / aa connect top / bb, such as establishing the connection between the aa module and the bb module; Establish a new connection: top / bb connect top / cc, such as establishing the connection between the bb module and the cc module.

[0121] This application automates and enhances the flexibility of chip module integration by introducing binary tree and linked list data structures, significantly improving the efficiency and maintainability of chip design. The method used in this application to automate and enhance chip module integration through binary tree and linked list data structures is not only applicable to current chip design processes but also provides a feasible solution for the integration of complex chips in the future.

[0122] The method embodiments of this application have been described in detail above with reference to the accompanying drawings. The device embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the description of the device embodiments corresponds to the method embodiments; therefore, any parts not described in detail can be referred to the method embodiments above.

[0123] Figure 9 This is a schematic diagram of the structure of a chip integration device provided in an embodiment of this application, as shown below. Figure 9 As shown, the chip integration device 900 includes a first acquisition module 910, a second acquisition module 920, a determination module 930, and a movement module 940.

[0124] The first acquisition module 910 is used to acquire hierarchical structure data for integrating the first chip; the hierarchical structure data is used to indicate the hierarchical relationship between the multiple modules included in the first chip;

[0125] The second acquisition module 920 is used to acquire the hierarchical path of the first module and the hierarchical path of the first target module based on the hierarchical structure data.

[0126] Module 930 is determined to traverse the hierarchical path of the first module and the hierarchical path of the first target module, and determine the first common parent module of the first module and the first target module.

[0127] The moving module 940 is used to move the first module to the next level of the first target module based on the first common parent module.

[0128] The moving module 940 is also used to disconnect the connection between the first module and its current parent module, and to move the first module to the next level of the first common parent module;

[0129] Disconnect the first module from the first common parent module and move the first module to the next level of the first target module.

[0130] The moving module 940 is also used to execute a first loop until the first module is moved to the next level of the first common parent module; the first loop is: disconnect the connection between the first module and the current parent module of the first module, and move the first module up one level along the hierarchical path of the first module.

[0131] The moving module 940 is also used to execute a second loop until the first module is moved to the next level of the first target module; the second loop is: disconnect the connection between the first module and the current parent module of the first module, and move the first module down one level along the hierarchical path of the first target module; in the case of the first execution of the second loop, the current parent module of the first module is the first common parent module.

[0132] In some embodiments, the chip integration device may further include a third acquisition module, a second confirmation module, and a signal adjustment module (all not shown in the figure).

[0133] The third acquisition module is used to, in response to the second instruction, acquire the hierarchical path of the second module and the hierarchical path of the second target module based on the hierarchical structure data; wherein, the second instruction is used to instruct the signal of the second module to pass through the transparent transmission module to reach the second target module;

[0134] The second confirmation module is used to determine the second common parent module of the second module and the second target module based on the hierarchical path of the second module and the hierarchical path of the second target module.

[0135] The signal adjustment module is used to transmit the signal of the second module through the pass-through module to the second target module based on the second common parent module.

[0136] The signal adjustment module is also used to remove the first signal channel from the integrated code of the second common parent module; the first signal channel is used to transmit the signal of the second module to the second target module; a second signal channel is established in the integrated code of the second common parent module; the second signal channel is used to transmit the signal of the second module to the second target module through the transparent transmission module.

[0137] The signal adjustment module is also used to remove the code in the integrated code of the second common parent module that defines the connection relationship between the first output port and the first input port.

[0138] The signal adjustment module is also used to add code to the integrated code of the second common parent module to define the connection relationship between the first output port and the input port of the transparent transmission module; and to add code to the integrated code of the second common parent module to define the connection relationship between the output port of the transparent transmission module and the input port of the second target module.

[0139] Figure 10 This is a schematic diagram of the structure of a chip integration device 1000 provided in an embodiment of this application. Exemplarily, the chip integration device 1000 includes one or more processors 1010 and one or more memories 1020. Figure 10 The chip integration device 1000 is used to implement the chip integration method described in the above method embodiments. The processor 1010 can support the chip integration device 1000 in implementing the method described in the preceding method embodiments.

[0140] The memory 1020 stores a program that can be executed by the processor 1010, causing the processor 1010 to perform the methods described in the preceding method embodiments. The memory 1020 may be independent of the processor 1010 or integrated into the processor 1010.

[0141] Optionally, the chip integration device 1000 may also include a transceiver 1030. The processor 1010 can communicate with other devices or chips through the transceiver 1030. For example, the processor 1010 can send and receive data with other devices or chips through the transceiver 1030.

[0142] This application provides a computer storage medium that stores one or more programs, which can be executed by one or more processors to implement the steps of the methods described in any of the above embodiments.

[0143] It should be noted that the descriptions of the storage medium and device embodiments above are similar to the descriptions of the method embodiments above, and have similar beneficial effects. For technical details not disclosed in the storage medium and device embodiments of this application, please refer to the descriptions of the method embodiments of this application for understanding.

[0144] The aforementioned processor can be at least one of the following: application-specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field-programmable gate array (FPGA), central processing unit (CPU), controller, microcontroller, and microprocessor. It is understood that other electronic devices can also implement the functions of the aforementioned processor, and this application does not specifically limit the specific implementation.

[0145] The aforementioned computer storage media / memory can be read-only memory, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD ROM), etc.

[0146] This application provides a computer program including computer-readable code. When the computer-readable code runs in an electronic device, the processor in the electronic device executes some or all of the steps in the above-described method.

[0147] This application provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program. When the computer program is read and executed by a computer, it implements some or all of the steps in the above-described method. This computer program product can be implemented specifically through hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium; in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0148] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0149] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0150] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0151] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0152] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0153] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0154] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A chip integration method, characterized in that, The method includes: In response to a first instruction, hierarchical structure data for integrating a first chip is acquired; wherein the first instruction is used to instruct a first module in the first chip to be moved from the current level to the level below the first target module; the hierarchical structure data is used to indicate the hierarchical relationship between the multiple modules included in the first chip; Based on the hierarchical structure data, the hierarchical path of the first module and the hierarchical path of the first target module are obtained. Traverse the hierarchical path of the first module and the hierarchical path of the first target module to determine the first common parent module of the first module and the first target module; the first module is connected to the first common parent module through an intermediate module; Disconnect the first module from its current parent module and move the first module to the next level of the first common parent module; disconnect the first module from its first common parent module and move the first module to the next level of the first target module.

2. The method according to claim 1, characterized in that, Disconnecting the first module from its current parent module and moving the first module to the next level of the first common parent module includes: The first loop is executed until the first module is moved to the next level of the first common parent module; the first loop is: disconnect the connection between the first module and the current parent module of the first module, and move the first module up one level along the hierarchical path of the first module.

3. The method according to claim 1, characterized in that, The first target module is connected to the first common parent module through an intermediate module; disconnecting the connection between the first module and the first common parent module, and moving the first module to the next layer below the first target module, includes: The second loop is executed until the first module is moved to the next level of the first target module; the second loop is: disconnect the connection between the first module and the current parent module of the first module, and move the first module down one level along the hierarchical path of the first target module; in the case of the first execution of the second loop, the current parent module of the first module is the first common parent module.

4. The method according to any one of claims 1-3, characterized in that, The method further includes: In response to the second instruction, based on the hierarchical structure data, the hierarchical path of the second module and the hierarchical path of the second target module are obtained; wherein, the second instruction is used to instruct the signal of the second module to pass through the transparent transmission module to reach the second target module; Based on the hierarchical path of the second module and the hierarchical path of the second target module, determine the second common parent module of the second module and the second target module; Based on the second common parent module, the signal of the second module is transmitted through the transparent transmission module to the second target module.

5. The method according to claim 4, characterized in that, Based on the second common parent module, the signal from the second module is transmitted through the transparent transmission module to the second target module, including: Remove the first signal channel from the integrated code of the second common parent module; the first signal channel is used to transmit signals from the second module to the second target module. A second signal channel is established in the integrated code of the second common parent module; the second signal channel is used to transmit the signal of the second module to the second target module through the transparent transmission module.

6. The method according to claim 5, characterized in that, The removal of the first signal channel from the integrated code of the second common parent module includes: Remove the code in the integrated code of the second common parent module that defines the connection relationship between the first output port and the first input port; The first output port is a port in the third module used to output signals from the second module. The third module is a module located at the next level below the second common parent module in the hierarchical path of the second module. The first input port is a port in the fourth module used to receive signals from the second module. The fourth module is a module located at the next level below the second common parent module in the hierarchical path of the second target module.

7. The method according to claim 6, characterized in that, The establishment of the second signal channel in the integrated code of the second common parent module includes: In the integrated code of the second common parent module, new code is added to define the connection relationship between the first output port and the input port of the transparent transmission module; In the integrated code of the second common parent module, new code is added to define the connection relationship between the output port of the transparent transmission module and the input port of the second target module.

8. A chip integration device, characterized in that, The device includes: The first acquisition module is used to acquire hierarchical structure data for integrating the first chip; the hierarchical structure data is used to indicate the hierarchical relationship between the multiple modules included in the first chip. The second acquisition module is used to acquire the hierarchical path of the first module and the hierarchical path of the first target module based on the hierarchical structure data. A determination module is used to traverse the hierarchical path of the first module and the hierarchical path of the first target module to determine the first common parent module of the first module and the first target module; the first module is connected to the first common parent module through an intermediate module; The moving module is used to disconnect the connection between the first module and its current parent module, and move the first module to the next level of the first common parent module; disconnect the connection between the first module and the first common parent module, and move the first module to the next level of the first target module.

9. A chip integration device, characterized in that, The device includes: One or more processors; A memory for storing one or more programs, which, when executed by one or more processors, cause the device to implement the chip integration method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the chip integration method according to any one of claims 1 to 7.

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