Modeling method, system and related device for chip layout planning

Abstract

The application is suitable for the chip technical field, and particularly relates to a chip layout planning modeling method and system and related equipment, the method comprises the following steps: obtaining configuration information of a chip, and establishing a configuration file according to the configuration information; saving module information into a module corresponding to a module list; establishing a multi-level nested data structure according to module relationship data; performing coordinate calculation and merging on modules of different levels in the nested data structure to obtain module coordinate data with coordinate information of all modules; performing shape drawing according to the module coordinate data to obtain a chip layout model. Compared with the prior art, the application can be iterated in real time according to the actual progress of chip design, greatly facilitating designers to deeply think about chip architecture design, more accurately estimate the layout area, and better determine the distribution position of the module, so that the over-reliance of top layout planning work on traditional EDA tools is eliminated.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a modeling method, system and related equipment for chip layout planning. Background Technology

[0002] With the advancement of integrated circuit process nodes, especially after entering the nanometer scale, the complexity, scale, and integration of designs have been continuously increasing. This phenomenon has directly led to an extension of the design cycle, including a corresponding increase in the back-end physical design cycle. However, front-end design can also significantly shorten back-end design time, posing extremely serious challenges to back-end designers. In this context, for the entire chip, from floorplanning to the rational partitioning of modules, becomes crucial. If the chip architecture can be modeled quickly in the early stages of a project, designers will be able to better understand the architecture design, more accurately estimate the layout area, and clearly define the distribution of modules, thereby greatly improving the efficiency of top-level floorplanning and design.

[0003] Traditional Electronic Design Automation (EDA) physical design methods have long faced the challenge of lengthy design cycles and are highly dependent on the results of lower-level modules. During the physical design of top-level modules, sub-modules must complete placement and routing first, and the complete accuracy of module connection information must be guaranteed. This requirement significantly extends runtime, severely hindering the placement planning process of top-level modules. Consequently, in the early stages of a project, designers struggle to accurately estimate crucial information such as the overall chip size, module location, and area. This leads to lengthy iteration times and numerous iterations, severely limiting chip design efficiency.

[0004] Therefore, there is an urgent need for a new modeling method, system, and related equipment for chip layout planning to solve the above-mentioned technical problems. Summary of the Invention

[0005] This invention provides a modeling method, system, and related equipment for chip layout planning, aiming to improve chip design efficiency.

[0006] In a first aspect, the present invention provides a modeling method for chip layout planning, the modeling method comprising the following steps:

[0007] S1. Obtain the configuration information of the chip and establish a configuration file based on the configuration information; wherein, the configuration information includes module information and module call information of each module in the chip, and the module information includes module name, module coordinate information and module offset information;

[0008] S2. Read the configuration file, iterate through the module names of all the modules in the configuration file, and build a module list based on the module call information; save the module information to the module corresponding to the module list to obtain module relationship data;

[0009] S3. Establish a multi-level nested data structure based on the module relationship data;

[0010] S4. Calculate and merge the coordinates of the modules at different levels in the nested data structure to obtain module coordinate data that contains the coordinate information of all the modules;

[0011] S5. Draw the shape according to the module coordinate data to obtain the chip layout model.

[0012] Preferably, step S3 specifically includes: defining the called module as a sub-module, the module that calls other modules as a parent module, and placing the module information of the sub-module in the module information of the parent module according to the module relationship data to form a multi-level nested data structure.

[0013] Preferably, step S4 includes the following sub-steps:

[0014] S41. Starting from the lowest level module in the nested data structure, calculate the displacement coordinate information of each module in the current level based on its corresponding module coordinate information and module offset information;

[0015] S42. Enter the next level, calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information, and add the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship.

[0016] S43, determine whether the current level is the top level in the nested data structure; if yes, merge the displacement coordinate information of each module in the top level to obtain the module coordinate data; if no, return to step S42.

[0017] Preferably, the module offset information includes module rotation information and module offset coordinates.

[0018] Secondly, the present invention also provides a modeling system for chip layout planning, comprising:

[0019] A configuration file creation module is used to obtain the chip's configuration information and create a configuration file based on the configuration information; wherein, the configuration information includes module information and module call information for each module in the chip, and the module information includes module name, module coordinate information and module offset information;

[0020] The module relationship establishment module is used to read the configuration file, traverse the module names of all the modules in the configuration file, and establish a module list based on the module call information; save the module information to the module corresponding to the module list to obtain module relationship data;

[0021] A nested data structure creation module is used to create multi-level nested data structures based on the module relationship data.

[0022] The coordinate calculation module is used to calculate and merge the coordinates of the modules at different levels in the nested data structure to obtain module coordinate data containing the coordinate information of all the modules.

[0023] The drawing module is used to draw shapes based on the coordinate data of the module to obtain a chip layout model.

[0024] Preferably, in the nested data structure establishment module, the called module is defined as a sub-module, the module that calls other modules is defined as a parent module, and the module information of the sub-module is placed in the module information of the parent module according to the module relationship data to form a multi-level nested data structure.

[0025] Preferably, the coordinate calculation module includes a module offset calculation unit, a comparison unit, and a judgment unit;

[0026] The module offset calculation unit is used to start the calculation from the lowest level of the module in the nested data structure, and calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information;

[0027] The comparison unit is used to enter the next level, calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information, and add the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship.

[0028] The judgment unit is used to determine whether the current level is the top level in the nested data structure; if so, the displacement coordinate information of each module in the top level is merged to obtain the module coordinate data; if not, the comparison unit is returned.

[0029] Preferably, the modeling system further includes a ruler module, which is used to calculate the distance between any two points in the chip layout model.

[0030] Thirdly, the present invention also provides a computer device, including: a memory, a processor, and a chip layout planning modeling program stored in the memory and executable on the processor, wherein when the processor executes the chip layout planning modeling program, it implements the steps in the chip layout planning modeling method as described in any of the above embodiments.

[0031] Fourthly, the present invention also provides a computer-readable storage medium storing a chip layout planning modeling program, wherein when the chip layout planning modeling program is executed by a processor, it implements the steps in the chip layout planning modeling method as described in any of the above embodiments.

[0032] Compared to existing technologies, this invention obtains chip configuration information through EDA tool reports or custom methods. It nests chip modules into nested data structures based on their calling relationships, calculates module coordinate data containing the coordinate information of all modules from these nested data structures, and draws a chip layout model based on this coordinate data. This allows for full-chip layout planning modeling in the early stages of a project, significantly improving chip design efficiency. Furthermore, this method can iterate in real-time according to the actual project progress, greatly facilitating designers to deeply consider chip architecture design, more accurately estimate layout area, and better determine module distribution, thereby reducing the over-reliance on traditional EDA tools for top-level layout planning. Attached Figure Description

[0033] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0034] Figure 1 This is a flowchart of the chip layout planning modeling method provided in the embodiments of the present invention;

[0035] Figure 2 This is a schematic diagram of the configuration file reading logic of the chip layout planning modeling method provided in this embodiment of the invention;

[0036] Figure 3 This is a schematic diagram of the nested data structure of the chip layout planning modeling method provided in the embodiments of the present invention;

[0037] Figure 4 This is a schematic diagram of the module coordinate data acquisition logic of the chip layout planning modeling method provided in this embodiment of the invention;

[0038] Figure 5 This is a schematic diagram of a chip layout model for the chip layout planning modeling method provided in this embodiment of the invention;

[0039] Figure 6 This is a schematic diagram of a chip layout model under a ruler display effect, illustrating the chip layout planning modeling method provided in this embodiment of the invention.

[0040] Figure 7 This is a schematic diagram of the chip layout planning modeling system provided in an embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of the computer device structure provided in an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0043] Example 1

[0044] Please refer to Figure 1 This invention provides a modeling method for chip layout planning, the modeling method comprising the following steps:

[0045] S1. Obtain the configuration information of the chip and establish a configuration file based on the configuration information; wherein, the configuration information includes module information and module call information of each module in the chip, and the module information includes module name, module coordinate information and module offset information.

[0046] In this embodiment of the invention, the configuration information can be obtained by using a script to capture EDA tool reports or by using a custom method. The configuration file is a CFG format file (Configuration File). Please refer to Table 1 below, which is a schematic table of the configuration file contents of the chip layout planning modeling method provided in this embodiment of the invention.

[0047] Table 1

[0048]

[0049] In this table, A, B, C, and D represent module names; subblock list represents the names of the submodules used (i.e., the modules being called); if empty, it means no other submodules are called; Boundary represents the vertex coordinates of the module; FloorPlan represents information about other modules being called; if empty, it means no other submodules are called; if a call exists, the first element of each line is the module instantiation name, the second element is the module name, the third and fourth elements represent the module offset coordinates, and the fifth element is the module rotation information.

[0050] In this embodiment of the invention, the module offset information includes module rotation information and module offset coordinates, which are used to represent the offset coordinate value and rotation value of the module when it is displaced from the original coordinate information.

[0051] S2. Read the configuration file, iterate through the module names of all the modules in the configuration file, and build a module list based on the module call information; save the module information to the module corresponding to the module list to obtain module relationship data.

[0052] In the embodiments of the present invention, please refer to Figure 2 , Figure 2 This is a schematic diagram of the configuration file reading logic of the chip layout planning modeling method provided in this embodiment of the invention. The module names of all modules in the configuration file are traversed, and a module list is established based on the module call information. The module relationship data includes multiple newly established modules and their corresponding module information, where "Module A / Module B" indicates that module B is a submodule of module A, and "Module A / Module B / Module C" indicates that module C is a submodule of module B.

[0053] S3. Establish a multi-level nested data structure based on the module relationship data;

[0054] In this embodiment of the invention, step S3 specifically includes: defining the called module as a sub-module, the module that calls other modules as a parent module, and placing the module information of the sub-module in the module information of the parent module according to the module relationship data to form a multi-level nested data structure.

[0055] For example, please refer to Figure 3 , Figure 3This is a schematic diagram of the nested data structure of the chip layout planning modeling method provided in this embodiment of the invention. The diagram includes module A, module A / module B, and module A / module B / module C. Module information from "module A / module B / module C" is placed in "module A / module B"; and module information from "module A / module B" is placed in "module A," thus completing the construction of the nested data structure. In this way, each module is in its corresponding level, forming a multi-level structure that conforms to the module calling relationship.

[0056] S4. Calculate and merge the coordinates of the modules at different levels in the nested data structure to obtain module coordinate data that contains the coordinate information of all the modules;

[0057] In this embodiment of the invention, step S4 includes the following sub-steps:

[0058] S41. Starting from the lowest level module in the nested data structure, calculate the displacement coordinate information of each module in the current level based on its corresponding module coordinate information and module offset information;

[0059] S42. Enter the next level, calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information, and add the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship.

[0060] S43, determine whether the current level is the top level in the nested data structure; if yes, merge the displacement coordinate information of each module in the top level to obtain the module coordinate data; if no, return to step S42.

[0061] For details, please refer to Figure 4. Figure 4 This is a schematic diagram illustrating the module coordinate data acquisition logic of the chip layout planning modeling method provided in this embodiment of the invention. The calculation begins with the lowest-level module in the nested data structure. For the lowest-level module, its displacement coordinates after displacement and rotation are calculated based on its module coordinate information and module offset information. Starting from the second-to-last module, not only is its own displacement coordinate information calculated, but the module information of other called models (i.e., sub-modules) is also added to its own coordinate information, ensuring it encompasses the coordinates of both its own module and the called modules. This process continues until the coordinate information of the top-level module is calculated. At this point, the coordinate information of the top-level module contains the coordinate information of all modules, and the module coordinate data is output.

[0062] S5. Draw the shape according to the module coordinate data to obtain the chip layout model.

[0063] In the embodiments of the present invention, please refer to Figures 5 to 6 , Figure 5 This is a schematic diagram of a chip layout model for the chip layout planning modeling method provided in this embodiment of the invention; Figure 6 This is a schematic diagram of the chip layout model under the scale display effect of the chip layout planning modeling method provided in the embodiment of the present invention.

[0064] Based on the nested structure hierarchy, display parameters such as transparency and font are set for different level modules to display information such as outline, side length, coordinates, and name, as shown in Figures 5 and 6. In Figure 5, the large square represents the top-level module layout, and the squares within it are sub-modules. The chip layout model also includes a ruler function that can calculate the distance between any two points in the model. This ruler function is detected by keyboard and mouse button presses; for example, it can be activated by the user pressing the "U" key, at which point the word "Ruler" appears in the chip layout model. The user can use the mouse to click on the start and end points of the measurement path, and a line segment will then appear on the canvas (e.g., ...). Figure 6 The line segment below module C in the upper left corner of the chip displays the distance between two points at the center of the line segment, in micrometers (um). It also displays the module name of each module, allowing you to quickly understand the layout of the chip's modules.

[0065] Furthermore, when subsequent iterations are needed, the module information corresponding to the module in the configuration file can be directly modified and populated to quickly model the chip layout plan and display the iterated chip layout model in real time.

[0066] Compared to existing technologies, this invention obtains chip configuration information through EDA tool reports or custom methods. It nests chip modules into nested data structures based on their calling relationships, calculates module coordinate data containing the coordinate information of all modules from these nested data structures, and draws a chip layout model based on this coordinate data. This allows for full-chip layout planning modeling in the early stages of a project, significantly improving chip design efficiency. Furthermore, this method can iterate in real-time according to the actual project progress, greatly facilitating designers to deeply consider chip architecture design, more accurately estimate layout area, and better determine module distribution, thereby reducing the over-reliance on traditional EDA tools for top-level layout planning.

[0067] Example 2

[0068] This invention also provides a chip layout planning modeling system, please refer to... Figure 7 , Figure 7This is a schematic diagram of the chip layout planning modeling system 200 provided in an embodiment of the present invention, which includes:

[0069] 201. A configuration file creation module is used to obtain the configuration information of the chip and create a configuration file based on the configuration information; wherein, the configuration information includes module information and module call information of each module in the chip, and the module information includes module name, module coordinate information and module offset information.

[0070] 202. Module relationship establishment module, used to read the configuration file, traverse the module names of all the modules in the configuration file and establish a module list based on the module call information; save the module information to the module corresponding to the module list to obtain module relationship data;

[0071] 203. Nested data structure establishment module, used to establish multi-level nested data structures based on the module relationship data;

[0072] In this embodiment of the invention, the nested data structure establishment module 203 defines the called module as a sub-module and the module that calls other modules as a parent module. Based on the module relationship data, the module information of the sub-module is placed in the module information of the parent module to form a multi-level nested data structure.

[0073] 204. Coordinate calculation module, used to calculate and merge the coordinates of the modules at different levels in the nested data structure to obtain module coordinate data containing the coordinate information of all the modules;

[0074] In this embodiment of the invention, the coordinate calculation module 204 includes a module offset calculation unit, a comparison unit, and a judgment unit;

[0075] The module offset calculation unit is used to start the calculation from the lowest level of the module in the nested data structure, and calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information;

[0076] The comparison unit is used to enter the next level, calculate the displacement coordinate information of each module in the current level according to its corresponding module coordinate information and module offset information, and add the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship.

[0077] The judgment unit is used to determine whether the current level is the top level in the nested data structure; if so, the displacement coordinate information of each module in the top level is merged to obtain the module coordinate data; if not, the comparison unit is returned.

[0078] 205. Drawing module, used to draw shapes based on the coordinate data of the module to obtain a chip layout model.

[0079] In this embodiment of the invention, the modeling system further includes a ruler module 206, which is used to calculate the distance between any two points in the chip layout model.

[0080] In the chip layout model, display parameters such as transparency and font are set for different levels of modules according to the nested structure, allowing them to display information such as outline, side length, coordinates, and name. The chip layout model also includes a ruler function that can calculate the distance between any two points in the model. This ruler function is detected by keyboard and mouse button presses and can be activated by the user pressing the "U" key, at which point the word "Ruler" appears on the chip layout model. The user can use the mouse to click on the start and end points of the measurement path, and a line segment will appear on the canvas, displaying the distance between the two points at the center of the line segment, in micrometers (µm). The module names of each module will also be displayed, allowing for a quick understanding of the layout of the chip's modules.

[0081] Furthermore, when subsequent iterations are needed, the module information corresponding to the module in the configuration file can be directly modified and filled in, which enables rapid modeling of chip layout planning and real-time display of the iteration results.

[0082] The chip layout planning modeling system 200 can implement the steps in the chip layout planning modeling method in the above embodiments and achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0083] Example 3

[0084] This invention also provides a computer device, please refer to... Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a chip layout planning modeling program stored in the memory 302 and capable of running on the processor 301.

[0085] The processor 301 calls the chip layout planning modeling program stored in the memory 302 and executes the steps in the chip layout planning modeling method provided in this embodiment of the invention. Please refer to... Figure 1Specifically, it includes the following steps:

[0086] S1. Obtain the configuration information of the chip and establish a configuration file based on the configuration information; wherein, the configuration information includes module information and module call information of each module in the chip, and the module information includes module name, module coordinate information and module offset information;

[0087] S2. Read the configuration file, iterate through the module names of all the modules in the configuration file, and build a module list based on the module call information; save the module information to the module corresponding to the module list to obtain module relationship data;

[0088] S3. Establish a multi-level nested data structure based on the module relationship data;

[0089] S4. Calculate and merge the coordinates of the modules at different levels in the nested data structure to obtain module coordinate data that contains the coordinate information of all the modules;

[0090] S5. Draw the shape according to the module coordinate data to obtain the chip layout model.

[0091] The computer device 300 provided in this embodiment of the invention can implement the steps in the chip layout planning modeling method as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0092] Example 4

[0093] This invention also provides a computer-readable storage medium storing a chip layout planning modeling program. When the chip layout planning modeling program is executed by a processor, it implements the various processes and steps in the chip layout planning modeling method provided in this invention and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0094] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0095] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0096] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0097] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A method of modeling a chip floorplan, the method comprising: The modeling method comprises the following steps: S1, obtaining configuration information of a chip, and establishing a configuration file according to the configuration information; wherein the configuration information comprises module information and module calling information of each module in the chip, and the module information comprises a module name, module coordinate information and module offset information; S2, reading the configuration file, traversing the module name of all the modules in the configuration file, and establishing a module list according to the module calling information; saving the module information into the module corresponding to the module list, and obtaining module relationship data; S3, establishing a multi-level nested data structure according to the module relationship data; S4, performing coordinate calculation and merging on the modules at different levels in the nested data structure, and obtaining module coordinate data, wherein the module coordinate data comprises coordinate information of all the modules; S5, performing shape drawing according to the module coordinate data, and obtaining a chip layout model; In step S3, the called module is defined as a child module, the module calling other modules is defined as a parent module, the module information of the child module is placed in the module information of the parent module according to the module relationship data, and a multi-level nested data structure is formed; In step S4, the following sub-steps are included: S41, starting calculation from the lowest level module in the nested data structure, and calculating the displacement coordinate information of each module in the current level according to the corresponding module coordinate information and the module offset information; S42, entering the next level, calculating the displacement coordinate information of each module in the current level according to the corresponding module coordinate information and the module offset information, and adding the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship; S43, judging whether the current level is the top level in the nested data structure; if yes, merging the displacement coordinate information of each module in the top level to obtain the module coordinate data; if not, returning to step S42.

2. The method of claim 1, wherein, The module offset information comprises module rotation information and module offset coordinates.

3. A system for modeling a chip floorplan, the system comprising: Comprise: A configuration file establishing module for obtaining configuration information of a chip, and establishing a configuration file according to the configuration information; wherein the configuration information comprises module information and module calling information of each module in the chip, and the module information comprises a module name, module coordinate information and module offset information; A module relationship establishing module for reading the configuration file, traversing the module name of all the modules in the configuration file, and establishing a module list according to the module calling information; saving the module information into the module corresponding to the module list, and obtaining module relationship data; A nested data structure establishing module for establishing a multi-level nested data structure according to the module relationship data; A coordinate calculation module is configured to perform coordinate calculation and merging on the modules at different levels in the nested data structure to obtain module coordinate data, wherein the module coordinate data includes coordinate information of all the modules. A drawing module is configured to perform shape drawing according to the module coordinate data to obtain a chip layout model. In the nested data structure establishing module, the called module is defined as a child module, the module calling other modules is defined as a parent module, and the module information of the child module is placed in the module information of the parent module according to the module relationship data to form the multi-level nested data structure. The coordinate calculation module includes a module offset calculation unit, a comparison unit, and a judgment unit. The module offset calculation unit is configured to start calculation from the lowest level module in the nested data structure, and calculate displacement coordinate information of each module in the current level according to the corresponding module coordinate information and the module offset information. The comparison unit is configured to enter the next level, calculate displacement coordinate information of each module in the current level according to the corresponding module coordinate information and the module offset information, and add the displacement coordinate information of the module in the previous level to the displacement coordinate information of the module in the current level according to the calling relationship. The judgment unit is configured to judge whether the current level is the top level in the nested data structure; if yes, the displacement coordinate information of each module in the top level is merged to obtain the module coordinate data; if not, the comparison unit is returned.

4. The system for modeling of chip floorplanning of claim 3, wherein, The modeling system further includes a ruler module configured to calculate the distance between any two points in the chip layout model.

5. A computer device, comprising: The modeling system further includes a memory, a processor, and a chip layout planning modeling program stored in the memory and executable on the processor, wherein the processor implements the steps in the chip layout planning modeling method according to any one of claims 1-2 when executing the chip layout planning modeling program. The computer readable storage medium stores a chip layout planning modeling program, and the chip layout planning modeling program implements the steps in the chip layout planning modeling method according to any one of claims 1-2 when executed by a processor.

6. A computer-readable storage medium, characterized in that, ​

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