Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided. The display device includes a display panel including pixels, a gate driver, and a data driver. The gate driver includes: an application transistor that applies a pre-lookahead signal to the transmitter in response to a clock signal; the transmitter is used for applying a forward look-ahead signal to the pull-down control node; a pull-up controller connected to the transmitter and controlling the pull-up control node; a pull-down transistor applying a low voltage to the output node in response to a pull-down control node voltage; a pull-up transistor applying a high voltage to the output node in response to the pull-up control node voltage; a carry pull-down transistor that applies a carry low voltage to the carry node in response to a pull-up control node voltage; and a carry pull-up transistor that applies a carry high voltage to the carry node in response to the pull-up control node voltage. The carry low voltage is higher than the low voltage.

Description

Technical Field

[0001] Embodiments of the present invention relate to display devices and electronic devices. More specifically, embodiments of the present invention relate to display devices with reduced power consumption and electronic devices including display devices. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel includes multiple gate lines, multiple data lines, multiple emitter lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, an emitter driver that provides emitter signals to the emitter lines, and a drive controller that controls the gate driver, data driver, and emitter driver.

[0003] Typically, power consumption may increase depending on the range of voltages applied to the gate driver. Summary of the Invention

[0004] Embodiments of the present invention provide a display device with reduced power consumption.

[0005] Embodiments of the present invention also provide an electronic device with reduced power consumption.

[0006] According to an embodiment, the display device includes: a display panel including pixels; a gate driver configured to output a gate signal to the pixels; and a data driver configured to apply a data voltage to the pixels. The gate driver may include: an application transistor configured to apply a previous carry signal to a transmitter in response to a clock signal; a transmitter configured to apply the previous carry signal to a pull-down control node; a pull-up controller connected to the transmitter and configured to control the pull-up control node; a pull-down transistor configured to apply a first low voltage to an output node in response to a voltage of the pull-down control node; a pull-up transistor configured to apply a high voltage to the output node in response to a voltage of the pull-up control node; a carry pull-down transistor configured to apply a carry low voltage to a carry node in response to a voltage of the pull-up control node; and a carry pull-up transistor configured to apply a carry high voltage to a carry node in response to a voltage of the pull-up control node. The carry low voltage may be higher than the first low voltage.

[0007] In this embodiment, the carry pull-down transistor can be an N-type transistor, and the carry pull-up transistor can be a P-type transistor.

[0008] In one embodiment, the transmitter may include a first transmission transistor configured to connect a first node and a second node, and a second transmission transistor configured to connect a second node and a pull-down control node.

[0009] In an embodiment, the first transmission transistor may include a control electrode for receiving a carry high voltage, a first electrode connected to a first node, and a second electrode connected to a second node.

[0010] In an embodiment, the second transmission transistor may include a control electrode for receiving a first low voltage, a first electrode connected to a second node, and a second electrode connected to a pull-down control node.

[0011] In an embodiment, the first transmission transistor may be an N-type transistor.

[0012] In an embodiment, the second transmission transistor may include a control electrode for receiving a first low voltage, a first electrode connected to a second node, and a second electrode connected to a pull-down control node.

[0013] In an embodiment, the pull-up controller may include a first pull-up control transistor and a second pull-up control transistor. The first pull-up control transistor includes a control electrode connected to a pull-down control node, a first electrode for receiving a first low voltage, and a second electrode connected to the pull-up control node. The second pull-up control transistor includes a control electrode connected to a pull-down control node, a first electrode for receiving a high voltage, and a second electrode connected to the pull-up control node.

[0014] In an embodiment, the difference between the carry-low voltage and the first low voltage can be higher than the absolute value of the threshold voltage of the carry-down transistor.

[0015] In an embodiment, the gate driver may include: a first transistor including a control electrode for receiving a clock signal, a first electrode for receiving a previous carry signal, and a second electrode connected to a first node; a second transistor including a control electrode for receiving a first low voltage, a first electrode connected to a second node, and a second electrode connected to a pull-down control node; a third transistor including a control electrode connected to a pull-down control node, a first electrode for receiving a first low voltage, and a second electrode connected to a pull-up control node; a fourth transistor including a control electrode connected to a pull-down control node, a first electrode for receiving a high voltage, and a second electrode connected to a pull-up control node; and a fifth transistor including a control electrode connected to a pull-down control node. The transistor comprises: a control electrode for a node, a first electrode for receiving a first low voltage, and a second electrode connected to an output node; a sixth transistor, including a control electrode connected to a pull-up control node, a first electrode for receiving a high voltage, and a second electrode connected to an output node; a seventh transistor, including a control electrode connected to a pull-up control node, a first electrode for receiving a carry low voltage, and a second electrode connected to a carry node; an eighth transistor, including a control electrode connected to a pull-up control node, a first electrode for receiving a carry high voltage, and a second electrode connected to a carry node; and a ninth transistor, including a control electrode for receiving a carry high voltage, a first electrode connected to a first node, and a second electrode connected to a second node. The first transistor may be an application transistor, the fifth transistor may be a pull-down transistor, the sixth transistor may be a pull-up transistor, the seventh transistor may be a carry pull-down transistor, and the eighth transistor may be a carry pull-up transistor.

[0016] According to an embodiment, the display device includes: a display panel including pixels; a gate driver configured to output a gate signal to the pixels; and a data driver configured to apply a data voltage to the pixels. The gate driver may include: an application transistor configured to apply a previous carry signal to a transmitter in response to a clock signal; a transmitter configured to apply the previous carry signal to a pull-down control node; a pull-up controller connected to the transmitter and configured to control the pull-up control node; a pull-down transistor configured to apply a first low voltage to an output node in response to a voltage of the pull-down control node; a pull-up transistor configured to apply a high voltage to the output node in response to a voltage of the pull-up control node; a carry pull-down transistor configured to apply a carry low voltage to a carry node in response to a voltage of the pull-down control node; and a carry pull-up transistor configured to apply a carry high voltage to a carry node in response to a voltage of the pull-up control node. The carry low voltage may be higher than the first low voltage.

[0017] In this embodiment, the carry-down transistor can be a P-type transistor.

[0018] In one embodiment, the transmitter may include a first transmission transistor configured to connect a first node and a second node, and a second transmission transistor configured to connect a second node and a pull-down control node.

[0019] In an embodiment, the first transmission transistor may include a control electrode for receiving a carry high voltage, a first electrode connected to a first node, and a second electrode connected to a second node.

[0020] In an embodiment, the first transmission transistor may be an N-type transistor.

[0021] In an embodiment, the second transmission transistor may include a control electrode for receiving a second low voltage different from the first low voltage, a first electrode connected to a second node, and a second electrode connected to a pull-down control node.

[0022] In an embodiment, the difference between the carry-low voltage and the first low voltage can be higher than the absolute value of the threshold voltage of the carry-down transistor.

[0023] According to an embodiment, an electronic device includes: a display panel including pixels; a gate driver configured to output a gate signal to the pixels; a data driver configured to apply a data voltage to the pixels; a drive controller configured to control the gate driver and the data driver; and a processor configured to output input image data and input control signals. The gate driver may include: an application transistor configured to apply a previous carry signal to a transmitter in response to a clock signal; a transmitter configured to apply a previous carry signal to a pull-down control node; a pull-up controller connected to the transmitter and configured to control a pull-up control node; a pull-down transistor configured to apply a first low voltage to an output node in response to a voltage of the pull-down control node; a pull-up transistor configured to apply a high voltage to the output node in response to a voltage of the pull-up control node; a carry pull-down transistor configured to apply a carry low voltage to a carry node in response to a voltage of the pull-up control node; and a carry pull-up transistor configured to apply a carry high voltage to a carry node in response to a voltage of the pull-up control node. The carry low voltage may be higher than the first low voltage.

[0024] In this embodiment, the carry pull-down transistor can be an N-type transistor, and the carry pull-up transistor can be a P-type transistor.

[0025] In an embodiment, the difference between the carry-low voltage and the first low voltage can be higher than the absolute value of the threshold voltage of the carry-down transistor.

[0026] As described above, according to the display device and the electronic device including the display device, the carry-low voltage is higher than the first low voltage, and the carry-high voltage is lower than the high voltage. Since the carry-low voltage is higher than the first low voltage and the carry-high voltage is lower than the high voltage, the power consumption of the display device can be effectively reduced.

[0027] Furthermore, the pull-down transistor is an N-type transistor. Therefore, the output stability of the gate signal can be effectively improved. In addition, the slew rate of the gate signal can be effectively improved. Furthermore, the on-off duty cycles of the gate signals of the previous stage, the current stage, and the next stage can be essentially the same. Attached Figure Description

[0028] The illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0030] Figure 2 It is shown Figure 1 A block diagram of an example of a gate driver included in a display device.

[0031] Figure 3 It is shown Figure 2 The circuit diagram of the gate drive circuit included in the gate driver.

[0032] Figure 4 It is shown Figure 3 Timing diagram of the input signal, output signal and node voltage of the gate drive circuit.

[0033] Figure 5 It is shown Figure 2 The circuit diagram of the gate drive circuit included in the gate driver.

[0034] Figure 6 It is shown Figure 1 A block diagram of an example of a gate driver included in a display device.

[0035] Figure 7 It is shown Figure 6 The circuit diagram of the gate drive circuit included in the gate driver.

[0036] Figure 8 It is shown Figure 6 The circuit diagram of the gate drive circuit included in the gate driver.

[0037] Figure 9 It is shown Figure 2 The circuit diagram of the gate drive circuit included in the gate driver.

[0038] Figure 10 It is shown Figure 2 The circuit diagram of the gate drive circuit included in the gate driver.

[0039] Figure 11 It is shown Figure 1 A diagram showing examples of pixels included in a display device.

[0040] Figure 12 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0041] Figure 13 It is shown Figure 12 A block diagram of an example electronic device. Detailed Implementation

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element” unless the context clearly indicates otherwise. “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that the terms “comprising” and / or “including” or “including” and / or “containing” as used in this specification specify the presence of the stated feature, area, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or clusters thereof.

[0043] It should be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, components, areas, layers, and / or sections, these elements, components, areas, layers, and / or sections should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or section from another. Therefore, the first element, component, area, layer, or section discussed below may be referred to as the second element, component, area, layer, or section without departing from the teachings of this document.

[0044] The present invention will now be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a block diagram illustrating a display device 1 according to an embodiment of the present invention.

[0046] Reference Figure 1 The display device 1 includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0047] The display panel 100 has a display area on which an image is displayed and a peripheral area adjacent to the display area.

[0048] The display panel 100 includes multiple gate lines GL, multiple data lines DL, and multiple pixels PX electrically connected to the gate lines GL and data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 intersecting the first direction D1.

[0049] The drive controller 200 receives input image data IMG and input control signals CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, cyan image data, and yellow image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0050] The drive controller 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0051] The drive controller 200 generates a first control signal CONT1 based on the input control signal CONT for controlling the operation of the gate driver 300, and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0052] The drive controller 200 generates a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0053] The drive controller 200 generates a data signal DATA based on the input image data IMG. The drive controller 200 outputs the data signal DATA to the data driver 500.

[0054] The drive controller 200 generates a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and outputs the third control signal CONT3 to the gamma reference voltage generator 400.

[0055] The gate driver 300 generates a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL.

[0056] In one embodiment, the gate driver 300 may be disposed in the peripheral region. Alternatively, the gate driver 300 may be integrated into the peripheral region.

[0057] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to the level of the data signal DATA.

[0058] In this embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0059] The data driver 500 receives a second control signal CONT2 and a data signal DATA from the drive controller 200, and a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 uses the gamma reference voltage VGREF to convert the data signal DATA into a data voltage VDATA of analog type. The data driver 500 outputs the data voltage VDATA to the data line DL.

[0060] In one embodiment, the data driver 500 may be located in the peripheral area. Alternatively, the data driver 500 may be integrated into the peripheral area.

[0061] Figure 2 It is shown Figure 1 A block diagram of an example of a gate driver 300 included in a display device 1.

[0062] Reference Figure 1 and Figure 2 The display device 1 may include a gate driver 300A. The gate driver 300A may include multiple stages STAGE1A, STAGE2A, STAGE3A, STAGE4A, ...

[0063] Stages STAGE1A, STAGE2A, STAGE3A, STAGE4A, ... can receive the vertical start signal FLM, the first clock signal CLK1, and the second clock signal CLK2. Stages STAGE1A, STAGE2A, STAGE3A, STAGE4A, ... can sequentially output gate signals GS[1], GS[2], GS[3], GS[4], ... to pixels PX row by row. For example, stages STAGE1A, STAGE2A, STAGE3A, STAGE4A, ... can receive the previous carry signal CR[n-1]. The previous carry signal CR[n-1] can be the carry signal CR[n] of the previous stage. The previous carry signal CR[n-1] of the first stage STAGE1A can be the vertical start signal FLM.

[0064] The first clock signal CLK1 can be applied to the clock terminal CLKT of the first stage STAGE1A. The second clock signal CLK2 can be applied to the clock terminal CLKT of the second stage STAGE2A. Similarly, the first clock signal CLK1 can be applied to the clock terminal CLKT of the third stage STAGE3A. The second clock signal CLK2 can be applied to the clock terminal CLKT of the fourth stage STAGE4A.

[0065] Stages STAGE1A, STAGE2A, STAGE3A, STAGE4A, ... can receive high voltage VGH, first low voltage VGL, carry high voltage SVGH, and carry low voltage SVGL. The carry high voltage SVGH can be higher than the first low voltage VGL. For example, the first low voltage VGL can be referred to as "output low voltage".

[0066] For example, the carry signal CR[n] can have a carry high voltage SVGH or a carry low voltage SVGL.

[0067] Figure 3 It is shown Figure 2 The circuit diagram of the gate drive circuit GDCA included in the gate driver 300A.

[0068] Reference Figures 1 to 3 The gate drive circuit GDCA may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7A, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, and a second capacitor C2. The gate drive circuit GDCA may include a transmitter 310 and a pull-up controller 320. The transmitter 310 may include the second transistor T2 and the ninth transistor T9. The pull-up controller 320 may include the third transistor T3 and the fourth transistor T4.

[0069] Transmitter 310 can apply the previous carry signal CR[n-1] to the pull-down control node Q.

[0070] The pull-up controller 320 can control the pull-up control node QB in response to the voltage of the pull-down control node Q. For example, the pull-up controller 320 can apply a first low voltage VGL to the pull-up control node QB in response to the voltage of the pull-down control node Q. For example, the pull-up controller 320 can apply a high voltage VGH to the pull-up control node QB in response to the voltage of the pull-down control node Q.

[0071] The first transistor T1 may include a control electrode for receiving a clock signal CLK, a first electrode for receiving a previous carry signal CR[n-1], and a second electrode connected to the first node N1. The first transistor T1 may apply the previous carry signal CR[n-1] to the first node N1 in response to the clock signal CLK. For example, the first transistor T1 may be referred to as the "application transistor".

[0072] The second transistor T2 may include a control electrode for receiving a first low voltage VGL, a first electrode connected to a second node N2, and a second electrode connected to a pull-down control node Q. The second transistor T2 may connect the second node N2 and the pull-down control node Q in response to the first low voltage VGL. For example, the first electrode of the second transistor T2 may be a source electrode. For example, the second transistor T2 may be referred to as a "second transmission transistor".

[0073] The third transistor T3 may include a control electrode connected to the pull-down control node Q, a first electrode for receiving a first low voltage VGL, and a second electrode connected to the pull-up control node QB. The third transistor T3 may apply the first low voltage VGL to the pull-up control node QB in response to the voltage at the pull-down control node Q. For example, the third transistor T3 may be referred to as the "first pull-up control transistor".

[0074] The fourth transistor T4 may include a control electrode connected to the pull-down control node Q, a first electrode for receiving a high voltage VGH, and a second electrode connected to the pull-up control node QB. For example, the fourth transistor T4 may be referred to as the "second pull-up control transistor".

[0075] The fifth transistor T5 may include a control electrode connected to the pull-down control node Q, a first electrode for receiving a first low voltage VGL, and a second electrode connected to the output node NO. The fifth transistor T5 may apply the first low voltage VGL to the output node NO in response to the voltage of the pull-down control node Q. For example, the fifth transistor T5 may be referred to as a "pull-down transistor".

[0076] The sixth transistor T6 may include a control electrode connected to the pull-up control node QB, a first electrode for receiving a high voltage VGH, and a second electrode connected to the output node NO. The sixth transistor T6 can apply a high voltage VGH to the output node NO in response to the voltage of the pull-up control node QB. For example, the sixth transistor T6 may be referred to as a "pull-up transistor".

[0077] The seventh transistor T7A may include a control electrode connected to the pull-up control node QB, a first electrode for receiving a carry-low voltage SVGL, and a second electrode connected to the carry node NC. The seventh transistor T7A may apply a carry-low voltage SVGL to the carry node NC in response to the voltage of the pull-up control node QB. For example, the seventh transistor T7A may be referred to as a "carry-pull-down transistor".

[0078] The eighth transistor T8 may include a control electrode connected to the pull-up control node QB, a first electrode for receiving a carry-high voltage SVGH, and a second electrode connected to the carry node NC. The eighth transistor T8 may apply a carry-high voltage SVGH to the carry node NC in response to the voltage of the pull-up control node QB. For example, the eighth transistor T8 may be referred to as a "carry pull-up transistor".

[0079] The ninth transistor T9 may include a control electrode for receiving a carry high voltage SVGH, a first electrode connected to a first node N1, and a second electrode connected to a second node N2. The ninth transistor T9 may connect the first node N1 and the second node N2 in response to the carry high voltage SVGH. For example, the ninth transistor T9 may be referred to as the "first transmission transistor". In this embodiment, the ninth transistor T9 may be an N-type transistor. For example, the first electrode of the ninth transistor T9 may be the source electrode.

[0080] The first capacitor C1 may include a first electrode connected to the output node NO and a second electrode connected to the pull-down control node Q. The first capacitor C1 can bootstrap the voltage change of the output node NO and output the bootstrap voltage to the pull-down control node Q.

[0081] The second capacitor C2 may include a first electrode for receiving a high voltage VGH and a second electrode connected to the pull-up control node QB.

[0082] The gate drive circuit GDCA can output the voltage of the output node NO as the gate signal GS[n]. The gate drive circuit GDCA can output the voltage of the carry node NC as the carry signal CR[n].

[0083] In this embodiment, the carry-low voltage SVGL can be higher than the first low voltage VGL, and the carry-high voltage SVGH can be lower than the high voltage VGH. Since the carry-low voltage SVGL can be higher than the first low voltage VGL, and the carry-high voltage SVGH can be lower than the high voltage VGH, the power consumption of the gate driver can be effectively reduced.

[0084] The difference between the carry-low voltage SVGL and the first low voltage VGL can be higher than the absolute value of the threshold voltage of the seventh transistor T7A. Therefore, when the first low voltage VGL is applied to the pull-up control node QB, the seventh transistor T7A can be turned off.

[0085] In this embodiment, the third transistor T3 can be an N-type transistor. Because the third transistor T3 can be an N-type transistor, the first low voltage VGL can be stably applied to the pull-up control node QB. For example, because the third transistor T3 can be an N-type transistor, the first low voltage VGL can be applied to the pull-up control node QB without any attenuation equal to the threshold voltage of the third transistor T3.

[0086] In this embodiment, the seventh transistor T7A can be an N-type transistor. Since the seventh transistor T7A can be an N-type transistor, the carry low voltage SVGL can be stably applied to the carry node NC. For example, since the seventh transistor T7A can be an N-type transistor, the carry low voltage SVGL can be applied to the carry node NC without attenuation equal to the threshold voltage of the seventh transistor T7A. Therefore, the stability of the carry signal CR[n] can be effectively improved. For example, the carry low level of the carry signal CR[n] can be substantially the same as the carry low voltage SVGL. Therefore, the previous carry low level of the previous carry signal CR[n-1] can be substantially the same as the carry low voltage SVGL. Since the previous carry low level of the previous carry signal CR[n-1] can be substantially the same as the carry low voltage SVGL, the voltage applied to the pull-down control node Q can be substantially the same as the carry low voltage SVGL. Therefore, when the first capacitor C1 bootstraps the voltage of the output node NO to the pull-down control node Q, the fifth transistor T5 can be stably turned on. For example, the fifth transistor T5 can be strongly turned on. Since the fifth transistor T5 can be stably turned on, the first low voltage VGL can be stably applied to the output node NO. Therefore, the output stability of the gate signal GS[n] can be effectively improved. In addition, the slew rate of the gate signal GS[n] can be effectively improved. Furthermore, the on / off duty cycles of the gate signals of the previous stage, the current stage, and the next stage can be basically the same.

[0087] Figure 4 It is shown Figure 3Timing diagram of the input signals, output signals, and node voltages of the gate drive circuit GDCA.

[0088] Reference Figure 3 and Figure 4 The time periods for driving the gate drive circuit GDCA may include the first time period TP1A, the second time period TP2A, the third time period TP3A, and the fourth time period TP4A.

[0089] During the first time period TP1A, the carry signal CR[n-1] may have a carry high voltage SVGH, and the clock signal CLK may have a clock low level. The first transistor T1 may turn on in response to the clock low level. Therefore, the carry signal CR[n-1] may be applied to the first node N1. The ninth transistor T9 may turn on in response to the carry high voltage SVGH. Since the ninth transistor T9 is on, the carry signal CR[n-1] may be applied to the second node N2. The second transistor T2 may turn on in response to the first low voltage VGL. Since the second transistor T2 is on, the carry signal CR[n-1] may be applied to the pull-down control node Q. During the first time period TP1A, the pull-down control node Q may have a carry high level. The third transistor T3 may turn on in response to the voltage of the pull-down control node Q. Since the third transistor T3 is on, the first low voltage VGL may be applied to the pull-up control node QB. Furthermore, the fourth transistor T4 may turn off in response to the voltage of the pull-down control node Q. The sixth transistor T6 can be turned on in response to the voltage of the pull-up control node QB. Since the sixth transistor T6 is turned on, a high voltage VGH can be applied to the output node NO. Therefore, the gate signal GS[n] can have a gate high level GSH. Furthermore, the eighth transistor T8 can be turned on in response to the voltage of the pull-up control node QB, and the seventh transistor T7A can be turned off in response to the voltage of the pull-up control node QB. Since the eighth transistor T8 is turned on and the seventh transistor T7A is turned off, a carry high voltage SVGH can be applied to the carry node NC. Therefore, the carry signal CR[n] can have a carry high voltage SVGH.

[0090] During the second time period TP2A, since the carry-high voltage SVGH can be applied to the second node N2, the difference between the voltage of the control node of the ninth transistor T9 and the voltage of the first node N1 can be approximately the same as the threshold voltage of the ninth transistor T9. Because the difference between the voltage of the control node of the ninth transistor T9 and the voltage of the first node N1 can be approximately the same as the threshold voltage of the ninth transistor T9, the ninth transistor T9 can be turned off. Because the ninth transistor T9 can be turned off, the second node N2 can be floated.

[0091] During the second time period TP2A, since the second node N2 is floatable, the first capacitor C1 can bootstrap the voltage change of the output node NO to the pull-down control node Q. For example, during the second time period TP2A, the voltage of the output node NO can change from a first low voltage VGL to a high voltage VGH. The first capacitor C1 can apply the difference between the first low voltage VGL and the high voltage VGH to the pull-down control node Q. Therefore, the pull-down control node Q can have a bootstrap voltage V1+VB. The fifth transistor T5 can be forcibly turned off in response to the bootstrap voltage V1+VB.

[0092] In the third time period TP3A, the previous carry signal CR[n-1] may have a carry low voltage SVGL, and the clock signal CLK may have a clock low level. Therefore, the first transistor T1 can be turned on. Since the first transistor T1 is turned on, the carry low voltage SVGL can be applied to the first node N1. Since the carry low voltage SVGL can be applied to the first node N1, the difference between the voltage of the first node N1 and the voltage of the control electrode of the ninth transistor T9 can be higher than the absolute value of the threshold voltage of the ninth transistor T9. Therefore, the ninth transistor T9 can be turned on. Since the ninth transistor T9 is turned on, the carry low voltage SVGL can be applied to the pull-down control node Q. Since the carry low voltage SVGL can be applied to the pull-down control node Q, the fifth transistor T5 can be turned on. The third transistor T3 can be turned off in response to the voltage of the pull-down control node Q. The fourth transistor T4 can be turned on in response to the voltage of the pull-down control node Q. Since the fourth transistor T4 is turned on, the high voltage VGH can be applied to the pull-up control node QB. The sixth transistor T6 can be turned off in response to the voltage of the pull-up control node QB. Since the fifth transistor T5 is turned on, a first low voltage VGL can be applied to the output node NO. Therefore, the gate signal GS[n] can have a gate low level GSL. Furthermore, in response to the voltage of the pull-up control node QB, the eighth transistor T8 can be turned off and the seventh transistor T7A can be turned on. Since the eighth transistor T8 is turned off and the seventh transistor T7A is turned on, a carry low voltage SVGL can be applied to the carry node NC. Therefore, the carry signal CR[n] can have a carry low voltage SVGL.

[0093] In the fourth time period TP4A, the clock signal CLK can have a high clock level. The first transistor T1 can be turned off in response to the clock signal CLK. Additionally, since a carry-low voltage SVGL can be applied to the second node N2, the difference between the voltage of the control electrode of the second transistor T2 and the voltage of the second node N2 can be lower than the absolute value of the threshold voltage of the second transistor T2. Therefore, the second transistor T2 can be turned off. Since the second transistor T2 can be turned off, the pull-down control node Q can be floated. Since the pull-down control node Q can be floated, the first capacitor C1 can bootstrap the voltage change of the output node NO to the pull-down control node Q. For example, in the fourth time period TP4A, the output node NO can change from a high voltage VGH to a first low voltage VGL. The first capacitor C1 can apply the difference between the first low voltage VGL and the high voltage VGH to the pull-down control node Q. Therefore, the voltage of the pull-down control node Q can be lower than the carry-low voltage SVGL. Therefore, the fifth transistor T5 can be strongly turned on. Since the fifth transistor T5 can be strongly turned on, the output stability of the gate signal GS[n] can be effectively improved.

[0094] Figure 5 It is shown Figure 2 The circuit diagram of the gate drive circuit GDCB ​​included in the gate driver 300A.

[0095] Reference Figure 5 The gate drive circuit GDCB ​​may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7B, an eighth transistor T8, and a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0096] According to the gate drive circuit GDCB ​​of this embodiment and Figure 3 The gate drive circuit GDCA is basically the same as that in the figure, except that the seventh transistor T7B is a P-type transistor, and the control electrode of the seventh transistor T7B is connected to the pull-down control node Q. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0097] In this embodiment, the carry-low voltage SVGL applied to the gate drive circuit GDCB ​​can be higher than the first low voltage VGL, and the carry-high voltage SVGH can be lower than the high voltage VGH. Since the carry-low voltage SVGL can be higher than the first low voltage VGL, and the carry-high voltage SVGH can be lower than the high voltage VGH, the power consumption of the gate drive circuit GDCB ​​can be effectively reduced.

[0098] Figure 6 It is shown Figure 1 A block diagram of an example of a gate driver 300 included in a display device 1.

[0099] Reference Figure 1 and Figure 6 The display device 1 may include a gate driver 300B. The gate driver 300B may include multiple stages STAGE1B, STAGE2B, STAGE3B, STAGE4B, ...

[0100] Stages STAGE1B, STAGE2B, STAGE3B, STAGE4B, ... can receive the vertical start signal FLM, the first clock signal CLK1, and the second clock signal CLK2. Stages STAGE1B, STAGE2B, STAGE3B, STAGE4B, ... can sequentially output gate signals GS[1], GS[2], GS[3], GS[4], ... to pixels PX row by row. For example, stages STAGE1B, STAGE2B, STAGE3B, STAGE4B, ... can receive the previous carry signal CR[n-1]. The previous carry signal CR[n-1] can be the carry signal CR[n] of the previous stage. The previous carry signal CR[n-1] of the first stage STAGE1B can be the vertical start signal FLM.

[0101] The first clock signal CLK1 can be applied to the clock terminal CLKT of the first stage STAGE1B. The second clock signal CLK2 can be applied to the clock terminal CLKT of the second stage STAGE2B. Similarly, the first clock signal CLK1 can be applied to the clock terminal CLKT of the third stage STAGE3B. The second clock signal CLK2 can be applied to the clock terminal CLKT of the fourth stage STAGE4B.

[0102] Stages 1B, 2B, 3B, 4B, ... can receive a high voltage VGH, a first low voltage VGL, a second low voltage VGL2 different from the first low voltage VGL, a carry high voltage SVGH, and a carry low voltage SVGL. The carry high voltage SVGH can be lower than the high voltage VGH. The carry low voltage SVGL can be higher than the first low voltage VGL.

[0103] For example, the carry signal CR[n] may have a carry high voltage SVGH or a carry low voltage SVGL. For example, the gate signal GS[n] may have a high voltage VGH or a first low voltage VGL.

[0104] Figure 7 It is shown Figure 6 The circuit diagram of the gate drive circuit GDCC included in the gate driver 300B.

[0105] Reference Figure 7The gate drive circuit GDCC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7A, an eighth transistor T8, and a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0106] According to the gate drive circuit GDCC of this embodiment and Figure 3 The gate drive circuit GDCA is essentially the same as that in the previous version, except that a second low voltage VGL2 can be applied to the control electrode of the second transistor T2. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0107] Reference Figure 1 , Figure 4 , Figure 6 and Figure 7 A second low voltage VGL2 can be applied to the control electrode of the second transistor T2. The first low voltage VGL and the second low voltage VGL2 can be different. The voltage of the pull-down control node Q can be controlled based on the second low voltage VGL2. For example, in the fourth time period TP4A, the timing of the turn-off of the second transistor T2 can be controlled based on the difference between the second low voltage VGL2 and the voltage of the second node N2.

[0108] When the second low voltage VGL2 is higher than the first low voltage VGL, the timing of the turn-off of the second transistor T2 can be faster. Because the turn-off timing of the second transistor T2 is faster, the timing of the pull-down control node Q floating can be faster. Therefore, the bootstrap voltage applied to the pull-down control node Q can be increased. Therefore, the fifth transistor T5 can be turned on more strongly. Furthermore, because the timing of the pull-down control node Q floating can be faster, the timing of the turn-on of the fourth transistor T4 can be faster. Therefore, the timing of the turn-on of the seventh transistor T7A can be faster. Because the turn-on timing of the seventh transistor T7A is faster, the conversion rate of the carry signal CR[n] can be effectively improved.

[0109] When the second low voltage VGL2 is lower than the first low voltage VGL, the timing of the turn-off of the second transistor T2 can be delayed. Because the turn-off timing of the second transistor T2 can be delayed, the timing of the floating of the pull-down control node Q can also be delayed. Therefore, the bootstrap voltage applied to the pull-down control node Q can be reduced. Consequently, the stress applied to the fifth transistor T5 can be reduced.

[0110] Figure 8 It is shown Figure 6 The circuit diagram of the gate drive circuit GDCD included in the gate driver 300B.

[0111] Reference Figure 8The gate drive circuit GDCD may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7B, an eighth transistor T8, and a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0112] According to the gate drive circuit GDCD of this embodiment, and Figure 5 The gate drive circuit GDCB ​​is essentially the same, except that a second low voltage VGL2 can be applied to the control electrode of the second transistor T2. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0113] Reference Figure 1 , Figure 4 , Figure 6 and Figure 8 A second low voltage VGL2 can be applied to the control electrode of the second transistor T2. The first low voltage VGL and the second low voltage VGL2 can be different. The voltage of the pull-down control node Q can be controlled based on the second low voltage VGL2. For example, in the fourth time period TP4A, the timing of the turn-off of the second transistor T2 can be controlled based on the difference between the second low voltage VGL2 and the voltage of the second node N2.

[0114] When the second low voltage VGL2 is higher than the first low voltage VGL, the timing of the turn-off of the second transistor T2 can be faster. Because the turn-off timing of the second transistor T2 is faster, the timing of the pull-down control node Q floating can be faster. Therefore, the bootstrap voltage applied to the pull-down control node Q can be increased. Therefore, the fifth transistor T5 can be turned on more strongly. Furthermore, because the timing of the pull-down control node Q floating can be faster, the timing of the turn-on of the fourth transistor T4 can be faster. Therefore, the timing of the turn-on of the seventh transistor T7A can be faster. Because the turn-on timing of the seventh transistor T7A is faster, the conversion rate of the carry signal CR[n] can be effectively improved.

[0115] When the second low voltage VGL2 is lower than the first low voltage VGL, the timing of the turn-off of the second transistor T2 can be delayed. Because the turn-off timing of the second transistor T2 can be delayed, the timing of the floating of the pull-down control node Q can also be delayed. Therefore, the bootstrap voltage applied to the pull-down control node Q can be reduced. Consequently, the stress applied to the fifth transistor T5 can be reduced.

[0116] Figure 9 It is shown Figure 2 The circuit diagram of the gate drive circuit GDCE included in the gate driver 300A.

[0117] Reference Figure 9The gate drive circuit GDCE may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4E, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7A, an eighth transistor T8, and a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0118] According to the gate drive circuit GDCE of this embodiment and Figure 3 The gate drive circuit is basically the same as that of GDCA, except that the control electrode of the fourth transistor T4E is connected to the second node N2. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0119] Figure 10 It is shown Figure 2 The circuit diagram of the gate drive circuit GDCF included in the gate driver 300A.

[0120] Reference Figure 10 The gate drive circuit GDCF may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4F, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7A, an eighth transistor T8 and a ninth transistor T9, a first capacitor C1 and a second capacitor C2.

[0121] According to the gate drive circuit GDCF of this embodiment and Figure 3 The gate drive circuit is basically the same as that of GDCA, except that the control electrode of the fourth transistor T4F is connected to the first node N1. Therefore, the same reference numerals will be used to refer to the same components, and any repeated descriptions of the above components will be omitted.

[0122] Figure 11 It is shown Figure 1 A diagram showing an example of pixels PX included in display device 1.

[0123] Reference Figure 11 A pixel PXA may include a first pixel transistor PT1, a second pixel transistor PT2, a storage capacitor CST, and a light-emitting element EE.

[0124] The first pixel transistor PT1 may include a control electrode for receiving a gate signal GS[n], a first electrode for receiving a data voltage VDATA, and a second electrode connected to the first pixel node P1. The first pixel transistor PT1 may apply the data voltage VDATA to the first pixel node P1 in response to the gate signal GS[n]. For example, the first pixel transistor PT1 may be referred to as a "write transistor".

[0125] The second pixel transistor PT2 may include a control electrode connected to the first pixel node P1, a first electrode for receiving a first power supply voltage VDD, and a second electrode connected to the second pixel node P2. The second pixel transistor PT2 can generate a drive current based on the voltage of the first pixel node P1. For example, the second pixel transistor PT2 may be referred to as a "drive transistor".

[0126] The storage capacitor CST may include a first electrode for receiving a first power supply voltage VDD and a second electrode connected to a first pixel node P1.

[0127] The light-emitting element EE may include a first electrode connected to the second pixel node P2 and a second electrode for receiving a second power supply voltage VSS. The light-emitting element EE may emit light based on a driving current.

[0128] Figure 12 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention.

[0129] Reference Figure 12 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be... Figure 1 The display device 1. In addition, the electronic device 1000 may also include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (USB) devices, other electronic devices, etc.

[0130] For example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device and the like.

[0131] Processor 1010 can perform various computing functions or tasks. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), and the like. Processor 1010 can be coupled to other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0132] Processor 1010 can output input image data IMG and input control signal CONT to Figure 1 The drive controller 200.

[0133] The memory device 1020 may store data for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one non-volatile memory device, such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, and the like, and / or at least one volatile memory device, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, and the like.

[0134] Storage device 1030 may include solid-state drive (SSD) devices, hard disk drive (HDD) devices, CD-ROM devices, and the like. I / O device 1040 may include input devices such as keyboards, keypads, mouse devices, touchpads, touchscreens, and the like, and output devices such as printers, speakers, and the like. In some embodiments, display device 1060 may be included in I / O device 1040. Power supply 1050 may provide power for the operation of electronic device 1000. Display device 1060 may be connected to other components via a bus or other communication link.

[0135] Figure 13 It is shown Figure 12 A block diagram of an example electronic device.

[0136] Electronic device 2101 can output various information via display module 2140 in the operating system. When processor 2110 executes an application stored in memory 2120, display module 2140 can provide application information to the user via display panel 2141.

[0137] Processor 2110 can obtain external input via input module 2130 or sensor module 2161, and can execute applications corresponding to the external input. For example, when a user selects the camera icon displayed on display panel 2141, processor 2110 can obtain user input via input sensor 2161-2 and can activate camera module 2171. Processor 2110 can transmit image data corresponding to the image captured by camera module 2171 to display module 2140. Display module 2140 can display the image corresponding to the captured image via display panel 2141.

[0138] As another example, when personal information authentication is performed in display module 2140, fingerprint sensor 2161-1 can obtain the input fingerprint information as input data. Processor 2110 can compare the input data obtained by fingerprint sensor 2161-1 with the authentication data stored in memory 2120, and execute the application based on the comparison result. Display module 2140 can display the information executed according to the application logic via display panel 2141.

[0139] As another example, when a music stream icon displayed on display module 2140 is selected, processor 2110 obtains user input via input sensor 2161-2 and can activate the music stream application stored in memory 2120. When a music execution command is entered in the music stream application, processor 2110 can activate sound output module 2163 to provide the user with sound information corresponding to the music execution command.

[0140] The operation of electronic device 2101 has been briefly described above. The configuration of electronic device 2101 will be described in detail below. Some components of electronic device 2101 described below can be integrated and provided as a single component, or they can be provided separately as two or more components.

[0141] Reference Figure 13 Electronic device 2101 can communicate with external electronic device 2102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In embodiments, electronic device 2101 may include processor 2110, memory 2120, input module 2130, display module 2140, power management module 2150, internal module 2160, and external module 2170. In embodiments, at least one of the components may be omitted from electronic device 2101, or one or more other components may be added to electronic device 2101. In embodiments, some of the components (e.g., sensor module 2161, antenna module 2162, or sound output module 2163) may be implemented as a single component (e.g., display module 2140).

[0142] Processor 2110 can execute software to control at least one other component (e.g., hardware or software component) of electronic device 2101 coupled to processor 2110, and can perform various data processing or calculations. According to an embodiment, as at least part of data processing or calculation, processor 2110 can store commands or data received from another component (e.g., input module 2130, sensor module 2161, or communication module 2173) in volatile memory 2121, can process commands or data stored in volatile memory 2121, and can store result data in non-volatile memory 2122.

[0143] Processor 2110 may include a main processor 2111 and an auxiliary processor 2112. Main processor 2111 may include at least one of a central processing unit (CPU) 2111-1 and an application processor (AP). Main processor 2111 may also include any one or more of a graphics processing unit (GPU) 2111-2, a communication processor (CP), and an image signal processor (ISP). Main processor 2111 may also include a neural processing unit (NPU) 2111-3. NPU 2111-3 may be a processor dedicated to processing artificial intelligence models, and the artificial intelligence models may be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural networks may be deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted Boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), deep Q-networks, or combinations of two or more thereof, but are not limited thereto. The artificial intelligence model may additionally or alternatively include software structures in addition to hardware structures. At least two of the aforementioned processing units and processors can be implemented as integrated components (e.g., a single chip), or each processing unit and processor can be implemented as an independent component (e.g., multiple chips).

[0144] The auxiliary processor 2112 may include a controller. The controller may include interface conversion circuitry and timing control circuitry. The controller can receive image signals from the main processor 2111, convert the data format of the image signals to meet the interface specifications of the display module 2140, and output image data. The controller can output various control signals for driving the display module 2140.

[0145] The auxiliary processor 2112 may also include a data conversion circuit 2112-2, a gamma correction circuit 2112-3, a rendering circuit 2112-4, or the like. The data conversion circuit 2112-2 can receive image data from the controller. The data conversion circuit 2112-2 can compensate the image data according to the characteristics of the electronic device 2101 or user settings to display the image at a desired brightness, or it can convert the image data to reduce power consumption or eliminate afterimages. Since the gamma correction circuit 2112-3 can convert the image data or the gamma reference voltage, the image displayed on the electronic device 2101 has the desired gamma characteristics. The rendering circuit 2112-4 can receive image data from the controller and can render the image data taking into account the pixel arrangement of the display panel 2141 in the electronic device 2101. At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 may be integrated into another component (e.g., the main processor 2111 or the controller). At least one of the data conversion circuit 2112-2, the gamma correction circuit 2112-3, and the rendering circuit 2112-4 may be integrated into the data driver 2143 described below.

[0146] Memory 2120 may store various data used by at least one component of electronic device 2101 (e.g., processor 2110 or sensor module 2161). The various data may include, for example, input or output data for commands associated therewith. Memory 2120 may include at least one of volatile memory 2121 and non-volatile memory 2122.

[0147] The input module 2130 can receive commands or data from external sources of the electronic device 2101 (e.g., a user or external electronic device 2102) used by components of the electronic device 2101 (e.g., processor 2110, sensor module 2161, or sound output module 2163).

[0148] Input module 2130 may include a first input module 2131 for receiving commands or data from a user and a second input module 2132 for receiving commands or data from an external electronic device 2102. The first input module 2131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or a pen (e.g., a passive or active pen). The second input module 2132 may support a specified protocol that enables wired or wireless connection of electronic device 2101 to external electronic device 2102. In embodiments, the second input module 2132 may include an High Definition Multimedia Interface (HDMI), a Universal Serial Bus (USB) interface, an SD card interface, or an audio interface. The second input module 2132 may include a connector that allows physical connection of electronic device 2101 to external electronic device 2102. For example, the second input module 2132 may include an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0149] Display module 2140 can provide information to a user visually. Display module 2140 may include display panel 2141, gate driver 2142, and data driver 2143. Display module 2140 may also include a window, chassis, and bracket for protecting display panel 2141.

[0150] Display panel 2141 may include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, but the type of display panel 2141 is not limited to these. Display panel 2141 may be a rigid type display panel or a flexible type display panel that can be rolled or folded. Display module 2140 may also include a support member, bracket, or heat dissipation member that supports display panel 2141.

[0151] The gate driver 2142 can be mounted on the display panel 2141 as a driver chip. Alternatively, the gate driver 2142 can be integrated into the display panel 2141. For example, the gate driver 2142 may include an amorphous silicon TFT gate driver circuit (ASG), a low-temperature polycrystalline silicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (OSG) embedded in the display panel 2141. The gate driver 2142 can receive control signals from a controller and can output gate signals to the display panel 2141 in response to the control signals.

[0152] The display panel 2141 may also include a transmitter driver. The transmitter driver can output a transmitter control signal to the display panel 2141 in response to a control signal received from the controller. The transmitter driver may be formed separately from the gate driver 2142, or it may be integrated into the gate driver 2142.

[0153] The data driver 2143 can receive control signals from the controller, can convert image data into analog voltage (e.g., data voltage) in response to the control signals, and can then output the data voltage to the display panel 2141.

[0154] The data driver 2143 can be incorporated into other components (e.g., a controller). Furthermore, the interface conversion circuitry and timing control circuitry of the aforementioned controller can be integrated into the data driver 2143.

[0155] The display module 2140 may also include a transmitter driver, a voltage generator circuit, or the like. The voltage generator circuit can output various voltages for driving the display panel 2141.

[0156] Power management module 2150 supplies power to components of electronic device 2101. Power management module 2150 may include a battery that is charged by a power supply voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power management module 2150 may include a power management integrated circuit (PMIC). The PMIC can supply optimal power to each of the modules described above and below. Power management module 2150 may include a wireless power transmitting / receiving component electrically connected to the battery. The wireless power transmitting / receiving component may include multiple antenna radiators in the form of coils.

[0157] The electronic device 2101 may also include an internal module 2160 and an external module 2170. The internal module 2160 may include a sensor module 2161, an antenna module 2162, and a sound output module 2163. The external module 2170 may include a camera module 2171, an optical module 2172, and a communication module 2173.

[0158] Sensor module 2161 can detect input through a user's body or through a pen in the first input module 2131, and can generate an electrical signal or data value corresponding to the input. Sensor module 2161 may include at least one of fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3.

[0159] The fingerprint sensor 2161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 2161-1 can include either an optical fingerprint sensor or a capacitive fingerprint sensor.

[0160] Input sensor 2161-2 can generate data values ​​corresponding to the coordinate information of user's body input or pen input. Input sensor 2161-2 can convert capacitance changes caused by input into data values. Input sensor 2161-2 can detect input through a passive pen, or can send data to or receive data from an active pen.

[0161] Input sensor 2161-2 can measure biosignals such as blood pressure, water content, or body fat. For example, when a part of a user's body is in contact with the sensor layer or sensing panel and remains stationary for a certain period of time, input sensor 2161-2 can detect biosignals based on changes in the electric field caused by the body part and output the information required by the user to display module 2140.

[0162] The digitizer 2161-3 generates data values ​​corresponding to coordinate information input via a pen. The digitizer 2161-3 converts the amount of electromagnetic change caused by the input into data values. The digitizer 2161-3 can detect input via a passive pen, or send data to or receive data from an active pen.

[0163] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be implemented as a sensor layer formed on the display panel 2141 by a continuous process. The fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed above the display panel 2141, or at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be disposed below the display panel 2141.

[0164] Two or more of the fingerprint sensor 2161-1, input sensor 2161-2, and digitizer 2161-3 can be integrated into a single sensing panel using the same process. When integrated into a single sensing panel, the sensing panel can be positioned between the display panel 2141 and a window positioned above the display panel 2141. In an embodiment, the sensing panel can be positioned on the window, but the position of the sensing panel is not limited thereto.

[0165] At least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be embedded in the display panel 2141. In other words, at least one of the fingerprint sensor 2161-1, the input sensor 2161-2, and the digitizer 2161-3 can be formed simultaneously during the formation of the elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 2141.

[0166] In addition, sensor module 2161 can generate electrical signals or data values ​​corresponding to the internal or external state of electronic device 2101. Sensor module 2161 may also include, for example, gesture sensors, gyroscope sensors, barometric pressure sensors, magnetic sensors, accelerometers, grip sensors, proximity sensors, color sensors, infrared (IR) sensors, biosensors, temperature sensors, humidity sensors, or illuminance sensors.

[0167] Antenna module 2162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In an embodiment, communication module 2173 may transmit or receive signals to or from external electronic device 2102 via an antenna suitable for a communication method. The antenna pattern of antenna module 2162 may be integrated into a component of display module 2140 (e.g., display panel 2141) or input sensor 2161-2.

[0168] The sound output module 2163 can output sound signals to the outside of the electronic device 2101. The sound output module 2163 may include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as playing multimedia or playing recordings. The receiver can be used to receive incoming calls. In embodiments, the receiver may be implemented separately from the speaker or as part of the speaker. The sound output mode of the sound output module 2163 may be integrated into the display module 2140.

[0169] Camera module 2171 can capture still and moving images. In embodiments, camera module 2171 may include one or more lenses, an image sensor, or an image signal processor. Camera module 2171 may also include an infrared camera capable of measuring the presence or absence of a user, the user's position, and the user's line of sight.

[0170] The optical module 2172 can provide light. The optical module 2172 may include a light-emitting diode or a xenon lamp. The optical module 2172 may operate in conjunction with the camera module 2171, or it may operate independently of the camera module 2171.

[0171] Communication module 2173 supports establishing a wired or wireless communication channel between electronic device 2101 and external electronic device 2102, and enables communication via the established communication channel. Communication module 2173 may include a wireless communication module (e.g., a cellular communication module, a short-range wireless communication module, or a Global Navigation Satellite System (GNSS) communication module) or a wired communication module (e.g., a local area network (LAN) communication module or a power line communication (PLC) module). Communication module 2173 can communicate via a short-range communication network (e.g., The external electronic device 2102 communicates with a wireless fidelity (Wi-Fi Direct) or infrared data association (IrDA) network or long-range communication network (e.g., cellular network, Internet, or computer network (e.g., LAN or WAN)). These various types of communication modules 2173 can be implemented as a single chip or as multiple chips that are separate from each other.

[0172] Input module 2130, sensor module 2161, camera module 2171 and the like can work in conjunction with processor 2110 to control the operation of display module 2140.

[0173] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on the input data received from the input module 2130. For example, the processor 2110 can generate image data corresponding to the input data applied by a mouse or active pen, and can output the image data to the display module 2140. Alternatively, the processor 2110 can generate command data corresponding to the input data, and can output the command data to the camera module 2171 or the optical module 2172. When no input data is received from the input module 2130 for a certain period of time, the processor 2110 can switch the operating mode of the electronic device 2101 to a low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device 2101.

[0174] The processor 2110 can output commands or data to the display module 2140, the sound output module 2163, the camera module 2171, or the optical module 2172 based on sensing data received from the sensor module 2161. For example, the processor 2110 can compare authentication data applied by the fingerprint sensor 2161-1 with authentication data stored in the memory 2120, and then execute an application based on the comparison result. The processor 2110 can execute commands or output corresponding image data to the display module 2140 based on sensing data sensed by the input sensor 2161-2 or the digitizer 2161-3. If the sensor module 2161 includes a temperature sensor, the processor 2110 can receive temperature data from the sensor module 2161 and can also perform brightness correction on the image data based on the temperature data.

[0175] Processor 2110 can receive measurement data from camera module 2171 regarding the presence or absence of a user, the user's position, and the user's gaze. Processor 2110 can also perform brightness correction on image data based on the measurement data. For example, after processor 2110 determines the presence or absence of a user based on input from camera module 2171, data conversion circuit 2112-2 or gamma correction circuit 2112-3 can perform brightness correction on the image data, and processor 2110 can provide the brightness-corrected image data to display module 2140.

[0176] At least some of the aforementioned components can be interconnected and transmit signals (e.g., commands or data) between them via inter-peripheral communication schemes (e.g., bus, general purpose input / output (GPIO), serial peripheral interface (SPI), mobile industry processor interface (MIPI), or ultrapath interconnect (UPI)). Processor 2110 can communicate with display module 2140 via a pre-defined interface. Furthermore, any of the aforementioned communication methods can be used between processor 2110 and display module 2140, but the communication methods between processor 2110 and display module 2140 are not limited to those described above.

[0177] The electronic device 2101 according to the above embodiments can be of various types. For example, the electronic device 2101 may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. However, the electronic device 2101 according to the embodiments is not limited to the devices described above.

[0178] The display device according to the embodiments can be applied to display devices included in computers, laptops, mobile phones, smartphones, smart tablets, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, or the like.

[0179] The foregoing description is illustrative of the invention and should not be construed as limiting it. Although some embodiments of the invention have been described, those skilled in the art will readily understand that many modifications may be made to the embodiments without materially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. In the claims, the means plus function clause is intended to cover structures described herein for performing said functions, and includes not only structural equivalents but also equivalent structures. Therefore, it should be understood that the foregoing description is illustrative of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the appended claims, wherein equivalents of the claims are included within the invention.

Claims

1. A display device, comprising: Display panel, including pixels; A gate driver configured to output a gate signal to the pixel; as well as A data driver configured to apply a data voltage to the pixel. The gate driver includes: An applied transistor is configured to apply a previous carry signal to the transmitter in response to a clock signal; The transmitter is configured to apply the previous carry signal by pulling down the control node; A pull-up controller, connected to the transmitter and configured to control the pull-up control node; A pull-down transistor configured to apply a low voltage to the output node in response to the voltage of the pull-down control node; A pull-up transistor configured to apply a high voltage to the output node in response to the voltage of the pull-up control node; A carry-down transistor configured to apply a carry-low voltage to the carry node in response to the voltage of the pull-up control node; and A carry pull-up transistor is configured to apply a carry high voltage to the carry node in response to the voltage of the pull-up control node, and Wherein, the carry-in low voltage is higher than the low voltage.

2. The display device according to claim 1, wherein, The carry-down transistor is an N-type transistor, and the carry-up transistor is a P-type transistor.

3. The display device according to claim 1, wherein, The transmitter includes: A first transmission transistor is configured to connect a first node and a second node; and The second transmission transistor is configured to connect the second node and the pull-down control node.

4. The display device according to claim 3, wherein, The first transmission transistor includes a control electrode for receiving the carry high voltage, a first electrode connected to the first node, and a second electrode connected to the second node.

5. The display device according to claim 4, wherein, The second transmission transistor includes a control electrode for receiving the low voltage, a first electrode connected to the second node, and a second electrode connected to the pull-down control node.

6. The display device according to claim 3, wherein, The first transmission transistor is an N-type transistor.

7. The display device according to claim 3, wherein, The second transmission transistor includes a control electrode for receiving the low voltage, a first electrode connected to the second node, and a second electrode connected to the pull-down control node.

8. The display device according to claim 1, wherein, The pull-up controller includes: A first pull-up control transistor includes a control electrode connected to the pull-down control node, a first electrode for receiving the low voltage, and a second electrode connected to the pull-up node; and The second pull-up control transistor includes a control electrode connected to the pull-down control node, a first electrode for receiving the high voltage, and a second electrode connected to the pull-up control node.

9. The display device according to claim 1, wherein, The difference between the carry-low voltage and the low voltage is higher than the absolute value of the threshold voltage of the carry-down transistor.

10. The display device according to claim 1, wherein, The gate driver includes: The first transistor includes a control electrode for receiving the clock signal, a first electrode for receiving the previous carry signal, and a second electrode connected to the first node; The second transistor includes a control electrode for receiving the low voltage, a first electrode connected to the second node, and a second electrode connected to the pull-down control node. The third transistor includes a control electrode connected to the pull-down control node, a first electrode for receiving the low voltage, and a second electrode connected to the pull-up control node; The fourth transistor includes a control electrode connected to the pull-down control node, a first electrode for receiving the high voltage, and a second electrode connected to the pull-up control node; The fifth transistor includes a control electrode connected to the pull-down control node, a first electrode for receiving the low voltage, and a second electrode connected to the output node; The sixth transistor includes a control electrode connected to the pull-up control node, a first electrode for receiving the high voltage, and a second electrode connected to the output node; The seventh transistor includes a control electrode connected to the pull-up control node, a first electrode for receiving the carry low voltage, and a second electrode connected to the carry node; The eighth transistor includes a control electrode connected to the pull-up control node, a first electrode for receiving the carry high voltage, and a second electrode connected to the carry node; and The ninth transistor includes a control electrode for receiving the carry high voltage, a first electrode connected to the first node, and a second electrode connected to the second node. Wherein, the first transistor is the applying transistor, the fifth transistor is the pull-down transistor, the sixth transistor is the pull-up transistor, the seventh transistor is the carry pull-down transistor, and the eighth transistor is the carry pull-up transistor.

11. A display device, comprising: Display panel, including pixels; A gate driver configured to output a gate signal to the pixel; as well as A data driver configured to apply a data voltage to the pixel. The gate driver includes: An applied transistor is configured to apply a previous carry signal to the transmitter in response to a clock signal; The transmitter is configured to apply the previous carry signal by pulling down the control node; A pull-up controller, connected to the transmitter and configured to control the pull-up control node; A pull-down transistor configured to apply a first low voltage to the output node in response to the voltage of the pull-down control node; A pull-up transistor configured to apply a high voltage to the output node in response to the voltage of the pull-up control node; A carry pull-down transistor, configured to apply a carry low voltage to the carry node in response to the voltage of the pull-down control node; and A carry pull-up transistor is configured to apply a carry high voltage to the carry node in response to the voltage of the pull-up control node, and Wherein, the carry-in low voltage is higher than the first low voltage.

12. The display device according to claim 11, wherein, The carry-down transistor is a P-type transistor.

13. The display device according to claim 11, wherein, The transmitter includes: A first transmission transistor is configured to connect a first node and a second node; and The second transmission transistor is configured to connect the second node and the pull-down control node.

14. The display device according to claim 13, wherein, The first transmission transistor includes a control electrode for receiving the carry high voltage, a first electrode connected to the first node, and a second electrode connected to the second node.

15. The display device according to claim 13, wherein, The first transmission transistor is an N-type transistor.

16. The display device according to claim 13, wherein, The second transmission transistor includes a control electrode for receiving a second low voltage different from the first low voltage, a first electrode connected to the second node, and a second electrode connected to the pull-down control node.

17. The display device according to claim 11, wherein, The difference between the carry-low voltage and the first low voltage is higher than the absolute value of the threshold voltage of the carry-down transistor.

18. An electronic device comprising: Display panel, including pixels; A gate driver configured to output a gate signal to the pixel; A data driver configured to apply a data voltage to the pixel; A drive controller configured to control the gate driver and the data driver; as well as The processor is configured to output input image data and input control signals. The gate driver includes: An applied transistor is configured to apply a previous carry signal to the transmitter in response to a clock signal; The transmitter is configured to apply the previous carry signal by pulling down the control node; A pull-up controller, connected to the transmitter and configured to control the pull-up control node; A pull-down transistor configured to apply a low voltage to the output node in response to the voltage of the pull-down control node; A pull-up transistor configured to apply a high voltage to the output node in response to the voltage of the pull-up control node; A carry-down transistor configured to apply a carry-low voltage to the carry node in response to the voltage of the pull-up control node; and A carry pull-up transistor is configured to apply a carry high voltage to the carry node in response to the voltage of the pull-up control node, and Wherein, the carry-in low voltage is higher than the low voltage.

19. The electronic device according to claim 18, wherein, The carry-down transistor is an N-type transistor, and the carry-up transistor is a P-type transistor.

20. The electronic device according to claim 18, wherein, The difference between the carry-low voltage and the low voltage is higher than the absolute value of the threshold voltage of the carry-down transistor.

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