Memory controller, memory training method and processor
By allocating delayed scan points in the memory controller and scanning data lines in parallel, the problem of long memory training time is solved, achieving more efficient memory training and improved system performance.
Patent Information
- Application Number
- CN202510846510.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-23
- Publication Date
- 2025-10-31
AI Technical Summary
Existing technologies involve long memory training times, which impact system performance, and require traversing all possible delay windows, leading to blocked memory access requests.
By acquiring multiple delayed scan points and allocating these scan points to each data line according to the number of data lines between the memory controller and the memory chip, memory training is performed to ensure that each data line scans multiple delayed scan points but the total number is less than the total number of scan points. Parallel scanning technology is used to shorten the training time.
It effectively shortens the memory training time, improves system performance, and reduces the impact of memory training on system performance.
Smart Images
Figure CN120877795A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and in particular to a memory controller, a memory training method, and a processor. Background Technology
[0002] Most modern electronic devices integrate processors and memory chips. Both the processor and memory chips require a memory controller, which connects to the memory chips via a memory bus. The memory bus consists of data lines and timing signal lines; the data lines transmit data signals, and the timing signal lines transmit data strobe pulse signals.
[0003] The accuracy of data transmission between the memory controller and the memory chip depends on the relative timing alignment between the data signal and the data strobe pulse signal. In other words, only when the data signal has sufficient timing margin relative to the data strobe pulse signal can the receiving end of the data signal achieve a low bit error rate, thus ensuring the accuracy of data transmission. Voltage, temperature, and frequency can all cause changes in the phase of the data signal and the data strobe pulse signal. Adjusting the phase position of the data signal and the data strobe pulse signal, i.e., memory training, has become a common strategy for improving memory reliability.
[0004] In related technologies, since it is necessary to find a suitable delay window for the data signal on each data line, all possible delays must be traversed for each data line. As a result, when the data bandwidth is large, it often takes a long time to complete memory training. Since memory training will block the application's access requests to memory, it will have a significant impact on system performance. Summary of the Invention
[0005] In view of this, embodiments of the present invention provide a memory controller, a memory training method, and a processor, which can effectively shorten the memory training time and improve system performance.
[0006] In a first aspect, embodiments of the present invention provide a memory controller, comprising: an acquisition module, configured to acquire a plurality of delay scan points, wherein the delay scan points are time points that need to be scanned when delay adjustment of data signals during memory training; an allocation module, configured to allocate the plurality of delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip, such that the number of delay scan points allocated to each of the data lines is greater than 0 and less than the total number of the plurality of delay scan points, wherein each of the plurality of delay scan points is allocated to at least one of the data lines; and a training execution module, configured to perform memory training based on the delay scan points allocated to each of the data lines.
[0007] In one implementation, the difference in the number of delayed scan points assigned to any two of the data lines is less than 2.
[0008] In one implementation, the number of delayed scan points assigned to each of the data lines is equal to the number of each other.
[0009] In one embodiment, the training execution module includes: a command issuing submodule for issuing memory training commands, the memory training commands including read training commands and / or write training commands; a first transceiver submodule for performing a first transceiver operation based on the memory training commands and the delay scan points assigned to each of the data lines, the first transceiver operation including sending data to memory granules and / or receiving data sent by memory granules; a selection submodule for selecting, from the first transceiver operations of each of the data lines, the first transceiver operation whose operation result is the same as the expected result as a candidate operation, the delay scan point corresponding to the candidate operation being a candidate scan point; a determination submodule for determining a target delay point based on the candidate scan points corresponding to each of the data lines; and a setting submodule for setting the delay parameters of each of the data lines based on the target delay point to obtain trained data lines.
[0010] In one implementation, the determining submodule is specifically used to: sort the candidate scanning points in chronological order to obtain a candidate sequence; and determine the target delay point based on the candidate scanning point located in the middle position of the candidate sequence.
[0011] In one embodiment, the training execution module further includes: a second transceiver submodule, configured to perform a second transceiver operation on the memory particle based on the trained data lines after setting the delay parameters of each of the data lines according to the target delay point, the second transceiver operation including sending data to the memory particle and / or receiving data sent by the memory particle; and a detection submodule, configured to detect whether the operation results of the second transceiver operation corresponding to each of the trained data lines are the same as the expected results.
[0012] In one embodiment, the training execution module further includes an adjustment submodule, which is used to adjust the delay parameter of the trained data line in response to a difference between the operation result of the second transmit / receive operation corresponding to any one of the trained data lines and the expected result after the detection submodule detects whether the operation result of the second transmit / receive operation corresponding to each of the trained data lines is the same as the expected result.
[0013] In one embodiment, the ratio of the difference in length between any two data lines between the memory controller and the memory chip to the length of the longer data line is less than a preset threshold.
[0014] Secondly, embodiments of the present invention also provide a memory training method applied to a memory controller. The method includes: acquiring a plurality of delay scan points, wherein the delay scan points are time points that need to be scanned when delaying data signals during memory training; allocating the plurality of delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chips, such that the number of delay scan points allocated to each data line is greater than 0 and less than the total number of the plurality of delay scan points, wherein each of the plurality of delay scan points is allocated to at least one data line; and performing memory training based on the delay scan points allocated to each of the data lines.
[0015] In one implementation, memory training based on the latency scan points assigned to each of the data lines includes: issuing a memory training command, the memory training command including a read training command and / or a write training command; performing a first transmit / receive operation based on the latency scan points assigned to each of the data lines according to the memory training command, the first transmit / receive operation including: sending data to memory chips, and / or receiving data sent by memory chips; selecting, from the first transmit / receive operations of each of the data lines, the first transmit / receive operation whose operation result is the same as the expected result as a candidate operation, the latency scan point corresponding to the candidate operation being a candidate scan point; determining a target latency point according to the candidate scan points corresponding to each of the data lines; and setting the latency parameters of each of the data lines according to the target latency point to obtain trained data lines.
[0016] In one embodiment, determining the target delay point based on the candidate scan points corresponding to each of the data lines includes: sorting the candidate scan points in chronological order to obtain a candidate sequence; and determining the target delay point based on the candidate scan point located in the middle of the candidate sequence.
[0017] In one embodiment, after setting the delay parameters of each data line according to the target delay point, the method further includes: performing a second transmit / receive operation on the memory particle based on the trained data line, the second transmit / receive operation including sending data to the memory particle and / or receiving data sent by the memory particle; and detecting whether the operation results of the second transmit / receive operation corresponding to each trained data line are the same as the expected results.
[0018] In one embodiment, after detecting whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results, the method further includes: adjusting the delay parameter of the trained data line in response to the fact that the operation result of the second transmit / receive operation corresponding to any of the trained data lines is different from the expected result.
[0019] In one embodiment, the ratio of the difference in length between any two data lines between the memory controller and the memory chip to the length of the longer data line is less than a preset threshold.
[0020] In one embodiment, the present invention also provides a processor, the processor including any of the memory controllers provided in the embodiments of the present invention. Attached Figure Description
[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0022] Figure 1 A schematic diagram of a memory controller provided for an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the connection relationship between the memory controller and the memory chip in an embodiment of the present invention; Figure 3 A flowchart of a memory training method provided for an embodiment of the present invention; Figure 4 A signal waveform diagram of a memory training method provided in an embodiment of the present invention; Figure 5 A detailed flowchart of a memory training method provided for embodiments of the present invention; Figure 6 A schematic diagram of a processor provided for an embodiment of the present invention. Detailed Implementation
[0023] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.
[0024] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.
[0025] In a first aspect, embodiments of the present invention also provide a memory controller that can effectively shorten the memory training time and improve system performance.
[0026] like Figure 1 As shown, the memory controller provided in the embodiments of the present invention may include: The acquisition module 31 is used to acquire multiple delayed scan points, which are time points that need to be scanned when adjusting the delay of data signals during memory training; The allocation module 32 is used to allocate the plurality of delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip, so that the number of delay scan points allocated to each of the data lines is greater than 0 and less than the total number of the plurality of delay scan points, and each of the plurality of delay scan points is allocated to at least one of the data lines. The training execution module 33 performs memory training based on the delay scan points to which each of the data lines is assigned.
[0027] The memory controller provided in the embodiments of the present invention can acquire multiple delay scan points, allocate the multiple delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip, and perform memory training based on the delay scan points allocated to each of the data lines. Since the number of delay scan points assigned to each data line is greater than 0, each data line scans the delay scan points during memory training. Furthermore, since the number of delay scan points assigned to each data line is less than the total number of delay scan points, and each data line can only scan one delay scan point per clock cycle, the number of clock cycles required to traverse the delay scan points of each data line is less than the total number of delay scan points. Even when data lines are scanned in parallel, the number of clock cycles required to traverse all delay scan points is also less than the total number of delay scan points. Therefore, compared to the prior art where the number of clock cycles required to traverse all delay scan points equals the total number of delay scan points, the memory training method provided by the embodiments of the present invention can effectively shorten the memory training time and improve system performance.
[0028] In embodiments of the present invention, the delay scan point can refer to the time point that needs to be scanned when adjusting the delay of the data signal during memory training. By adjusting the delay of the data signal, the time when data is sent to each data line can be adjusted so that the data signals on each data line can be sampled simultaneously by the data receiver. It is understood that there is a corresponding relationship between signal delay and signal phase; if the delay of the data signals on different data lines is different, then their phases will also be different accordingly.
[0029] Specifically, the delay scan points can be evenly distributed within the maximum allowable delay range, which can be, for example, one clock cycle. In one embodiment of the invention, the multiple delay scan points can be predetermined; in another embodiment, they can be determined based on the maximum allowable delay range and the delay adjustment precision supported by the memory controller. For example, in one instance, if the maximum allowable delay range is 5 nanoseconds and the delay adjustment precision supported by the memory controller is 0.5 nanoseconds, then each delay scan point can be determined to include 10 (5 nanoseconds / 0.5 nanoseconds = 10) time points evenly distributed within this maximum range.
[0030] Depending on the data width, the number of data lines between the memory controller and the memory chips varies. During memory training, these data lines can be used to perform parallel read or write operations on each bit.
[0031] The number of delay scan points assigned to each data line can vary depending on the number of data lines and the total number of delay scan points. For example, in one instance, if the number of data lines is greater than the total number of delay scan points, after assigning each delay scan point to one data line, there will still be data lines without assigned delay scan points. Therefore, a subset of delay scan points can be selected from the total number of delay scan points and assigned to these data lines. In other words, if the number of data lines is greater than the total number of delay scan points, each delay scan point can be assigned to one or more data lines.
[0032] In another example, if the number of data lines is less than the total number of delay scan points, after assigning one delay scan point to each data line, some delay scan points will still remain unassigned. Therefore, a subset of data lines can be selected, and the remaining delay scan points can be allocated to these data lines. In other words, if the number of data lines is less than the total number of delay scan points, each data line can be assigned one or more delay scan points.
[0033] It should be noted that when allocating the multiple delay scan points to each of the data lines, the specific allocation rules are not limited. For example, they can be allocated in a preset order or randomly, as long as the number of delay scan points allocated to each data line is greater than 0 and less than the total number of the multiple delay scan points, and each of the multiple delay scan points is allocated to at least one data line.
[0034] After each data line is assigned a corresponding delay scan point, the training execution module 33 can perform memory training based on the delay scan points assigned to each data line. Specifically, since each clock cycle can scan one delay scan point of each data line, and since the delay scan points corresponding to each data line are not exactly the same, multiple delay scan points can be verified to meet the read and write requirements in one clock cycle.
[0035] Specifically, such as Figure 2 As shown, in one embodiment of the present invention, the memory controller and the memory chip are connected via a memory bus, wherein CA is the bus for the memory controller to send read and write commands, DQ is the bus for the memory controller and the memory chip to send and receive data, and DQS is the reference signal sampled by the receiving end. The training module in the memory controller for memory training (here, the training module includes the aforementioned acquisition module 31, allocation module 32, and training execution module 33) can interact with the training module in the memory chip for memory training, thereby realizing memory training.
[0036] In one implementation, the allocation module 32 can allocate the plurality of delay scan points to each of the data lines based on the number of data lines between the memory controller and the memory chip. The specific allocation rule is not limited, as long as it ensures that the number of delay scan points allocated to each data line is greater than 0 and less than the total number of the plurality of delay scan points, and that each of the plurality of delay scan points is allocated to at least one data line.
[0037] In one implementation, the number of delay scan points assigned to each data line can vary considerably; for example, one data line may be assigned to one delay scan point while another data line may be assigned to four delay scan points.
[0038] In another implementation, the number of delay scan points assigned to each data line can be relatively close. For example, the difference between the number of delay scan points assigned to any two data lines is less than 2 (e.g., 0 or 1). This ensures a more even distribution of delay scan points across the data lines, preventing any single data line from having a large number of delay scan points. Since the number of clock cycles required for memory training is determined by the data line containing the most delay scan points, the number of clock cycles required for memory training can be further reduced, thereby further improving system performance.
[0039] For example, in one implementation, the number of delay scan points assigned to each data line can be equal to each other, for example, each data line can be assigned 2 delay scan points.
[0040] In one embodiment of the present invention, among the data lines between the memory controller and the memory chip, the ratio of the difference in length between any two data lines to the length of the longer data line is less than a preset threshold. This ensures that the lengths of the data lines are relatively close, thereby effectively improving the success rate of memory training. For example, in one instance, such data lines could be data lines in HBM (high bandwidth memory).
[0041] Furthermore, by assigning the plurality of delayed scan points to each of the data lines, the training execution module 33 can perform memory training based on the delayed scan points to which each of the data lines is assigned.
[0042] Specifically, in one implementation, the training execution module 33 may include: a command issuing submodule, a first transceiver submodule, a selection submodule, a determination submodule, and a setting submodule. The command issuing submodule is used to issue memory training commands, including read training commands and / or write training commands; the first transceiver submodule is used to perform a first transceiver operation based on the memory training commands and the delay scan points assigned to each of the data lines, the first transceiver operation including: sending data to memory chips and / or receiving data sent by memory chips; the selection submodule is used to select, from the first transceiver operations of each of the data lines, the first transceiver operation whose operation result is the same as the expected result as a candidate operation, the delay scan point corresponding to the candidate operation being a candidate scan point; the determination submodule is used to determine a target delay point based on the candidate scan points corresponding to each of the data lines; and the setting submodule is used to set the delay parameters of each of the data lines according to the target delay point to obtain trained data lines.
[0043] In this embodiment, since the lengths of the data lines are not identical, and the allocated delay scan points are also different, the arrival times of data on each data line at the receiver may vary during the first transmit / receive operation of memory training. This may result in the first transmit / receive operation succeeding on some data lines while failing on others. Optionally, if the first transmit / receive operation succeeds, the result is the same as expected; if the first transmit / receive operation fails, the result is different from expected.
[0044] In embodiments of the present invention, the specific form of the first transmit / receive operation varies depending on the specific form of the memory training command, and the specific forms of the operation result and the expected result can also differ. In one example, the memory training command is a read training command, then the first transmit / receive operation is receiving data sent by the memory chip (i.e., a read memory operation). Based on this, the operation result can be the data read by the memory controller, and the expected result can be the data stored in the memory chip. Optionally, if the operation result is the same as the expected result, it indicates that the data stored in the memory chip has been correctly read into the memory controller, and the read memory operation is successful; otherwise, if the operation result is different from the expected result, it indicates that the data stored in the memory chip has not been correctly read into the memory controller, and the read memory operation fails.
[0045] In another example, if the memory training command is a write training command, then the first transmit / receive operation is sending data to the memory granules (i.e., a write memory operation). Based on this, the operation result can be the data received by the memory granules, and the expected result can be the data sent by the memory controller. Optionally, if the operation result is the same as the expected result, it means that the data to be written was correctly written to memory, and the write memory operation was successful; otherwise, if the operation result is different from the expected result, it means that the data to be written was not correctly written to memory, and the write memory operation failed.
[0046] In the embodiments of the present invention, for the write training command, since it is necessary to verify whether the data to be written is correctly written to memory by reading the written data again, read training can be performed first, and then write training can be performed. This ensures that the actual written data is consistent with the data to be written, based on the reliable reading of the data.
[0047] Whether it is read training or write training, after the first transmit and receive operation is performed, the first transmit and receive operation with the same result as the expected result can be selected from the first transmit and receive operations of each data line as the alternative operation, and the delay scan point corresponding to the alternative operation is the alternative scan point. For example, in one scenario, there are 8 data lines: DL0 (delay scan point is -0.3 nanoseconds), DL1 (delay scan point is -0.2 nanoseconds), DL2 (delay scan point is -0.1 nanoseconds), DL3 (delay scan point is 0 nanoseconds), DL4 (delay scan point is +0.1 nanoseconds), DL5 (delay scan point is +0.2 nanoseconds), DL6 (delay scan point is +0.3 nanoseconds), and DL7 (delay scan point is +0.4 nanoseconds). The first transmit / receive operation results for DL0, DL6, and DL7 differ from the expected results, while the first transmit / receive operation results for the other data lines are the same as expected. Therefore, the first transmit / receive operations for DL1...DL5 are the alternative operations, and the alternative scan points include: -0.2 nanoseconds, -0.1 nanoseconds, 0 nanoseconds, 0.1 nanoseconds, and 0.2 nanoseconds. After obtaining each candidate scanning point, the target delay point can be determined based on the candidate scanning point corresponding to each data line, and the delay parameters of each data line can be set according to the target delay point to obtain the trained data line.
[0048] Specifically, in one implementation, the determining submodule 334 can be used to: sort the candidate scanning points in chronological order to obtain a candidate sequence; and determine the target delay point based on the candidate scanning point located in the middle position of the candidate sequence.
[0049] Taking the aforementioned data lines DL0 to DL7 as an example, the candidate scan points can be arranged in chronological order to obtain a candidate sequence. This candidate sequence could be, for example, -0.2, -0.1, 0, 0.1, 0.2. The candidate scan point in the middle of the candidate sequence is "0". The target delay point can then be determined based on this candidate scan point "0". For instance, the candidate scan point "0" in the middle of the candidate sequence can be determined as the target delay point.
[0050] Furthermore, after obtaining the target delay point, the setting submodule 335 can set the delay parameters of each data line according to the target delay point to obtain the trained data line. For example, the setting submodule 335 can set the delay parameters of each data line to the target delay point to obtain the trained data line.
[0051] Based on this, in one embodiment, the training execution module 33 may further include: a second transceiver submodule, used to perform a second transceiver operation on the memory particle based on the trained data lines after setting the delay parameters of each of the data lines according to the target delay point, the second transceiver operation including sending data to the memory particle and / or receiving data sent by the memory particle; and a detection submodule, used to detect whether the operation results of the second transceiver operation corresponding to each of the trained data lines are the same as the expected results. In this way, it is possible to detect whether the delay parameters set in each trained data line can correctly complete the data read and write operations of the memory particle, thereby improving the reliability and success rate of memory training.
[0052] In one embodiment, the training execution module 33 may further include an adjustment submodule, configured to adjust the delay parameter of the trained data line in response to a difference between the operation result of the second transmit / receive operation corresponding to any one of the trained data lines and the expected result, after the detection submodule detects whether the operation results of the second transmit / receive operations corresponding to each of the trained data lines are the same as the expected results. In this case, since only the operation results of the second transmit / receive operations corresponding to a few trained data lines differ from the expected results, only the delay parameters of these few trained data lines need to be adjusted, which can effectively shorten the memory training time and improve system performance.
[0053] Secondly, embodiments of the present invention provide a memory training method applied to a memory controller, which can effectively shorten the memory training time and improve system performance.
[0054] like Figure 3 As shown, an embodiment of the present invention provides a memory training method applied to a memory controller, the method including: S11, acquire multiple delayed scan points, wherein the delayed scan points are the time points that need to be scanned when the data signal is delayed and adjusted during memory training; In embodiments of the present invention, the delay scan point can refer to the time point that needs to be scanned when adjusting the delay of the data signal during memory training. By adjusting the delay of the data signal, the time when data is sent to each data line can be adjusted so that the data signals on each data line can be sampled simultaneously by the data receiver. It is understood that there is a corresponding relationship between signal delay and signal phase; if the delay of the data signals on different data lines is different, then their phases will also be different accordingly.
[0055] Specifically, the delay scan points can be evenly distributed within the maximum allowable delay range, which can be, for example, one clock cycle. In one embodiment of the invention, the multiple delay scan points can be predetermined; in another embodiment, they can be determined based on the maximum allowable delay range and the delay adjustment precision supported by the memory controller. For example, in one instance, if the maximum allowable delay range is 5 nanoseconds and the delay adjustment precision supported by the memory controller is 0.5 nanoseconds, then each delay scan point can be determined to include 10 (5 nanoseconds / 0.5 nanoseconds = 10) time points evenly distributed within this maximum range.
[0056] S12, according to the number of data lines between the memory controller and the memory chip, the plurality of delay scan points are assigned to each of the data lines, so that the number of delay scan points assigned to each data line is greater than 0 and less than the total number of the plurality of delay scan points, and each of the plurality of delay scan points is assigned to at least one of the data lines. Depending on the data width, the number of data lines between the memory controller and the memory chips varies. During memory training, these data lines can be used to perform parallel read or write operations on each bit.
[0057] In this step, the number of delay scan points assigned to each data line can vary depending on the number of data lines and the total number of delay scan points. For example, in one instance, if the number of data lines is greater than the total number of delay scan points, after assigning each delay scan point to one data line, there will still be data lines without assigned delay scan points. Therefore, a subset of delay scan points can be selected from the total number of delay scan points and assigned to these data lines. That is, if the number of data lines is greater than the total number of delay scan points, each delay scan point can be assigned to one or more data lines.
[0058] In another example, if the number of data lines is less than the total number of delay scan points, after assigning one delay scan point to each data line, some delay scan points will still remain unassigned. Therefore, a subset of data lines can be selected, and the remaining delay scan points can be allocated to these data lines. In other words, if the number of data lines is less than the total number of delay scan points, each data line can be assigned one or more delay scan points.
[0059] It should be noted that when allocating the multiple delay scan points to each of the data lines, the specific allocation rules are not limited. For example, they can be allocated in a preset order or randomly, as long as the number of delay scan points allocated to each data line is greater than 0 and less than the total number of the multiple delay scan points, and each of the multiple delay scan points is allocated to at least one data line.
[0060] S13, memory training is performed based on the delay scan points to which each of the data lines is assigned.
[0061] After each data line is assigned a corresponding delay scan point, memory training can be performed in this step based on the delay scan points assigned to each data line. Specifically, since each clock cycle can scan one delay scan point of each data line, and the delay scan points corresponding to each data line are not exactly the same, multiple delay scan points can be verified to meet the read and write requirements within one clock cycle.
[0062] The memory training method provided in the embodiments of the present invention allows the memory controller to acquire multiple delay scan points, allocate the multiple delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip, and perform memory training based on the delay scan points allocated to each of the data lines. Since the number of delay scan points assigned to each data line is greater than 0, each data line scans the delay scan points during memory training. Furthermore, since the number of delay scan points assigned to each data line is less than the total number of delay scan points, and each data line can only scan one delay scan point per clock cycle, the number of clock cycles required to traverse the delay scan points of each data line is less than the total number of delay scan points. Even when data lines are scanned in parallel, the number of clock cycles required to traverse all delay scan points is also less than the total number of delay scan points. Therefore, compared to the prior art where the number of clock cycles required to traverse all delay scan points equals the total number of delay scan points, the memory training method provided by the embodiments of the present invention can effectively shorten the memory training time and improve system performance.
[0063] The memory training method provided in the embodiments of the present invention can be applied to a memory controller; that is, the memory training method can be executed by the memory controller. Specifically, as shown in the embodiments of the present invention... Figure 2As shown, in one embodiment of the present invention, the memory controller and the memory chip are connected via a memory bus, wherein CA is the bus for the memory controller to send read and write commands, DQ is the bus for the memory controller and the memory chip to transmit and receive data, and DQS is the reference signal sampled by the receiving end. The training module in the memory controller can interact with the memory training module in the memory chip to realize memory training.
[0064] Specifically, after obtaining multiple delay scan points in step S11, in step S12, the multiple delay scan points can be allocated to each of the data lines according to the number of data lines between the memory controller and the memory chip. The allocation rule is not limited, as long as it ensures that the number of delay scan points allocated to each data line is greater than 0 and less than the total number of the multiple delay scan points, and each of the multiple delay scan points is allocated to at least one data line.
[0065] In one implementation, the number of delay scan points assigned to each data line can vary considerably; for example, one data line may be assigned to one delay scan point while another data line may be assigned to four delay scan points.
[0066] In another implementation, the number of delay scan points assigned to each data line can be relatively close. For example, the difference between the number of delay scan points assigned to any two data lines is less than 2 (e.g., 0 or 1). This ensures a more even distribution of delay scan points across the data lines, preventing any single data line from having a large number of delay scan points. Since the number of clock cycles required for memory training is determined by the data line containing the most delay scan points, the number of clock cycles required for memory training can be further reduced, thereby further improving system performance.
[0067] For example, in one implementation, the number of delay scan points assigned to each data line can be equal to each other, for example, each data line can be assigned 2 delay scan points.
[0068] In one embodiment of the present invention, among the data lines between the memory controller and the memory chip, the ratio of the difference in length between any two data lines to the length of the longer data line is less than a preset threshold. This ensures that the lengths of the data lines are relatively close, thereby effectively improving the success rate of memory training. For example, in one instance, such data lines could be data lines in HBM (high bandwidth memory).
[0069] Furthermore, by assigning the plurality of delayed scan points to each of the data lines, memory training can be performed in step S13 based on the delayed scan points to which each of the data lines is assigned.
[0070] Specifically, in one embodiment of the present invention, memory training based on the delay scan points assigned to each of the data lines may include: issuing a memory training command, the memory training command including a read training command and / or a write training command; according to the memory training command, performing a first transmit / receive operation based on the delay scan points assigned to each of the data lines, the first transmit / receive operation including: sending data to memory chips, and / or receiving data sent by memory chips; selecting, from the first transmit / receive operations of each of the data lines, the first transmit / receive operation whose operation result is the same as the expected result as a candidate operation, the delay scan point corresponding to the candidate operation being a candidate scan point; determining a target delay point according to the candidate scan points corresponding to each of the data lines; setting the delay parameters of each of the data lines according to the target delay point to obtain trained data lines.
[0071] In this embodiment, since the lengths of the data lines are not identical, and the allocated delay scan points are also different, the arrival times of data on each data line at the receiver may vary during the first transmit / receive operation of memory training. This may result in the first transmit / receive operation succeeding on some data lines while failing on others. Optionally, if the first transmit / receive operation succeeds, the result is the same as expected; if the first transmit / receive operation fails, the result is different from expected.
[0072] In embodiments of the present invention, the specific form of the first transmit / receive operation varies depending on the specific form of the memory training command, and the specific forms of the operation result and the expected result can also differ. In one example, the memory training command is a read training command, then the first transmit / receive operation is receiving data sent by the memory chip (i.e., a read memory operation). Based on this, the operation result can be the data read by the memory controller, and the expected result can be the data stored in the memory chip. Optionally, if the operation result is the same as the expected result, it indicates that the data stored in the memory chip has been correctly read into the memory controller, and the read memory operation is successful; otherwise, if the operation result is different from the expected result, it indicates that the data stored in the memory chip has not been correctly read into the memory controller, and the read memory operation fails.
[0073] In another example, if the memory training command is a write training command, then the first transmit / receive operation is sending data to the memory granules (i.e., a write memory operation). Based on this, the operation result can be the data received by the memory granules, and the expected result can be the data sent by the memory controller. Optionally, if the operation result is the same as the expected result, it means that the data to be written was correctly written to memory, and the write memory operation was successful; otherwise, if the operation result is different from the expected result, it means that the data to be written was not correctly written to memory, and the write memory operation failed.
[0074] In the embodiments of the present invention, for the write training command, since it is necessary to verify whether the data to be written is correctly written to memory by reading the written data again, read training can be performed first, and then write training can be performed. This ensures that the actual written data is consistent with the data to be written, based on the reliable reading of the data.
[0075] Whether it is read training or write training, after the first transmit and receive operation is performed, the first transmit and receive operation with the same result as the expected result can be selected from the first transmit and receive operations of each data line as the alternative operation, and the delay scan point corresponding to the alternative operation is the alternative scan point. For example, in one scenario, there are 8 data lines: DL0 (delay scan point is -0.3 nanoseconds), DL1 (delay scan point is -0.2 nanoseconds), DL2 (delay scan point is -0.1 nanoseconds), DL3 (delay scan point is 0 nanoseconds), DL4 (delay scan point is +0.1 nanoseconds), DL5 (delay scan point is +0.2 nanoseconds), DL6 (delay scan point is +0.3 nanoseconds), and DL7 (delay scan point is +0.4 nanoseconds). The first transmit / receive operation results for DL0, DL6, and DL7 differ from the expected results, while the first transmit / receive operation results for the other data lines are the same as expected. Therefore, the first transmit / receive operations for DL1...DL5 are the alternative operations, and the alternative scan points include: -0.2 nanoseconds, -0.1 nanoseconds, 0 nanoseconds, 0.1 nanoseconds, and 0.2 nanoseconds. After obtaining each candidate scanning point, the target delay point can be determined based on the candidate scanning point corresponding to each data line, and the delay parameters of each data line can be set according to the target delay point to obtain the trained data line.
[0076] Specifically, in one embodiment of the present invention, determining the target delay point based on the candidate scan points corresponding to each of the data lines may include: sorting the candidate scan points in chronological order to obtain a candidate sequence; and determining the target delay point based on the candidate scan point located in the middle position of the candidate sequence.
[0077] Taking the aforementioned data lines DL0 to DL7 as an example, the candidate scan points can be arranged in chronological order to obtain a candidate sequence. This candidate sequence could be, for example, -0.2, -0.1, 0, 0.1, 0.2. The candidate scan point in the middle of the candidate sequence is "0". The target delay point can then be determined based on this candidate scan point "0". For instance, the candidate scan point "0" in the middle of the candidate sequence can be determined as the target delay point.
[0078] Furthermore, after obtaining the target delay point, the delay parameters of each data line can be set according to the target delay point to obtain the trained data line. For example, the delay parameters of each data line can be set to the target delay point to obtain the trained data line.
[0079] After reaching the trained data lines, in another embodiment of the present invention, the memory training method provided by the embodiments of the present invention may further include: performing a second transmit / receive operation on the memory particles based on the trained data lines, the second transmit / receive operation including sending data to the memory particles and / or receiving data sent by the memory particles; and detecting whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results. In this way, it is possible to detect whether the delay parameters set in each trained data line can correctly complete the data read / write operations of the memory particles, thereby improving the reliability and success rate of memory training.
[0080] Furthermore, in one embodiment, after detecting whether the operation results of the second transmit / receive operations corresponding to each of the trained data lines are the same as the expected results, the memory training method provided by the embodiments of the present invention may further include: adjusting the delay parameter of the trained data line in response to a difference between the operation result of the second transmit / receive operation corresponding to any one of the trained data lines and the expected result. In this case, since only the operation results of the second transmit / receive operations corresponding to a few trained data lines differ from the expected results, it is only necessary to adjust the delay parameter of the few trained data lines, which can also effectively shorten the memory training time and improve system performance.
[0081] The application of the memory training method provided in the embodiments of the present invention in read training and write training will be described in detail below.
[0082] First, let's introduce reading training.
[0083] The memory controller can determine multiple delay scan points based on the clock cycle and the precision of the delay adjustment supported by the data lines. Then, based on the number of delay scan points and the number of data lines, different delay scan points are configured to the read directions of different data lines, and then all data lines start reading training simultaneously.
[0084] During read training, the memory controller's training module can issue read commands to the memory chip's training module, which in turn can return specific training data via data lines. The memory controller can learn the details of this specific training data through other means and determine whether the corresponding delay parameter configuration on each data line can correctly receive data by judging whether the data received on each data line is correct. Furthermore, the memory controller's training module can quickly derive the delay window that can correctly receive data based on the data reception results at different delay scan points on all data lines, then find the median value of the window and apply it to the read direction of all data lines.
[0085] The following section introduces writing exercises.
[0086] The memory controller can determine multiple delay scan points based on the clock cycle and the precision of the delay adjustment supported by the data lines. Then, based on the number of delay scan points and the number of data lines, different delay scan points are configured to the read directions of different data lines, and then all data lines start writing training simultaneously.
[0087] During write training, the memory controller's training module can issue write commands to the memory chip training module. The memory chip can store the data received from each data line in the training module's buffer. Subsequently, the memory controller's training module can issue read commands, and upon receiving a read command, the memory chip's training module can transmit the data in its buffer through the data lines. The memory controller's training module can receive this data and determine whether the data received on each data line is the same as the transmitted data, thus determining whether the data transmitted by the data line under the specified delay parameter configuration can be correctly received by the memory chip. Furthermore, the memory controller's training module can quickly determine the delay window that can correctly transmit data based on the data transmission results at different delay scan points on all data lines, then find the median value of this delay window and apply it to the write direction of all data lines.
[0088] like Figure 4As shown, taking DDR SDRAM (double data rate synchronous dynamic random access memory) memory training as an example, in one embodiment of the present invention, it is assumed that the clock signal clk and the sampling signal (i.e., the data strobe signal) dqs are already in an ideal alignment state, that is, they flip simultaneously. dq+0 is the ideal alignment state of dq and dqs, that is, when dqs flips, dq is in the middle of the high and low level phases. dq-0.1 means a delay of -0.1 time units, corresponding to a phase shifted to the right of the ideal state phase; dq+0.1 means a delay of +0.1 time units, corresponding to a phase shifted to the left of the ideal state phase. In this embodiment, the data signals on the data lines have 8 different phases, corresponding to 8 different delay scan points, which are configured on 8 data lines respectively. The training module of the memory controller can determine whether the delay scan point can correctly transmit data based on the sampling results of different data lines. For example, in this embodiment, dq-0.3, dq+0.3, and dq+0.4 cannot transmit data correctly during training. Therefore, the delay scan point corresponding to the intermediate value dq+0 of dq-0.2, dq-0.1, dq+0, dq+0.1, and dq+0.2 can be used as the delay parameter of these 8 data lines.
[0089] For example, in another embodiment of the present invention, the memory controller and the memory chip may include 32 data lines DQ, and the delay adjustment accuracy of the memory controller is 1 / 32 of a time unit, which may be, for example, a clock cycle.
[0090] During read training, the memory controller's training module can configure 32 delayed scan points to the read direction of each of the 32 data lines, and all data lines begin read training. Specifically, the memory controller's training module can issue read commands to the memory chip's training module. The memory chip's training module can return pre-set training data via the data lines. The memory controller's training module can receive data via each data line and compare it with the pre-set training data. If they are the same, the delayed scan point corresponding to that data line is recorded as passed; if they are different, it is recorded as a failure. For example, in this example, the delayed scan points used by data lines DQ0, DQ1, DQ2, DQ30, and DQ31 will cause the comparison results between the received data and the pre-set training data to be different, while the delayed scan points used by other data lines will cause the comparison results to be the same. Next, the delay scan points corresponding to the data lines with the same comparison results can be sorted in ascending or descending order, and the delay scan point in the middle can be found. For example, among the multiple delay scan points with delay scan points ranging from 0 / 32 time units to 31 / 32 time units, the delay scan points that successfully transmit data include multiple delay scan points ranging from 3 / 32 time units to 29 / 32 time units, with the middle value being a delay scan point with a delay of 13 / 32 time units. Then, the delay parameter for the read direction of all data lines can be configured to a delay scan point of 13 / 32 time units.
[0091] Similarly, write training can be performed to obtain the delay parameters for all data line write directions, which has been explained in detail above and will not be repeated here.
[0092] The memory training method provided by the embodiments of the present invention will be described in detail below through a specific example.
[0093] like Figure 5 As shown, the memory training method provided in the embodiments of the present invention is applied to a memory controller, and the method may include: S201. Obtain multiple delayed scan points, wherein the delayed scan points are the time points that need to be scanned when the data signal is delayed and adjusted during memory training; S202. Assign the plurality of delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip; In this case, the number of delayed scan points assigned to each data line is greater than 0 and less than the total number of the plurality of delayed scan points, and each of the plurality of delayed scan points is assigned to at least one data line. S203, Issue the memory training command; The memory training commands may include read training commands and / or write training commands; S204. According to the memory training command, perform the first transmit and receive operation based on the delay scan points to which each of the data lines is assigned; The first transmit / receive operation includes: sending data to the memory chip, and / or receiving data sent by the memory chip; S205. From the first transmit and receive operations of each data line, select the first transmit and receive operation whose operation result is the same as the expected result as the alternative operation, and the delayed scan point corresponding to the alternative operation is the alternative scan point. S206. Sort the candidate scanning points in chronological order to obtain a candidate sequence; S207. Determine the target delay point based on the candidate scan point located in the middle position of the candidate sequence.
[0094] S208. Set the delay parameters of each data line according to the target delay point to obtain the trained data lines.
[0095] S209. Based on the trained data line, perform a second transmit / receive operation on the memory chip.
[0096] The second transmit / receive operation includes sending data to the memory chip and / or receiving data sent by the memory chip; S210. Detect whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results.
[0097] S211. In response to the fact that the operation result of the second transmit / receive operation corresponding to any of the trained data lines is different from the expected result, the delay parameter of the trained data line is adjusted.
[0098] Thirdly, such as Figure 6 As shown, embodiments of the present invention also provide a processor 6, which includes a memory controller 5 provided in the embodiments of the present invention. Since the processor 6 includes any of the memory controllers 5 provided in the foregoing embodiments, it can also achieve the corresponding beneficial technical effects, which have been described above and will not be repeated here.
[0099] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0100] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0101] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.
[0102] For ease of description, the above apparatus is described by dividing it into various modules / modules based on their functions. Of course, in implementing this invention, the functions of each module / module can be implemented in one or more software and / or hardware components.
[0103] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0104] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. A memory controller, characterized in that, include: The acquisition module is used to acquire multiple delayed scan points, which are the time points that need to be scanned when adjusting the delay of the data signal during memory training; An allocation module is used to allocate the plurality of delay scan points to each of the data lines according to the number of data lines between the memory controller and the memory chip, so that the number of delay scan points allocated to each of the data lines is greater than 0 and less than the total number of the plurality of delay scan points, and each of the plurality of delay scan points is allocated to at least one of the data lines. The training execution module performs memory training based on the delay scan points to which each of the data lines is assigned.
2. The memory controller according to claim 1, characterized in that, The difference in the number of delayed scan points assigned to any two of the data lines is less than 2.
3. The memory controller according to claim 1, characterized in that, The number of delayed scan points assigned to each of the data lines is equal to the number of each other.
4. The memory controller according to any one of claims 1 to 3, characterized in that, The training execution module includes: The command issuing submodule is used to issue memory training commands, which include read training commands and / or write training commands. The first transceiver submodule is used to perform a first transceiver operation based on the delay scan points to which each of the data lines is assigned, according to the memory training command. The first transceiver operation includes: sending data to the memory granules and / or receiving data sent by the memory granules. The selection submodule is used to select, from the first transmit and receive operations of each data line, the first transmit and receive operation whose operation result is the same as the expected result as the candidate operation, and the delay scan point corresponding to the candidate operation is the candidate scan point. The determination submodule is used to determine the target delay point based on the candidate scan points corresponding to each of the data lines; The setting submodule is used to set the delay parameters of each data line according to the target delay point to obtain the trained data lines.
5. The memory controller according to claim 4, characterized in that, The determining submodule is specifically used for: The candidate scanning points are sorted in chronological order to obtain the candidate sequence; The target delay point is determined based on the candidate scan point located in the middle of the candidate sequence.
6. The memory controller according to claim 4, characterized in that, The training execution module also includes: The second transceiver submodule is used to perform a second transceiver operation on the memory particle based on the trained data line after setting the delay parameters of each data line according to the target delay point. The second transceiver operation includes sending data to the memory particle and / or receiving data sent by the memory particle. The detection submodule is used to detect whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results.
7. The memory controller according to claim 6, characterized in that, The training execution module further includes an adjustment submodule, which is used to adjust the delay parameter of the trained data line in response to a difference between the operation result of the second transmit / receive operation corresponding to any one of the trained data lines and the expected result after the detection submodule detects whether the operation result of the second transmit / receive operation corresponding to each of the trained data lines is the same as the expected result.
8. The memory controller according to any one of claims 1 to 3, characterized in that, The ratio of the difference in length between any two data lines between the memory controller and the memory chip to the length of the longer data line is less than a preset threshold.
9. A memory training method, characterized in that, Applied to a memory controller, the method includes: Multiple delayed scan points are obtained, which are the time points that need to be scanned when adjusting the delay of the data signal during memory training; Based on the number of data lines between the memory controller and the memory chip, the plurality of delay scan points are assigned to each of the data lines, such that the number of delay scan points assigned to each of the data lines is greater than 0 and less than the total number of the plurality of delay scan points, and each of the plurality of delay scan points is assigned to at least one of the data lines. Memory training is performed based on the delay scan points to which each of the data lines is assigned.
10. The method according to claim 9, characterized in that, The memory training based on the delayed scan points assigned to each of the data lines includes: Issue a memory training command, which includes a read training command and / or a write training command; According to the memory training command, a first transmit / receive operation is performed based on the delay scan point to which each of the data lines is assigned. The first transmit / receive operation includes: sending data to the memory chip and / or receiving data sent by the memory chip. From the first transmit and receive operations of each of the data lines, the first transmit and receive operation whose operation result is the same as the expected result is selected as the alternative operation, and the delayed scan point corresponding to the alternative operation is the alternative scan point. The target delay point is determined based on the candidate scan points corresponding to each of the data lines. The delay parameters of each data line are set according to the target delay point to obtain the trained data lines.
11. The method according to claim 10, characterized in that, The step of determining the target delay point based on the candidate scan points corresponding to each of the data lines includes: The candidate scanning points are sorted in chronological order to obtain the candidate sequence; The target delay point is determined based on the candidate scan point located in the middle of the candidate sequence.
12. The method according to claim 10, characterized in that, After setting the delay parameters of each data line according to the target delay point, the method further includes: Based on the trained data line, a second transmit / receive operation is performed on the memory chip, the second transmit / receive operation including sending data to the memory chip and / or receiving data sent by the memory chip; Check whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results.
13. The method according to claim 12, characterized in that, After detecting whether the operation results of the second transmit / receive operation corresponding to each of the trained data lines are the same as the expected results, the method further includes: In response to a difference between the operational result of the second transmit / receive operation corresponding to any of the trained data lines and the expected result, the delay parameter of the trained data line is adjusted.
14. The method according to any one of claims 9, characterized in that, The ratio of the difference in length between any two data lines between the memory controller and the memory chip to the length of the longer data line is less than a preset threshold.
15. A processor, characterized in that, The processor includes the memory controller according to any one of claims 1 to 8.