A cross-coupled floating gate type memory-compute integrated cell and memory-compute array

Abstract

The application discloses a cross-coupled floating gate type memory and computing integrated unit and a memory and computing array, and belongs to the technical field of semiconductors. Each cross-coupled floating gate type memory and computing integrated unit comprises two coupled read-write subunits arranged in conjugation and a write switch tube, the memory and computing integrated unit stores electronic information through a silicon substrate depletion region, compared with a traditional eDRAM device gate storage charge mode, the structure of the depletion region storing weights has no leakage between gate capacitance and a PN junction, and the weight maintenance capacity is more than one order of magnitude stronger than that of a traditional 2T 1C type eDRAM. In addition, the cross-coupled memory and computing integrated device provided by the application can calibrate the inconsistency caused by the process deviation of the floating gate transistor, so that the precision of the memory and computing unit is higher due to the floating gate structure, and these characteristics make it possible for some applications requiring large-scale volatile memory and computing array deployment.

Description

TECHNICAL FIELD

[0001] The application relates to a cross-coupled floating gate type memory-computing integrated unit and memory-computing array, and belongs to the technical field of semiconductors. BACKGROUND

[0002] The Von Neumann architecture has made a great contribution to the development of various types of hardware in the computer field, but its memory-computing separation feature makes the memory operation more time-consuming and energy-consuming than data processing when the computer performs a massive data computing task. In particular, in the scene of convolutional neural network, large language model computing and other scenes requiring a large number of matrix-vector multiplications, not only do the classic architecture need to deploy tens of thousands of transistors as computing cores in the processor to compute and process data, but also a large amount of energy and delay is consumed to move the data to be computed from the memory to the processor, which greatly affects the energy efficiency of processing such algorithms under the classic architecture.

[0003] In order to solve the bottleneck of the above-mentioned power wall and memory wall, people have proposed memory-computing integrated devices and in-memory computing schemes. The feature of the scheme is that the weight values to be computed can be stored in the memory-computing array composed of memory-computing units, and the pure analog accumulation method can deploy a small number of memory-computing units to complete the matrix-vector multiplication locally at a higher speed. This local computing method can greatly reduce the power waste and delay caused by data movement, effectively solving the problems of memory wall and power wall.

[0004] The memory-computing integrated scheme can be divided into non-volatile memory-computing and volatile memory-computing according to the storage medium. The main difference between the two is whether the weight information in the device can be quickly erased and written, and whether the weight will be lost after power failure. They are respectively suitable for different use scenarios. Non-volatile memory-computing mainly processes the weights that do not need to change in the network, while volatile memory-computing corresponds to the calculation of some weights that need to change quickly in the network, such as the matrix multiplication of two constantly changing matrices in the self-attention mechanism calculation of large language models. At this time, volatile memory-computing is more suitable.

[0005] At present, the main medium of volatile memory-computing is SRAM and eDRAM. SRAM is suitable for pure digital schemes, and the size of a single device is more than 100F 2 , which restricts the parallelism and scale; while eDRAM devices can be used for analog domain computing, but the area of eDRAM devices also reaches 40F 2 , which is not small for large-scale integration requirements. Moreover, the weight maintenance capability of the device is in the order of milliseconds, and if the array size is too large, the refresh of the device weight becomes a problem. It can be seen that both SRAM and eDRAM devices are not suitable for scenes such as large language model algorithms that require the deployment of a super large scale memory-computing array. At present, a volatile memory-computing integrated unit that meets the requirements of high precision and high storage density in pure analog computing is needed. SUMMARY

[0006] In order to solve the existing problems, the application provides a cross-coupled floating gate type memory and computing integrated unit, which is used as an eDRAM volatile memory and computing integrated unit, and the cross-coupled structure enables the structure in the memory and computing integration to realize maximum reuse, and realizes high weight retention capability and small size of the volatile memory and computing integrated medium.

[0007] The first object of the application is to provide a cross-coupled floating gate type memory and computing integrated unit, which comprises a first coupled read-write subunit, a second coupled read-write subunit and a write switch tube, all formed on the same substrate, and the first coupled read-write subunit and the second coupled read-write subunit are symmetrically arranged on both sides of the write switch tube.

[0008] Optionally, the first coupled read-write subunit and the second coupled read-write subunit have the same structure.

[0009] The first coupled read-write subunit comprises a first write drain, a first write source and a first gate structure, a first shallow trench isolation layer is arranged in the substrate area corresponding to the first gate structure, the first coupled read-write subunit is isolated by the first shallow trench isolation layer to form a first charge coupled tube and a first read-write tube, the first charge coupled tube and the first read-write tube share the first gate structure, and the first charge coupled tube does not have a source and a drain; the first gate structure comprises a substrate, a bottom dielectric layer, a first floating gate, a first top dielectric layer and a first control gate from bottom to top.

[0010] Correspondingly, the second coupled read-write subunit comprises a second write drain, a second write source and a second gate structure, a second shallow trench isolation layer is arranged in the substrate area corresponding to the second gate structure, the second coupled read-write subunit is isolated by the second shallow trench isolation layer to form a second charge coupled tube and a second read-write tube, the second charge coupled tube and the second read-write tube share the second gate structure, and the second charge coupled tube does not have a source and a drain; the second gate structure comprises a substrate, a bottom dielectric layer, a second floating gate, a second top dielectric layer and a second control gate from bottom to top.

[0011] Optionally, the write switch tube comprises a substrate, a bottom dielectric layer, a third floating gate, a third top dielectric layer and a third control gate from bottom to top; a third shallow trench isolation layer is arranged in the substrate area corresponding to the write switch tube, which is used to isolate two paths formed by the two coupled read-write subunits arranged symmetrically, so as to avoid short circuit during writing.

[0012] Optionally, the first read-write tube is used to read out the number of collected electrons in the first charge-coupled tube substrate, and write the number of electrons into the second charge-coupled tube substrate under the control of the write switch tube through the first write drain, and the second charge-coupled tube collects electrons and reads out the electronic information through the second read-write tube, and the second read-write tube writes the number of electrons into the first charge-coupled tube through the second write drain under the control of the write switch tube.

[0013] Optionally, the first read-write tube is on the same side as the second charge-coupled tube, and the first read-write tube is on the same side as the first charge-coupled tube, so that the first write drain is connected to the second charge-coupled tube through the write switch tube when the write switch tube is turned on, and the second write drain is connected to the first charge-coupled tube through the write switch tube.

[0014] Optionally, the substrate is P-type or N-type; the first write drain, the first write source, the second write drain, and the second write source are N-type or P-type.

[0015] Optionally, the first floating gate, the second floating gate, the third floating gate, the first control gate, the second control gate, and the third control gate are N-type polysilicon, P-type polysilicon, or metal; the bottom dielectric layer, the first top dielectric layer, the second top dielectric layer, the third top dielectric layer, the first shallow trench isolation layer, the second shallow trench isolation layer, and the third shallow trench isolation layer 304 are silicon dioxide or silicon nitride, or a combination thereof.

[0016] The second object of the present application is to provide a storage and calculation array composed of m×n cross-coupled floating gate type storage and calculation integrated units, the first write drain and the second write drain of the storage and calculation integrated units in the same column are connected to form bit line one and bit line two respectively, the first write source and the second write source of the storage and calculation integrated units in the same column are connected to form source line one and source line two respectively, the first control gate and the second control gate of the storage and calculation integrated units in the same row are connected to form word line one and word line two respectively, and the third control gate of the storage and calculation integrated units in the same row is connected to form a write word line.

[0017] The third object of the present application is to provide a readout and write method of the above cross-coupled floating gate type storage and calculation integrated unit, during writing, a positive bias voltage is applied between the first control gate and the substrate and between the second control gate and the substrate to generate a depletion region below the first and second charge-coupled tubes, the write switch tube is turned on, at this time, a weight voltage is applied to the first write drain and the second write drain respectively, the size of the weight voltage represents the weight information to be written into the second charge-coupled tube and the first charge-coupled tube, at this time, the depletion regions below the first charge-coupled tube and the second charge-coupled tube store a corresponding number of electrons, and different numbers of electrons will affect the potential on the first floating gate and the second floating gate to different degrees, then the second write switch tube is turned off, and the write operation is completed.

[0018] In the read operation, a positive voltage is applied to the first control gate or the second control gate of the cross-coupled floating gate type memory and calculation integrated unit, and a bias voltage is applied between the first write drain and the first write source, and between the write drain and the second write source, the current value read by the first electronic read-write tube reflects the number of stored electrons in the depletion region of the first charge coupled tube, and the current value read by the second electronic read-write tube reflects the number of stored electrons in the depletion region of the second charge coupled tube, and the read operation is completed.

[0019] A fourth object of the present application is to provide a calibration method for the cross-coupled floating gate type memory and calculation integrated unit described above, the method comprising:

[0020] A strong electric field is applied between the first write drain / second write drain and the first write source / second write source, and a positive voltage is applied to the first control gate / second control gate, so that a transverse electric field along the channel direction and a longitudinal electric field from the corresponding floating gate to the substrate are generated in the first read-write tube / second read-write tube, and electrons gain energy through the electric field to enter the corresponding floating gate, thereby increasing the initial threshold voltage of the first read-write tube / second read-write tube;

[0021] A positive voltage is applied to the first control gate / second control gate, and the first write drain / second write drain and the first write source / second write source are at low potential, generating a strong electric field from the corresponding floating gate to the substrate direction, and electrons enter the corresponding floating gate through tunneling, thereby increasing the initial threshold voltage of the first read-write tube / second read-write tube; a negative voltage is applied to the first control gate / second control gate, generating an electric field from the substrate to the corresponding floating gate, and the electrons in the corresponding floating gate pass out of the corresponding floating gate through the tunneling effect, thereby reducing the initial threshold voltage of the first read-write tube / second read-write tube.

[0022] The present application has the following advantages:

[0023] The cross-coupled floating gate type memory and calculation integrated unit provided by the present application stores electronic information in the depletion region of the silicon substrate, compared with the traditional eDRAM device which stores charges in the gate, the structure of the depletion region storing weights does not have leakage between the gate capacitance and the PN junction, and the weight maintenance capability is more than one order of magnitude stronger than the traditional 2T 1C eDRAM, in addition, the cross-coupled memory and calculation integrated device provided by the present application has a floating gate structure, which can calibrate the inconsistency caused by process deviation by erasing and writing electrons in the floating gate transistor, so that the accuracy of the memory and calculation unit is higher, and these characteristics make it possible for some applications that require large-scale volatile memory and calculation array deployment.

[0024] The existing memory and calculation array is usually written by row or by column, and the weight of a row or a column of units is written at a time, while the memory and calculation array composed of the cross-coupled memory and calculation integrated unit provided by the present application can write two rows of devices at the same time during writing, and the writing speed is doubled compared with the traditional scheme. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a top view of a cross-coupled floating gate type in-memory computing unit provided in one embodiment of the present invention;

[0027] Figure 2 This is a cross-sectional view of an in-memory computing unit along the X direction provided in an embodiment of the present invention;

[0028] Figure 3 This is a cross-sectional view of a memory computing unit along the Y direction provided in an embodiment of the present invention;

[0029] Figure 4 This is a cross-sectional view of an in-memory computing unit along the Z direction provided in an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of a local layout method that can be reused when in-memory computing units are composed of a large-scale array, according to an embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of a method for writing 2×N weights in a single operation to an M×N scale in-memory computing unit array, according to an embodiment of the present invention.

[0032] Wherein, 100-first coupled read / write subunit, 200-second coupled read / write subunit, 300-write switch, 101-first write drain, 102-first write source, 110-first gate structure, 201-second write drain, 202-second write source, 210-second gate structure;

[0033] 111-First floating gate, 112-First top dielectric layer, 113-First control gate; 203-Second charge-coupled diode for collecting electrons depletion region, 211-Second floating gate, 212-Second top dielectric layer, 213-Second control gate; 301-Third floating gate, 302-Third top dielectric layer, 303-Third control gate; 400-Substrate, 500-Bottom dielectric layer;

[0034] 204 - Second shallow trench isolation layer; 304 - Third shallow trench isolation layer;

[0035] 1000 - First dashed box, 2000 - Second dashed box, 3000 - Third dashed box. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

[0037] Example 1

[0038] This embodiment provides a cross-coupled floating-gate type in-memory computing unit and corresponding read and write methods, such as Figure 1 As shown, the cross-coupled floating gate type in-memory computing unit includes a first coupled read / write subunit 100, a second coupled read / write subunit 200, and a write switch transistor 300. The three are formed on the same substrate 400, and the first coupled read / write subunit 100 and the second coupled read / write subunit 200 are conjugately disposed on both sides of the write switch transistor 300.

[0039] See Figure 1 , Figure 1 This is a top view of the in-memory computing unit. A first shallow trench isolation layer is provided in the substrate 400 region corresponding to the first gate structure 110. The first coupled read / write subunit 100 is isolated through the first shallow trench isolation layer to form a first charge-coupled transistor (CCT) and a first read / write transistor. The first CCT and the first read / write transistor share the first gate structure 110. The first CCT does not have a source or drain. Correspondingly, a second shallow trench isolation layer is provided in the substrate 400 region corresponding to the second gate structure 210. The second coupled read / write subunit 200 is isolated through the second shallow trench isolation layer to form a second CCT and a second read / write transistor. The second CCT and the second read / write transistor share the second gate structure 210. The second CCT does not have a source or drain.

[0040] As shown above, the in-memory computing unit is composed of a first charge-coupled transistor, a first read / write transistor, a second charge-coupled transistor, a second read / write transistor, a write switch transistor, and a substrate that cannot be directly observed in the top view.

[0041] Figure 2 This is a cross-sectional view of the in-memory computing unit along the direction of the first read / write transistor - write switch transistor - second charge-coupled transistor. Figure 1 (Central X-direction section), i.e. Figure 2 The image shows the morphology of the first read / write transistor and write switch transistor 300 in the first coupled read / write subunit 100, and the second charge-coupled transistor in the second coupled read / write subunit 200 in this cross-section. This is for ease of understanding. Figure 2 Each part is outlined by a first dashed box 1000, a third dashed box 3000, and a second dashed box 2000.

[0042] The first dashed box 1000 shows the profile of the first read-write tube under the cross section; the second dashed box 2000 shows the profile of the second charge-coupled tube under the cross section; and the third dashed box 3000 shows the profile of the write switch tube under the cross section.

[0043] Figure 3 The cross section of the cross-coupled floating gate type memory-computing unit along the X direction is shown in FIG. 1. Figure 1 The cross section of the cross-coupled floating gate type memory-computing unit along the Y direction is shown in FIG. 2. Figure 3 The second shallow trench isolation layer 204 separates the second charge-coupled tube and the second read-write tube. As can be seen, the floating gate and the control gate are shared by the charge-coupled tube and the read-write tube. The number of electrons collected in the depletion region of the charge-coupled tube will change the potential in the floating gate, thereby affecting the threshold voltage of the read-write tube.

[0044] Figure 4 The cross section of the cross-coupled floating gate type memory-computing unit along the Z direction is shown in FIG. 3. Figure 1 The cross section of the cross-coupled floating gate type memory-computing unit along the Z direction is shown in FIG. 3. Figure 4 The third shallow trench isolation layer 304 under the write switch tube is used to isolate the two paths of the first drain-write switch tube-second charge-coupled region depletion layer and the second drain-write switch tube-first charge-coupled region depletion layer, thereby avoiding short circuit during writing. In essence, it can be connected with the shallow trench isolation layer used to isolate the charge-coupled tube and the read-write tube to form the same insulating layer.

[0045] The method for reading and writing the cross-coupled floating gate type memory-computing unit includes:

[0046] During writing, a positive bias voltage is applied between the first control gate 113 and the substrate 400 and between the second control gate 213 and the substrate 400, so as to generate a depletion region under the first and second charge-coupled tubes, and the write switch tube 300 is turned on. At this time, a weight voltage is applied to the first write drain 101 and the second write drain 201, respectively. The size of the weight voltage represents the weight information to be written into the second charge-coupled tube and the first charge-coupled tube. At this time, the depletion regions under the first and second charge-coupled tubes store a corresponding number of electrons, and different numbers of electrons will affect the potential on the first floating gate 111 and the second floating gate 211 to different degrees. Subsequently, the second write switch tube is turned off, and the writing operation is completed.

[0047] During reading, a positive voltage is applied to the first control gate 113 or the second control gate 213 of the cross-coupled floating gate type memory-computing unit, and a bias voltage is applied between the first write drain 101 and the first write source 102 and between the second write drain 201 and the second write source 202. The current value read by the first electron read-write tube will reflect the number of electrons stored in the depletion region of the first charge-coupled tube, and the current value read by the second electron read-write tube will reflect the number of electrons stored in the depletion region of the second charge-coupled tube. The reading operation is completed.

[0048] Embodiment Two

[0049] The embodiment provides an array composed of cross-coupled floating gate type memory-computing integrated units, as shown in Figure 5 , Figure 5 A local layout method which can be repeatedly reused when integrating a large-scale array is shown, wherein arrows represent the direction of weight value writing, and it can be seen that the gate structure of the write switch tube of the memory-computing integrated unit in the same row can be shared, and the first source / second source structure of the memory-computing integrated unit in the same column can be shared, and such a structure can further reduce the size of the array composed of memory-computing integrated units.

[0050] The first drain and the second drain of the memory-computing integrated unit in the same column are connected to form a bit line one (BL1) and a bit line two (BL2), respectively, the first source and the second source of the memory-computing integrated unit in the same column are connected to form a source line one (SL1) and a source line two (SL2), respectively, the first control gate and the second control gate of the memory-computing integrated unit in the same row are connected to form a word line one (WL1) and a word line two (WL2), respectively, and the third control gate of the memory-computing integrated unit in the same row is connected to form a write word line (WWL).

[0051] When performing a programming operation, 0V is applied to the write word line WWL of the whole chip, 5V is applied to the word line corresponding to the read-write tube to be programmed, 0V is applied to the unselected word line, 3V is applied to the bit line corresponding to the read-write tube to be programmed, 0V is applied to the source line, and 0V is applied to the unselected bit line, at this time, channel hot electron programming occurs in the selected read-write tube, the threshold voltage of the read-out tube increases, and programming does not occur in other read-write tubes.

[0052] When performing an array erasing operation, 0V is applied to the write word line WWL of the whole chip, -10V is applied to all word lines, and 0V is applied to the bit line, the source line and the substrate, at this time, FN tunneling occurs in all read-write tubes of the whole array, electrons pass out from the floating gate, and the threshold voltage of the read-out tube decreases.

[0053] When performing array writing, 3V is applied to the write word line WWL corresponding to the unit to be written, so that all write switch tubes in the row are turned on, at this time, the voltage of all bit line one BL1 and bit line two BL2 in the row is applied, and the voltage value is the weight value to be written of the corresponding first charge-coupled tube and second charge-coupled tube, after the application is completed, the write word line WWL of the row is set to 0V, the writing of the row is completed, and then the write word line WWL of other rows is turned on to perform the above operation until the array writing is completed. When performing array-level writing in a traditional memory-computing array, the method is to write by row or by column, and the weight value of a row unit or a column unit is written at a time, and when the cross-coupled floating gate type memory-computing integrated unit array provided by the present application is used, two rows of devices can be written at the same time, and the writing speed is doubled compared with the traditional scheme.

[0054] The embodiment provides an array composed of cross-coupled floating gate type memory-computing integrated units, as shown in Figure 6 , Figure 6It is shown that when the integrated large-scale array is opened, the write word line WWL<0> is opened, and the corresponding unit write voltage is applied to the bit line one BL1<0:n> and the bit line two BL2<0:n> at the same time, the scene of writing the storage weight of the first row of storage-computing integrated units can be written, and since the single storage-computing integrated unit provided by the application has two storage nodes, it is equivalent to the write amount of two rows of traditional storage-computing integrated units, so the write speed can be doubled compared with the traditional scheme. When reading out or calculating, the read-write tube corresponding to the word line to be read out or calculated is applied with a read-out voltage 3V, and a read-out source-drain voltage difference 0.2V is applied on the corresponding source and drain, at this time, the current flowing out of the read-write tube represents the weight information stored by the charge-coupled tube thereof, and the current in the same column can be simulated and accumulated by the parallel connection relationship of different read-write tubes, so as to complete the calculation.

[0055] Some steps in the embodiments of the application can be realized by software, and the corresponding software program can be stored in a readable storage medium, such as an optical disc or a hard disk.

[0056] The above description is only the preferred embodiment of the application, and is not intended to limit the application, and any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A cross-coupled floating gate type in-memory computing unit, characterized in that, The first coupling read-write subunit (100), the second coupling read-write subunit (200) and the write switch tube (300) are formed on the same substrate (400), and the first coupling read-write subunit (100) and the second coupling read-write subunit (200) are symmetrically arranged on both sides of the write switch tube (300); The first coupling read-write subunit (100) and the second coupling read-write subunit (200) are of the same structure; The first coupling read-write subunit (100) comprises a first write drain (101), a first write source (102) and a first gate structure (110), the first gate structure (110) is provided with a first shallow trench isolation layer in the corresponding substrate (400) region, the first coupling read-write subunit (100) is isolated by the first shallow trench isolation layer to form a first charge coupling tube and a first read-write tube, the first charge coupling tube and the first read-write tube share the first gate structure (110), and the first charge coupling tube is not provided with a source and a drain; the first gate structure (110) comprises, from bottom to top, a substrate (400), a bottom dielectric layer (500), a first floating gate (111), a first top dielectric layer (112) and a first control gate (113); Correspondingly, the second coupling read-write subunit (200) comprises a second write drain (201), a second write source (202) and a second gate structure (210), the second gate structure (210) is provided with a second shallow trench isolation layer in the corresponding substrate (400) region, the second coupling read-write subunit (200) is isolated by the second shallow trench isolation layer to form a second charge coupling tube and a second read-write tube, the second charge coupling tube and the second read-write tube share the second gate structure (210), and the second charge coupling tube is not provided with a source and a drain; the second gate structure (210) comprises, from bottom to top, a substrate (400), a bottom dielectric layer (500), a second floating gate (211), a second top dielectric layer (212) and a second control gate (213); The write switch tube (300) comprises, from bottom to top, a substrate (400), a bottom dielectric layer (500), a third floating gate (301), a third top dielectric layer (302) and a third control gate (303); the write switch tube (300) is provided with a third shallow trench isolation layer (304) in the corresponding substrate (400) region, which is used for isolating two paths formed by the two coupling read-write subunits symmetrically arranged to avoid short circuit during writing. 2.The cross-coupled floating gate type compute-in-memory cell of claim 1, wherein, The first read-write tube is used for reading out the information of the number of electrons collected in the first charge coupling tube substrate, and writing the information of the number of electrons into the second charge coupling tube substrate under the control of the write switch tube (300) through the first write drain (101); after the second coupling tube collects electrons, the information of the number of electrons is read out through the second read-write tube, and the second read-write tube writes the information of the number of electrons into the first charge coupling tube through the second write drain (201) under the control of the write switch tube (300). 3.The cross-coupled floating gate type compute-in-memory cell of claim 2, wherein, The first read-write tube is on the same side as the second charge-coupled tube, and the first read-write tube is on the same side as the first charge-coupled tube, so that the first write drain (101) is connected to the second charge-coupled tube through the write switch tube (300) after the write switch tube (300) is turned on, and the second write drain (201) is connected to the first charge-coupled tube through the write switch tube (300).

4. The cross-coupled floating-gate type compute-in-memory cell of claim 3, wherein, The substrate (400) is P-type or N-type; the first write drain (101), the first write source (102), the second write drain (201), and the second write source (202) are N-type or P-type.

5. The cross-coupled floating-gate type compute-in-memory cell of claim 4, wherein, The first floating gate (111), the second floating gate (211), the third floating gate (301), the first control gate (113), the second control gate (213), and the third control gate (303) are N-type polysilicon, P-type polysilicon, or metal; the bottom dielectric layer (500), the first top dielectric layer (112), the second top dielectric layer (212), the third top dielectric layer (302), the first shallow trench isolation layer, the second shallow trench isolation layer (204), and the third shallow trench isolation layer (304) are silicon dioxide or silicon nitride, or a combination thereof.

6. A compute-in-memory array comprising: The memory and computing array is composed of m*n cross-coupled floating gate type memory and computing integrated units according to any one of claims 1-5, the first write drain (101) and the second write drain (201) of the memory and computing integrated units in the same column are connected to form bit line one and bit line two respectively, the first write source (102) and the second write source (202) of the memory and computing integrated units in the same column are connected to form source line one and source line two respectively, the first control gate (113) and the second control gate (213) of the memory and computing integrated units in the same row are connected to form word line one and word line two respectively, and the third control gate (303) of the memory and computing integrated units in the same row is connected to form a write word line.

7. A readout and write method of the cross-coupled floating gate type memory and computing integrated cell according to any one of claims 1 to 5, characterized in that, During writing, a positive bias voltage is applied between the first control gate (113) and the substrate (400) and between the second control gate (213) and the substrate (400) to generate a depletion region below the first and second charge-coupled tubes, and the write switch tube (300) is turned on, at which time a weight voltage is applied to the first write drain (101) and the second write drain (201), the size of the weight voltage representing the weight information to be written into the second charge-coupled tube and the first charge-coupled tube, at which time the depletion region below the first charge-coupled tube and the second charge-coupled tube stores a corresponding number of electrons, and different numbers of electrons will affect the potential on the first floating gate (111) and the second floating gate (211) to different degrees, and then the second write switch tube is turned off, and the writing operation is completed. When reading, a positive voltage is applied to the first control gate (113) or the second control gate (213) of the cross-coupled floating gate type memory and computing integrated cell, and a bias voltage is applied between the first write drain (101) and the first write source (102), and between the second write drain (201) and the second write source (202), the current value read by the first electronic read-write tube reflects the number of electrons stored in the first charge-coupled tube depletion region, and the current value read by the second electronic read-write tube reflects the number of electrons stored in the second charge-coupled tube depletion region, and the reading operation is completed.

8. A method of calibrating the cross-coupled floating gate type compute-in-memory cell of any one of claims 1-5, wherein, The method comprises: A strong electric field is applied between the first write drain (101) / second write drain (201) and the first write source (102) / second write source (202), and a positive voltage is applied to the first control gate (113) / second control gate (213), so that a transverse electric field along the channel direction and a longitudinal electric field from the corresponding floating gate to the substrate (400) are generated in the first read-write tube / second read-write tube, and electrons enter the corresponding floating gate by obtaining energy through the electric field, thereby increasing the initial threshold voltage of the first read-write tube / second read-write tube; A positive voltage is applied to the first control gate (113) / second control gate (213), and the first write drain (101) / second write drain (201) and the first write source (102) / second write source (202) are at low potential, generating a strong electric field from the corresponding floating gate to the substrate (400), and electrons enter the corresponding floating gate by tunneling, thereby increasing the initial threshold voltage of the first read-write tube / second read-write tube; a negative voltage is applied to the first control gate (113) / second control gate (213), generating an electric field from the substrate (400) to the corresponding floating gate, and the electrons in the corresponding floating gate are out of the corresponding floating gate by tunneling effect, thereby reducing the initial threshold voltage of the first read-write tube / second read-write tube.

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