Programming method of memory, memory and memory system

Abstract

The application of the invention is a divisional application of Chinese application 202210187020.9. The invention provides a programming method of a memory, the memory and a memory system, and relates to the technical field of storage. The method comprises the steps of applying a first programming voltage to a selected word line with a first pulse width in a first pulse stage of programming a selected memory unit; and in a second pulse stage for programming the selected memory unit, applying a second programming voltage to the selected word line with a second pulse width. Different pulse bandwidths are adopted in different pulse stages in the programming process, the corresponding pulse bandwidths are adopted for programming according to programming voltages of the pulse stages, and when the programming voltages are low, the long pulse bandwidths can be adopted, and enough programming duration is guaranteed; and when the programming voltage is relatively high, a relatively short pulse bandwidth is adopted, so that the supplementary potential is improved, and the loss caused by programming voltage interference is reduced.

Description

[0001] This application is a divisional application of Chinese patent application filed on February 28, 2022, with application number 202210187020.9 and entitled "Programming method for memory, memory and storage system". Technical Field

[0002] This application relates to the field of storage technology, and in particular to a programming method for a memory, a memory, and a storage system. Background Technology

[0003] Three-dimensional (3D) memory typically comprises multiple arrays of memory strings, each containing multiple memory cells connected in series. When programming (i.e., writing data) a selected memory cell, a programming voltage is applied to the selected word line (WL) connected to that cell, causing electrons in the cell's channel to tunnel to the floating gate.

[0004] The programming process is implemented through Increment Step Pulse Program (ISPP), in which a programming voltage of a certain pulse width is applied in each pulse stage of ISPP for programming.

[0005] However, when the pulse width of the pulse phase in ISPP is large, it will reduce programming efficiency and affect the programming speed of the memory when the programming voltage is high. Summary of the Invention

[0006] This application provides a method for programming a memory, a memory, and a storage system, which can improve programming efficiency. The technical solution is as follows:

[0007] On the one hand, a method for programming a memory is provided, the method comprising:

[0008] During the first pulse phase, a first programming voltage is applied to the selected word line with a first pulse width;

[0009] During the second pulse phase, a second programming voltage is applied to the selected word line with a second pulse width;

[0010] The first pulse phase and the second pulse phase are two of a plurality of pulse phases for programming a selected memory cell, the selected memory cell is the memory cell to be programmed, and the selected word line is the word line connected to the selected memory cell;

[0011] The selected memory cell is programmed using a step-pulse voltage programming method. The first pulse phase precedes the second pulse phase in timing, the width of the first pulse is greater than the width of the second pulse, and the first programming voltage is less than the second programming voltage.

[0012] In an optional embodiment, the plurality of pulse phases are divided into a first programming phase and a second programming phase;

[0013] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage.

[0014] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0015] In an optional embodiment, the first programming stage includes a first number of pulse stages arranged in succession, and the second programming stage includes a second number of pulse stages arranged in succession.

[0016] or,

[0017] In the first programming stage, the programming voltage of each pulse stage is less than the stage voltage threshold, and in the second programming stage, the programming voltage of each pulse stage is greater than the stage voltage threshold.

[0018] In an optional embodiment, the pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0019] In an optional embodiment, the first programming voltage corresponds to a first initial programming voltage at the beginning of the first pulse phase, the first programming voltage corresponds to a first termination programming voltage at the end of the first pulse phase, and the first initial programming voltage is less than the first termination programming voltage.

[0020] The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase, and the second programming voltage corresponds to the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

[0021] In an optional embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0022] The difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference;

[0023] The first pressure difference is greater than the second pressure difference.

[0024] In an optional embodiment, the first programming voltage increases in a stepwise manner during the first pulse phase and the second programming voltage increases in a stepwise manner during the second pulse phase.

[0025] or,

[0026] Both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse phase;

[0027] or,

[0028] The first programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the first pulse phase, and the second programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the second pulse phase.

[0029] In an optional embodiment, the method further includes:

[0030] During the third pulse phase, a third programming voltage is applied to the selected word line with a third pulse width;

[0031] The second pulse phase precedes the third pulse phase in timing, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0032] On the other hand, a memory is provided, the memory comprising: a memory array unit and a peripheral logic unit, the peripheral logic unit including a control circuit;

[0033] The control circuit is configured to apply a first programming voltage to a selected word line with a first pulse width during a first pulse phase, and to apply a second programming voltage to the selected word line with a second pulse width during a second pulse phase.

[0034] The first pulse phase and the second pulse phase are two of a plurality of pulse phases for programming a selected memory cell, the selected memory cell is the memory cell to be programmed, and the selected word line is the word line connected to the selected memory cell;

[0035] The selected memory cell is programmed using a step-pulse voltage programming method. The first pulse phase precedes the second pulse phase in timing, the width of the first pulse is greater than the width of the second pulse, and the first programming voltage is less than the second programming voltage.

[0036] In an optional embodiment, the plurality of pulse phases are divided into a first programming phase and a second programming phase;

[0037] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage.

[0038] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0039] In an optional embodiment, the first programming stage includes a first number of pulse stages arranged in succession, and the second programming stage includes a second number of pulse stages arranged in succession.

[0040] or,

[0041] In the first programming stage, the programming voltage of each pulse stage is less than the stage voltage threshold, and in the second programming stage, the programming voltage of each pulse stage is greater than the stage voltage threshold.

[0042] In an optional embodiment, the pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0043] In an optional embodiment, the first programming voltage corresponds to a first initial programming voltage at the beginning of the first pulse phase, the first programming voltage corresponds to a first termination programming voltage at the end of the first pulse phase, and the first initial programming voltage is less than the first termination programming voltage.

[0044] The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase, and the second programming voltage corresponds to the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

[0045] In an optional embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0046] The difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference;

[0047] The first pressure difference is greater than the second pressure difference.

[0048] In an optional embodiment, the first programming voltage increases in a stepwise manner during the first pulse phase and the second programming voltage increases in a stepwise manner during the second pulse phase.

[0049] or,

[0050] Both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse phase;

[0051] or,

[0052] The first programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the first pulse phase, and the second programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the second pulse phase.

[0053] In an optional embodiment, the control circuitry is further configured to apply a third programming voltage to the selected word line with a third pulse width during the third pulse phase;

[0054] The second pulse phase precedes the third pulse phase in timing, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0055] On the other hand, a storage system is provided, the storage system comprising:

[0056] One or more memories as described in the above embodiments, and,

[0057] A memory controller coupled to the memory and configured to control the memory.

[0058] On the other hand, a computer-readable storage medium is provided, wherein instructions are stored therein, which, when executed on a control circuit, implement the memory programming method as described in any of the above embodiments.

[0059] The technical solution provided in this application may include the following beneficial effects:

[0060] During the programming process, different pulse bandwidths are used in different pulse stages. The corresponding pulse bandwidth is used for programming according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming time; while when the programming voltage is high, a shorter pulse bandwidth is used. In the programming environment of step-pulse voltage programming, the programming efficiency of the memory can be improved and the programming speed can be increased. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0062] Figure 1 This is a schematic diagram of the structure of a 3D memory provided in an illustrative embodiment of this application;

[0063] Figure 2 This is a schematic diagram of a step-pulse voltage programming provided in an illustrative embodiment of this application;

[0064] Figure 3 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application;

[0065] Figure 4 Based on Figure 3 A schematic diagram illustrating the application process of the first programming voltage provided in the illustrated embodiment;

[0066] Figure 5 This is a schematic diagram illustrating the division of the programming process into two programming stages, provided by an exemplary embodiment of this application;

[0067] Figure 6 This is a schematic diagram illustrating the division of the programming process into three programming stages, provided by an exemplary embodiment of this application;

[0068] Figure 7 This is a schematic diagram illustrating the determination of pulse width based on programming stage divisions, provided in an exemplary embodiment of this application.

[0069] Figure 8 This is a schematic diagram of the pulse width provided in an exemplary embodiment of this application;

[0070] Figure 9 This is a flowchart of a memory programming method provided in another exemplary embodiment of this application;

[0071] Figure 10 This is a schematic diagram illustrating the linear increase of the programming voltage provided in an exemplary embodiment of this application;

[0072] Figure 11 This is a schematic diagram of a stepped increase in programming voltage provided in an exemplary embodiment of this application;

[0073] Figure 12 This is a schematic diagram of the structure of a memory provided in an exemplary embodiment of this application;

[0074] Figure 13 This is a schematic diagram of the structure of a storage system provided in an exemplary embodiment of this application. Detailed Implementation

[0075] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0076] The memory programming method provided in this application embodiment can be applied to a memory. This memory can be a 3D memory, such as a 3D NAND flash memory.

[0077] 3D memory is a multi-layered, stacked memory; schematically, this 3D memory is a 3D NAND flash memory. For example... Figure 1 As shown, the 3D memory 100 includes multiple memory strings 110 arranged in a direction parallel to the substrate's bearing surface, and multiple memory cells 120 in each memory string 110 are arranged in a direction perpendicular to the substrate's bearing surface. That is, the multiple memory cells included in the 3D memory are arranged in a three-dimensional array on the substrate, forming a memory array.

[0078] One end of the storage string 110 is connected to the bit line (BL), and the other end is connected to the source line (SL).

[0079] The memory cells in each memory string are also connected to memory cells in other memory strings via word lines (WL). For example, if each memory string can include 64 memory cells, then the 3D memory can include 64 word lines WL<63:0>, and each word line is connected to a portion of memory cells located on the same layer (i.e., having the same height relative to the substrate). It should be noted that 64 memory cells is only a specific example, and the application is not limited to this. In some embodiments, each memory string can include more than 64 memory cells, such as 128, 196, etc. In the 3D memory, the memory cells connected to the same word line are called a memory page, and all memory strings sharing a set of word lines are called a memory block.

[0080] The memory string 110 also includes an upper select transistor connected to the drain of the first memory cell and a lower select transistor connected to the source of the last memory cell. The upper select transistor is also called a top select gate (TSG) or drain select transistor. The lower select transistor is also called a bottom select gate (BSG) or source select transistor.

[0081] The gate of the TSG is connected to the drain select line (DSL), the source of the TSG is connected to the drain of the first memory cell, and the drain of the TSG is connected to the bit line.

[0082] The gate of the BSG is connected to the source select line (SSL), the drain of the BSG is connected to the source of the last memory cell, and the source of the BSG is connected to the source line.

[0083] Depend on Figure 1It is known that the memory cells in memory string 110 share a set of memory lines (WL) with the memory cells in other memory strings. Assuming each memory string includes m+1 memory cells, the 3D memory can include m+1 WLs: WL0 to WLm, where m is an integer greater than 1. Each WL is connected to each memory cell located on the same layer (i.e., at the same height relative to the substrate's bearing surface). Alternatively, it can be understood that the control gates of each memory cell located on the same layer, and the gate connection lines between each control gate, constitute a WL.

[0084] Based on the amount of data that a storage unit can store, storage units can be classified into single-level cells (SLC), multi-level cells (MLC), tri-level cells (TLC), and quadri-level cells (QLC). Each SLC can store 1 bit of data, each MLC can store 2 bits, each TLC can store 3 bits, and each QLC can store 4 bits. In 3D memory, the data stored in storage units located in the same layer can form k storage pages, where k is the number of bits of data that each storage unit can store.

[0085] In this embodiment, the storage cell in the 3D memory can be a floating-gate field-effect transistor (FET) or a charge-trap FET, or other FET capable of storing data. The TSG and BSG can be ordinary FETs or FETs capable of storing data. The floating-gate FET includes a source, a drain, and two gates. Both gates are conductors, and one is a control gate (CG), while the other is a floating gate (FG), referred to simply as a floating gate. The control gate is used to connect word lines, and the floating gate is used as a data storage cell. The charge-trap FET includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is used as a data storage cell and is made of an insulating material such as silicon nitride. The following description uses a floating-gate FET as an example to illustrate the data writing principle of the storage cell.

[0086] When writing data into a memory cell, a programming voltage is applied to the control gate of the floating-gate field-effect transistor (FET), causing electrons in the FET's channel to tunnel to the floating gate. By controlling the magnitude of this programming voltage, the number of electrons tunneling to the floating gate can be controlled, thereby controlling the threshold voltage Vth of the FET. Generally, the higher the amount of charge stored in the floating gate, the higher the threshold voltage Vth of the FET. It is understandable that different threshold voltages Vth require different voltages applied to the control gate to turn the FET on. Therefore, the magnitude of the threshold voltage Vth of the FET reflects the content of the stored data.

[0087] It should be understood that in 3D memory, the channels of each memory cell in each memory string can be connected sequentially to form a columnar structure perpendicular to the substrate.

[0088] Currently, the main programming method used in memory programming is Increment Step Pulse Program (ISPP). During the programming process, the programming voltage is not applied all at once, but is increased step by step until the voltage meets the programming requirements.

[0089] This is illustrative; please refer to it. Figure 2 It illustrates an ISPP programming diagram provided in an exemplary embodiment of this application, such as Figure 2 As shown, during the programming process, firstly, in the first pulse phase 210, an initial voltage is applied to the selected word line corresponding to the selected memory cell. Then, it is verified whether the initial voltage reaches the required programming voltage. If not, a voltage step size ΔVpp is added to the initial voltage to obtain a second pulse voltage. In the second pulse phase 220, this second pulse voltage is applied to the selected word line corresponding to the selected memory cell, and the verification of whether the second pulse voltage reaches the required programming voltage continues. This process is repeated until the pulse voltage applied to the selected word line reaches the required programming voltage, at which point programming stops.

[0090] In related technologies, to improve programming speed, the pulse width is usually extended, thereby increasing the step size to accelerate programming. In the ISPP process, the longer the pulse width, the larger the step size between two adjacent pulse stages. For example, if pulse stage 1 corresponds to pulse width 1, then 0.4V is added to the programming voltage of pulse stage 1 as the programming voltage of pulse stage 2, and then pulse stage 2 is entered; if pulse stage 1 corresponds to pulse width 2, and pulse width 2 is greater than pulse width 1, then 0.7V is added to the programming voltage of pulse stage 1 as the programming voltage of pulse stage 2, and then pulse stage 2 is entered.

[0091] However, extending the pulse width leads to a margin loss in the read window, as the duration of the programming voltage pulse in each pulse phase increases, resulting in a time loss in the process of reaching the required programming voltage.

[0092] Margin loss includes the loss caused by the lower boosting potential of the selected memory cell when the programming voltage is high after extending the pulse width, thus reducing programming efficiency.

[0093] In this embodiment, the pulse width of the pulse stage in the above-mentioned ISPP process is adaptively adjusted to control the pulse width of the preceding pulse stage in the ISPP process to be greater than the pulse width of the following pulse stage in the ISPP process, thereby improving the programming speed while avoiding margin loss caused by programming interference.

[0094] Figure 3 This is a flowchart of a memory programming method provided in an exemplary embodiment of this application, taking the application of this method in 3D memory as an example. Figure 3 As shown, the method includes:

[0095] Step 301: Apply a first programming voltage to the selected word line with a first pulse width during the first pulse phase.

[0096] The first pulse phase is one of a series of pulse phases used to program a selected memory cell.

[0097] Here, the selected storage unit is the storage unit where data is to be written, and the selected word line is the word line connected to the selected storage unit.

[0098] The first pulse phase is the phase in the programming process where a programming voltage is applied to the memory cell. In the first pulse phase, the programming voltage continuously applied to the selected word line is the first programming voltage, and the pulse width is the first pulse width. In some embodiments, the programming voltage is directly increased to the first programming voltage in the first pulse phase, or the programming voltage is first increased to a first intermediate voltage in the first pulse phase, and then increased from the first intermediate voltage to the first programming voltage. This embodiment does not limit this to any particular approach.

[0099] In this embodiment, the first pulse width refers to the pulse width corresponding to the applied first programming voltage, that is, the process of applying the first intermediate voltage and the process of voltage rise are pulses outside the pulse width; or, the first pulse width refers to the pulse width corresponding to the period from the application of the first intermediate voltage until the application of the first programming voltage is completed.

[0100] To illustrate, let's take the example where the first pulse width is the pulse width corresponding to the applied first programming voltage. Figure 4 As shown, for the selected word line 400, during the first pulse phase (Loop) of the selected memory cell through the selected word line 400, a first programming voltage is applied to the selected word line 400. First, a first intermediate voltage is applied to the selected word line 400, and then the voltage is increased to the first programming voltage based on the first intermediate voltage. The application process corresponding to the first programming voltage corresponds to the first pulse width.

[0101] The first intermediate voltage is a stage voltage between the starting voltage and the first programming voltage. The value of this first intermediate voltage can be the midpoint between the starting voltage and the first programming voltage, or a voltage value between the starting voltage and the first programming voltage determined according to other optimization principles, or any value between the starting voltage and the first programming voltage. This embodiment does not limit this. The starting voltage can be the pre-charge voltage of the pre-charge stage or the verification voltage of the verification stage.

[0102] Step 302: In the second pulse phase, a second programming voltage is applied to the selected word line with a second pulse width.

[0103] The first pulse phase and the second pulse phase are two of a total of pulse phases used to program a selected memory cell.

[0104] The first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

[0105] Optionally, the selected memory cell is programmed using the Stepped Pulse Voltage Programming (ISPP) method, where the first pulse phase precedes the second pulse phase in timing.

[0106] The second pulse phase is the phase in the programming process where a programming voltage is applied to the memory cell. In the second pulse phase, the programming voltage continuously applied to the selected word line is the second programming voltage, and the pulse width is the second pulse width. In some embodiments, the programming voltage is directly increased to the second programming voltage in the second pulse phase, or the programming voltage is first increased to a second intermediate voltage in the second pulse phase, and then increased from the second intermediate voltage to the second programming voltage. This embodiment does not limit this to any particular approach.

[0107] In this embodiment of the application, the second pulse width refers to the pulse width corresponding to the applied second programming voltage, that is, the process of applying the second intermediate voltage and the process of voltage rise are pulses outside the pulse width; or, the second pulse width refers to the pulse width corresponding to the period from the application of the second intermediate voltage until the application of the second programming voltage is completed.

[0108] The second intermediate voltage is a stage voltage between the starting voltage and the second programming voltage. The value of the second intermediate voltage can be the midpoint between the starting voltage and the second programming voltage, or it can be a voltage value between the starting voltage and the second programming voltage determined according to other optimization principles, or it can be any value between the starting voltage and the second programming voltage. This embodiment does not limit this value.

[0109] In some embodiments, if the first pulse phase precedes the second pulse phase in timing, then the starting voltage is the verification voltage of the verification phase preceding the second pulse phase.

[0110] That is, in the embodiments of this application, there are at least two pulse stages during the programming stage: the pulse stage with a smaller programming voltage has a larger pulse width, and the pulse stage with a larger programming voltage has a smaller pulse width.

[0111] In some embodiments, during programming, the channel of the selected memory string is grounded, and the channel of the deselected memory string is left floating. The selected memory string refers to the memory string to which the selected memory cell belongs; other memory strings besides the selected memory string are the deselected memory strings. In this embodiment, the TSG in the selected memory string is turned on, the BSG in the selected memory string is turned off, and the BL connected to the TSG is grounded, thus grounding the channel of the selected memory string. Furthermore, both the TSG and BSG in the deselected memory string are turned off, leaving the channel of the deselected memory string floating. Therefore, programming the selected memory cell via the selected word line will not affect the memory cells in the deselected memory string.

[0112] Optionally, a programming voltage V is applied to a selected word line. pgm Simultaneously, a conduction voltage V can be applied to both the unselected (unselected) and unselded (unselected) WL. pass The on-state voltage V pass This is used to turn on all the deselected memory units connected to unselWL, so that the selected memory unit is connected to selBL. The deselected memory unit is the memory unit that does not correspond to a programming task.

[0113] It is understandable that the programming voltage V pgm The voltage is typically high, thus allowing a large voltage difference to be created between the control gate and the channel of the selected memory cell. This enables electrons in the channel to tunnel to the floating gate of the selected memory cell, thereby storing data. Furthermore, by adjusting the programming voltage V... pgm The size of the value can be adjusted to change the number of electrons stored in the floating gate, which in turn can adjust the threshold voltage Vth of the selected memory cell.

[0114] Due to the on-voltage V pass Typically below the programming voltage V pgmTherefore, the voltage difference between the control gate and the channel of the deselected memory cell connected to unselWL is relatively small, thus preventing electrons in the channel from tunneling to the floating gate. For the deselected memory cells connected to selWL in the deselected memory string, since the channel of that deselected memory string is floating, the voltage difference between the control gate and the channel of the deselected memory cell connected to selWL is also relatively small, again preventing electrons in the channel from tunneling to the floating gate. In other words, when programming a selected memory cell, neither the deselected memory cells connected to unselWL nor the deselected memory cells connected to selWL will be programmed; that is, programming of the deselected memory cells is suppressed.

[0115] In summary, the method provided in this application uses different pulse bandwidths at different pulse stages during the programming process. The corresponding pulse bandwidth is used for programming according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming time and improve the step size at low programming voltage stages, thus accelerating programming. When the programming voltage is high, a shorter pulse bandwidth is used. In the programming environment of step-pulse voltage programming, the programming efficiency of the memory can be improved and the programming speed can be increased.

[0116] Optionally, the pulse width can be determined in at least one of the following ways:

[0117] First, divide the programming process into programming stages.

[0118] That is, the programming process of the selected memory cell is divided into at least two programming stages, each programming stage includes at least one pulse stage, and each programming stage corresponds to a pulse width; that is, pulse stages in the same programming stage correspond to the same pulse width. The programming stages include a first programming stage and a second programming stage.

[0119] Optionally, the programming process can be divided into programming stages according to the programming sequence. For example, the first n pulse stages of the programming process can be divided into the first programming stage, and the (n+1)th to (n+m)th pulse stages can be divided into the second programming stage, where n and m are positive integers.

[0120] In this embodiment, the multiple pulse stages are divided into a first programming stage and a second programming stage; the pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage;

[0121] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage containing the second pulse stage.

[0122] Optionally, the first programming stage and the second programming stage can be two adjacent programming stages, or any two non-adjacent programming stages.

[0123] The number of pulse stages contained in each programming stage may be the same or different.

[0124] To illustrate, let's take dividing the programming process into two stages as an example, such as... Figure 5 As shown, the programming process for a selected memory cell is divided into programming stage 510 and programming stage 520. Programming stage 510 includes pulse stages (Loop) 1 to Loop k, totaling k pulse stages, with each pulse stage in programming stage 510 corresponding to a pulse bandwidth of 1 (pulsewidth_1). Programming stage 520 includes Loop k+1 to Loop k+m, totaling m pulse stages, with each pulse stage in programming stage 520 corresponding to a pulse bandwidth of 2 (pulse width_2). Here, k, m, and n are all positive integers.

[0125] To illustrate, let's take dividing the programming process into three stages as an example, such as... Figure 6 As shown, the programming process of the selected memory cell is divided into programming stage 610, programming stage 620 and programming stage 630. Programming stage 610 includes pulse stages (Loop) 1 to Loopk, a total of k pulse stages, and the pulse stages in programming stage 610 correspond to pulse width 1. Programming stage 620 includes Loopk+1 to Loopk+m, a total of m pulse stages, and the pulse stages in programming stage 620 correspond to pulse width 2. Programming stage 630 includes Loopk+m+1 to Loopk+m+n, a total of n pulse stages, and the pulse stages in programming stage 630 correspond to pulse width 3.

[0126] It is worth noting that the above division into two and three programming stages is only an illustrative example. In some embodiments, multiple pulse stages can be divided into more programming stages, and this embodiment does not limit this.

[0127] To illustrate, let's take dividing the programming process into three stages as an example, such as... Figure 7 As shown, the selected memory unit is memory unit n, and its corresponding selected word line is Select WLn. The programming process is divided into three programming stages. The first programming stage includes Loop 710, the second programming stage includes Loop 720, and the third programming stage includes Loop 730.

[0128] In Loop 710, a first programming voltage is applied to Select WLn, and this first programming voltage corresponds to a first pulse width. In Loop 720, a second programming voltage is applied to Select WLn, and this second programming voltage corresponds to a second pulse width. In Loop 730, a third programming voltage is applied to Select WLn, and this third programming voltage corresponds to a third pulse width. Due to the characteristics of the step-pulse voltage programming (ISPP) method, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; while the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0129] In this design, Loop710 is one pulse stage in the first programming stage, Loop720 is one pulse stage in the second programming stage, and Loop730 is one pulse stage in the third programming stage. Figure 7 The examples shown are merely illustrative.

[0130] The above pulse phases are illustrated in a bar chart, as follows: Figure 8 As shown, the programming process includes step-like pulse stages 810, 820, and 830. Pulse stage 810 corresponds to a wider pulse width and a smaller programming voltage. The pulse width of pulse stage 820 is smaller than that of pulse stage 810, and the programming voltage of pulse stage 820 is greater than that of pulse stage 810. The pulse width of pulse stage 830 is smaller than that of pulse stage 820, and the programming voltage of pulse stage 830 is greater than that of pulse stage 820.

[0131] Optionally, the above-mentioned division of programming stages includes at least one of the following methods:

[0132] 1.1 Divide the programming stages of multiple pulse stages based on the number of steps;

[0133] The step count refers to the number of times the programming voltage is adjusted in the ISPP. In some embodiments, if the required programming voltage is not reached, the programming voltage is adjusted once between the i-th pulse stage and the (i+1)-th pulse stage, that is, once between two adjacent pulse stages, and there is one step between two adjacent pulse stages.

[0134] Then, the first programming stage includes a first number of pulse stages arranged in succession, and the second programming stage includes a second number of pulse stages arranged in succession. The first number and the second number are the same, or the first number and the second number are different. Taking the first number and the second number being the same as an example, the first programming stage includes 3 pulse stages arranged in sequence, and the second programming stage includes 3 pulse stages arranged in sequence. Taking the first number and the second number being different, and the first number and the second number decreasing according to the order of the programming stages as an example, the first programming stage includes 4 pulse stages arranged in succession, and the second programming stage includes 3 pulse stages arranged in succession.

[0135] To illustrate, each step involves three loops, forming a programming stage. For example, if you step from Loop 1 to Loop 2, and from Loop 2 to Loop 3, then Loop 1, Loop 2, and Loop 3 are in the same programming stage, corresponding to the same pulse width of 1. After Loop 3, the pulse width decreases to pulse width 2. Starting from Loop 4, the pulse width is 2. If you step from Loop 3 to Loop 4, from Loop 4 to Loop 5, and from Loop 5 to Loop 6, then Loop 4, Loop 5, and Loop 6 are in the same programming stage, corresponding to the same pulse width of 2, and so on.

[0136] 1.2 The programming process is divided into stages based on the step size of the programming voltage;

[0137] The step size refers to the adjustment range of the programming voltage between two adjacent pulse phases. For example, if the programming voltage difference between two adjacent pulse phases is 1V during programming, then the step size is 1V. The rated programming phase is determined based on this step size.

[0138] To illustrate, when the step size is less than 1V, every four pulse stages constitute a programming stage; when the step size is greater than 1V, every three pulse stages constitute a programming stage; and when the step size is 3V, every two pulse stages constitute a programming stage.

[0139] For example, if the step size of the ISPP programming process is 2V, then Loop1, Loop2, and Loop3 are divided into one programming stage, corresponding to a pulse width of 1. If the step size of the ISPP programming process is 0.7V, then Loop4, Loop5, Loop6, and Loop7 are divided into one programming stage, corresponding to a pulse width of 2, and so on, until the programming voltage reaches the required programming voltage.

[0140] 1.3 The programming process is divided into stages based on stage voltage thresholds;

[0141] Among them, the stage voltage threshold is used to limit the programming voltage range corresponding to each programming stage.

[0142] Therefore, in the first programming stage, the programming voltage of each pulse stage is less than the stage voltage threshold, and in the second programming stage, the programming voltage of each pulse stage is greater than the stage voltage threshold.

[0143] To illustrate, if the stage voltage thresholds are set to 2V, 5V, and 8V, then when the programming voltage reaches 2V, pulse stages with programming voltages of 2V and below are grouped into the same programming stage, corresponding to pulse width 1; when the programming voltage reaches 5V, pulse stages with programming voltages in the range of 2V to 5V are grouped into the same programming stage, corresponding to pulse width 2; and when the programming voltage reaches 8V, pulse stages with programming voltages in the range of 5V to 8V are grouped into the same programming stage, corresponding to pulse width 3.

[0144] It is worth noting that the above-described division of programming stages is merely an illustrative example, and the embodiments of this application do not limit it.

[0145] Secondly, the pulse width during the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0146] That is, during the ISPP programming process, each loop uses a different pulse width, and the pulse width gradually decreases as the programming voltage increases during ISPP programming.

[0147] Indicatively, Loop1, Loop2, and Loop3 represent three consecutive pulse phases. Loop1 corresponds to the programming voltage Vpp1, Loop2 to the programming voltage Vpp2, and Loop3 to the programming voltage Vpp3. The difference between Vpp2 and Vpp1 is ΔVpp1, and the difference between Vpp3 and Vpp2 is ΔVpp2. Therefore, the pulse width 1 corresponding to Loop1 is greater than the pulse width 2 corresponding to Loop2, and the pulse width 2 corresponding to Loop2 is greater than the pulse width 3 corresponding to Loop3.

[0148] In some embodiments, the pulse width decreases in a stepwise manner as the pulse phase changes, such as: Loop1 corresponds to pulse width 1, Loop2 corresponds to pulse width 2, and Loop3 corresponds to pulse width 3, wherein the difference between pulse width 1 and pulse width 2 is a preset pulse width difference; the difference between pulse width 2 and pulse width 3 is a preset pulse width difference.

[0149] In other embodiments, the pulse width decreases linearly as the pulse phase changes. For example, Loop1 corresponds to pulse width 1, Loop2 corresponds to pulse width 2, and Loop3 corresponds to pulse width 3, where pulse width 2 is half of pulse width 1 and pulse width 3 is half of pulse width 2.

[0150] In summary, the method provided in this application uses different pulse bandwidths at different pulse stages during the programming process. The corresponding pulse bandwidth is used for programming according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth can be used to ensure sufficient programming time; while when the programming voltage is high, a shorter pulse bandwidth is used to improve the boosting potential and reduce margin loss caused by programming voltage interference.

[0151] The method provided in this embodiment divides the programming process into different programming stages, with each stage corresponding to a different pulse width. Based on the programming stages, the pulse width corresponding to each stage is determined. The programming stages are divided according to the order of the programming process, thereby controlling the pulse width to be larger in the early stage, moderate in the middle stage, and smaller in the later stage, thus improving programming efficiency.

[0152] The method provided in this embodiment improves the adaptability between pulse width and programming voltage by determining the negative correlation between pulse width and programming voltage during the programming process and adaptively adjusting the pulse width according to the real-time changes in programming voltage. This results in the application of programming voltage with an appropriate pulse width, thereby improving programming efficiency.

[0153] The method provided in this embodiment uses a relatively long pulse width during the first few pulse stages / low programming state of the programming process, when the PGM voltage is relatively low, to ensure sufficient programming time. If the pulse width is relatively small, the effective programming efficiency is relatively low, and the number of programming pulses increases, resulting in lower programming efficiency. During the middle pulse stages / middle programming state, a moderate PGM pulse width is used. During the last few pulse stages / high programming state, programming disturbance is mainly caused by Fowler-Nordheim (FN) tunneling, and the programming voltage is relatively large, requiring a relatively high channel potential. A shorter pulse width can be used to increase the boosting potential and reduce the losses caused by PGM disturbance.

[0154] In this embodiment of the application, the programming process includes at least three pulse stages as an example for illustration. Figure 9 As shown above, in the above Figure 3 Following step 302 shown, the method further includes:

[0155] Step 303: In the third pulse phase, a third programming voltage is applied to the selected word line with a third pulse width.

[0156] Taking the ISPP programming method as an example, the second pulse stage precedes the third pulse stage in terms of timing, the width of the second pulse is greater than the width of the third pulse, and the second programming voltage is less than the third programming voltage.

[0157] one, The programming process is divided into at least three programming stages, including a first programming stage, a second programming stage, and a third programming stage arranged in sequence. The first pulse stage, occurring within the first programming stage, applies a first programming voltage to the selected word line; the second pulse stage, occurring within the second programming stage, applies a second programming voltage to the selected word line; and the third pulse stage, occurring within the third programming stage, applies a third programming voltage to the selected word line. The pulse stages in the first programming stage correspond to the first pulse width, the pulse stages in the second programming stage correspond to the second pulse width, and the pulse stages in the third programming stage correspond to the third pulse width.

[0158] Wherein, the first pulse width is greater than the second pulse width, the second pulse width is greater than the third pulse width; the first programming voltage is less than the second programming voltage, and the second programming voltage is less than the third programming voltage.

[0159] two, The first, second, and third pulse stages are three pulse stages in the programming process, arranged sequentially. These three pulse stages may be continuous or discontinuous, and the programming voltage applied in each pulse stage increases sequentially. That is, the first programming voltage applied in the first pulse stage is less than the second programming voltage applied in the second pulse stage, and the second programming voltage applied in the second pulse stage is less than the third programming voltage applied in the third pulse stage. The magnitude of the programming voltage is negatively correlated with the pulse width; therefore, the first pulse width in the first pulse stage is greater than the second pulse width in the second pulse stage, and the second pulse width in the second pulse stage is greater than the third pulse width in the third pulse stage.

[0160] In summary, the method provided in this application uses different pulse bandwidths in the three pulse stages during the programming process. The corresponding pulse bandwidth is used for programming according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth is used to ensure sufficient programming time; while when the programming voltage is high, a shorter pulse bandwidth is used to improve the boosting potential and reduce the margin loss caused by programming voltage interference.

[0161] In an optional embodiment, the first programming voltage and / or the second programming voltage are programming voltages that exhibit a changing trend during the pulse phase.

[0162] That is, the first programming voltage corresponds to the first initial programming voltage at the beginning of the first pulse phase, the first programming voltage corresponds to the first termination programming voltage at the end of the first pulse phase, and the first initial programming voltage is less than the first termination programming voltage.

[0163] The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase and the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

[0164] Optionally, the difference between the first termination programming voltage and the first initial programming voltage is the first voltage difference; the difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference; the first voltage difference is greater than the second voltage difference.

[0165] When a third programming voltage is present, the third initial programming voltage at the beginning of the third pulse phase is less than the third termination programming voltage at the end of the third pulse phase.

[0166] Optionally, the difference between the third termination programming voltage and the third initial programming voltage is the third voltage difference; the second voltage difference is greater than the third voltage difference.

[0167] The changing trend of the programming voltage includes at least one of the following methods:

[0168] 1. The first programming voltage and / or the second programming voltage exhibit a step-increasing trend during the pulse phase; that is, the first programming voltage exhibits a step-increasing trend during the first pulse phase, and the second programming voltage exhibits a step-increasing trend during the second pulse phase.

[0169] Second, the first programming voltage and / or the second programming voltage exhibit a linear increasing trend during the pulse phase; that is, the first programming voltage exhibits a linear increasing trend during the first pulse phase, and the second programming voltage exhibits a linear increasing trend during the second pulse phase.

[0170] That is, the first programming voltage increases in a stepwise manner during the first pulse phase; or, the first programming voltage increases linearly during the first pulse phase.

[0171] The second programming voltage increases in a stepwise manner during the second pulse phase; or, the second programming voltage increases linearly during the second pulse phase.

[0172] The first programming voltage may change in the same way as the second programming voltage, or they may change in different ways. That is, the first programming voltage may increase in a step-like or linear manner during the first pulse phase, while the second programming voltage may increase in a step-like or linear manner during the second pulse phase.

[0173] In some embodiments, when a third programming voltage is present, the third programming voltage increases in a stepwise manner during the third pulse phase; or, the third programming voltage increases linearly during the third pulse phase.

[0174] The linear increasing trend and the step-like increasing trend will be explained separately.

[0175] Linear increasing trend:

[0176] Optionally, based on controlling the pulse width of each pulse stage during the programming process, the programming voltage exhibits a "triangular peak" shape within a pulse stage, meaning that the programming voltage shows an upward trend during the effective programming process within a pulse stage.

[0177] Optionally, the voltage difference ΔVpgm of the rising voltage during the pulse phase of the programming voltage can be controlled independently for different pulse phases. Here, ΔVpgm is the difference between the maximum and minimum voltages during the effective programming process of the programming voltage in the pulse phase.

[0178] In this embodiment, the programming process is illustrated by dividing it into three programming stages: a first programming stage, a second programming stage, and a third programming stage. The three programming stages are arranged in sequence. The first programming stage includes a first pulse stage, where the first programming voltage corresponds to the first pulse width. The second programming stage includes a second pulse stage, where the second programming voltage corresponds to the second pulse width. The third programming stage includes a third pulse stage, where the third programming voltage corresponds to the third pulse width.

[0179] The first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0180] In some embodiments, taking the first programming stage as an example, the voltage difference of the rising voltage corresponding to each pulse stage within the first programming stage may be the same or different. When the voltage difference of the rising voltage corresponding to each pulse stage within the first programming stage is different, the voltage difference of the rising voltage decreases sequentially according to the timing of the pulse stages; or, the voltage difference of the rising voltage of each pulse stage is reduced in batches during the first programming stage, such as: the first programming stage includes 5 pulse stages, wherein the voltage difference 1 corresponding to the first pulse stage and the second pulse stage, the voltage difference 2 corresponding to the third pulse stage and the fourth pulse stage, and the voltage difference 3 corresponding to the fifth pulse stage, wherein voltage difference 1 is greater than voltage difference 2, and voltage difference 2 is greater than voltage difference 3. This application does not limit this aspect.

[0181] This is illustrative; please refer to it. Figure 10This illustrates a schematic diagram of the linear rise of the programming voltage provided in an exemplary embodiment of this application. Figure 10 As shown, the programming process is divided into three programming stages: the first programming stage 1010, the second programming stage 1020, and the third programming stage 1030.

[0182] Specifically, in the first pulse phase of the first programming phase 1010, a first programming voltage with a linearly increasing trend is applied to the selected word line during the first pulse phase, such as... Figure 10 As shown, during the effective programming process within the first pulse phase, the first programming voltage exhibits a linear upward trend, and this upward trend continues across the first pulse bandwidth. Optionally, the effective programming process refers to the portion of the first pulse phase excluding the intermediate voltage and transition voltage, and this effective programming process includes the first pulse bandwidth portion of the first programming voltage. The voltage difference during the rise of the first programming voltage within the first pulse bandwidth portion is ΔVpgm1.

[0183] For the second pulse phase in the second programming phase 1020, a second programming voltage with a linearly increasing trend is applied to the selected word line during the second pulse phase, such as... Figure 10 As shown, during the effective programming process within the second pulse phase, the second programming voltage exhibits a linear upward trend, and this upward trend continues across the second pulse bandwidth. Optionally, the effective programming process includes the second pulse bandwidth portion of the second programming voltage. The voltage difference during the rise of the second programming voltage in the second pulse bandwidth portion is ΔVpgm2.

[0184] For the third pulse phase in the third programming phase 1030, a third programming voltage with a linearly increasing trend is applied to the selected word line during the third pulse phase, such as... Figure 10 As shown, during the effective programming process in the third pulse phase, the third programming voltage exhibits a linear upward trend, and this upward trend continues across the third pulse bandwidth. Optionally, the effective programming process includes the third pulse bandwidth portion of the third programming voltage. The voltage difference during the rise of the third programming voltage in the third pulse bandwidth portion is ΔVpgm3.

[0185] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, the second pulse width is greater than the third pulse width, and △Vpgm1 is greater than △Vpgm2, and △Vpgm2 is greater than △Vpgm3.

[0186] Since the first programming voltage, the second programming voltage, and the third programming voltage are all programming voltages that show an upward trend, the following example illustrates the situation where the first programming voltage is lower than the second programming voltage. This means that the programming voltage at the beginning of the first programming voltage is lower than the programming voltage at the beginning of the second programming voltage; or, the programming voltage at the end of the first programming voltage is lower than the programming voltage at the end of the second programming voltage; or, the programming voltage at the beginning of the first programming voltage is lower than the programming voltage at the end of the second programming voltage; or, the programming voltage at the end of the first programming voltage is lower than the programming voltage at the beginning of the second programming voltage. This embodiment does not limit this to any particular case.

[0187] It is worth noting that, in the above embodiments, the first programming voltage, the second programming voltage, and the third programming voltage all show a linear upward trend as an example. In some embodiments, the first programming voltage, the second programming voltage, and the third programming voltage may be stable and unchanged; or the first programming voltage, the second programming voltage, and the third programming voltage may show a gradient upward trend. The embodiments of this application do not limit this.

[0188] In addition, the above embodiments are illustrated by taking the rising pattern of the three programming voltages and the voltage difference relationship between the three programming voltages as examples. In this embodiment, the voltage difference of the programming voltages decreases as the pulse width decreases, and it can also be realized between more pulse stages with the same or different pulse widths.

[0189] In summary, during the first few pulse stages / low programming state of the programming process, the PGM voltage is relatively low, and a relatively long pulse width is used to ensure sufficient programming time. However, programming efficiency is relatively low when the PGM voltage is low. If a relatively high programming voltage is used, it will lead to overprogramming. Therefore, the programming voltage is gradually increased in one pulse stage, which greatly improves the effective programming rate while ensuring that overprogramming is not prevented.

[0190] During the intermediate pulse phase / intermediate programming state, use an appropriate PGM pulse width, ΔVpgm2 < ΔVpgm1;

[0191] During the last few pulse stages / high programming state, the programming voltage is relatively large. When the programming voltage shows an upward trend, it will further increase the boosting potential, thereby reducing margin loss caused by programming interference. Specifically, ΔVpgm3 < ΔVpgm2; otherwise, overprogramming will occur, leading to margin loss.

[0192] Step-like increasing trend:

[0193] Based on controlling the pulse width of each pulse stage during the programming process, the programming voltage is presented in a "step" manner within a pulse stage, that is, the programming voltage increases in a stepwise manner during the effective programming process of a pulse stage.

[0194] Optionally, the programming voltage may rise in two steps within a pulse phase, i.e., first reaching the initial programming voltage in a pulse phase, and then rising to the termination programming voltage after a certain period of time, until the pulse width is reached; or, the programming voltage may rise in more than two steps within a pulse phase, i.e. first reaching the initial programming voltage in a pulse phase, and then rising to a certain value at certain intervals until the termination programming voltage is reached, ultimately reaching the pulse width.

[0195] Optionally, the voltage difference ΔVpgm of the rising voltage during the pulse phase of the programming voltage can be controlled independently for different pulse phases. Here, ΔVpgm is the difference between the maximum and minimum voltages during the effective programming process of the programming voltage in the pulse phase.

[0196] In this embodiment, the programming process is illustrated by dividing it into three programming stages: a first programming stage, a second programming stage, and a third programming stage. The three programming stages are arranged in sequence. The first programming stage includes a first pulse stage, where the first programming voltage corresponds to the first pulse width. The second programming stage includes a second pulse stage, where the second programming voltage corresponds to the second pulse width. The third programming stage includes a third pulse stage, where the third programming voltage corresponds to the third pulse width.

[0197] The first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, and the second pulse width is greater than the third pulse width.

[0198] In some embodiments, taking the first programming stage as an example, the voltage difference of the rising voltage corresponding to each pulse stage within the first programming stage may be the same or different. When the voltage difference of the rising voltage corresponding to each pulse stage within the first programming stage is different, the voltage difference of the rising voltage decreases sequentially according to the timing of the pulse stages; or, the voltage difference of the rising voltage of each pulse stage is reduced in batches during the first programming stage, such as: the first programming stage includes 5 pulse stages, wherein the voltage difference 1 corresponding to the first pulse stage and the second pulse stage, the voltage difference 2 corresponding to the third pulse stage and the fourth pulse stage, and the voltage difference 3 corresponding to the fifth pulse stage, wherein voltage difference 1 is greater than voltage difference 2, and voltage difference 2 is greater than voltage difference 3. This application does not limit this aspect.

[0199] This is illustrative; please refer to it. Figure 11 This illustration shows a schematic diagram of the linear increase of the programming voltage provided in an exemplary embodiment of this application, wherein a two-step increase is used as an example to illustrate the step-like increasing trend. Figure 11 As shown, the programming process is divided into three programming stages: the first programming stage 1110, the second programming stage 1120, and the third programming stage 1130.

[0200] Specifically, in the first pulse phase of the first programming phase 1110, a first programming voltage with a two-step gradient increasing trend is applied to the selected word line during the first pulse phase, such as... Figure 11 As shown, during the effective programming process within the first pulse phase, the first programming voltage first reaches a first initial voltage value, and then, after a certain duration, such as half or nearly half of the first pulse bandwidth, it increases from the initial voltage value to a first boost voltage value, and is applied until it reaches the first pulse bandwidth. Optionally, the effective programming process refers to the portion of the first pulse phase excluding the intermediate voltage and transition voltage, and includes the first pulse bandwidth portion of the first programming voltage. The voltage difference during the rise of the first programming voltage in the first pulse bandwidth portion is ΔVpgm1.

[0201] For the second pulse phase in the second programming phase 1120, a second programming voltage with a two-step gradient increasing trend is applied to the selected word line during the second pulse phase, such as... Figure 11 As shown, during the effective programming process within the second pulse phase, the second programming voltage first reaches a second initial voltage value, and then, after a certain duration, such as half or nearly half of the second pulse bandwidth, it increases from the initial voltage value to a second boost voltage value, and is applied until it reaches the second pulse bandwidth. Optionally, the effective programming process refers to the portion of the second pulse phase excluding the intermediate voltage and transition voltage, and includes the second pulse bandwidth portion of the second programming voltage. The voltage difference during the rise of the second programming voltage in the second pulse bandwidth portion is ΔVpgm2.

[0202] For the third pulse stage in the third programming stage 1130, a third programming voltage with a two-step gradient increasing trend is applied to the selected word line during the third pulse stage, such as... Figure 11As shown, during the effective programming process in the third pulse phase, the third programming voltage first reaches a third initial voltage value, and then, after a certain duration, such as half or nearly half of the third pulse bandwidth, it increases from the initial voltage value to a third boost voltage value, and is applied until it reaches the third pulse bandwidth. Optionally, the effective programming process refers to the portion of the third pulse phase excluding the intermediate voltage and transition voltage, and includes the third pulse bandwidth portion of the third programming voltage. The voltage difference during the rise of the third programming voltage in the third pulse bandwidth portion is ΔVpgm3.

[0203] Among them, the first programming voltage is lower than the second programming voltage, and the second programming voltage is lower than the third programming voltage; the first pulse width is greater than the second pulse width, the second pulse width is greater than the third pulse width, and △Vpgm1 is greater than △Vpgm2, and △Vpgm2 is greater than △Vpgm3.

[0204] Since the first, second, and third programming voltages are all programming voltages with an upward trend, the following explanation uses the example of the first programming voltage being lower than the second programming voltage. The first programming voltage being lower than the second programming voltage means that the programming voltage at the start of the first programming voltage is lower than the programming voltage at the start of the second programming voltage; or, the programming voltage at the end of the first programming voltage is lower than the programming voltage at the end of the second programming voltage; or, the programming voltage at the start of the first programming voltage is lower than the programming voltage at the end of the second programming voltage; or, the programming voltage at the end of the first programming voltage is lower than the programming voltage at the start of the second programming voltage; or, when the first and second programming voltages are implemented as three-step or multi-step rising voltages, the intermediate step programming voltage of the first programming voltage is lower than the intermediate step programming voltage of the second programming voltage, such as: the second step programming voltage in the first programming voltage is lower than the second step programming voltage in the second programming voltage. This embodiment does not limit this.

[0205] It is worth noting that, in the above embodiments, the first programming voltage, the second programming voltage, and the third programming voltage all show a step-like upward trend as an example. In some embodiments, the first programming voltage, the second programming voltage, and the third programming voltage may be stable and unchanged; or the first programming voltage, the second programming voltage, and the third programming voltage may show a linear upward trend. The embodiments of this application do not limit this.

[0206] In addition, the above embodiments are illustrated by taking the rising pattern of the three programming voltages and the voltage difference relationship between the three programming voltages as examples. In this embodiment, the voltage difference of the programming voltages decreases as the pulse width decreases, and it can also be realized between more pulse stages with the same or different pulse widths.

[0207] In summary, during the first few pulse stages / low programming state of the programming process, the PGM voltage is relatively low, and a relatively long pulse width is used to ensure sufficient programming time. However, programming efficiency is relatively low when the PGM voltage is low. If a relatively high programming voltage is used, it will lead to overprogramming. Therefore, the programming voltage is increased in a stepwise manner within a pulse stage, which greatly improves the effective programming rate while ensuring that overprogramming is not prevented.

[0208] During the intermediate pulse phase / intermediate programming state, use an appropriate PGM pulse width, ΔVpgm2 < ΔVpgm1;

[0209] During the last few pulse stages / high programming state, the programming voltage is relatively large. When the programming voltage shows an upward trend, it will further increase the boosting potential, thereby reducing margin loss caused by programming interference. Specifically, ΔVpgm3 < ΔVpgm2; otherwise, overprogramming will occur, leading to margin loss.

[0210] Figure 12 This is a schematic diagram of the structure of a memory provided in an embodiment of this application. For example... Figure 12 As shown, the memory includes peripheral circuitry 1200 and a memory cell array 1210;

[0211] The peripheral circuit 1200 is used to write data to the memory cell array 1210 and to read data from the memory cell array 1210.

[0212] The peripheral circuitry 1200 includes: a voltage generator 1202, a page buffer / sensor amplifier 1204, a column decoder / bit line (BL) driver 1206, a row decoder / word line (WL) driver 1208, a peripheral logic unit 1212, a register 1214, input / output circuitry 1216, and a data bus 1218. It should be understood that in some examples, it may also include... Figure 12 Additional peripheral circuitry not shown.

[0213] Page buffer / sensor amplifier 1204 can be configured to read data from memory cell array 1210 and program (write) data to memory cell array 1210 according to control signals from peripheral logic unit 1212. In one example, page buffer / sensor amplifier 1204 can store a page of programming data (write data) to be programmed into a page of memory cell array 1210. In another example, page buffer / sensor amplifier 1204 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to a selected word line. In yet another example, page buffer / sensor amplifier 1204 can also sense a low-power signal from a bit line representing a data bit stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation.

[0214] The column decoder / bit line driver 1206 can be configured to be controlled by the peripheral logic unit 1212 and to select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 1202.

[0215] The line decoder / word line driver 1208 can be configured to be controlled by the peripheral logic unit 1212 and to select / deselect blocks of the memory cell array 1210 and select / deselect word lines of the blocks. The line decoder / word line driver 1208 can also be configured to use word line voltages (V) generated from the voltage generator 1202. WL The line decoder / word line driver 1208 can also select / deselect and drive the source select gate line and the drain select gate line. Illustratively, the line decoder / word line driver 1208 is configured to perform an erase operation on memory cells coupled to one or more selected word lines.

[0216] Voltage generator 1202 can be configured to be controlled by peripheral logic unit 1212 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 1210.

[0217] Peripheral logic unit 1212 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Peripheral logic unit 1212 includes the above-described components. Figure 12 The control circuit shown is shown.

[0218] Register 1214 can be coupled to peripheral logic unit 1212 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Input / output circuit 1216 can be coupled to peripheral logic unit 1212 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to peripheral logic unit 1212, and to buffer status information received from peripheral logic unit 1212 and relay it to the host. Input / output circuit 1216 can also be coupled to column decoder / bit line driver 1206 via data bus 1218 and acts as a data input / output interface and data buffer to buffer data and relay it to or from memory cell array 1210.

[0219] It should be emphasized that the peripheral circuit 1200 is configured to perform the memory programming method provided in the embodiments of this disclosure on a selected memory cell row among a plurality of memory cell rows.

[0220] Figure 13 This is a structural block diagram of a storage system provided in an exemplary embodiment of this application, such as... Figure 13 As shown, the storage system 1300 includes: one or more memories 1310, and,

[0221] A memory controller 1320 is coupled to the memory 1310 and configured to control the memory 1310.

[0222] The storage system 1300 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0223] Optionally, the storage system 1300 may include a host and a storage subsystem, the storage subsystem having one or more memories 1310 and a memory controller 1320. The host may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host may be configured to send data to the memory 1310. Alternatively, the host may be configured to receive data from the memory 1310.

[0224] According to some implementations, the memory controller 1320 is also coupled to a host. The memory controller 1320 can manage data stored in the memory 1310 and communicate with the host.

[0225] In some implementations, the memory controller 1320 is designed to operate in low duty cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0226] In some implementations, the memory controller 1320 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0227] The memory controller 1320 can be configured to control the operation of the memory 1310, such as read, erase, and program operations. The memory controller 1320 can also be configured to manage various functions relating to data stored or to be stored in the memory 1310, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 1320 is also configured to process error correction codes (ECC) relating to data read from or written to the memory 1310.

[0228] The memory controller 1320 can also perform any other suitable functions, such as formatting the memory 1310. The memory controller 1320 can communicate with external devices according to a specific communication protocol.

[0229] The memory controller 1320 and one or more memories 1310 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 1300 can be implemented and packaged into different types of end electronic products.

[0230] Schematic illustration: The memory controller 1320 and a single memory 1310 can be integrated into a memory card. The memory card can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card may also include a memory card connector that couples the memory card to the host computer.

[0231] Schematic, the memory controller 1320 and multiple memories 1310 may be integrated into a solid-state drive (SSD). In some embodiments, the storage capacity and / or operating speed of the SSD is greater than that of the memory card.

[0232] It is understood that the memory controller 1320 can perform memory programming methods as provided in any embodiment of this disclosure.

[0233] This application provides a control circuit that includes programmable logic circuitry and / or program instructions. The control circuit can be used to implement the memory programming method provided in the foregoing embodiments of this application.

[0234] Indicative, such as Figure 13 The memory 1310 shown includes: a memory array unit and a peripheral logic unit. The memory array unit includes a memory string, and the memory string includes memory cells. The peripheral logic unit includes a control circuit.

[0235] The control circuit is configured to apply a first programming voltage to a selected word line with a first pulse width during a first pulse phase, and to apply a second programming voltage to the selected word line with a second pulse width during a second pulse phase.

[0236] The first pulse phase and the second pulse phase are two of a plurality of pulse phases for programming a selected memory cell, the selected memory cell is the memory cell to be programmed, and the selected word line is the word line connected to the selected memory cell;

[0237] The selected memory cell is programmed using a step-pulse voltage programming method. The first pulse phase precedes the second pulse phase in timing, the width of the first pulse is greater than the width of the second pulse, and the first programming voltage is less than the second programming voltage.

[0238] In an optional embodiment, the plurality of pulse phases are divided into a first programming phase and a second programming phase;

[0239] The pulse width of each pulse stage in the first programming stage corresponds to the first pulse width, and the first programming stage includes at least one pulse stage including the first pulse stage.

[0240] The pulse width of each pulse stage in the second programming stage corresponds to the second pulse width, and the second programming stage includes at least one pulse stage including the second pulse stage.

[0241] In an optional embodiment, the first programming stage includes a first number of pulse stages arranged in succession, and the second programming stage includes a second number of pulse stages arranged in succession.

[0242] or,

[0243] In the first programming stage, the programming voltage of each pulse stage is less than the stage voltage threshold, and in the second programming stage, the programming voltage of each pulse stage is greater than the stage voltage threshold.

[0244] In an optional embodiment, the pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

[0245] In an optional embodiment, the first programming voltage corresponds to a first initial programming voltage at the beginning of the first pulse phase, the first programming voltage corresponds to a first termination programming voltage at the end of the first pulse phase, and the first initial programming voltage is less than the first termination programming voltage.

[0246] The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase, and the second programming voltage corresponds to the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

[0247] In an optional embodiment, the difference between the first termination programming voltage and the first initial programming voltage is a first voltage difference;

[0248] The difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference;

[0249] The first pressure difference is greater than the second pressure difference.

[0250] In an optional embodiment, the first programming voltage increases in a stepwise manner during the first pulse phase and the second programming voltage increases in a stepwise manner during the second pulse phase.

[0251] or,

[0252] Both the first programming voltage and the second programming voltage show a linear increasing trend during the pulse phase;

[0253] or,

[0254] The first programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the first pulse phase, and the second programming voltage exhibits either a step-like increasing trend or a linear increasing trend during the second pulse phase.

[0255] In an optional embodiment, the control circuitry is further configured to apply a third programming voltage to the selected word line with a third pulse width during the third pulse phase;

[0256] The second pulse phase precedes the third pulse phase in timing, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

[0257] In summary, the memory provided in this application uses different pulse bandwidths in three pulse stages during the programming process. The corresponding pulse bandwidth is used for programming according to the programming voltage of the pulse stage. When the programming voltage is low, a longer pulse bandwidth is used to ensure sufficient programming time; while when the programming voltage is high, a shorter pulse bandwidth is used to increase the boosting potential and reduce the margin loss caused by programming voltage interference.

[0258] This application provides a computer-readable storage medium storing instructions that, when executed on a control circuit, implement the memory programming method provided in the foregoing embodiments of this application.

[0259] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "at least one" means one or more, and the term "multiple" means two or more, unless otherwise expressly defined.

[0260] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0261] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for programming a memory, characterized in that, The method includes: During the first time interval of the first pulse phase, an intermediate voltage is applied to the selected word line; During the second time period of the first pulse phase, a transition voltage is applied to the selected word line; During the third time period of the first pulse phase, a first programming voltage is applied to the selected word line; Wherein, the second time period of the first pulse phase is after the first time period of the first pulse phase, the third time period of the first pulse phase is after the second time period of the first pulse phase, the first programming voltage is greater than the transition voltage, and the transition voltage is greater than the intermediate voltage.

2. The method according to claim 1, characterized in that, During the second time period of the first pulse phase, the transition voltage is applied to the selected word line in an upward trend; During the third time interval of the first pulse phase, the first programming voltage is applied to the selected word line in an upward trend. The rise rate of the transition voltage is greater than the rise rate of the first programming voltage.

3. The method according to claim 2, characterized in that, The first programming voltage increases linearly during the first pulse phase.

4. The method according to claim 1, characterized in that, During the first sub-period of the third time period of the first pulse phase, the first programming voltage maintains its initial voltage value; During the second sub-time period of the third time period of the first pulse phase, the first programming voltage is raised from the initial voltage value to the boosted voltage value.

5. The method according to claim 1, characterized in that, The second time period of the first pulse phase is shorter than the third time period of the first pulse phase.

6. The method according to claim 1, characterized in that, The method further includes: During the first pulse phase, the first programming voltage is applied to the selected word line with a first pulse width; During the second pulse phase, a second programming voltage is applied to the selected word line with a second pulse width; The first pulse phase precedes the second pulse phase in timing, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

7. The method according to claim 6, characterized in that, The pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

8. The method according to claim 6, characterized in that, The method further includes: During the third pulse phase, a third programming voltage is applied to the selected word line with a third pulse width; The second pulse phase precedes the third pulse phase in timing, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

9. The method according to claim 6, characterized in that, The first programming voltage corresponds to the first initial programming voltage at the beginning of the first pulse phase, and the first programming voltage corresponds to the first termination programming voltage at the end of the first pulse phase. The first initial programming voltage is less than the first termination programming voltage. The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase, and the second programming voltage corresponds to the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

10. The method according to claim 9, characterized in that, The difference between the first termination programming voltage and the first initial programming voltage is the first voltage difference; The difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference; The first pressure difference is greater than the second pressure difference.

11. A memory, characterized in that, The memory includes: a memory array unit and peripheral circuitry, wherein the peripheral circuitry is configured as follows: During the first time interval of the first pulse phase, an intermediate voltage is applied to the selected word line; During the second time period of the first pulse phase, a transition voltage is applied to the selected word line; During the third time period of the first pulse phase, a first programming voltage is applied to the selected word line; Wherein, the second time period of the first pulse phase is after the first time period of the first pulse phase, the third time period of the first pulse phase is after the second time period of the first pulse phase, the first programming voltage is greater than the transition voltage, and the transition voltage is greater than the intermediate voltage.

12. The memory according to claim 11, characterized in that, During the second time period of the first pulse phase, the transition voltage is applied to the selected word line in an upward trend; During the third time interval of the first pulse phase, the first programming voltage is applied to the selected word line in an upward trend. The rise rate of the transition voltage is greater than the rise rate of the first programming voltage.

13. The memory according to claim 12, characterized in that, The first programming voltage increases linearly during the first pulse phase.

14. The memory according to claim 11, characterized in that, During the first sub-period of the third time period of the first pulse phase, the first programming voltage maintains its initial voltage value; During the second sub-time period of the third time period of the first pulse phase, the first programming voltage is raised from the initial voltage value to the boosted voltage value.

15. The memory according to claim 11, characterized in that, The second time period of the first pulse phase is shorter than the third time period of the first pulse phase.

16. The memory according to claim 11, characterized in that, The peripheral circuit is also configured to: During the first pulse phase, the first programming voltage is applied to the selected word line with a first pulse width; During the second pulse phase, a second programming voltage is applied to the selected word line with a second pulse width; The first pulse phase precedes the second pulse phase in timing, the first pulse width is greater than the second pulse width, and the first programming voltage is less than the second programming voltage.

17. The memory according to claim 16, characterized in that, The pulse width of the pulse phase is negatively correlated with the magnitude of the programming voltage applied to the selected word line.

18. The memory according to claim 16, characterized in that, The peripheral circuit is also configured to: During the third pulse phase, a third programming voltage is applied to the selected word line with a third pulse width; The second pulse phase precedes the third pulse phase in timing, the second pulse width is greater than the third pulse width, and the second programming voltage is less than the third programming voltage.

19. The memory according to claim 16, characterized in that, The first programming voltage corresponds to the first initial programming voltage at the beginning of the first pulse phase, and the first programming voltage corresponds to the first termination programming voltage at the end of the first pulse phase. The first initial programming voltage is less than the first termination programming voltage. The second programming voltage corresponds to the second initial programming voltage at the beginning of the second pulse phase, and the second programming voltage corresponds to the second termination programming voltage at the end of the second pulse phase. The second initial programming voltage is less than the second termination programming voltage.

20. The memory according to claim 19, characterized in that, The difference between the first termination programming voltage and the first initial programming voltage is the first voltage difference; The difference between the second termination programming voltage and the second initial programming voltage is the second voltage difference; The first pressure difference is greater than the second pressure difference.

21. A storage system, characterized in that, The storage system includes: One or more memories as described in any one of claims 11 to 20, and, A memory controller coupled to the memory and configured to control the memory.

22. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores instructions that, when executed on a control circuit, implement the memory programming method as described in any one of claims 1 to 10.

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