Total dose effect test system for NAND flash memory solid state disk

Abstract

The invention discloses a total dose effect test system for an NAND flash memory solid state disk, which comprises a test mainboard and an NAND flash memory solid state disk to be tested which are arranged in an irradiation environment, a test machine I arranged in an anti-irradiation environment, and a power supply and a test machine II which are arranged outside the irradiation environment, and is characterized in that the test mainboard is connected with the power supply through a power supply interface; data transmission between the NAND flash memory solid state disk to be tested and the first test machine is achieved through the communication interface, the first test machine communicates with the second test machine through a network cable, an operator remotely controls the first test machine through the second test machine, and working index monitoring of the NAND flash memory solid state disk to be tested is achieved through the test mainboard. And performing a board-level irradiation test and a device-level irradiation test on the to-be-tested NAND flash memory solid state disk, analyzing a monitoring result of the working index, and determining a fault mode of the to-be-tested NAND flash memory solid state disk.

Description

Technical Field

[0001] This invention belongs to the field of aerospace technology, specifically relating to a total dose effect testing system and irradiation testing method for NAND flash solid-state drives. Background Technology

[0002] NAND solid-state drives (SSDs) may experience faults such as bit flips, read / write failures, reduced read / write speeds, and current surges after irradiation. These faults manifest differently under different operating modes. Currently, there is a lack of detailed methods and standardized testing systems for the total dose effect of NAND SSDs. Existing technology 1, "Test System and Experimental Method for Space Environmental Effects of NAND Flash Solid-State Drives," mentions a total dose testing method, but the description is rather general, failing to detail the testing methods under static and dynamic operating modes, and also neglecting to consider the impact of irradiation on other chips on the overall SSD. Existing technology 2, "Single-Event Effect Testing Method and Device for Large-Capacity Solid-State Drives Based on High-Energy Particles," elaborates on the single-event effect testing method for NAND SSDs, but does not cover the testing method and device for the total dose effect. Summary of the Invention

[0003] This invention proposes a total dose effect testing system and irradiation test method for NAND flash solid-state drives, which solves the technical problems of existing testing devices and methods that cannot comprehensively detect various fault phenomena that may occur in SSDs under total dose effect and have a single testing mode.

[0004] This invention can be achieved through the following technical solutions:

[0005] A total dose effect testing system for NAND flash solid-state drives includes a test motherboard and a NAND flash solid-state drive under test set in an irradiated environment, a test unit 1 set in an irradiated environment, and a power supply and a test unit 2 set outside the irradiated environment.

[0006] The test motherboard is connected to the power supply via a power interface, and data transmission between the NAND flash memory solid-state drive under test and test machine one is achieved via a communication interface. Test machine one communicates with test machine two via a network cable.

[0007] The operator remotely controls the test machine 1 using the test machine 2 and uses the test motherboard to monitor the working parameters of the NAND flash memory solid-state drive under test, so as to complete the board-level irradiation test and the device-level irradiation test of the sensitive chips in the NAND flash memory solid-state drive under test, and analyze the monitoring results of the working parameters to determine the failure mode of the NAND flash memory solid-state drive under test.

[0008] Furthermore, the test motherboard includes a processor, a communication interface, a power interface, a PCIe interface, a voltage conversion chip, an MCU, a bridge chip, and a current monitoring module. The processor is connected to the current monitoring module, the voltage conversion chip, and the bridge chip. The voltage conversion chip is connected to a power source via the power interface. The current monitoring module is used to detect the operating current value of the NAND flash memory solid-state drive under test. The PCIe interface is used for high-speed data transmission from the NAND flash memory solid-state drive. The bridge chip is used to convert the high-speed data signal output from the PCIe interface into a USB serial port readable data signal, facilitating communication between the device under test and the test machine.

[0009] Furthermore, the test motherboard and the NAND flash memory solid-state drive under test are set on a test rack, and a metal shield is set on the test rack to shield specific module chip areas of the NAND flash memory solid-state drive under test.

[0010] Further operational features include real-time single-event upset detection and statistics within a defined area, recording fault time, fault data, register address, sample data, and counting the number of upsets and the number of bits. It also features single-event interruption detection capability, real-time current detection and protection, single-event latch-up detection and power-off re-energization function, and manual full disk write and read ratio functions.

[0011] An irradiation test method based on the total dose effect testing system for NAND flash solid-state drives described above, characterized by comprising the following steps:

[0012] Step 1: Divide the memory area of ​​the NAND flash solid-state drive under test into two areas, A and B. Use dynamic operation mode for area A and static bias operation mode for area B.

[0013] Step 2: Begin irradiation according to the irradiation dose points set by the indicators. During irradiation, monitor the operating current value, read / write rate value, and whether the read / write function is normal in area A, and record the monitoring results;

[0014] Step 3: During the irradiation process, acquire the stored data in region B and the read data in region A, and determine whether the data bits have flipped.

[0015] Step 4: When the irradiation dose point is reached, if the analysis results of the working indicators in Step 2 and Step 3 are both normal, then perform the 50% over-irradiation test and high-temperature annealing treatment in sequence, and then re-determine whether the working indicators in Step 2 and Step 3 are normal. If they are normal, the NAND flash memory solid-state drive under test is determined to have passed the set dose test; otherwise, the NAND flash memory solid-state drive under test is determined to have failed the test, and a fault mode is output.

[0016] The beneficial technical effects of this invention are as follows:

[0017] This invention, based on ground-based simulation testing technology, designs a testing system for the total dose effect of NAND flash memory solid-state drives and establishes corresponding testing methods. It provides two operating modes for detecting fault phenomena of NAND flash memory solid-state drives under the total dose effect, so as to comprehensively evaluate different fault phenomena: the dynamic operating mode is used to monitor changes in operating current, changes in read / write speed, and read / write function failures; the static bias mode is used to observe faults such as data bit flipping.

[0018] Furthermore, this invention also supports detailed observation and analysis of the fault phenomena and fault location of different chips or the entire hard drive on NAND flash solid-state drives after irradiation. By combining board-level and device-level irradiation tests, the fault source appearing in the board-level test can be accurately located to the specific device-level chip on the NAND solid-state drive, thus providing important support for fault analysis and radiation-resistant design. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the overall structure of the total dose effect testing system of the present invention;

[0020] Figure 2 This is a schematic diagram of the firmware functional structure of the test motherboard of the present invention;

[0021] Figure 3 This is a schematic diagram of the method for conducting irradiation tests using the total dose effect testing system of the present invention;

[0022] Figure 4 This is a graph showing the dynamic current values ​​of a Western Digital SSD at several dose points during total dose effect testing using this invention.

[0023] Figure 5 This is a graph showing the dynamic current values ​​of a Samsung SSD at several dose points during total dose effect testing using this invention.

[0024] Figure 6 This is a reading rate graph of Western Digital samples at various dose points for total dose effect testing using this invention;

[0025] Figure 7 This is a reading rate graph of a Samsung sample at various dose points used in the total dose effect test conducted using this invention. Detailed Implementation

[0026] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings and practical examples.

[0027] This invention provides a total dose effect testing system for NAND flash memory solid-state drives (SSDs), including a test motherboard and a NAND flash memory SSD under test, both placed in an irradiation environment; a first test unit placed in a radiation-proof environment; and a power supply and a second test unit placed outside the irradiation environment. The test motherboard is connected to the power supply via a power interface and enables data transmission between the NAND flash memory SSD under test and the first test unit via a communication interface. The first test unit communicates with the second test unit via a network cable. An operator remotely controls the first test unit using the second test unit and utilizes the test motherboard to monitor the operating parameters of the NAND flash memory SSD under test, thereby completing the irradiation test. The monitoring results of the operating parameters are analyzed to determine the failure mode of the NAND flash memory SSD under test. This invention, through monitoring and analyzing operating parameters, can identify various possible failure modes of NAND flash memory SSDs, including data bit flipping, surge in operating current, loss of read / write functionality, and decreased read / write speed. It also provides both static and dynamic testing modes to comprehensively evaluate different failure phenomena. Furthermore, by combining board-level and device-level irradiation tests, this invention can accurately locate the fault source in the board-level test to the specific device-level chip on the NAND flash solid-state drive, thereby providing important support for fault analysis and radiation-resistant design and solving the problem that existing technologies cannot achieve fault location.

[0028] Specifically as follows:

[0029] like Figure 1 As shown, a total dose effect testing system for NAND flash solid-state drives includes a test motherboard, a NAND flash solid-state drive under test, a test power supply, a test machine one, and a test machine two. The NAND flash solid-state drive under test, the test motherboard, and the test machine one are all placed in a total dose irradiation test environment, while the power supply and the test machine two are placed outside the total dose irradiation test environment.

[0030] The test motherboard is connected to the test machine 1 via a data transmission line and a signal control line. The data transmission line transmits the data exported from the test motherboard to the test machine 1, and the signal control line transmits the control signals to be executed by the test machine 1 to the test motherboard.

[0031] The test motherboard includes a communication interface, a power interface, a PCIe interface, a voltage conversion chip, an MCU, a bridge chip, and a current monitoring module. The communication interface facilitates data and control signal transmission between the NAND flash memory SSD under test and the test machine. The bridge chip handles data transmission between the NAND flash memory SSD and the test machine but does not directly process the data. The MCU handles signal transmission between the NAND flash memory SSD and the test machine, and simultaneously controls the current monitoring module to monitor the current of the NAND flash memory SSD through the PCIe interface. The power interface converts the voltage supplied by the power supply to the NAND flash memory SSD by a voltage conversion chip, and connects to the power supply via two positive and negative power lines. The power supply then supplies power to the test motherboard through these two positive and negative power lines.

[0032] The NAND flash solid-state drive under test is connected to the test motherboard via a PCIe interface, and transmits its internally stored data to the test motherboard via the PCIe interface.

[0033] Test machine 1 is connected to test machine 2 via a wireless communication module such as an Ethernet cable. Test machine 2 can remotely operate test machine 1 via the Ethernet cable, and thus operate the test motherboard.

[0034] Preferably, the total dose irradiation test environment is mainly composed of a cobalt-60 radiation source. Since the NAND flash memory solid-state drive under test and the test motherboard are connected as one unit through the PCIe interface and NVMe bridge chip, the NAND flash memory solid-state drive under test and the test motherboard are fixed together on the test rack within the radiation range of the cobalt-60 radiation source. Considering that the NAND flash memory solid-state drive under test will undergo separate board-level and device-level irradiation tests, a metal shield is set on the test rack to specifically shield the corresponding chip areas that do not need to be irradiated. For example, when conducting device-level irradiation tests, the position of the metal shield is adjusted to selectively shield specific module chip areas of the NAND flash memory solid-state drive under test; while when conducting board-level irradiation tests, it is not necessary to use a metal shield to shield the NAND flash memory solid-state drive under test.

[0035] The outer perimeter of the first test unit is equipped with lead bricks for shielding against radiation, while the power supply and the second test unit are placed outside the radiation range of the cobalt-60 radiation source. The second test unit communicates with the first test unit via a network cable.

[0036] The firmware functional structure diagram of the test motherboard is as follows: Figure 2 As shown, it includes the following modules:

[0037] (a) Interface layer, whose main function is to connect the test machine, power supply and NAND flash memory solid-state drive under test; (b) Driver layer, whose main function is to interact with hardware devices, responsible for managing and controlling the specific operation of hardware devices; (c) Business layer, whose main function is to perform various test operations, including random and manual operations, write and read operations, power-on and power-off operations, etc.; (d) Application layer, whose main function is to save test data and display data in images.

[0038] like Figure 3 As shown, the present invention also provides an irradiation test method based on a total dose effect test system for NAND flash solid-state drives, comprising the following steps:

[0039] Step 1: Divide the memory area of ​​the NAND flash solid-state drive under test into two areas, A and B. Use dynamic operation mode for area A and static bias operation mode for area B.

[0040] S1. Complete the hardware setup and connection of the test system, measure and record relevant parameters, including the operating current and read / write speed of the NAND flash solid-state drive under test under no-irradiation conditions. At the same time, divide the memory area of ​​the NAND flash solid-state drive under test into two regions, A and B. Region A remains unchanged and is not operated; data writing operations are performed in region B.

[0041] Specifically, the testing software was opened, and the operating current of the NAND flash memory solid-state drive under normal conditions was found to be around 0.22mA. The write and read speed of the NAND flash memory solid-state drive under normal conditions was found to be around 12.5Mb / s. 10Gb of memory in the NAND flash memory solid-state drive under test was selected and divided into two areas of equal capacity, A and B. Area A was not operated on, and area B was randomly written with four types of data: "55", "00", "AA" and "FF".

[0042] S2, depending on the level type of the current irradiation test, such as device level or board level, determine whether it is necessary to selectively block specific module chip areas of the tested NAND flash solid-state drive by adjusting the position of the metal shield. Note: Device level requires this, board level does not.

[0043] Step 2: Monitor the operating current value, read / write speed value, and read / write function of area A, and output the monitoring results corresponding to the NAND flash solid-state drive under test when it reaches the specified point of the test design scheme;

[0044] S3. Before the irradiation test, calibrate and adjust the dose rate. For example, if the calibrated dose rate is 50 rad / s, ensure that the dose rate of the γ-rays emitted by the irradiation source reaching the NAND flash solid-state drive under test meets the specified value of the test design scheme.

[0045] S4. After starting the irradiation test, select the working mode: use dynamic operation mode for area A and static bias operation mode for area B.

[0046] S5. Monitor the working indicators of the NAND flash solid-state drive under test, including working current value, read and write speed, and read and write function, and determine whether there is a functional abnormality. The functional abnormality includes abnormal fluctuation of working current value, abnormal fluctuation of read and write speed, and interruption of read and write function. If so, jump to step S6, S7, and S8; otherwise, jump to step S12.

[0047] S6 collects and records the read and write operation status logs of the NAND flash solid-state drive under irradiation;

[0048] S7 collects and records the operating current curve of the NAND flash solid-state drive under irradiation and plots the log.

[0049] S8 collects and records the read and write speed curves of the NAND flash solid-state drive under irradiation, and plots logs.

[0050] S9. Based on the log information collected in step S7, determine whether the internal operating current of the NAND flash memory solid-state drive under test exhibits abnormal fluctuations during irradiation, and plot the fluctuations in the internal operating current of the NAND flash memory solid-state drive under test during irradiation as shown in the figure. Figure 4 , 5 As shown. From Figure 4 It can be determined that as the cumulative dose increases, the device's operating current also increases until the cumulative dose causes the device to malfunction.

[0051] S10, Based on the log information collected in step S6, determine whether the NAND flash memory solid-state drive under test has experienced a read / write failure, and plot the read / write speeds as indicated by the NAND flash memory solid-state drive under test experiencing a read / write failure. Figure 6 , 7 As shown in the figure, it can be determined from the graph that the device read / write rate has not changed significantly;

[0052] S11, Based on the log information collected in step S8, determine whether the read and write speeds of the NAND flash memory solid-state drive under test exhibit abnormal fluctuations during the irradiation period, and plot the fluctuations in read and write speeds of the NAND flash memory solid-state drive under test throughout the irradiation test, as shown in the following figure. Figure 6 , 7 As shown in the figure, it can be determined from the graph that the device read / write rate has not changed significantly;

[0053] S12, determine whether the NAND flash solid-state drive under test has reached the specified point of the test design scheme, that is, the total dose value that the NAND flash solid-state drive under test needs to receive when passing the total dose test according to the test outline. If yes, jump to step S13; if no, jump to S5 and continue to observe the working indicators of the NAND flash solid-state drive under test.

[0054] Step 3: Obtain the stored data in area B and the read data in area A, and determine whether the data bits have flipped.

[0055] S13, read the data stored in area B, and collect the data read during the dynamic read and write process in area A, and collect the data bit information of these two areas;

[0056] S14, compare the data collected in step S13 with the original written data to analyze the flipping of data bits;

[0057] Step 4: When the irradiation dose point is reached, determine whether the NAND solid-state drive under test meets the requirements for aerospace use based on the analysis results of Step 2 and Step 3, and output the fault mode.

[0058] If the analysis results of the working indicators in steps two and three are normal, then perform the 50% over-irradiation test and high-temperature annealing treatment in sequence, and then re-determine whether the working indicators in steps two and three are normal. If they are normal, the NAND flash memory solid-state drive under test is determined to have passed the set dose test; otherwise, the NAND flash memory solid-state drive under test is determined to have failed the test and a fault mode is output.

[0059] Specifically as follows:

[0060] S15. After reaching the irradiation dose point, irradiation stops. Based on the analysis results of steps S9, S10, S11 and S14, determine whether all relevant parameters of the NAND flash solid-state drive under test are normal. The working indicators of relevant parameters include stable operating current value, stable read / write rate value, normal read / write function, and no data bit flipping. If yes, proceed to step S18; otherwise, proceed to step S16.

[0061] S16, room temperature annealing of the NAND flash solid-state drive under test;

[0062] S17. After room temperature annealing, determine whether all relevant parameters of the NAND flash memory solid-state drive under test are normal. If yes, proceed to step S18; otherwise, proceed to step S20 and determine that the sample is not suitable for aerospace applications.

[0063] S18, a 50% over-irradiation test is conducted on the NAND flash solid-state drive under test that has passed the room temperature annealing test;

[0064] After the S19 50% over-irradiation test, the NAND flash memory solid-state drive under test is then subjected to high-temperature annealing.

[0065] S20. After the high-temperature annealing test, the working parameters of the NAND flash solid-state drive under test are checked again to see if they are normal. If they are, the NAND flash solid-state drive under test is deemed to be qualified and meets the requirements for aerospace use. Otherwise, the NAND flash solid-state drive under test is deemed to be unqualified and a fault mode is output, indicating that it does not meet the requirements for aerospace use. That is, all working parameters must be qualified to be considered to meet the requirements for aerospace use. Partial qualification still does not meet the requirements for aerospace use.

[0066] For example, after irradiation stops, based on the analysis results of steps S9, S10, S11, S13 and S15, it is determined that all relevant parameters of the NAND flash solid-state drive under test are not normal, so the process jumps to step S17.

[0067] S17, the NAND flash solid-state drive to be tested is annealed at room temperature for 128 hours;

[0068] S18. After room temperature annealing, not all relevant parameters of the NAND flash solid-state drive under test were normal, and data bits still exhibited flipping phenomena, thus ending the test process.

[0069] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A total dose effect testing system for NAND flash solid-state drives, characterized in that: The system includes a test motherboard and a NAND flash memory solid-state drive (SSD) under test, both set up in an irradiation environment; a test machine 1 set up in an irradiation-proof environment; and a power supply and a test machine 2 located outside the irradiation room. The test motherboard is connected to the power supply via a power interface and transmits data between the NAND flash memory SSD and the test machine 1 via a communication interface. The test machine 1 communicates with the test machine 2 via a network cable. Operators can remotely control the test machine 1 using the test machine 2 and monitor the operating parameters of the NAND flash memory SSD using the test motherboard. This allows for board-level irradiation testing of the NAND flash memory SSD and device-level irradiation testing of sensitive chips within it. The monitoring results of the operating parameters are then analyzed to determine the failure mode of the NAND flash memory SSD under test.

2. The total dose effect testing system for NAND flash solid-state drives according to claim 1, characterized in that: The test motherboard includes a processor, a communication interface, a power interface, a PCIe interface, a voltage conversion chip, an MCU, a bridge chip, and a current monitoring module. The processor is connected to the current monitoring module, the voltage conversion chip, and the bridge chip. The voltage conversion chip is connected to the power supply through the power interface. The current monitoring module is used to detect the operating current value of the NAND flash memory solid-state drive under test. The PCIe interface is used for high-speed data transmission from the NAND flash memory solid-state drive and for signal transmission between the test motherboard and the NAND flash memory solid-state drive under test. The bridge chip is used to convert the high-speed data signal output from the PCIe interface into a USB serial port readable data signal to assist communication between the NAND flash memory solid-state drive under test and the test machine.

3. The total dose effect testing system for NAND flash solid-state drives according to claim 1, characterized in that: The test motherboard and the NAND flash memory solid-state drive under test are set on a test rack, and a metal shield is set on the test rack to shield specific module chip areas of the NAND flash memory solid-state drive under test.

4. The total dose effect testing system for NAND flash solid-state drives according to claim 1, characterized in that: The operating characteristics include real-time single-event upset detection and statistics within a set area, recording fault time, fault data, register address, sample data and counting the number of upsets and the number of bits, having single-event interruption detection capability, real-time current detection and protection, single-event latch-up detection and power-off re-energization function, and manual full disk write and read ratio functions.

5. An irradiation test method based on the total dose effect testing system for NAND flash solid-state drives according to claim 1, characterized in that... Includes the following steps: Step 1: Divide the memory area of ​​the NAND flash solid-state drive under test into two areas, A and B. Use dynamic operation mode for area A and static bias operation mode for area B. Step 2: Start irradiation according to the irradiation dose point set by the index. During the irradiation process, monitor the working current value, read / write rate value, and whether the read / write function is normal in area A, and record the monitoring results. Step 3: During the irradiation process, acquire the stored data in region B and the read data in region A, and determine whether the data bits have flipped. Step 4: When the irradiation dose point is reached, if the analysis results of the working indicators in Step 2 and Step 3 are both normal, then perform the 50% over-irradiation test and high-temperature annealing treatment in sequence, and then re-determine whether the working indicators in Step 2 and Step 3 are normal. If they are normal, the NAND flash memory solid-state drive under test is determined to have passed the set dose test; otherwise, the NAND flash memory solid-state drive under test is determined to have failed the test, and a fault mode is output.

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