High-heat-dissipation packaging method and structure

Abstract

The invention discloses a high-heat-dissipation packaging method and a high-heat-dissipation packaging structure. The high-heat-dissipation packaging method comprises the following steps: step 1, mounting a chip on a carrier plate; 2, covering a metal layer on the surface of the chip; step 3, wrapping all the chips with a dielectric layer; 4, thinning the dielectric layer until the chip is exposed; 5, bonding the heat dissipation layer on the surface of the chip, and then removing the carrier plate to expose the metal pad surface of the chip; 6, preparing a metal circuit layer I on the metal pad surface of the chip; 7, preparing an insulating dielectric layer on the first metal circuit layer; 8, preparing a metal circuit layer II on the insulating dielectric layer; ninthly, preparing an insulating layer on the second metal circuit layer; and 10, performing ball mounting, and cutting into single packaging bodies. The heat dissipation layer is arranged, so that heat is dissipated in time, and the reliability of a product is improved; the metal layer is arranged to realize heat conduction and signal shielding, so that the signal quality of the product is improved; the packaging efficiency is high, tens of thousands of packaging bodies can be packaged at a time, and therefore the packaging cost is remarkably reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a high heat dissipation packaging method and structure. Background Technology

[0002] With the continuous development of semiconductor technology, various electronic devices are increasingly showing a trend of functional integration, and the integration requirements for chips are also becoming higher and higher. Therefore, chip packaging faces enormous challenges. Traditional packaging usually processes single chips or several chips together, which is inefficient and difficult to meet the increasingly dense wiring requirements. Conventional wafer-level packaging is mostly single-chip packaging, making it difficult to achieve high-integration packaging. Fan-out packaging is a flexible and advanced packaging technology that can package multiple chips together.

[0003] In mainstream fan-out wafer-level packaging, the chip is surrounded by a suitable material and a fan-out packaging structure is formed by molding. The thermal management performance of the packaged device is greatly limited. In addition, the process is also characterized by high cost and complexity, which leads to problems such as high cost and heat dissipation. Summary of the Invention

[0004] To address the multi-chip integration issues in existing technologies, improve packaging efficiency, and reduce packaging costs, this invention provides a high-heat-dissipation packaging method and structure.

[0005] To achieve the above objectives and technical effects, the technical solution adopted by this invention is as follows:

[0006] A high heat dissipation packaging method includes the following steps:

[0007] The first step is to mount several chips onto a carrier board;

[0008] The second step is to cover the surface of each chip with a metal layer;

[0009] The third step is to wrap all the chips with a dielectric layer;

[0010] The fourth step is to thin the dielectric layer until the chip is exposed;

[0011] The fifth step is to bond the heat dissipation layer to the chip surface, and then remove the carrier board to expose the metal pad surface of the chip.

[0012] Step 6: Fabricate metal circuit layer 1 on the metal pad surface of the chip;

[0013] Step 7: Prepare an insulating dielectric layer on the metal circuit layer 1;

[0014] Step 8: Prepare a second metal circuit layer on the insulating dielectric layer;

[0015] Step 9: Prepare an insulating layer on the second metal circuit layer;

[0016] Step 10: Plant the balls and cut them into individual packages.

[0017] Furthermore, in the first step, several chips of the same or different types are mounted on a carrier board through a temporary bonding layer. The chips include storage, computing, or radio frequency chips. The temporary bonding layer is an adhesive or film material, which is applied to the carrier board by spraying or pressing. The carrier board is made of organic material or glass.

[0018] Furthermore, in the second step, the metal layer is made of aluminum, titanium copper, or a conductive colloid.

[0019] Furthermore, in the fifth step, the heat dissipation layer is bonded to the chip surface using a bonding layer.

[0020] Furthermore, the heat dissipation layer is made of metal.

[0021] Furthermore, in step seven, when the insulating dielectric layer uses an insulating material with photolithography capabilities, the opening is achieved through photolithography; when the insulating dielectric layer uses an insulating material without photolithography capabilities, the opening is achieved through laser.

[0022] Furthermore, in the ninth step, when the insulating layer uses an insulating material with photolithography capabilities, the opening is achieved through photolithography; when the insulating layer uses an insulating material without photolithography capabilities, the opening is achieved through laser.

[0023] Furthermore, in step ten, solder balls are prepared at the opening positions of the metal pads on the second metal circuit layer of step nine.

[0024] The present invention also discloses a high heat dissipation packaging structure prepared by a high heat dissipation packaging method.

[0025] Furthermore, the high heat dissipation packaging structure includes a heat dissipation layer, on which several chips of the same or different types are disposed. Each chip surface is covered with a metal layer. A metal circuit layer one is prepared on the metal pad surface of the chip. An insulating dielectric layer is prepared on the metal circuit layer one. A metal circuit layer two is prepared on the insulating dielectric layer. An insulating layer is prepared on the metal circuit layer two. Solder balls are prepared at the opening positions of the metal pads on the metal circuit layer two.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] 1) The substrate packaging technology can solve the multi-chip wiring problem that is difficult to solve with traditional packaging. In addition, the packaging efficiency is high, and tens of thousands of packages can be packaged at one time, thereby significantly reducing the packaging cost.

[0028] 2) A heat dissipation layer is installed to dissipate heat in a timely manner, thereby improving product reliability;

[0029] 3) A metal layer is set to achieve heat conduction and signal shielding, so that the signal will not be interfered with or interfere with nearby products, thereby improving the signal quality of the product. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of the first step of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of the second step of the present invention;

[0032] Figure 3 This is a schematic diagram of the third step of the present invention;

[0033] Figure 4 This is a schematic diagram of the fourth step of the present invention;

[0034] Figure 5-6 This is a schematic diagram of the fifth step of the present invention;

[0035] Figure 7 This is a schematic diagram of the sixth step of the present invention;

[0036] Figure 8 This is a schematic diagram of the seventh step of the present invention;

[0037] Figure 9 This is a schematic diagram of the structure of the eighth step of the present invention;

[0038] Figure 10 This is a structural schematic diagram of the ninth step of the present invention;

[0039] Figure 11 This is a schematic diagram of the tenth step of the present invention. Detailed Implementation

[0040] The present invention will now be described in detail so that its advantages and features can be more easily understood by those skilled in the art, thereby providing a clearer and more explicit definition of the scope of protection of the present invention.

[0041] The following provides a brief overview of one or more aspects to offer a basic understanding of them. This overview is not an exhaustive summary of all conceived aspects, nor is it intended to identify key or decisive elements of all aspects, nor to define the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form to prepare for the more detailed descriptions that follow.

[0042] like Figure 1-11 As shown, this invention discloses a high heat dissipation packaging method, comprising the following steps:

[0043] First step, such as Figure 1As shown, several chips of the same or different types are attached to a carrier board 2 through a temporary bonding layer 1. The chips can be high-power chips such as memory, computing or radio frequency chips. The temporary bonding layer 1 can be an adhesive material, which is sprayed onto the carrier board 2, or it can be an adhesive film material, which is laminated onto the carrier board 2. The carrier board 2 can be an organic material, glass or other materials.

[0044] The second step, as Figure 2 As shown, a metal layer 3 is coated on the chip surface. This can be achieved by plasma sputtering, using aluminum or titanium copper as the corresponding metal, or by spraying, using silver paste or other conductive colloids. This metal layer 3 can be used for heat conduction or signal shielding.

[0045] The third step, as Figure 3 As shown, all chips are wrapped with dielectric layer 4, which is generally achieved through plastic encapsulation technology. Dielectric layer 4 is an insulating plastic encapsulation material.

[0046] Step four, as Figure 4 As shown, the dielectric layer 4 is thinned until the chip is exposed. The method is usually grinding, which is a conventional process.

[0047] Step 5, as Figure 5 As shown, the heat dissipation layer 5 is bonded to the chip surface via the bonding layer 6. The heat dissipation layer 5 can be made of copper, aluminum, or other metals, or other heat dissipation materials or other special heat dissipation structures. The bonding layer 6 is a conductive adhesive layer, generally composed of an adhesive resin and a conductive substance. The conductive substance can be metal powder or graphite powder. The conductive adhesive layer allows the chip and the heat dissipation layer 5 to be in direct contact, facilitating rapid heat dissipation. Then, the carrier board 2 is removed, as shown... Figure 6 As shown;

[0048] Step 6, as follows Figure 7 As shown, metal circuit layer 7 is fabricated by forming a seed layer, photolithographically patterning the circuit, electroplating a metal layer, removing the photoresist and etching the metal layer, thereby forming metal circuit layer 7. The seed layer can be achieved by metal sputtering or copper plating. Photolithography involves applying a photolithographic film to the substrate using vacuum pressing or by spraying photoresist onto the substrate. Exposure and development are conventional methods to fabricate the photolithographic pattern. The other three steps are standard processes.

[0049] Step 7, as Figure 8 As shown, an insulating dielectric layer 8 is prepared on the metal circuit layer 7. The insulating dielectric layer 8 is generally an insulating resin material. When the insulating dielectric layer 8 is an insulating material with photolithography capability, the opening can be achieved by photolithography. The insulating dielectric layer 8 can also be an insulating material without photolithography capability, in which case the opening can be achieved by laser.

[0050] Step 8, as Figure 9 As shown, in order to meet the requirements of circuit setup, it is generally necessary to prepare metal circuit layer 2 9, and the preparation method and materials are similar to those of metal circuit layer 1 7.

[0051] Step 9, as Figure 10 As shown, an insulating layer 10 is prepared on the metal circuit layer 9. The insulating layer 10 is generally made of insulating resin material. The preparation method is the same as that of the insulating dielectric layer 8.

[0052] Step 10, as follows Figure 11 As shown, solder balls 11 are prepared at the metal pad positions on the second metal circuit layer 9 and cut into individual packages.

[0053] The present invention also discloses a high heat dissipation packaging structure prepared by the high heat dissipation packaging method described above, including a heat dissipation layer 5, a plurality of chips of the same or different types disposed on the heat dissipation layer 5, each chip surface covered with a metal layer 3, a metal circuit layer 7 prepared on the metal pad surface of the chip, an insulating dielectric layer 8 prepared on the metal circuit layer 7, a second metal circuit layer 9 prepared on the insulating dielectric layer 8, an insulating layer 10 prepared on the second metal circuit layer 9, and solder balls 11 prepared at the opening positions of the metal pads on the second metal circuit layer 9.

[0054] Example 1

[0055] like Figure 1-11 As shown, a high heat dissipation packaging method includes the following steps:

[0056] First step, such as Figure 1 As shown, three different types of chips (referred to as chip 1 12, chip 2 13, and chip 3 14 respectively) are attached to the carrier board 2 through a temporary bonding layer 1. Chip 1 12, chip 2 13, and chip 3 14 are high-power chips for storage, computing, and radio frequency, respectively. The temporary bonding layer 1 is a conventional adhesive film material, which is covered on the carrier board 2 using a pressure film. The carrier board 2 is made of glass.

[0057] The second step, as Figure 2 As shown, a metal layer 3 is covered on the surface of each chip. The method can be plasma sputtering, and the corresponding metal can be aluminum. The metal layer 3 is used for heat conduction and signal shielding.

[0058] The third step, as Figure 3 As shown, all chips are wrapped with dielectric layer 4, which is generally achieved through plastic encapsulation technology. Dielectric layer 4 is a conventional insulating plastic encapsulation material.

[0059] Step four, as Figure 4 As shown, the dielectric layer 4 is thinned until the chip is exposed. The method is usually grinding, which is a conventional process.

[0060] Step 5, as Figure 5As shown, the heat dissipation layer 5 is bonded to the chip surface via the bonding layer 6. The heat dissipation layer 5 is made of copper, and the bonding layer 6 is a conventional conductive adhesive layer, typically composed of adhesive polyurethane resin and graphite carbon powder. The conductive adhesive layer allows direct contact between the chip and the heat dissipation layer 5, facilitating rapid heat dissipation. Then, the carrier board 2 is removed, as shown... Figure 6 As shown;

[0061] Step 6, as follows Figure 7 As shown, metal circuit layer 7 is fabricated by forming a seed layer, photolithographically patterning the circuit, electroplating a metal layer, removing the photoresist and etching the metal layer, thereby forming metal circuit layer 7. The seed layer can be achieved by metal sputtering. Photolithography involves vacuum pressing a photolithographic film onto the substrate; exposure and development are conventional methods that can produce the photolithographic pattern. The other three steps are also conventional processes.

[0062] Step 7, as Figure 8 As shown, an insulating dielectric layer 8 is prepared on the metal circuit layer 7. The insulating dielectric layer 8 is generally an insulating resin material. When the insulating dielectric layer 8 is an insulating material with photolithography capability, the opening is achieved by photolithography.

[0063] Step 8, as Figure 9 As shown, in order to meet the requirements of circuit setup, it is generally necessary to prepare metal circuit layer 2 9, and the preparation method and materials are similar to those of metal circuit layer 1 7.

[0064] Step 9, as Figure 10 As shown, an insulating layer 10 is prepared on the metal circuit layer 9. The insulating layer 10 is generally made of insulating resin material. The preparation method is the same as that of the insulating dielectric layer 8.

[0065] Step 10, as follows Figure 11 As shown, solder balls 11 are prepared at the metal pad positions on the second metal circuit layer 9 and cut into individual packages.

[0066] This embodiment also discloses a high heat dissipation packaging structure prepared by the high heat dissipation packaging method described above, including a heat dissipation layer 5, on which a plurality of chips of the same or different types are disposed, each chip surface is covered with a metal layer 3, a metal circuit layer 7 is prepared on the metal pad surface of the chip, an insulating dielectric layer 8 is prepared on the metal circuit layer 7, a second metal circuit layer 9 is prepared on the insulating dielectric layer 8, an insulating layer 10 is prepared on the second metal circuit layer 9, and solder balls 11 are prepared at the opening positions of the metal pads on the second metal circuit layer 9.

[0067] Any parts or structures not specifically described in this invention can be made using existing technologies or products, and will not be elaborated upon here.

[0068] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A high heat dissipation packaging method, characterized in that, Includes the following steps: The first step is to mount several chips onto a carrier board; The second step is to cover the surface of each chip with a metal layer; The third step is to wrap all the chips with a dielectric layer; The fourth step is to thin the dielectric layer until the chip is exposed; The fifth step is to bond the heat dissipation layer to the chip surface, and then remove the carrier board to expose the metal pad surface of the chip. Step 6: Fabricate metal circuit layer 1 on the metal pad surface of the chip; Step 7: Prepare an insulating dielectric layer on the metal circuit layer 1; Step 8: Prepare a second metal circuit layer on the insulating dielectric layer; Step 9: Prepare an insulating layer on the second metal circuit layer; Step 10: Plant the balls and cut them into individual packages.

2. The high heat dissipation packaging method according to claim 1, characterized in that, In the first step, several chips of the same or different types are mounted on a carrier board through a temporary bonding layer. The chips include storage, computing, or radio frequency chips. The temporary bonding layer is an adhesive or film material, which is applied to the carrier board by spraying or pressing. The carrier board is made of organic material or glass.

3. The high heat dissipation packaging method according to claim 1, characterized in that, In the second step, the metal layer is made of aluminum, titanium copper, or conductive colloid.

4. The high heat dissipation packaging method according to claim 1, characterized in that, In the fifth step, the heat dissipation layer is bonded to the chip surface using a bonding layer.

5. The high heat dissipation packaging method according to claim 4, characterized in that, The heat dissipation layer is made of metal.

6. The high heat dissipation packaging method according to claim 1, characterized in that, In the seventh step, when the insulating dielectric layer uses an insulating material with photolithography capabilities, the opening is achieved by photolithography; when the insulating dielectric layer uses an insulating material without photolithography capabilities, the opening is achieved by laser.

7. The high heat dissipation packaging method according to claim 1, characterized in that, In the ninth step, when the insulating layer uses an insulating material with photolithography capabilities, the opening is achieved through photolithography; when the insulating layer uses an insulating material without photolithography capabilities, the opening is achieved through laser.

8. The high heat dissipation packaging method according to claim 1, characterized in that, In step 10, solder balls are prepared at the opening positions of the metal pads on the second metal circuit layer in step 9.

9. A high heat dissipation packaging structure prepared by any one of the high heat dissipation packaging methods according to claims 1-8.

10. A high heat dissipation packaging structure according to claim 9, characterized in that, The device includes a heat dissipation layer on which several chips of the same or different types are disposed. Each chip surface is covered with a metal layer. A metal circuit layer one is prepared on the metal pad surface of the chip. An insulating dielectric layer is prepared on the metal circuit layer one. A metal circuit layer two is prepared on the insulating dielectric layer. An insulating layer is prepared on the metal circuit layer two. Solder balls are prepared at the opening positions of the metal pads on the metal circuit layer two.

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