A method and structure for a multi-layer stacked chip package

Abstract

The embodiment of the present disclosure provides a multi-layer stacked chip packaging method and a packaging structure. The packaging method comprises: sequentially stacking a plurality of chips on a substrate to form a chip packaging module; providing a plastic packaging jig, the plastic packaging jig comprising a first mold and a second mold matched with the first mold, and laying a metal layer in the first mold; forming a first plastic packaging layer with a preset thickness on the metal layer; placing the uppermost chip in the chip packaging module on the first plastic packaging layer; covering the second mold on the first mold to form a second plastic packaging layer wrapping the chip packaging module; and removing the plastic packaging jig to obtain a multi-layer stacked chip packaging structure. The metal layer is formed on the surface of the plastic packaging layer in the entire chip packaging structure by the method, which avoids the transmission and positioning problems of the ultra-thin metal layer in the mounting process, improves the strength of the ultra-thin chip packaging structure, and improves the reliability of the ultra-thin chip packaging structure.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a multi-layer stacked chip packaging method and packaging structure. BACKGROUND

[0002] The consumer electronics continues to develop towards thinness, especially for applications such as smart phones, the PoP (package on package, stacked packaging) structure is the mainstream packaging form of the processor. As shown in Figure 1 , the overall PKG thickness of the current PoP packaging form is relatively thick, which cannot meet the current market demand, and therefore it is necessary to develop an ultra-thin PoP product.

[0003] In the current packaging, due to the height limitation of gold wire forming and the protection distance limitation of plastic packaging material to gold wire, the height of the plastic packaging material to the surface of the chip is strictly limited and cannot be continuously reduced. At the same time, due to the material limitation and the strength limitation of the substrate, the production of ultra-thin substrates is extremely difficult, which limits the application of traditional packaging in ultra-thin storage stacked packaging. With the popularization of foldable screen mobile phones, packaging thinning has become a major trend, and how to reduce the thickness of PoP storage packaging has become an important technical research direction.

[0004] At present, one direction of ultra-thinning is to adopt a hybrid bonding stacked packaging method, such as Figure 2 structure, by adopting a combination of wire bonding and bump technology, and by using the flip-chip process of the top layer to cooperate with the thinning of the ultra-thin chip. However, the particle strength of the ultra-thin product will decrease with the decrease of the overall plastic package thickness. Therefore, by laying an ultra-thin metal 1 on the surface of the stacked packaging structure, the strength of the product is improved. The main difficulty of this structure lies in the surface mounting operation of the ultra-thin metal, and one problem of the process is the conveying problem of the ultra-thin metal <20 μm in the equipment track; the positioning problem of the metal during placement.

[0005] In view of the above problems, it is necessary to provide a multi-layer stacked chip packaging method and packaging structure which is reasonable in design and effective in solving the above problems. SUMMARY

[0006] The embodiment of the present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a multi-layer stacked chip packaging method and packaging structure.

[0007] An aspect of the embodiment of the present disclosure provides a multi-layer stacked chip packaging method, which comprises:

[0008] stacking a plurality of chips on a substrate in sequence to form a chip packaging module;

[0009] A plastic packaging jig is provided, which includes a first mold and a second mold matched with the first mold, a metal layer is laid in the first mold;

[0010] A first plastic packaging layer with a preset thickness is formed on the metal layer;

[0011] The uppermost chip in the chip packaging module is placed in the first plastic packaging layer;

[0012] The second mold cover is arranged on the first mold to form a second plastic packaging layer wrapping the chip packaging module;

[0013] The plastic packaging jig is removed to obtain a multilayer stacked chip packaging structure.

[0014] Optionally, forming a first plastic packaging layer with a preset thickness on the metal layer includes:

[0015] The plastic packaging material powder is uniformly covered on the metal layer by a spraying or powdering device;

[0016] The plastic packaging material powder is heated and solidified to form the first plastic packaging layer.

[0017] Optionally, before the metal layer is laid in the first mold, the method further includes:

[0018] A release film is laid in the first mold, and the metal layer is laid on the release film.

[0019] Optionally, removing the plastic packaging jig includes:

[0020] The second mold is separated from the first mold, and the release film is separated from the metal layer.

[0021] Optionally, forming the second plastic packaging layer includes:

[0022] The second plastic packaging layer is formed by an injection molding process.

[0023] Optionally, a plurality of chips are sequentially stacked on a substrate to form a chip packaging module, which includes:

[0024] The topmost chip is flip-chip arranged on the lower chip, and the remaining chips are electrically connected by bonding wires.

[0025] Optionally, the remaining chips are provided with a non-conductive adhesive layer.

[0026] Optionally, placing the uppermost chip in the chip packaging module in the first plastic packaging layer includes:

[0027] The formed chip package module is reversely arranged, so that the uppermost chip is placed downward on the first plastic encapsulation layer.

[0028] Exemplarily, the material of the first plastic encapsulation layer is the same as that of the second plastic encapsulation layer.

[0029] Another aspect of the embodiments of the present disclosure provides a multilayer stacked chip package structure, which is formed by using the multilayer stacked chip package method described above.

[0030] The multilayer stacked chip package method and structure of the embodiments of the present disclosure, the package method comprises: sequentially stacking a plurality of chips on a substrate to form a chip package module; providing a plastic encapsulation jig, the plastic encapsulation jig comprises a first mold and a second mold matched with the first mold, and a metal layer is laid in the first mold; forming a first plastic encapsulation layer with a preset thickness on the metal layer; placing the uppermost chip in the chip package module on the first plastic encapsulation layer; covering the second mold on the first mold to form a second plastic encapsulation layer wrapping the chip package module; and removing the plastic encapsulation jig to obtain a multilayer stacked chip package structure. By this method, the metal layer is formed on the surface of the plastic encapsulation layer in the entire chip package structure, avoiding the transmission and positioning problems of the ultra-thin metal layer in the mounting process, improving the strength of the ultra-thin chip package structure, and improving the reliability of the ultra-thin chip package structure. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 It is a schematic diagram of a multilayer stacked chip package structure in the prior art;

[0032] Figure 2 It is a schematic diagram of another multilayer stacked chip package structure in the prior art;

[0033] Figure 3 It is a flowchart of a multilayer stacked chip package method in an embodiment of the embodiments of the present disclosure;

[0034] Figures 4 to 10 It is a process flowchart of a multilayer stacked chip package method in another embodiment of the embodiments of the present disclosure. DETAILED DESCRIPTION

[0035] In order for those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below with reference to the drawings and specific embodiments.

[0036] As shown in the drawings, Figure 3 An aspect of the embodiments of the present disclosure provides a multilayer stacked chip package method S100, the method S100 comprises:

[0037] S110, sequentially stack a plurality of chips on a substrate to form a chip package module.

[0038] Specifically, as shown in Figure 4 a plurality of chips 120 are sequentially stacked on the substrate 110, wherein the plurality of chips 120 and the bottommost chip 120 and the substrate 110 are electrically connected by the bonding wires 121. Then, the uppermost chip is flip-chip disposed on the lower chip to form a chip package module A.

[0039] Among them, there is a non-conductive adhesive layer between the two adjacent chips 120, which can realize the fixation between the chips and also provide insulation isolation.

[0040] It should be noted that in this embodiment, the chip 120 can be a memory chip, of course, the chip 120 can also be other types of chips, and the present embodiment is not limited, and can be selected according to actual needs. In addition, the number of stacked chips 120 is not limited in this embodiment, and can be selected according to actual needs.

[0041] In this embodiment, the uppermost chip in the multilayer stacked chip is disposed on the lower chip in the form of flip-chip, and the electrical connection between the chips is realized without using bonding wires, which greatly reduces the thickness of the entire packaging structure, and realizes the ultra-thin multilayer stacked chip packaging.

[0042] It should be noted that in addition to the electrical connection by the bonding wires, the plurality of chips 120 can also be connected by thermal compression bonding or other bonding methods to reduce the thickness of the chip packaging structure.

[0043] S120, providing a plastic packaging jig, the plastic packaging jig comprising a first mold and a second mold matched with the first mold, and laying a metal layer in the first mold.

[0044] Specifically, as shown in Figure 5 , a plastic packaging jig is provided, which includes a first mold 131 and a second mold 132 matched with the first mold 131.

[0045] As shown in Figure 5 , the first mold 131 is placed on the support table, the release film 140 is laid in the first mold 131, and the metal layer 150 is laid on the release film 140. Among them, the release film 140 is laid in the first mold 131 to facilitate the stripping of the first mold 131 and the metal layer 150.

[0046] In the embodiment, the metal layer 150 can adopt a metal copper layer, specifically, can adopt a pure copper of Mitsui, with a thickness of 12 μm~20 μm, in a hard state, and without an anti-oxidation plating layer treatment on the surface. The material of the metal layer 150 is not specifically limited, and can be selected according to actual needs. The thickness of the metal layer 150 is <20 μm, and the specific thickness of the metal layer 150 can be selected according to actual needs, which is not specifically limited in the embodiment.

[0047] In the embodiment, the release film 140 can adopt a fluorine release film, which can withstand a high temperature of 180 °C~220 °C for a long time, can withstand a higher temperature for a short time, perfectly matches the curing process of an epoxy resin molding compound (EMC), has good chemical stability, stable release force, and a smooth surface. Of course, the release film 140 can also adopt other types, which is not specifically limited in the embodiment, and can be selected according to actual needs.

[0048] S130, forming a first plastic sealing layer with a preset thickness on the metal layer.

[0049] Specifically, as shown in Figure 6 first, the plastic sealing material powder can be uniformly covered on the metal layer 150 by a spraying or powdering device. In the embodiment, the plastic sealing material can adopt an epoxy resin molding compound.

[0050] Secondly, the plastic sealing material powder is heated and cured to form a first plastic sealing layer 160 with a preset thickness. The temperature range of the heating and curing is 180 °C ± 5 °C, and specifically, in the embodiment, the preliminary curing condition is to heat at a temperature of 170 °C~175 °C for 110 s~120 s, and then to cure at 175 °C for 4 h to fully release stress and achieve complete curing. The temperature rising and falling process (from room temperature to 175 °C) is controlled to be 1 hour.

[0051] In the embodiment, the thickness of the first plastic sealing layer 160 is not specifically limited, and can be selected according to actual needs.

[0052] In the embodiment, the plastic sealing material powder is uniformly covered on the metal layer, and the first plastic sealing layer with a preset thickness is formed by heating and curing, which has a simple process, can accurately control the amount of plastic sealing material, has high material utilization rate, reduces waste, has uniform coverage, and reduces the generation of voids.

[0053] It should be noted that in the embodiment, the metal layer 150 and the first plastic sealing layer 160 are not coupled by coupling agent, and are adhered by the adhesive of the plastic sealing material and the surface of the metal layer 150. In the embodiment, the metal layer 150 is a copper layer, and the plastic sealing material is an epoxy resin plastic sealing material. The adhesion of the high-performance epoxy resin plastic sealing material to the copper is 82.3 N / cm 2 . The adhesion of the high-performance epoxy resin plastic sealing material to the copper is 82.3 N / cm 2 . The adhesion of the high-performance epoxy resin plastic sealing material to the copper is 82.3 N / cm

[0054] In addition, the heat conduction channel of the heat generated by the chip is upward through the plastic sealing material to dissipate heat outward. The plastic sealing gap of the current plastic sealing material is only 20 μm, and the resistance to heat conduction is much smaller than that of the conventional product. Secondly, the thermal conductivity of copper is better than that of plastic sealing material, and the addition of the copper layer on the first plastic sealing layer can also better dissipate heat.

[0055] S140, placing the uppermost chip in the chip packaging module in the first plastic sealing layer.

[0056] Specifically, as shown in Figure 7 , the formed chip packaging module A is inverted, so that the substrate 110 is located at the top, and the multi-layer stacked chips are located below the substrate 110. Then the uppermost flip-chip 120 is placed in the first plastic sealing layer 160 with a preset thickness.

[0057] S150, placing the second mold cover on the first mold to form a second plastic sealing layer wrapping the chip packaging module.

[0058] Specifically, as shown in Figure 7 , the second mold 132 is covered on the first mold 131, so that a cavity is formed between the first mold 131 and the second mold 132, and the cavity contains the first plastic sealing layer 160 and the chip packaging module A above the first plastic sealing layer 160.

[0059] The second plastic sealing layer wrapping the chip packaging module A is formed in the plastic sealing jig by using the injection molding process commonly used in the prior art. The temperature range of the injection molding is 165 °C~175 °C; the pressure range is 15 ton~20 ton; and the curing time is 100 s~151 s.

[0060] As shown in Figure 8 , the first plastic sealing layer 160 and the second plastic sealing layer together constitute the plastic sealing layer B of the packaging structure. The process steps of forming the second plastic sealing layer by injection molding are not described herein again, and can be referred to the corresponding process steps in the prior art.

[0061] In this embodiment, the material of the second plastic sealing layer is the same as that of the first plastic sealing layer 160, and both can use epoxy resin molding sealing material. Since the materials of the first plastic sealing layer 160 and the second plastic sealing layer are the same, there is no interface delamination between the two. The thermal expansion coefficient of the epoxy resin sealing material in the glass state region is in the range of 6 ppm / °C~12 ppm / °C, and the thermal expansion coefficient of the epoxy resin sealing material in the high elastic state region is in the range of 25 ppm / °C~70 ppm / °C. The elastic modulus of the epoxy resin sealing material at room temperature is in the range of 15 GPa~25 GPa, and the elastic modulus of the epoxy resin sealing material at high temperature is in the range of 0.5 GPa~2 GPa.

[0062] S160, removing the plastic sealing jig to obtain a multilayer stacked chip packaging structure.

[0063] Specifically, as shown in Figure 9 , the second mold 132 is separated from the first mold 131, and the release film 140 is separated from the metal layer 150. The release film 140 can be removed by manual peeling, or an automatic equipment can be used to peel the release film 140, to obtain a multilayer stacked chip packaging structure as shown in Figure 10 .

[0064] The multilayer stacked chip packaging method of the embodiments of the present disclosure comprises: sequentially stacking a plurality of chips on a substrate to form a chip packaging module; providing a plastic sealing jig, the plastic sealing jig comprising a first mold and a second mold matched with the first mold, and a metal layer is laid in the first mold; forming a first plastic sealing layer with a predetermined thickness on the metal layer; placing the uppermost chip in the chip packaging module on the first plastic sealing layer; covering the second mold on the first mold to form a second plastic sealing layer wrapping the chip packaging module; and removing the plastic sealing jig to obtain a multilayer stacked chip packaging structure. By this method, the metal layer is formed on the surface of the plastic sealing layer in the entire chip packaging structure, avoiding the transmission and positioning problems of the ultra-thin metal layer in the mounting process, improving the strength of the ultra-thin chip packaging structure, and improving the reliability of the ultra-thin chip packaging structure.

[0065] Another aspect of the embodiments of the present disclosure provides a multilayer stacked chip package structure, which is formed by using the multilayer stacked chip package method S100 described above. The specific process steps of the multilayer stacked chip package method S100 have been described in detail above, and will not be repeated here.

[0066] As shown in FIG. 1, the multilayer stacked chip package structure includes a substrate 110, a plurality of chips 120 stacked on the substrate 110, a plastic encapsulation layer B, and a metal layer 150. Figure 10

[0067] Among them, the plurality of chips 120 are electrically connected through bonding wires 121 between the plurality of chips 120 and between the bottommost chip 120 and the substrate 110. Then, the topmost chip is flip-chip mounted on the lower chip to form a chip package module A. In this embodiment, the chip 120 can be a memory chip, and other types of chips can be used, which can be selected according to actual needs.

[0068] The plastic encapsulation layer B wraps the plurality of chips 120 stacked, and protects the plurality of chips 120.

[0069] The metal layer 150 is disposed on the surface of the plastic encapsulation layer B away from the substrate 110, and serves to enhance the entire chip package structure. The metal layer 150 can be made of a metal copper layer or other materials, and the thickness of the metal layer 150 is < 20 μm.

[0070] The multilayer stacked chip package structure of the embodiments of the present disclosure is formed by using the multilayer stacked chip package method described above. The topmost chip in the multilayer stacked chip is flip-chip mounted on the lower chip, and the electrical connection between the chips is achieved without using bonding wires, which greatly reduces the thickness of the entire package structure and realizes ultra-thin multilayer stacked chip package. By disposing the metal layer on the surface of the plastic encapsulation layer away from the substrate, the strength of the entire ultra-thin package structure is improved, and the reliability of the ultra-thin package structure is enhanced.

[0071] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. Those skilled in the art can make various modifications and improvements without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered within the protection scope of the embodiments of the present disclosure.​

Claims

1. A multi-layer stacked chip packaging method, characterized in that, The method includes: Multiple chips are stacked sequentially on a substrate to form a chip packaging module; A molding fixture is provided, the molding fixture comprising a first mold and a second mold matching the first mold, wherein a metal layer is laid in the first mold; Forming a first molding layer with a preset thickness on the metal layer specifically includes: uniformly covering the metal layer with molding compound powder using a spraying or powdering device, and heating and curing the molding compound powder to form the first molding layer; The uppermost chip in the chip packaging module is placed on the first molding layer; The second mold is placed over the first mold, and a second plastic encapsulation layer is formed to encapsulate the chip packaging module using an injection molding process. Remove the plastic encapsulation fixture to obtain a multi-layer stacked chip package structure.

2. The method according to claim 1, characterized in that, Before laying the metal layer inside the first mold, the method further includes: A release film is laid inside the first mold, and the metal layer is laid on the release film.

3. The method according to claim 2, characterized in that, Removing the plastic sealant fixture includes: Separate the second mold from the first mold, and separate the release film from the metal layer.

4. The method according to any one of claims 1 to 3, characterized in that, Multiple chips are stacked sequentially on a substrate to form a chip packaging module, including: The topmost chip is flip-chip mounted on the chip below it, and the remaining chips are electrically connected to each other via bonding wires.

5. The method according to claim 4, characterized in that, A non-conductive adhesive layer is disposed between the remaining chips.

6. The method according to any one of claims 1 to 3, characterized in that, Placing the uppermost chip in the chip packaging module on the first molding layer includes: The formed chip packaging module is inverted so that the topmost chip is placed face down on the first molding layer.

7. The method according to any one of claims 1 to 3, characterized in that, The material of the first molding layer is the same as the material of the second molding layer.

8. A multi-layer stacked chip packaging structure, characterized in that, It is packaged using the multilayer stacked chip packaging method according to any one of claims 1 to 7.

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