Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The manufacturing method of the semiconductor device comprises the following steps: sequentially forming a patterned first conductive layer, a first dielectric layer, a second conductive layer and a second dielectric layer on one side of a substrate; the second conductive layer comprises a first type of metal; an initial hole penetrates through the second dielectric layer and the second conductive layer, a first contact region is formed at the end part, exposed out of the initial hole, of the second conductive layer, and the first contact region comprises metal oxide materials of the first type of metal and the second type of metal; a via hole penetrating through the first dielectric layer is formed, a metal oxide semiconductor layer is deposited on the side wall of the via hole, and the metal oxide semiconductor layer makes contact with the first contact area and is electrically connected with the first conductive layer. The scheme can effectively improve the performance of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a semiconductor device and its manufacturing method, and an electronic device. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of semiconductor devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that small differences in the manufacturing process may affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] This application proposes a semiconductor device and its manufacturing method, as well as an electronic device, which can effectively improve the performance of the semiconductor device.

[0005] This application provides a method for manufacturing a semiconductor device, including: A patterned first conductive layer is formed on the substrate; A first dielectric layer covering the first conductive layer is fabricated on the substrate; A patterned second conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer; the second conductive layer comprises a first type of metal. An initial hole is formed that penetrates at least the second dielectric layer and the second conductive layer, exposing the end of the second conductive layer; A first contact area is formed at the end of the second conductive layer exposed by the initial hole, and the first contact area contains a metal oxide material of the first type of metal and the second type of metal; The first dielectric layer is etched downwards within the initial hole to form a via that penetrates the second dielectric layer, the second conductive layer, and the first dielectric layer, with the via exposing the first conductive layer. A metal oxide semiconductor layer is deposited on the sidewall of the via, and the metal oxide semiconductor layer is connected to the second conductive layer through the first contact region.

[0006] In some embodiments, forming a first contact area at the end of the second conductive layer exposed in the initial hole includes: The end of the second conductive layer exposed by the initial hole is subjected to an oxidation treatment to form a metal oxide material containing the first type of metal at the end; A second type of metal ions are injected at the end to form a first contact region comprising the first type of metal and the second type of metal; and / or, a metal oxide layer of the second type of metal is deposited at the end to form a first contact region comprising the first type of metal and the second type of metal.

[0007] In some embodiments, the first conductive layer comprises the first type of metal; After forming the patterned first conductive layer on the substrate, and before fabricating the first dielectric layer covering the first conductive layer on the substrate, the method further includes: An oxidation treatment is performed on the upper surface of the first conductive layer to form a metal oxide material containing the first type of metal on the upper surface of the first conductive layer; A second type of metal ions are implanted on the upper surface of the first conductive layer to form a second contact region containing the first type of metal and the second type of metal; and / or, a metal oxide layer of the second type of metal is deposited on the upper surface of the first conductive layer to form a second contact region containing the first type of metal and the second type of metal.

[0008] In some embodiments, after depositing a metal oxide semiconductor layer on the sidewalls of the via, the method further includes: A gate dielectric layer is deposited on the sidewall of the via and the gate is filled in the via.

[0009] In some embodiments, forming an initial hole that at least penetrates the second dielectric layer and the second conductive layer includes: An initial hole is formed that penetrates only the second dielectric layer and the second conductive layer. The initial hole stops at the upper surface of the first dielectric layer, and the thickness of the first dielectric layer is equal to the length of the channel of the metal oxide semiconductor layer.

[0010] In some embodiments, the first type of metal comprises at least one of tungsten, zinc, and tin; The second category of metals includes indium; The metal material of the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, and tin.

[0011] This application also provides a semiconductor device, including: A first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially stacked on a substrate; A via, penetrating the second dielectric layer, the second conductive layer and the first dielectric layer, stopping at the first conductive layer, the second conductive layer surrounding the via, the end of the second conductive layer exposed on the sidewall of the via, the second conductive layer comprising a first type of metal; The first contact area includes at least the end of the second conductive layer; the first contact area includes a metal oxide material of the first type of metal and the second type of metal; A metal oxide semiconductor layer is located on the sidewall and bottom of the via, and is connected to the second conductive layer through the first contact area; the metal oxide semiconductor layer is electrically connected to the first conductive layer.

[0012] In some embodiments, a metal oxide layer located on the sidewall of the via and covering the second dielectric layer is also included, the metal oxide layer comprising the second type of metal; The first contact area also includes a region located at the end of the metal oxide layer that covers the second conductive layer, and the metal oxide layer corresponding to the first contact area further includes the first type of metal.

[0013] In some embodiments, it also includes: A second contact area is located on the first conductive layer. The second contact area contains metal oxide materials formed by oxidizing the first type of metal and the second type of metal. The metal oxide semiconductor layer is connected to the first conductive layer through the second contact area.

[0014] In some embodiments, The first class of metals includes at least one of tungsten, zinc, and tin; The second type of metal includes indium; the metal material of the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, and tin.

[0015] In some embodiments, the thickness of the first dielectric layer is equal to the length of the channel of the metal oxide semiconductor layer.

[0016] This application provides an electronic device, including the semiconductor device described above.

[0017] The beneficial technical effects of the technical solutions provided in this application include: In the semiconductor device manufacturing method provided in this application embodiment, the end of the second conductive layer exposed in the initial hole includes a first contact area of ​​a first type of metal and a second type of metal, which reduces the contact resistance between the second conductive layer and the metal oxide semiconductor layer and simplifies the process.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and will become apparent from the description or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1-12 This is a schematic diagram of different manufacturing processes in a semiconductor device manufacturing method provided in an embodiment of this application. Figure label: 11-Substrate; 12-First conductive layer; 13-First dielectric layer; 14-Second conductive layer; 15-Second dielectric layer; 16-Initial hole; 17-First metal oxide layer; 18-First contact region; 19-Metal oxide semiconductor layer; 21-Second contact region; 22-Via; 23-Gate dielectric layer; 24-Gate; 25-Third conductive layer. Detailed Implementation

[0020] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0021] Those skilled in the art will understand that, unless specifically stated otherwise, the terms "described" and "the" as used herein may also include plural forms. It should be further understood that the term "comprising" as used in the specification of this application means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art. The term "and / or" as used herein refers to at least one of the items defined by the term; for example, "A and / or B" can be implemented as "A," or as "B," or as "A and B."

[0022] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0023] The technical solution of this application and how it solves the above-mentioned technical problems are described in detail below with specific embodiments. It should be noted that the following embodiments can be referenced, borrowed, or combined with each other, and the same terms, similar features, and similar implementation steps in different embodiments will not be described again.

[0024] The semiconductor device in this application embodiment can be a transistor, which is a vertical transistor, and can be a vertical channel transistor or a horizontal channel transistor. In a horizontal channel transistor, the semiconductor layer is formed on the sidewall of a via, but the source and drain are located on the same layer and spaced apart from each other. In a vertical channel transistor, the semiconductor layer is formed on the sidewall of a via, and the source and drain are stacked in a direction perpendicular to the substrate. Both the source and drain can be disposed on the sidewall, or at least one can be disposed on the sidewall.

[0025] The following explanation uses a vertical transistor with vertical channel characteristics as an example.

[0026] This application provides a method for manufacturing a semiconductor device, including: A patterned first conductive layer is formed on the substrate; A first dielectric layer covering the first conductive layer is fabricated on the substrate; A patterned second conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer; An initial hole is formed that at least penetrates the second dielectric layer and the second conductive layer, exposing the end of the second conductive layer; the second conductive layer comprises a first type of metal. A first contact area is formed at the end of the second conductive layer exposed by the initial hole, and the first contact area contains a metal oxide material of the first type of metal and the second type of metal; The first dielectric layer is etched downwards within the initial hole to form a via that penetrates the second dielectric layer, the second conductive layer, and the first dielectric layer, with the via exposing the first conductive layer. A metal oxide semiconductor layer is deposited on the sidewall of the via, and the metal oxide semiconductor layer is connected to the second conductive layer through the first contact region.

[0027] In some embodiments, forming a first contact area at the end of the second conductive layer exposed in the initial hole includes: Oxidation is performed on the end of the second conductive layer exposed by the initial hole to form a metal oxide material containing the first type of metal; A second type of metal ions are implanted into the metal oxide layer to form a first contact region containing the first type of metal and the second type of metal; and / or, a metal oxide layer of the second type of metal is deposited on the metal oxide layer to form a first contact region containing the first type of metal and the second type of metal.

[0028] Furthermore, a first contact area containing a first type of metal and a second type of metal can be formed during the formation of the first conductive layer.

[0029] This application provides a method for manufacturing a semiconductor device, which includes the following steps: S101: As Figure 1 A patterned first conductive layer 12 is formed on the substrate 11. The first conductive layer 12 is formed on the upper surface of the substrate 11 or the substrate is etched to form a groove, and the first conductive layer 12 is formed in the groove.

[0030] S102: As Figures 2-3 A first dielectric layer 13 covering the first conductive layer 12 is formed on the substrate 11.

[0031] S103: As Figure 4 A patterned second conductive layer 14 and a second dielectric layer 15 are sequentially formed on the first dielectric layer 13.

[0032] S104: Form an initial hole 16 that penetrates at least the second dielectric layer 15 and the second conductive layer 14, with the initial hole exposing the end of the second conductive layer 14.

[0033] S105: Oxidize the sidewall of the second conductive layer 14 exposed in the initial hole 16 to obtain the end of a metal oxide material containing a first type of metal, for example, the first conductive layer and the second conductive layer are tungsten metal layers, and oxidize the end of the tungsten metal layer to form tungsten oxide material; A first metal oxide layer 17 containing a second type of metal (e.g., an indium oxide layer) is deposited within the initial hole 16, such that tungsten oxide reacts with the corresponding indium oxide to form a first contact region 18 (indium tungsten oxide, or IWO). The material of the first contact region 18 comprises a metal oxide material of the first type of metal and the second type of metal; or A second type of metal ions (such as In ions) are implanted into the end of the second conductive layer in the initial hole 16 by ion implantation, so that the oxidized end of the second conductive layer forms a metal oxide material of the two types of metals, that is, a first contact area 18 containing the first type of metal and the second type of metal oxide material is formed.

[0034] In other embodiments, a second type of metal ions may be implanted into the end of the second conductive layer within the initial hole 16 by ion implantation to form an initial contact region. A first metal oxide layer 17 containing the second type of metal (such as an indium oxide layer) is then deposited on the initial contact region, so that the tungsten oxide in the initial contact region reacts with the corresponding indium oxide to generate a first contact region 18 (indium tungsten oxide, i.e., IWO). The material of the first contact region 18 includes a metal oxide material of the first type of metal and the second type of metal.

[0035] In the embodiments of this application, the first type of metal includes at least one of tungsten, zinc, and tin. The second type of metal includes indium or similar materials.

[0036] S106: The first dielectric layer 13 is etched downwards within the initial hole 16 to form a via 22 that penetrates the second dielectric layer 15, the second conductive layer 14 and the first dielectric layer 13. The via 22 exposes the upper surface of the first conductive layer 12.

[0037] S107: A first metal oxide semiconductor layer 19 is deposited on the sidewall of the via 22. The first metal oxide semiconductor layer 19 is in contact with the first contact area 18 and is electrically connected to the first conductive layer 12.

[0038] For example, the metal material of the metal oxide semiconductor layer 19 includes at least one of indium, gallium, zinc, and tin. For instance, the metal oxide semiconductor layer 19 is IGZO, IZO, IGO, etc.

[0039] In the semiconductor device manufacturing method provided in this application embodiment, an initial hole 16 penetrates a second dielectric layer 15 and a second conductive layer 14. The second conductive layer 14 is the source or drain of a transistor. The end of the second conductive layer 14 exposed in the initial hole 16 is oxidized to obtain an end containing a first type of metal. This end is part of the second conductive layer 14. A first metal oxide layer 17 containing a second type of metal, deposited in the initial hole 16 and located at the end of the second conductive layer 14, reacts with the end containing the first type of metal to form a first contact region 18. A metal oxide semiconductor layer 19 is deposited on the sidewall of the via 22 that penetrates the second dielectric layer 15, the second conductive layer 14, and the first dielectric layer 13. It can be seen that by providing the first contact region 18 between the metal oxide semiconductor layer 19 and the second conductive layer of the transistor, the contact resistance between the channel region and the source or drain in the metal oxide semiconductor layer 19 can be reduced, thereby increasing the on-state current of the transistor. This process does not involve photolithography etching, simplifying the process steps and reducing manufacturing costs.

[0040] In some embodiments, the first contact area only includes the end of the second conductive layer. In this embodiment, the first contact area is formed by ion implantation of the end of the second conductive layer. For example, the first contact area only includes the end of the second conductive layer formed of tungsten metal, which contains a metal oxide material of tungsten metal and indium metal. Excluding this end region, the second conductive layer is a tungsten metal layer.

[0041] In some embodiments, the first contact area includes an end of the second conductive layer and a portion of the first metal oxide layer 17 (indium oxide), the end and the portion of the first metal oxide layer 17 being stacked horizontally and forming a binary metal oxide material, such as tungsten indium oxide (WIO), through contact.

[0042] This application embodiment also enables the adjustment of the channel length of the semiconductor device by adjusting the etching length of the initial hole 16 so that the initial hole 16 stops at any designed depth on the upper surface or inside the first dielectric layer 13.

[0043] Optionally, in one embodiment of this application, such as Figure 1 As shown, after forming the patterned first conductive layer 12 on the substrate 11 in step S101, and before forming the first dielectric layer 13 covering the first conductive layer 12 on the substrate 11 in step S102, the method further includes: The side of the first conductive layer 12 away from the substrate 11 is oxidized, and the surface of the first conductive layer 12 is obtained with a metal oxide material containing a first type of metal.

[0044] A second type of metal ions are implanted into the upper surface of the first conductive layer 12 containing the first type of metal to form a second contact region 21. The second contact region 21 contains the first type of metal and the metal oxide material after the first type of metal and the second type of metal are oxidized.

[0045] And, in step S107, a metal oxide semiconductor layer 19 is deposited on the sidewall of the via 22, including: A metal oxide semiconductor layer 19 is deposited within the via 22. The metal oxide semiconductor layer 19 covers and contacts the first metal oxide layer 17, the first contact region 18, the first dielectric layer 13, and the second contact region 21 at the corresponding locations of the second dielectric layer 15. For example... Figure 9 As shown.

[0046] In this embodiment, the first conductive layer 12 is the source or drain of the semiconductor device. By providing a second contact area 21 between the first conductive layer 12 and the metal oxide semiconductor layer 19, the contact resistance between the metal oxide semiconductor layer and the source or drain can be reduced, and the on-state current of the semiconductor device can be increased. This process can simplify the manufacturing process and reduce manufacturing costs.

[0047] Optionally, in one embodiment of this application, such as Figure 1 As shown, second-type metal ions are doped onto the upper surface of the first conductive layer to form a second contact region 21, including: The second type of metal ions are injected into the first conductive layer to obtain the second contact region 21.

[0048] In this embodiment, the second type of metal ions includes In3+ ions. The In3+ ions react with the metal oxide on the upper surface of the first conductive layer to form a conductive metal oxide containing In, which serves as the second contact region 21. The second contact region 21 is disposed between the first conductive layer 12 and the metal oxide semiconductor layer 19, thereby reducing the contact resistance between the channel and the source or drain, and increasing the on-state current of the transistor.

[0049] Optionally, in one embodiment of this application, such as Figure 1 As shown, a second type of metal ions are doped into the metal oxide layer to form a second contact region 21, including: A metal oxide layer containing a second type of metal is deposited into the first conductive layer, such that the metal oxide (tungsten oxide) on the upper surface of the first conductive layer reacts with the metal oxide layer (indium oxide) to form a second contact region 21.

[0050] In the embodiments of this application, see Figure 1As shown, the first electrode (source or drain) of the transistor is formed in a groove in the substrate 11. A first conductive layer 12 is formed on the substrate 11 through photolithography, etching, and metallization processes. The side of the first conductive layer 12 away from the substrate 11 is oxidized to obtain a metal oxide material containing a first type of metal. Second type of metal ions are doped into the upper surface of the first conductive layer, reacting to form a second contact region 21, thereby forming a good contact between the second contact region 21 and the metal oxide semiconductor layer. The metallization process can employ direct metal etching or a damascus process. The material of the first conductive layer 12 includes metals such as tungsten, zinc, and tin that can react with indium oxide or In3+ ions to form conductive metal oxides. The second contact region 21 contains a metal oxide formed by at least one of tungsten, zinc, and tin with indium, for example, the conductive metal oxide of the second contact region 21 is IWO.

[0051] In some embodiments, the first electrode is formed on the substrate 11, rather than in a recess in the substrate 11.

[0052] In the embodiments of this application, such as Figure 2 As shown, a first dielectric layer 13 is deposited on the side of the second contact region 21 and the substrate 11 not blocked by the second contact region 21. This first dielectric layer 13 serves as an etch stop layer for the initial via 16. The first dielectric layer 13 can be any insulating dielectric, such as alumina, silicon nitride, or silicon oxide. The deposition method of the first dielectric layer 13 includes CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), and ALD (Atomic Layer Deposition). The first dielectric layer 13 and the substrate 11 should be made of different materials and have different etching selectivity ratios.

[0053] In the embodiments of this application, such as Figure 3 As shown, a second conductive layer 14 is formed on the side of the first dielectric layer 13 away from the substrate 11 through photolithography, etching, and metallization processes. The material of the second conductive layer 14 includes metals such as tungsten, zinc, and tin that can react with indium oxide or In3+ ions to form conductive metal oxides. The second conductive layer 14 is the second electrode (source or drain) of the transistor.

[0054] In the embodiments of this application, such as Figure 4 As shown, a second dielectric layer 15 is deposited on the side of the second conductive layer 14 away from the substrate 11, and the thickness of the deposited second dielectric layer 15, together with the total thickness of the second conductive layer 14, the first dielectric layer 13, and the substrate 11, meets the requirements for the device contact area.

[0055] In the embodiments of this application, such as Figure 5As shown, an initial hole 16 is formed through photolithography and etching processes. The initial hole 16 penetrates at least the second dielectric layer 15 and the second conductive layer 14. The initial hole 16 can stop at the upper surface of the first dielectric layer 13, or it can stop at any designed depth inside the first dielectric layer 13. However, the initial hole 16 cannot penetrate the first dielectric layer 13 to expose the second contact area 21. The etching depth of the initial hole 16 is determined according to specific circumstances, and this application does not impose any limitations.

[0056] When the initial hole 16 stops at the upper surface of the first dielectric layer 13, in actual products, in order to ensure that the second conductive layer 14 is completely etched through, the initial hole 16 may have a small or negligible or allowable over-etching within the error range, so that the initial hole 16 extends beyond the lower surface of the second conductive layer 14.

[0057] In the embodiments of this application, such as Figure 6 As shown, the end of the second conductive layer 14 exposed in the initial hole 16 is oxidized to obtain an end of a metal oxide material containing a first type of metal. A first metal oxide layer 17 containing a second type of metal is deposited in the initial hole 16 using atomic layer deposition, such that the oxidized end of the second conductive layer reacts with the corresponding first metal oxide layer 17 to form a first contact region 18. The first contact region 18 extends in a direction perpendicular to the substrate 11, covering only the sidewall of the second conductive layer 14, and together with the adjacent second conductive layer 14, constitutes the second electrode (source or drain) of the semiconductor device. The second electrode includes the source of a transistor and a second signal line, which can serve as a bit line or word line of an array. The first contact region 18 extends from the sidewall of the initial hole 16 toward the substrate 11 and does not exceed the first dielectric layer 13. The material of the first metal oxide layer 17 includes In2O3 or other materials; this application does not impose specific material limitations. The material of the first contact region 18 includes a conductive metal oxide formed by at least one of tungsten, zinc, and tin with indium. For example, if the material of the second conductive layer 14 is W (tungsten), the material of the metal oxide layer is WO3, and the material of the first metal oxide layer 17 is In2O3, then the material of the first contact area 18 is IWO.

[0058] In the embodiments of this application, such as Figure 7 As shown, anisotropic etching is performed through an etching process to remove the first metal oxide layer 17 on the first dielectric layer 13 at the bottom of the initial hole 16, and to remove the first metal oxide layer 17 on the side of the second dielectric layer 15 away from the substrate 11, while retaining at least the first metal oxide layer 17 in contact with the second dielectric layer 15; then, the first dielectric layer 13 is etched downwards into the initial hole 16 to expose the second contact area 21 or the first conductive layer, forming a via 22 that penetrates the second dielectric layer 15, the second conductive layer 14 and the first dielectric layer 13.

[0059] In the above embodiments, if a second contact area is formed between the formation of the first conductive layer and the formation of the second conductive layer, the first dielectric layer 13 is etched downwards within the initial hole 16 to expose the second contact area. If no second contact area is formed after the formation of the first conductive layer, and instead, a dielectric layer and a second conductive layer are formed, the first dielectric layer 13 is etched downwards within the initial hole 16 to expose the first conductive layer.

[0060] In the embodiments of this application, such as Figure 9 As shown, a metal oxide semiconductor layer 19 is deposited on the sidewall of via 22. The metal oxide semiconductor layer 19 covers the first metal oxide layer 17, the first contact region 18, the first dielectric layer 13, and the second contact region 21. The material of the metal oxide semiconductor layer 19 includes indium gallium zinc oxide (IGZO), and the indium (In), gallium (Ga), and zinc (Zn) precursors do not contain metal-oxygen bonds. Alcohols are used as precursors for oxidation. The metal oxide semiconductor layer 19 includes a metal oxide semiconductor containing at least one of indium, gallium, zinc, tin, and aluminum.

[0061] Optionally, in one embodiment of this application, after depositing the metal oxide semiconductor layer 19 on the sidewall of the via 22 in step S107, as... Figure 10-11 As shown, it also includes: A gate dielectric layer 23 is deposited on the sidewall of via 22 and a gate 24 is filled in the via.

[0062] like Figure 10 As shown, a gate dielectric layer 23 and a gate 24 are sequentially deposited in the via, forming a basic vertical channel transistor structure. The material of the gate dielectric layer 23 includes common oxide semiconductors such as Al2O3, HfO2, or SiO2.

[0063] like Figure 11 As shown, excess film layers in the metal oxide semiconductor layer 19, gate dielectric layer 23, and gate 24 are removed by photolithography and etching processes.

[0064] like Figure 12 As shown, a third conductive layer 25 is obtained on one side of the second dielectric 15 and the gate 24 through a metallization process, and interconnections are formed at each end to obtain the desired semiconductor device.

[0065] Optionally, in one embodiment of this application, such as Figure 5 As shown, the initial hole 16 stops at the first dielectric layer 13, including: the initial hole 16 stops at the upper surface of the first dielectric layer 13, and the thickness of the first dielectric layer is equal to the length of the channel in the metal oxide semiconductor.

[0066] In this embodiment, the initial hole 16 stops on the upper surface of the first dielectric layer 13; along the extension direction of the initial hole 16, the first metal oxide layer 17 contacts the second dielectric layer 15 exposed in the initial hole 16, and the first metal oxide layer 17 deposited at the end of the second conductive layer 14 reacts with the metal oxide layer at the end of the second conductive layer 14 to form a first contact area 18, so that the channel length in the metal oxide semiconductor is equal to the thickness of the first dielectric layer 13. Therefore, the channel length of the transistor can be controlled by controlling the thickness of the first dielectric layer 13, thereby reducing the manufacturing difficulty of semiconductor devices and improving device performance.

[0067] In some embodiments, the initial hole 16 stops inside the first dielectric layer 13; along the extension direction of the initial hole 16, the first metal oxide layer 17 contacts the second dielectric layer 15 exposed in the initial hole 16, and the first metal oxide layer 17 deposited on the sidewall of the second conductive layer 14 reacts with the metal oxide layer at the end of the second conductive layer 14 to form a first contact region 18, and the first metal oxide layer 17 contacts the first dielectric layer 13. Thus, the channel length of the transistor can be controlled simply by controlling the thickness of the first dielectric layer 130, thereby reducing manufacturing difficulty and improving device performance.

[0068] Based on the same inventive concept, embodiments of this application provide a semiconductor device, such as... Figure 10-12 As shown, the semiconductor device can be obtained by the manufacturing method of the above embodiments, and the semiconductor device includes: A first conductive layer 12, a first dielectric layer 13, a second conductive layer 14, and a second dielectric layer 15 are sequentially stacked on a substrate 11.

[0069] Via 22 penetrates the second dielectric layer 15, the second conductive layer 14 and the first dielectric layer 13, and stops at the first conductive layer 12. The second conductive layer 14 surrounds the via 22, and the end of the second conductive layer 14 is exposed on the sidewall of the via 22. The second conductive layer 14 and the first conductive layer 12 contain a first type of metal, such as tungsten metal. It can be understood that the second conductive layer 14 and the first conductive layer 12 are both tungsten metal layers.

[0070] The first contact area 18 is located at the end of the second conductive layer 14; the material of the first contact area 18 includes a first type of metal and a second type of metal.

[0071] The metal oxide semiconductor layer 19 is located on the sidewall and bottom of the via 22 and is electrically connected to the first conductive layer 12 and the second conductive layer 14. The first contact area 18 is in contact with the metal oxide semiconductor layer 19.

[0072] In this embodiment, the first metal oxide layer 17 covers the sidewall of the second dielectric layer 15 exposed in the via 22, and the second conductive layer 14 is exposed at the oxidized end in the via 22, reacting with the first metal oxide layer 17 at the sidewall to form a first contact region 18. By adding the first contact region 18 between the metal oxide semiconductor layer 19 and the second conductive layer 14, the contact resistance between the channel and the source or drain is reduced, thereby increasing the on-state current of the transistor.

[0073] Optionally, in one specific embodiment of this application, such as Figure 8 As shown, the material of the second conductive layer 14 includes tungsten. After the end of the second conductive layer 14 is oxidized, a tungsten-containing metal oxide material is obtained. After indium ions are doped into the tungsten-containing end, IWO is generated.

[0074] In addition to the end containing the second conductive layer, the first contact area also includes a metal oxide layer that extends along the via sidewall and covers the end of the second conductive layer. The metal oxide layer comprises indium and tungsten.

[0075] In this embodiment, the first contact area 18 is annular in cross-section parallel to the substrate 11.

[0076] Optionally, in one embodiment of this application, such as Figure 10-12 As shown, the first contact area 18 includes the end of the second conductive layer 14 near the surface region of the metal oxide semiconductor layer 19, and the surface region includes a metal oxide material after the first type of metal and the second metal are oxidized.

[0077] Optionally, in one embodiment of this application, the first contact area 18 further includes a metal oxide layer on one side of the surface region at the end of the second conductive layer 14, the metal oxide layer comprising a metal oxide layer after the first type of metal and the second type of metal have been oxidized.

[0078] Optionally, in one embodiment of this application, such as Figure 10-12 As shown, the semiconductor device further includes: a second contact region 21 disposed on the first conductive layer 12, the area exposed at the bottom of the via 22 being in contact with the metal oxide semiconductor layer 19; the second contact region 21 includes a surface region of the first conductive layer 12 near the metal oxide semiconductor layer 19, the surface region including a metal oxide material after the first type of metal and the second type of metal are oxidized.

[0079] Optionally, in one embodiment of this application, the second contact area 21 further includes a metal oxide layer located above the surface region of the first conductive layer 12, the metal oxide layer comprising a metal oxide layer of a first type of metal and a second type of metal after oxidation.

[0080] In this embodiment, by adding a second contact region 21 between the metal oxide semiconductor layer 19 and the first conductive layer 12, the contact resistance between the channel and the source or drain is reduced, thereby increasing the on-state current of the transistor.

[0081] In this embodiment, the first type of metal includes at least one of tungsten, zinc, and tin. The second type of metal includes indium. The metal material of the metal oxide semiconductor layer 19 includes at least one of indium, gallium, zinc, and tin. The material of the metal oxide semiconductor layer 19 includes a metal oxide semiconductor.

[0082] In this embodiment, the material of the metal oxide semiconductor layer 19 includes indium gallium zinc oxide (IGZO).

[0083] The material of the metal oxide semiconductor layer 19 can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc., as long as the leakage current of the transistor meets the requirements. The specific materials can be adjusted according to the actual situation.

[0084] For example, the material of semiconductor layer 19 can be a wide bandgap material, such as a metal oxide material with a bandgap greater than 1.65 eV.

[0085] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0086] In some embodiments, the material of the metal oxide semiconductor layer or channel may comprise any one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InW). Materials such as O, IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) are all acceptable, as long as the leakage current of the transistor meets the requirements. Specific adjustments can be made based on the actual situation.

[0087] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10⁻¹⁵ A to 10⁻¹⁸ A, which can improve the performance of dynamic memory.

[0088] Optionally, in one embodiment of this application, such as Figure 10-12 As shown, the thickness of the first dielectric layer 13 is equal to the length of the device channel in the metal oxide semiconductor layer, which is the length of the transistor channel.

[0089] In this embodiment, the first metal oxide layer 17 covers the sidewalls of the second dielectric layer 15 exposed within the via 22. The first metal oxide layer 17 located at the second conductive layer 14 reacts with the oxidized end of the second conductive layer 14 exposed within the via 22 to form a first contact region 18. At this time, the thickness of the first dielectric layer 13 is equal to the channel length of the semiconductor device. The channel length of the semiconductor device can be understood as the length of the transistor channel, or the length of the channel in the metal oxide semiconductor layer that serves as the channel.

[0090] In some embodiments, the first metal oxide layer 17 covers the sidewalls of the second dielectric layer 15 exposed in the via 22. The first metal oxide layer 17 located at the second conductive layer 14 reacts with the oxidized end of the second conductive layer 14 exposed in the via 22 to form a first contact area 18. Part of the sidewalls of the first dielectric layer 13 exposed in the via 22 are covered by the first metal oxide layer 17. At this time, the thickness of the first dielectric layer 13 corresponding to the first metal oxide layer 17 is equal to the channel length of the semiconductor device.

[0091] In this embodiment, the channel length of the semiconductor device along the extension direction of the via 22 is related to the thickness of the first dielectric layer 13. In practical applications, if the required channel length of the semiconductor device is small, it can be achieved by reducing the thickness of the first dielectric layer 13.

[0092] Based on the same inventive concept, embodiments of this application provide an electronic device, including a semiconductor device of any embodiment.

[0093] It should be noted that since the electronic device in the embodiments of this application includes the semiconductor device in the embodiments of this application, the electronic device in the embodiments of this application also has the above-mentioned beneficial effects of the semiconductor device in the embodiments of this application, which will not be repeated here.

[0094] In some optional embodiments of this application, the electronic device includes a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal, etc.

[0095] By applying the embodiments of this application, at least the following beneficial effects can be achieved: In the semiconductor device manufacturing method provided in this application embodiment, an initial hole 16 penetrates a second dielectric layer 15 and a second conductive layer 14. The second conductive layer 14 is the source or drain of a transistor. The sidewalls of the second conductive layer 14 exposed in the initial hole 16 are oxidized to obtain a metal oxide material containing a first type of metal. A first metal oxide layer 17 containing a second type of metal, deposited in the initial hole 16 and located on the sidewall of the second conductive layer 14, reacts with the metal oxide layer to form a first contact region 18. A metal oxide semiconductor layer 19 is deposited on the sidewall of the via 22 that penetrates the second dielectric layer 15, the second conductive layer 14, and the first dielectric layer 13. It can be seen that by providing the first contact region 18 between the metal oxide semiconductor layer 19 and the source or drain of the transistor, the contact resistance between the channel region in the metal oxide semiconductor layer 19 and the source or drain can be reduced, thereby increasing the on-state current of the transistor.

[0096] Furthermore, by adjusting the etching length of the initial hole 16, the initial hole 16 can be stopped at any designed depth on the upper surface or inside the first dielectric layer 13, thereby enabling the adjustment of the channel length of the semiconductor device.

[0097] Those skilled in the art will understand that the steps, measures, and solutions in the various operations, methods, and processes discussed in this application can be alternated, modified, combined, or deleted. Furthermore, other steps, measures, and solutions in the various operations, methods, and processes discussed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted. Furthermore, steps, measures, and solutions in related technologies that are similar to those disclosed in this application can also be alternated, modified, rearranged, decomposed, combined, or deleted.

[0098] In the description of this application, the terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate directions or positional relationships based on the exemplary directions or positional relationships shown in the accompanying drawings. They are used to facilitate the description or simplification of the embodiments of this application and are not intended to indicate or imply that the device or component referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0099] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0100] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0101] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0102] The above description is only a partial implementation of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, A patterned first conductive layer is formed on the substrate; A first dielectric layer covering the first conductive layer is fabricated on the substrate; A patterned second conductive layer and a second dielectric layer are sequentially formed on the first dielectric layer; the second conductive layer comprises a first type of metal. An initial hole is formed that penetrates at least the second dielectric layer and the second conductive layer, exposing the end of the second conductive layer; A first contact area is formed at the end of the second conductive layer exposed by the initial hole, and the first contact area contains a metal oxide material of the first type of metal and the second type of metal; The first dielectric layer is etched downwards within the initial hole to form a via that penetrates the second dielectric layer, the second conductive layer, and the first dielectric layer, with the via exposing the first conductive layer. A metal oxide semiconductor layer is deposited on the sidewall of the via, and the metal oxide semiconductor layer is connected to the second conductive layer through the first contact region.

2. The manufacturing method according to claim 1, characterized in that, The formation of a first contact area at the end of the second conductive layer exposed in the initial hole includes: The end of the second conductive layer exposed by the initial hole is subjected to an oxidation treatment to form a metal oxide material containing the first type of metal at the end; A second type of metal ions are injected at the end to form a first contact region comprising the first type of metal and the second type of metal; and / or, a metal oxide layer of the second type of metal is deposited at the end to form a first contact region comprising the first type of metal and the second type of metal.

3. The manufacturing method according to claim 1, characterized in that, The first conductive layer comprises the first type of metal; After forming the patterned first conductive layer on the substrate, and before fabricating the first dielectric layer covering the first conductive layer on the substrate, the method further includes: An oxidation treatment is performed on the upper surface of the first conductive layer to form a metal oxide material containing the first type of metal on the upper surface of the first conductive layer; A second type of metal ions are implanted on the upper surface of the first conductive layer to form a second contact region containing the first type of metal and the second type of metal; and / or, a metal oxide layer of the second type of metal is deposited on the upper surface of the first conductive layer to form a second contact region containing the first type of metal and the second type of metal.

4. The manufacturing method according to claim 1, characterized in that, After depositing a metal oxide semiconductor layer on the sidewall of the via, the method further includes: A gate dielectric layer is deposited on the sidewall of the via and the gate is filled in the via.

5. The manufacturing method according to claim 1, characterized in that, The initial hole formed at least through the second dielectric layer and the second conductive layer includes: An initial hole is formed that penetrates only the second dielectric layer and the second conductive layer. The initial hole stops at the upper surface of the first dielectric layer, and the thickness of the first dielectric layer is equal to the length of the channel of the metal oxide semiconductor layer.

6. The manufacturing method according to any one of claims 1-5, characterized in that, The first class of metals includes at least one of tungsten, zinc, and tin; The second category of metals includes indium; The metal material of the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, and tin.

7. A semiconductor device, characterized in that, include: A first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer are sequentially stacked on a substrate; A via, penetrating the second dielectric layer, the second conductive layer and the first dielectric layer, stopping at the first conductive layer, the second conductive layer surrounding the via, the end of the second conductive layer exposed on the sidewall of the via, the second conductive layer comprising a first type of metal; The first contact area includes at least the end of the second conductive layer; the first contact area includes a metal oxide material of the first type of metal and the second type of metal; A metal oxide semiconductor layer is located on the sidewall and bottom of the via, and is connected to the second conductive layer through the first contact area; the metal oxide semiconductor layer is electrically connected to the first conductive layer.

8. The semiconductor device according to claim 7, characterized in that, It also includes a metal oxide layer located on the sidewall of the via and covering the second dielectric layer, the metal oxide layer comprising the second type of metal; The first contact area also includes a region located at the end of the metal oxide layer that covers the second conductive layer, and the metal oxide layer corresponding to the first contact area further includes the first type of metal.

9. The semiconductor device according to claim 7, characterized in that, Also includes: A second contact area is located on the first conductive layer. The second contact area contains metal oxide materials formed by oxidizing the first type of metal and the second type of metal. The metal oxide semiconductor layer is connected to the first conductive layer through the second contact area.

10. The semiconductor device according to any one of claims 7-9, characterized in that, The first class of metals includes at least one of tungsten, zinc, and tin; The second type of metal includes indium; the metal material of the metal oxide semiconductor layer includes at least one of indium, gallium, zinc, and tin.

11. The semiconductor device according to claim 7, characterized in that, The thickness of the first dielectric layer is equal to the length of the channel of the metal oxide semiconductor layer.

12. An electronic device, characterized in that, Includes the semiconductor device described in any one of claims 7-11.

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