Method of forming semiconductor structure

Abstract

The invention provides a method for forming a semiconductor structure, and relates to the technical field of semiconductors, and the method comprises the steps: providing a substrate which is provided with a first surface and a second surface; selectively forming an inhibition layer on the first surface; a target layer is selectively formed on the second surface, and the inhibition layer serves as an inhibitor of the target layer; and performing a treatment to remove the suppression layer, the treatment including at least one of irradiating the suppression layer with light and heating.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a method for forming a semiconductor structure. Background Technology

[0002] As the critical dimensions of integrated circuits shrink, the requirements for semiconductor fabrication processes become increasingly stringent. In some scenarios, semiconductor structures involve multiple types of surfaces, but specific material layers may or may not be formed on only certain types of surfaces.

[0003] In one aspect of the related technology, an inhibitory material is formed on a certain type of surface to suppress the formation of other materials subsequently, and then the inhibitory material is removed, thereby achieving the purpose of selectively preventing the formation of the aforementioned other materials on that type of surface. Summary of the Invention

[0004] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising: providing a substrate having a first surface and a second surface; selectively forming a suppression layer on the first surface; selectively forming a target layer on the second surface, wherein the suppression layer serves as an inhibitor of the target layer; and performing a process to remove the suppression layer, the process comprising at least one of irradiating the suppression layer with light and heating.

[0005] According to some embodiments of this disclosure, the suppression layer is a monolayer with photoresponsive properties.

[0006] According to some embodiments of this disclosure, the inhibition layer is a self-assembled monolayer based on azobenzene.

[0007] According to some embodiments of this disclosure, the azobenzene has one or more substituents.

[0008] According to some embodiments of this disclosure, the azobenzene has two symmetrically distributed substituents, wherein one of the two substituents is on one benzene ring of the azobenzene, and the other of the two substituents is on another benzene ring of the azobenzene.

[0009] According to some embodiments of this disclosure, the azobenzene has two substituents of the same kind.

[0010] According to some embodiments of this disclosure, at least one substituent is a methoxy or nitro group.

[0011] According to some embodiments of this disclosure, the light is ultraviolet light.

[0012] According to some embodiments of this disclosure, the wavelength range of the ultraviolet light is 250nm to 400nm; and / or the power range of the ultraviolet light is 1W to 500W; and / or the time for irradiating the suppression layer with the ultraviolet light is 1 second to 120 seconds.

[0013] According to some embodiments of this disclosure, the first surface is the surface of a metal layer, the second surface is the surface of a dielectric layer, and the target layer includes a barrier layer; the dielectric layer has a through-hole, the first surface is located at the bottom of the through-hole, and the second surface includes the sidewall of the through-hole.

[0014] According to some embodiments of this disclosure, after removing the inhibition layer, the through-hole is filled with a conductive material.

[0015] According to some embodiments of this disclosure, an adhesion layer is formed on the first surface and the target layer before the conductive material is filled.

[0016] According to some embodiments of this disclosure, the light is emitted by a light source disposed at the top of a cavity used to form the target layer.

[0017] According to some embodiments of this disclosure, the cavity has a spraying component for allowing gas to pass through and reach the substrate, the spraying component being made of a material for transmitting light.

[0018] According to some embodiments of this disclosure, during the execution of the process, a flowing gas is introduced into the chamber in which the process is performed.

[0019] Other features, aspects, and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings form part of this specification, illustrating exemplary embodiments of the present disclosure, and together with the specification serve to explain the principles of the present disclosure.

[0021] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, in which:

[0022] Figure 1 A flowchart illustrating a method for forming a semiconductor structure according to some embodiments of the present disclosure is shown.

[0023] Figures 2A-2C This is a schematic diagram illustrating different stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure.

[0024] Figures 3-6 This is a schematic diagram illustrating different stages of a method for forming a semiconductor structure according to other embodiments of the present disclosure.

[0025] Figures 7A-7D This is a schematic diagram illustrating the molecular structures of various small molecules having an azobenzene structure according to some embodiments of this disclosure.

[0026] Figure 8 This is a schematic diagram illustrating the molecular structures of various polymer monomers having an azobenzene structure according to some embodiments of the present disclosure.

[0027] Figure 9 This is a schematic diagram illustrating the filling of conductive material into the via after removing the inhibition layer according to some embodiments of the present disclosure.

[0028] Figure 10 This is a schematic diagram illustrating the adsorption interaction between a small molecule with an azobenzene structure and a metal.

[0029] Figure 11 This is a schematic diagram illustrating the positional distribution of a light source for emitting light relative to a cavity for forming a target layer, and the structure of the cavity for forming the target layer, according to some embodiments of the present disclosure.

[0030] It should be understood that the same or similar reference numerals indicate the same or similar components. Detailed Implementation

[0031] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0032] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0033] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0034] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0035] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0036] In one aspect of the related technology, an inhibitory material is formed on a certain type of surface to suppress the formation of other materials subsequently, and then the inhibitory material is removed, thereby achieving the purpose of selectively preventing the formation of the aforementioned other materials on that type of surface.

[0037] As an example, as critical dimensions shrink in the integrated circuit manufacturing process, the proportion of metal in via structures used to connect different circuit layers decreases while the proportion of barrier layers increases. This leads to a significant increase in the resistance of via structures, which increases resistive-capacitive delay (RC delay) and seriously affects the overall performance and energy consumption of semiconductor structures.

[0038] To reduce the resistance of via structures, one approach in related technologies is to form a suppressing material at the bottom of the via to suppress the barrier layer, and then remove the suppressing material.

[0039] The inventors noted that while the resistance of the via structure could be reduced, the overall performance of the semiconductor structure was still not sufficiently improved. Through analysis, they discovered that in the aforementioned scenarios, the removal of the suppressor material was achieved using plasma bombardment (e.g., Ar / N2 / H2 plasma), which could damage existing materials within the semiconductor structure. Furthermore, in these exemplary scenarios, partial defects in the barrier layer were also caused, necessitating an increase in the thickness of the formed barrier layer.

[0040] In view of this, the present disclosure proposes the following technical solutions, which can effectively improve the overall performance of semiconductor structures.

[0041] Figure 1 This is a flowchart illustrating a method for forming a semiconductor structure according to some embodiments of the present disclosure. Figures 2A-2C This is a schematic diagram illustrating different stages of a method for forming a semiconductor structure according to some embodiments of the present disclosure. The following is in conjunction with... Figure 1 , 2A - Figure 2C Methods for forming semiconductor structures according to some embodiments of the present disclosure will be described.

[0042] In step S10, a substrate 100 is provided. For example... Figure 2A As shown, the substrate 100 has a first surface 101 and a second surface 102.

[0043] Substrate 100 refers to any material surface on which a thin film can be deposited, including but not limited to semiconductor wafers. In some embodiments, the material of the surface of substrate 100 may include: silicon oxide (e.g., silicon oxide), silicon germanide (e.g., silicon germanide), silicon in different forms (e.g., strained silicon, silicon-on-insulator (SOI)), element-doped silicon oxide, ceramics, glass, sapphire, metals, metal oxides, metal alloys, or insulating materials, dielectric materials, etc., depending on the specific application.

[0044] In some embodiments, the materials of the first surface 101 and the second surface 102 are different. As some implementations, the first surface 101 is the surface of a metal layer; the second surface 102 is the surface of a non-metallic layer, such as the surface of a dielectric layer. The dielectric layer is, for example, a low-k dielectric layer.

[0045] It should be noted that, Figure 2A The second surface 102 of the substrate 100 is shown schematically only, located between the two first surfaces 101. In other embodiments, the first surface 101 may be located between the two second surfaces 102.

[0046] It should be understood that the substrate 100 may also have other surfaces besides the first surface 101 and the second surface 102.

[0047] In step S20, an inhibition layer 103 is selectively formed on the first surface 101, such as... Figure 2B As shown.

[0048] The inhibition layer 103 acts as an inhibitor for the subsequent formation of a specific material layer (i.e., target layer 104) to inhibit the formation of target layer 104 on the inhibition layer 103 and the first surface 101.

[0049] In some embodiments, a self-assembled monolayer (SAM) is formed on the first surface 101 as the target layer 103 by utilizing the adsorption between small molecules and the first surface 101.

[0050] In step S30, the target layer 104 is selectively formed on the second surface 102, such as... Figure 2C As shown.

[0051] Since the inhibition layer 103 can inhibit the formation of the target layer 104 on the inhibition layer 103, the target layer 104 can be selectively formed on the second surface 102 instead of on the inhibition layer 103.

[0052] In step S40, a process is performed to remove the inhibition layer 103. Here, the process includes at least one of irradiating the inhibition layer 103 with light and heating.

[0053] In some implementations, the process performed only involves using the light-shielding layer 103. In other implementations, the process performed only involves heating. In still other implementations, the process performed includes both using the light-shielding layer 103 and heating.

[0054] In some embodiments, after irradiating the inhibition layer 103 with light and / or heating the inhibition layer 103, the structure of the molecules in the inhibition layer 103 changes from a planar configuration to a three-dimensional configuration, thereby changing the adsorption characteristics between the inhibition layer 103 and the underlying first surface 101, so as to remove the inhibition layer 103.

[0055] In the above embodiments, at least one of light irradiation and heating is used to remove the suppression layer 103. Compared with plasma bombardment, this method can reduce or eliminate damage to existing materials in the semiconductor structure, thereby helping to improve the overall performance of the semiconductor structure.

[0056] In some embodiments, the method for forming a semiconductor structure proposed in this disclosure can be applied to at least one of the mid-stage process (MEOL) and back-end process (BEOL) in semiconductor manufacturing processes.

[0057] Figures 3-6 This is a schematic diagram illustrating different stages of a method for forming a semiconductor structure according to other embodiments of the present disclosure. Figures 3-6 This illustrates a scenario where different layers of circuits are interconnected during integrated circuit manufacturing. The following section will combine... Figure 1 , Figures 3-6 Methods for forming semiconductor structures according to other embodiments of this disclosure will be described.

[0058] Referring to Figure 2, in step S10, a substrate 100 is provided. For example... Figure 3As shown, the substrate 100 has a first surface 101 and a second surface 102. According to some embodiments, the substrate 100 may be subjected to pretreatment processes, including but not limited to one or more of the following pretreatments: oxidation, reduction, etching, polishing, hydroxylation, carboxylation, hydrophobic surface treatment, hydrophilic surface treatment, annealing, ultraviolet curing, electron beam bombardment, heating and baking the surface, or removing the surface oxide layer.

[0059] like Figure 3 As shown, in some embodiments, the substrate 100 is divided into a lower layer 110 and an upper layer 120.

[0060] In the lower layer 110, interconnects 111 are surrounded by a first dielectric layer 112. Interconnects 111 include metals such as Cu (copper), Co (cobalt), Ru (ruthenium), Al (aluminum), Ir (iridium), Rh (rhodium), Mo (molybdenum), etc. The first dielectric layer 112 includes dielectric materials such as SiO2, SiOCN, SiOCH, ceramics, sapphire, glass, etc.

[0061] A second dielectric layer 122 exists in the upper layer 120. The material of the second dielectric layer 122 may be the same as or different from that of the first dielectric layer 112.

[0062] In some embodiments, the lower layer 110 has a first separator layer 113 below the first dielectric layer 112, such as an etch stop layer. In some embodiments, the upper layer 120 has a second separator layer 123 located between the first dielectric layer 112 and the second dielectric layer 122, such as an etch stop layer. As some implementations, the material of at least one of the first separator layer 113 and the second separator layer 123 may include one or more of aluminum oxide (e.g., aluminum oxide), oxygen-doped silicon carbide (e.g., silicon carbide), and aluminum nitride (e.g., aluminum nitride). The material of the second separator layer 123 may be the same as or different from the first separator layer 113.

[0063] According to some embodiments, the first surface 101 includes the surface of a metal layer, the second surface 102 includes the surface of a dielectric layer, and the target layer 103 includes a barrier layer. For example, in Figure 3 In the scenario shown, the first surface 101 is the surface of the interconnect 111, and the second surface 102 includes the surface of the second dielectric layer 122. In some embodiments, a portion of the surface of the second dielectric layer 122 further has an oxide layer 124, in which case the second surface 102 may also include the surface of the oxide layer 124 on the second dielectric layer 122.

[0064] In the case where the first surface 101 includes a metal layer and the second surface 102 includes a dielectric layer, the dielectric layer has a through-hole. For example, as... Figure 3As shown, a through hole 125 exists in the second dielectric layer 122, a first surface 101 is located at the bottom of the through hole 125, and a second surface 102 includes the sidewall of the through hole 125.

[0065] Returning to Figure 2, in step S20, as follows Figure 4 As shown, an inhibition layer 103 is selectively formed on the first surface 101.

[0066] The material of the inhibition layer 103 can be implemented in various ways, such as a monolayer, an oligomer layer, or a polymer layer. These will be described below with reference to different embodiments.

[0067] According to some embodiments, the suppression layer 103 is a monolayer, for example, the suppression layer 103 is a monolayer with photoresponsive properties.

[0068] As some implementations, the inhibition layer 103 includes a spiropyran monolayer, a coumarin monolayer, or an anthracene monolayer.

[0069] In some other implementations, the suppression layer 103 is a self-assembled monolayer (SAM) based on azobenzene. Here, azobenzene can be either unsubstituent or substituent-containing, as will be explained later with reference to some examples.

[0070] Azobenzene-based monolayers exhibit photoresponsive properties. Upon irradiation with light within a specific wavelength range, the monolayer's structure transforms from a planar configuration to a three-dimensional configuration, and its properties (such as adsorption characteristics with metals) also change. Using an azobenzene-based monolayer as the suppression layer 103 effectively inhibits the formation of subsequent target layers and facilitates subsequent removal, thus balancing semiconductor structure performance improvement with ease of fabrication. For example, an azobenzene-based monolayer can effectively suppress the formation of a barrier layer and is also easily removed by subsequent light irradiation.

[0071] In some applications, selectivity refers to the fact that the adsorption of a material formed on a certain surface (e.g., the inhibition layer 103) on a certain surface (e.g., the first surface 101) is about 1.5 times or more than the adsorption on other surfaces (e.g., the second surface 102), for example, 1.5 times, 2 times, 3 times, 4 times, 5 times, 7 times, 10 times, 15 times, 20 times, 25 times, 30 times, 35 times, 40 times, 45 times or 50 times.

[0072] According to some embodiments, after step S20, molecules that were not adsorbed during the formation of the inhibition layer 103 are removed.

[0073] As one implementation method, after the suppression layer 103 is formed, N2 or inert gases such as Ar or He are introduced into the substrate 100 to remove molecules that were not adsorbed during the formation of the suppression layer 103.

[0074] Returning to Figure 2, in step S30, as follows Figure 5 As shown, a target layer 104 is selectively formed on the second surface 102, wherein an inhibition layer 103 serves as an inhibitor of the target layer 104.

[0075] According to some embodiments, the material of the target layer 104 includes TaN. For example, the target layer 104 is formed by an atomic layer deposition (ALD) process.

[0076] During the formation of the target layer 104, molecules in the inhibition layer 103 (e.g., a self-organized monolayer based on azobenzene) prevent the raw material molecules (e.g., TaN) of the target layer 104 from binding to the first surface 101, which is equivalent to weakening the adsorption between the raw material molecules of the target layer 104 and the first surface 101. This results in the adsorption between the raw material molecules of the target layer 104 and the second surface 102 being greater than or much greater than the adsorption between the raw material molecules of the target layer 104 and the first surface 101, thereby allowing the target layer 104 to be selectively formed on the second surface 102.

[0077] Referring again to Figure 2, in step S40, a process is performed to remove the inhibition layer 103, which includes at least one of irradiating the inhibition layer 103 with light and heating.

[0078] like Figure 6 As shown, the adsorption between the monomolecules in the inhibition layer 103 and the first surface 101 weakens or disappears due to heating or light irradiation, and is thus removed from the first surface 101. As previously mentioned, after being irradiated with light of a specific wavelength range, the structure of the monomolecules in the azobenzene-based self-organized monolayer changes from a planar configuration to a three-dimensional configuration, resulting in a weakening or disappearance of the adsorption of the monomolecules on the first surface 101. According to some embodiments, the environment of the chamber for performing the processing is maintained under vacuum during the processing. According to some embodiments, during the processing, a flowing gas is introduced into the chamber for performing the processing to assist in the removal of the inhibition layer 103, thereby more effectively removing the inhibition layer 103 and reducing the possibility of residual inhibition layer 103.

[0079] As some implementations, during the process of irradiating the suppression layer 103 with light, one or more gases selected from inert gases Ar or He, or N2, are introduced. For example, the gas flow rate can be 100 sccm, 200 sccm, 500 sccm, 1000 sccm, 2000 sccm, or 5000 sccm. For example, during the ventilation process, the pressure inside the chamber is maintained at 0.1 Torr, 0.2 Torr, 0.5 Torr, 1.0 Torr, 2.0 Torr, 5.0 Torr, 10.0 Torr, 20 Torr, or 50 Torr.

[0080] To more effectively remove the suppression layer 103, different embodiments are provided below in combination with the type, wavelength, power, and illumination time of the light used.

[0081] According to some embodiments, ultraviolet light is used in the process of removing the inhibition layer 103. In some embodiments, ultraviolet light is used to remove the azobenzene-based self-assembled monolayer that serves as the inhibition layer 103. This allows for more efficient removal of the inhibition layer 103.

[0082] According to some embodiments, the wavelength range of the ultraviolet light used in the process of removing the inhibition layer 103 is 250 nm to 400 nm. This allows for more efficient removal of the inhibition layer 103.

[0083] According to some embodiments, the power range of the ultraviolet light used in the process of removing the suppression layer 103 is 1W to 500W. This effectively removes the suppression layer 103 while avoiding adverse effects on the semiconductor structure during illumination.

[0084] In some implementations, the power range of the ultraviolet light used is approximately 1W to approximately 50W, approximately 20W to approximately 200W, approximately 20W to approximately 350W, approximately 50W to approximately 500W, approximately 100W to approximately 400W, approximately 100W to approximately 500W, or approximately 200W to approximately 400W, etc.

[0085] According to some embodiments, the ultraviolet light irradiation time ranges from 1 second to 120 seconds in the process of removing the suppression layer 103. This effectively removes the suppression layer 103 while avoiding adverse effects on the semiconductor structure during the process.

[0086] In some implementations, the duration of ultraviolet (UV) irradiation ranges from about 1 second to about 120 seconds, from about 2 seconds to about 10 seconds, or from about 2 seconds to about 30 seconds. As some examples, the duration of UV irradiation is about 2 seconds, about 5 seconds, about 10 seconds, about 30 seconds, or about 60 seconds.

[0087] It should be understood that multiple parameters in the above wavelength range, power range, and time range can be combined to more effectively remove the suppression layer 103.

[0088] According to some embodiments, in the process of removing the suppression layer 103, the wavelength range of the ultraviolet light used is 250nm to 400nm, the power range of the ultraviolet light used is 1W to 500W, and the irradiation time ranges from 1 second to 120 seconds. This allows for more effective removal of the suppression layer 103 while effectively avoiding adverse effects on the semiconductor structure during the process.

[0089] The above combination Figures 3-6The process of selectively forming a material layer on a specific surface in different types of surfaces is introduced.

[0090] Figures 7A-7D This illustrates a self-organizing monolayer according to different embodiments of the present disclosure.

[0091] In some embodiments, such as Figure 7A As shown, the self-assembled monolayer is based on azobenzene without substituents.

[0092] In other embodiments, such as Figure 7B As shown, the self-assembled monolayer is based on azobenzene with substituents. As some implementations, the substituents may include one or more functional groups selected from methoxy, hydroxy, amino, carboxyl, aldehyde, nitro, hydroxymethyl, ketone, heteroatom, methyl, or ethyl. Heteroatoms are, for example, -F, -Cl, etc.

[0093] like Figure 7B As shown, X and Y represent substituents of azobenzene. The positions of the substituents are, for example, ortho P1, meta P2, or para P3.

[0094] like Figure 10 As shown, because small molecules with azobenzene structure can form lone pair electron-metal coordination bonds and metal-aromatic ring π-conjugated bonds with metals, and because of the electrostatic adsorption between small molecules with azobenzene structure and metals, small molecules with azobenzene structure can selectively adsorb on the metal surface (e.g., the first surface 101), and hardly form on the second surface 102.

[0095] In some embodiments, by adjusting the type and position of substituents, the electron cloud density on the benzene ring of azobenzene can be adjusted, thereby regulating the adsorption properties between small molecules with an azobenzene structure and metal surfaces.

[0096] According to some embodiments, the azobenzene in the suppression layer 103 has one or more substituents. When the azobenzene has multiple substituents, the types of substituents can be the same or different. In other words, the azobenzene in the suppression layer 103 can have one or more substituents.

[0097] Figure 7C Different embodiments of azobenzene with one substituent are shown.

[0098] like Figure 7C As shown in (a), there is a substituent -OH at the ortho position of one of the benzene rings of azobenzene.

[0099] like Figure 7C As shown in (b), there is a substituent -OH at the meta position of one of the benzene rings of azobenzene.

[0100] like Figure 7C As shown in (c), there is a substituent -OH at the para position of one of the benzene rings of azobenzene.

[0101] like Figure 7C As shown in (d), there is a substituent -F at the para position of one of the benzene rings of azobenzene.

[0102] like Figure 7C As shown in (e), there is a substituent -CHO at the para position of one of the benzene rings of azobenzene.

[0103] like Figure 7C As shown in (f), there is a substituent -CH2OH at the para position of one of the benzene rings of azobenzene.

[0104] Figure 7D Different embodiments of azobenzene with two substituents are shown.

[0105] like Figure 7D As shown in (a), azobenzene has two different substituents, one -NH2 on one benzene ring of azobenzene and the other -OH on another benzene ring of azobenzene.

[0106] like Figure 7D As shown in (b), azobenzene has two substituents of the same kind, both of which are -OH, and one -OH is on one benzene ring of azobenzene and the other -OH is on another benzene ring of azobenzene.

[0107] According to some embodiments, the azobenzene in the suppression layer 103 has two symmetrically distributed substituents, wherein one of the two substituents is on one benzene ring of the azobenzene, and the other of the two substituents is on another benzene ring of the azobenzene. The symmetrically distributed two substituents facilitate the formation of a self-assembled monolayer and can effectively suppress the formation of the subsequent target layer, while also facilitating its subsequent removal.

[0108] As one implementation, the two symmetrically distributed substituents can be located at the para, ortho, or meta positions on their respective benzene rings. For example, Figure 7D As shown in (b), both substituents are located at the para position on their respective benzene rings.

[0109] According to some embodiments, the azobenzene in the suppression layer 103 has two substituents of the same kind. For example, such as Figure 7D As shown in (b), both substituents are -OH. Two substituents of the same type facilitate the formation of a self-assembled monolayer, and can effectively inhibit the formation of the subsequent target layer, while also facilitating its subsequent removal.

[0110] According to some embodiments, at least one substituent in the azobenzene of the suppression layer 103 is methoxy or nitro. As some implementations, the azobenzene has two substituents; for example, both substituents are methoxy; for another example, both substituents are nitro; and for yet another example, one of the two substituents is methoxy and the other is nitro. A self-organized monolayer of azobenzene with at least one substituent being methoxy or nitro can more effectively suppress the formation of subsequent target layers and is also easier to remove, thus better balancing the performance improvement of the semiconductor structure with the simplicity of process implementation.

[0111] According to some embodiments, the inhibition layer 103 is a polymer layer, such as an oligomer layer or a polymer layer. As some embodiments, the inhibition layer 103 is an azobenzene-based polymer layer. Figure 8 As shown, Figure 8 (a) and (b) show two different azobenzene-based polymer monomers that can form corresponding polymer layers. Figure 8 (c) shows another azobenzene-based polymer monomer and the structural changes of this polymer monomer before and after receiving light. Figure 8 (d) shows the structural changes of another azobenzene-based polymer monomer before and after receiving light.

[0112] In combination with the above Figures 3-6 In the scenario of interconnecting circuits of different layers in the integrated circuit manufacturing process, a through-hole structure with no obstruction layer at the bottom has been realized. On this basis, upper-layer circuit structures can be formed.

[0113] According to some embodiments, such as Figure 9 As shown, after removing the suppression layer 103 via step S40, conductive material 126 is filled into the via 125. For example, the conductive material 126 can be filled using methods such as chemical plating or reflow. The conductive material 126 can be used for interconnects in the upper circuit structure. After filling the conductive material 126, the target layer 104 (e.g., TaN) is used to isolate the conductive material 126 from the second dielectric layer 122 to prevent the conductive material 126 from diffusing into the second dielectric layer 122.

[0114] According to some embodiments, the conductive material 126 includes metals, such as Cu (copper), Co (cobalt), Ru (ruthenium), Al (aluminum), Ir (iridium), Rh (rhodium), Mo (molybdenum), etc. The type of conductive material 126 may be the same as or different from the material of the interconnect 111.

[0115] According to some embodiments, an adhesive layer may also be formed on the first surface 101 and the target layer 104 before the conductive material 126 is filled. The adhesive layer is used to make the contact between the conductive material 126 and the target layer 104 more reliable. According to some embodiments, the adhesive layer comprises Ta (tantalum). As one implementation, the adhesive layer is formed by a physical vapor deposition (PVD) process.

[0116] Furthermore, since plasma is required to remove the suppression layer 103 in the related technology, the application of plasma cannot be carried out in the chamber where the target layer 104 is formed, but needs to be transferred to another chamber, which complicates the process.

[0117] According to the method provided in this disclosure, the processes performed to remove the inhibition layer 103 (including at least one of heating and light irradiation) can be performed in the chamber forming the target layer 104 without additional transfer.

[0118] According to some embodiments, when the suppression layer 103 is illuminated with light, the light used is emitted by a light source 201 disposed on top of the cavity 200 for forming the target layer 104, such as... Figure 11 As shown. By integrating the light source 201 on top of the cavity 200 used to form the target layer 104, it is possible to avoid transferring the substrate 100 to other cavities, reduce the possibility of environmental contamination and reduce process complexity, thereby achieving cost reduction and efficiency improvement.

[0119] According to some embodiments, such as Figure 11 As shown, the cavity 200 for forming the target layer 104 has a spray member 202 inside, which allows gas to pass through and reach the substrate 100. The spray member 202 is made of a material for transmitting light that irradiates the suppression layer. For example, the spray member 202 is made of a transparent material (e.g., quartz glass or sapphire). The spray member 202 can also be referred to as a showerhead. The opening 203 is used to introduce the process gas, such as the precursor gas of the barrier layer, into the spray member 202. The spray member 202 is made of a material for transmitting light that irradiates the suppression layer, which ensures that the light emitted by the light source 201 (e.g., ultraviolet light) can pass through to irradiate the substrate 100 and the suppression layer 103.

[0120] According to some embodiments, the inner wall of the cavity 200 used to form the target layer 104 is treated with a hydrophobic coating or is cleaned periodically to prevent impurity particles from accumulating on the surface of the inner wall of the cavity 200.

[0121] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0122] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate having a first surface and a second surface; An inhibition layer is selectively formed on the first surface; A target layer is selectively formed on the second surface, wherein the inhibition layer acts as an inhibitor of the target layer; A process is performed to remove the inhibition layer, the process including at least one of irradiating the inhibition layer with light and heating.

2. The method according to claim 1, wherein, The suppression layer is a monolayer with photoresponsive properties.

3. The method according to claim 2, wherein, The inhibition layer is a self-assembled monolayer based on azobenzene.

4. The method according to claim 3, wherein, The azobenzene has one or more substituents.

5. The method according to claim 4, wherein, The azobenzene has two symmetrically distributed substituents, wherein one of the two substituents is on one benzene ring of the azobenzene, and the other of the two substituents is on another benzene ring of the azobenzene.

6. The method according to claim 4 or 5, wherein, The azobenzene has two substituents of the same type.

7. The method according to claim 4 or 5, wherein, At least one substituent is a methoxy or nitro group.

8. The method according to any one of claims 1-5, wherein, The light mentioned is ultraviolet light.

9. The method according to claim 8, wherein: The wavelength range of the ultraviolet light is 250nm to 400nm; and / or The power range of the ultraviolet light is 1W to 500W; and / or The duration of irradiation of the inhibition layer with ultraviolet light is 1 second to 120 seconds.

10. The method according to any one of claims 1-5, wherein, The first surface includes the surface of a metal layer, the second surface includes the surface of a dielectric layer, and the target layer includes a barrier layer; The dielectric layer has a through-hole, the first surface is located at the bottom of the through-hole, and the second surface includes the sidewall of the through-hole.

11. The method of claim 10, further comprising: After removing the inhibition layer, the through-hole is filled with a conductive material.

12. The method of claim 11, further comprising: An adhesive layer is formed on the first surface and the target layer before the conductive material is filled.

13. The method according to any one of claims 1-5, wherein, The light is emitted by a light source positioned at the top of the cavity used to form the target layer.

14. The method according to claim 13, wherein, The cavity has a spray component inside for allowing gas to pass through and reach the substrate, and the spray component is made of a material for transmitting light.

15. The method according to any one of claims 1-5, wherein, During the process of performing the process, flowing gas is introduced into the chamber in which the process is performed.

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