Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the method comprises the steps: removing a residual silicon oxide layer located in an inclined plane region before forming a metal silicide, then forming a metal silicide layer, enabling a subsequently formed adhesion layer to be in contact with the inclined plane metal silicide layer in the inclined plane region through forming the inclined plane metal silicide layer in the inclined plane region, and enabling the adhesion layer to be in contact with the inclined plane metal silicide layer in the inclined plane region. As the stress of the adhesion layer and the stress of the inclined surface metal silicide layer are adaptive, the adhesion layer does not generate bulge peeling, so that sheet-shaped defects are not generated to block the contact hole, and the production yield is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology and relates to a semiconductor device and its fabrication method. Background Technology

[0002] In semiconductor manufacturing, before filling contact holes with tungsten (W), an adhesion layer (Glue Layer) is first formed to ensure good adhesion between the tungsten and the underlying material and to prevent tungsten diffusion.

[0003] Ti / TiN composite films are typically used as the adhesion layer. During the formation of the adhesion layer, the adhesion layer comes into direct contact with the bevel area of ​​the wafer, generating huge stress. This causes large bulges and peeling of the adhesion layer, resulting in sheet-like defects that block the contact holes. Consequently, tungsten cannot fill the contact holes, leading to tungsten deficiency in the contact holes and causing severe yield loss.

[0004] If a non-metallic dielectric layer is deposited on the beveled area of ​​the wafer as a buffer layer before the adhesion layer is formed, so that the subsequent adhesion layer does not directly contact the beveled area of ​​the wafer, bulging of the adhesion layer can be avoided, but the cost will increase.

[0005] Therefore, how to provide a semiconductor device and its fabrication method to reduce costs and improve yield has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which solves the problem of adhesion layer bulging and peeling, resulting in reduced yield and increased production costs in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0008] A semiconductor substrate is provided, wherein the semiconductor substrate is divided into a central region, an edge region and a sloped region in a direction from the center of the semiconductor substrate to the edge, and the upper surface of the sloped region is lower than the upper surface of the central region;

[0009] An STI structure and a MOS structure are formed in the central region. The MOS structure includes a source region, a drain region in the semiconductor substrate, and a gate polysilicon located above the semiconductor substrate. After the STI structure and the MOS structure are formed, a residual silicon oxide layer is formed on the upper surface of the sloped region.

[0010] Remove the residual silicon oxide layer on the upper surface of the sloped region to expose the upper surface of the sloped region;

[0011] A metal layer is formed on the structure after the residual silicon oxide layer is removed and then annealed. A source metal silicide layer is formed in the source region, a drain metal silicide layer is formed in the drain region, a gate metal silicide layer is formed on the top surface of the gate polysilicon, and a slope metal silicide layer is formed on the top surface of the slope region.

[0012] An etch stop layer and an insulating dielectric layer are stacked on the semiconductor substrate, and the insulating dielectric layer and the etch stop layer are patterned to form contact holes that expose the source metal silicide layer, the drain metal silicide layer and the gate metal silicide layer. During the patterning of the insulating dielectric layer and the etch stop layer, the insulating dielectric layer and the etch stop layer located above the sloped metal silicide layer are removed.

[0013] An adhesion layer is formed, which is located on the inner wall and bottom of the contact hole, and is located above and in contact with the inclined metal silicide layer.

[0014] Optionally, the step of removing the residual silicon oxide layer from the upper surface of the sloped region includes:

[0015] With the lower surface of the semiconductor substrate facing upwards, an etching solution is applied from the lower surface of the semiconductor substrate, and the etching solution flows to the upper surface of the semiconductor substrate;

[0016] A purge gas is applied to the upper surface of the semiconductor substrate to purge the etching solution, thereby causing the etching solution to etch away the residual silicon oxide layer on the upper surface of the beveled region.

[0017] Optionally, the etching solution is a hydrofluoric acid solution, and the purging gas is nitrogen.

[0018] Optionally, the semiconductor substrate is a silicon substrate.

[0019] Optionally, the metal layer includes at least one of a Ni layer, a Pt layer, and a NiPt layer.

[0020] Optionally, the etching stop layer is a silicon nitride layer, and the insulating dielectric layer is a silicon oxide layer.

[0021] Optionally, the adhesion layer comprises a stacked Ti layer and a TiN layer.

[0022] Optionally, after forming the adhesion layer, the method further includes the step of forming a tungsten conductive layer in the contact hole.

[0023] Optionally, the sidewalls of the gate polysilicon are formed with sidewalls, and the source metal silicide layer, the drain metal silicide layer, the gate metal silicide layer and the sloped metal silicide layer are formed using a self-aligned metal silicide process.

[0024] The present invention also provides a semiconductor device, which is manufactured by the method for manufacturing a semiconductor device described in any of the preceding claims.

[0025] As described above, in the semiconductor device and its fabrication method of the present invention, before forming the metal silicide, the residual silicon oxide layer located in the inclined region is removed first, and then the metal silicide layer is formed. By forming the inclined metal silicide layer in the inclined region, the subsequently formed adhesion layer contacts the inclined metal silicide layer in the inclined region. Due to the stress matching between the adhesion layer and the inclined metal silicide layer, the adhesion layer will not bulge or peel off, thereby preventing sheet-like defects from blocking the contact holes and improving the production yield. Attached Figure Description

[0026] Figures 1 to 4 This is a cross-sectional view showing the various stages of a semiconductor device fabrication process.

[0027] Figure 5 Displayed as Figure 4 An enlarged view of the area within the dashed elliptical box.

[0028] Figure 6 The diagram shown is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention.

[0029] Figure 7 The diagram shown is a schematic representation of a semiconductor substrate provided in an embodiment of the present invention.

[0030] Figure 8 The diagram shown illustrates the formation of the STI and MOS structures in an embodiment of the present invention.

[0031] Figure 9 Displayed as Figure 8 An enlarged view of the area within the dashed elliptical box.

[0032] Figure 10 The diagram shown is a schematic diagram of removing the residual oxide layer in the inclined area in an embodiment of the present invention.

[0033] Figure 11 Displayed as Figure 10 An enlarged view of the area within the dashed elliptical box.

[0034] Figure 12 This diagram illustrates the process of introducing purge gas when using an etching solution to remove residual oxide layer in a sloped area, as shown in an embodiment of the present invention.

[0035] Figure 13The diagram shown is a schematic diagram of the formation of a metal silicide layer in an embodiment of the present invention.

[0036] Figure 14 Displayed as Figure 13 An enlarged view of the area within the dashed elliptical box.

[0037] Figure 15 The diagram shown illustrates the formation of an etch stop layer and an insulating dielectric layer in an embodiment of the present invention.

[0038] Figure 16 The diagram shown is a schematic diagram of the formation of a contact hole in an embodiment of the present invention.

[0039] Figure 17 The diagram shown is a schematic diagram of the formation of the adhesion layer in an embodiment of the present invention.

[0040] Figure 18 Displayed as Figure 17 An enlarged view of the area within the dashed elliptical box.

[0041] Component designation explanation

[0042] 1 Semiconductor substrate

[0043] 100 Central Area

[0044] 101 Edge Area

[0045] 102 Slope area

[0046] 2 STI Structure

[0047] 3. MOS Structure

[0048] 300 source region

[0049] 301 Leakage Zone

[0050] 302 gate polysilicon

[0051] 4. Electrostatic discharge structure

[0052] 5 Residual silicon oxide layer

[0053] 6. Etching solution

[0054] 7 Source-end metal silicide layer

[0055] 8. Drain-end metal silicide layer

[0056] 9. Gate-end metallide layer

[0057] 10. Sloping metal silicide layer

[0058] 11 Etching Stop Layer

[0059] 12 Insulating dielectric layer

[0060] 13 Contact Holes

[0061] 14 Adhesion layer

[0062] Steps S1 to S6 Detailed Implementation

[0063] Currently, the formation of semiconductor devices includes the following steps:

[0064] (a) such as Figure 1 As shown, an STI structure 2 and a MOS structure 3 are formed in the central region 100 of the semiconductor substrate 1. When the silicon oxide layer of the STI structure 2 is chemically mechanically polished, silicon oxide remains in the edge region and the inclined region of the semiconductor substrate 1, forming a residual silicon oxide layer 5.

[0065] (ii) Figure 2 As shown, a source metal silicide layer 7, a drain metal silicide layer 8, and a gate metal silicide layer 9 are formed by a self-aligned metal silicide process.

[0066] (III) Figure 3 As shown, an etch stop layer 11 and an insulating dielectric layer 12 are formed, and the insulating dielectric layer 12 and the etch stop layer 11 are patterned to form a contact hole 13. During the patterning process, the photoresist layer needs to be "washed" and the photoresist layer above the slope area will be removed, resulting in the removal of the insulating dielectric layer 12, the etch stop layer 11 and the residual silicon oxide layer 5 above the slope area.

[0067] (iv) such as Figure 4 and Figure 5 As shown, an adhesion layer 14 (Ti / TiN) is formed. Since the insulating dielectric layer 12, the etch stop layer 11 and the residual silicon oxide layer 5 above the inclined region 102 are removed, the adhesion layer 14 (Ti / TiN) and the semiconductor substrate 1 (Si) are in direct contact in the inclined region 102, generating huge stress. This causes large bulges and peeling of the adhesion layer, resulting in sheet-like defects that block the contact holes and reduce the yield.

[0068] Therefore, the purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, so as to prevent the adhesive layer from bulging and peeling off and blocking the contact holes, thereby improving yield and reducing cost.

[0069] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] Please see Figures 6 to 18 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0071] This embodiment provides a method for fabricating a semiconductor device. Please refer to [link / reference]. Figure 6 The method for manufacturing the semiconductor device includes the following steps:

[0072] S1: A semiconductor substrate is provided, wherein the semiconductor substrate is divided into a central region, an edge region and a sloped region in a direction from the center of the semiconductor substrate to the edge, and the upper surface of the sloped region is lower than the upper surface of the central region;

[0073] S2: An STI structure and a MOS structure are formed in the central region. The MOS structure includes a source region, a drain region in the semiconductor substrate, and a gate polysilicon located above the semiconductor substrate. After the STI structure and the MOS structure are formed, a residual silicon oxide layer is formed on the upper surface of the sloped region.

[0074] S3: Remove the residual silicon oxide layer on the upper surface of the inclined area to expose the upper surface of the inclined area;

[0075] S4: A metal layer is formed on the structure after the residual silicon oxide layer is removed and annealing is performed. A source metal silicide layer is formed in the source region, a drain metal silicide layer is formed in the drain region, a gate metal silicide layer is formed on the top surface of the gate polysilicon, and a slope metal silicide layer is formed on the top surface of the slope region.

[0076] S5: An etch stop layer and an insulating dielectric layer are stacked on the semiconductor substrate, and the insulating dielectric layer and the etch stop layer are patterned to form contact holes that expose the source metal silicide layer, the drain metal silicide layer and the gate metal silicide layer. During the patterning of the insulating dielectric layer and the etch stop layer, the insulating dielectric layer and the etch stop layer located above the inclined metal silicide layer are removed.

[0077] S6: Form an adhesion layer located on the inner wall and bottom of the contact hole, and the adhesion layer is located above and in contact with the inclined metal silicide layer.

[0078] The fabrication method of the semiconductor device in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0079] First, please refer to Figure 7 Step S1: Provide a semiconductor substrate 1, which is divided into a central region 100, an edge region 101 and a sloped region 102 in a direction from the center of the semiconductor substrate 1 to the edge. The upper surface of the sloped region 102 is lower than the upper surface of the central region 100.

[0080] As an example, the semiconductor substrate 1 may be a wafer, or the semiconductor substrate 1 may be composed of a wafer and an epitaxial layer, depending on the requirements.

[0081] As an example, the semiconductor substrate 1 can be any suitable semiconductor material. In this embodiment, the semiconductor substrate 1 is a silicon substrate.

[0082] As an example, the upper surface of the beveled region 102 is lower than the upper surface of the central region 100, that is, the outermost edge of the wafer is chamfered to prevent the wafer edge from cracking or stress concentration from causing fragmentation.

[0083] As an example, a well region is formed in the semiconductor substrate 1.

[0084] Next, please refer to Figure 8 and Figure 9 Step S2 is performed: an STI structure 2 and a MOS structure 3 are formed in the central region 100. The MOS structure 3 includes a source region 300, a drain region 301 located in the semiconductor substrate 1, and a gate polysilicon 302 located above the semiconductor substrate 1. After the STI structure 2 and the MOS structure 3 are formed, a residual silicon oxide layer 5 is formed on the upper surface of the sloped region 102.

[0085] As an example, the STI structure 2 is a shallow trench isolation structure, which is used to isolate the central region 100 into different functional areas.

[0086] As an example, the steps for forming the STI structure 2 include:

[0087] (i) A groove is formed at a predetermined position on the semiconductor substrate 1;

[0088] (ii) A silicon oxide dielectric layer is formed on the semiconductor substrate 1 and the silicon oxide dielectric layer is filled into the groove;

[0089] (iii) The silicon oxide dielectric layer located above the semiconductor substrate 1 is removed by chemical mechanical polishing (CMP), while the silicon oxide dielectric layer located in the groove is retained.

[0090] As an example, when forming the groove of the STI structure 2 in the central region 100, the photoresist "washing" will form "useless grooves" in the bevel region 102 and the edge region 101. The silicon oxide dielectric layer is also deposited in the "useless grooves". The silicon oxide dielectric layer in the "useless grooves" serves as a residual silicon oxide layer. Since there is no pattern support in the bevel region 102 and the edge region 101, and the pressure in the bevel region 102 and the edge region 101 is uncontrollable during the chemical mechanical polishing process, the polishing rate of the silicon oxide dielectric layer in the bevel region 102 will be faster, making the thickness of the residual silicon oxide layer 5 in the bevel region 102 smaller than the thickness of the residual silicon oxide layer 5 in the edge region 101.

[0091] As an example, the method for forming the MOS structure 2 is well known in the art and will not be described in detail here. A gate oxide layer is disposed below the gate polysilicon 302, and a sidewall layer is disposed on the sidewall of the gate polysilicon 302.

[0092] As an example, an electrostatic discharge (ESD) protection structure 4 is also formed at a predetermined location in the central region 100 to prevent electrostatic breakdown. The method for forming the ESD protection structure 4 is well known in the art and will not be described in detail here.

[0093] Next, please refer to Figures 10 to 12 Step S3: Remove the residual silicon oxide layer 5 on the upper surface of the inclined region 102 to expose the upper surface of the inclined region 102.

[0094] As an example, the beveled region 102 is the outermost region of the wafer, 149-150 mm, which means that the residual silicon oxide layer 5 with a width of about 150 mm in the beveled region 102 is removed.

[0095] For example, please refer to Figure 12 The step of removing the residual silicon oxide layer 5 from the upper surface of the inclined region 102 includes:

[0096] (i) With the lower surface of the semiconductor substrate 1 facing upward, an etching solution 6 is applied from the lower surface of the semiconductor substrate 1, and the etching solution 6 flows to the upper surface of the semiconductor substrate 1.

[0097] (ii) Apply a purge gas to the upper surface of the semiconductor substrate 1 to purge the etching solution 6, so that the etching solution 6 etches away the residual silicon oxide layer 5 on the upper surface of the inclined region 102.

[0098] As an example, the etching solution 6 is a hydrofluoric acid solution (HF), and the purging gas is nitrogen (N2). The purging gas is used to purge the etching solution 6, ensuring that the etching solution 6 removes only the residual silicon oxide layer 5 on the upper surface of the beveled region 102 without affecting other areas. During the removal of the residual silicon oxide layer 5 on the upper surface of the beveled region 102, the wafer is rotated by a rotating device.

[0099] Next, please refer to Figure 13 and Figure 14 Step S4: A metal layer is formed on the structure after the residual silicon oxide layer 5 is removed and annealing is performed. A source metal silicide layer 7 is formed in the source region 300, a drain metal silicide layer 8 is formed in the drain region 301, a gate metal silicide layer 9 is formed on the top surface of the gate polysilicon 302, and a sloped metal silicide layer 10 is formed on the top surface of the sloped region 102.

[0100] As an example, the metal layer includes at least one of a Ni layer, a Pt layer, and a NiPt layer. The metal layer is in contact with the source region 300, the drain region 301, the gate polysilicon 302, and the sloped region 102. After annealing, the source metal silicide layer 7, the drain metal silicide layer 8, the gate metal silicide layer 9, and the sloped metal silicide layer 10 are formed.

[0101] Specifically, the source metal silicide layer 7, the drain metal silicide layer 8, the gate metal silicide layer 9, and the beveled metal silicide layer 10 are formed using a self-aligned metal silicide process. That is, in areas where metal silicides do not need to be formed, the metal layer is in contact with the dielectric layer. During the annealing process, the metal layer will not react with the dielectric layer to form metal silicides. After annealing, the unreacted metal layer is removed.

[0102] Next, please refer to Figure 15 and Figure 16 Step S5: An etch stop layer 11 and an insulating dielectric layer 12 are stacked on the semiconductor substrate 1, and the insulating dielectric layer 12 and the etch stop layer 11 are patterned to form contact holes 13 that expose the source metal silicide layer 7, the drain metal silicide layer 8 and the gate metal silicide layer 9. During the patterning of the insulating dielectric layer 11 and the etch stop layer 12, the insulating dielectric layer 11 and the etch stop layer 12 located above the inclined metal silicide layer 10 are removed.

[0103] As an example, the etch stop layer 11 is a silicon nitride layer, and the insulating dielectric layer 12 is a silicon oxide layer. The etch stop layer 11 serves as an etch stop layer during the etching process of forming the contact hole to prevent over-etching from damaging the metal silicide or transistor structure below the contact hole 13. The insulating dielectric layer 12 serves as a metal front dielectric layer to isolate the front end of the transistor from the rear end metal interconnect.

[0104] As an example, the insulating dielectric layer 12 is relatively thick. After depositing the insulating dielectric layer 12, the insulating dielectric layer 12 is subjected to chemical mechanical polishing to obtain a globally planarized surface, which is beneficial for performing subsequent processes.

[0105] As an example, the steps for forming the contact hole 13 include:

[0106] (i) A photoresist layer is formed on the insulating dielectric layer 12, and the photoresist layer is patterned by processes such as exposure and development to define the position of the contact hole 13;

[0107] (ii) The insulating dielectric layer 12 is etched using a dry etching process. Due to the difference in etching selectivity, the etching stops at the etching stop layer 11. Different etching gases are switched to etch the etching stop layer 11 to expose the metal silicide layer.

[0108] (iii) Wet cleaning is used to remove byproducts (Polymer) from the etching process.

[0109] As an example, when forming a photoresist layer on the insulating dielectric layer 12, due to centrifugal force, excess photoresist will flow towards the edges, resulting in the photoresist layer above the inclined region 102 and the edge region 101 being thicker than the photoresist layer above the central region 100. It is necessary to "wash" away the photoresist layer above the inclined region 102 and the edge region 101. If the photoresist layer above the inclined region 102 and the edge region 101 is not removed, due to its thickness, it cannot be completely dissolved during subsequent exposure and development, resulting in photoresist residue that will contaminate the effective area of ​​the wafer.

[0110] As an example, since the "edge washing" removes the photoresist layer above the beveled region 102 and the edge region 101, the etching stop layer 11 and the insulating dielectric layer 12 above the beveled region 102 and the edge region 101 will be removed during the formation of the contact hole 13. The beveled metal silicide layer 10 will be exposed in the beveled region 102, and the residual silicon oxide layer 5 will be exposed in the edge region 101. Since the residual silicon oxide layer 5 in the edge region 101 is relatively thick, it will not be completely "eaten up" during the formation of the contact hole 13.

[0111] Next, please refer to Figure 17 and Figure 18 Step S6 is executed: forming an adhesion layer 14, which is located on the inner wall and bottom of the contact hole 13, and is located above and in contact with the inclined metal silicide layer 10.

[0112] As an example, the material of the adhesion layer 14 includes a stacked Ti layer and a TiN layer (Ti / TiN). The Ti layer can improve the bonding force between the subsequently formed tungsten conductive layer and the metal silicide layer, and the TiN layer can prevent the subsequently formed tungsten conductive layer from diffusing into the metal silicide layer or the dielectric layer.

[0113] As an example, in the inclined region 102, the adhesive layer 14 and the inclined metal silicide layer 10 are in contact. Due to the stress matching between the adhesive layer 14 and the inclined metal silicide layer 10, the adhesive layer 14 will not bulge or peel off, thus preventing sheet defects and improving production yield.

[0114] As an example, after forming the adhesion layer 14, the method further includes the step of forming a tungsten conductive layer in the contact hole 13, wherein the tungsten conductive layer fills the contact hole 13 to form a tungsten contact plug.

[0115] This embodiment also provides a semiconductor device, which is manufactured by the semiconductor device manufacturing method described above.

[0116] In summary, in the semiconductor device and its fabrication method of the present invention, before forming the metal silicide, the residual silicon oxide layer located in the inclined region is removed, and then the metal silicide layer is formed. By forming an inclined metal silicide layer in the inclined region, the subsequently formed adhesion layer contacts the inclined metal silicide layer in the inclined region. Due to the stress matching between the adhesion layer and the inclined metal silicide layer, the adhesion layer will not bulge or peel off, thus preventing sheet-like defects from blocking contact holes and improving production yield. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A semiconductor substrate is provided, wherein the semiconductor substrate is divided into a central region, an edge region and a sloped region in a direction from the center of the semiconductor substrate to the edge, and the upper surface of the sloped region is lower than the upper surface of the central region; An STI structure and a MOS structure are formed in the central region. The MOS structure includes a source region, a drain region in the semiconductor substrate, and a gate polysilicon located above the semiconductor substrate. After the STI structure and the MOS structure are formed, a residual silicon oxide layer is formed on the upper surface of the sloped region. Remove the residual silicon oxide layer on the upper surface of the sloped region to expose the upper surface of the sloped region; A metal layer is formed on the structure after the residual silicon oxide layer is removed and then annealed. A source metal silicide layer is formed in the source region, a drain metal silicide layer is formed in the drain region, a gate metal silicide layer is formed on the top surface of the gate polysilicon, and a slope metal silicide layer is formed on the top surface of the slope region. An etch stop layer and an insulating dielectric layer are stacked on the semiconductor substrate, and the insulating dielectric layer and the etch stop layer are patterned to form contact holes that expose the source metal silicide layer, the drain metal silicide layer and the gate metal silicide layer. During the patterning of the insulating dielectric layer and the etch stop layer, the insulating dielectric layer and the etch stop layer located above the sloped metal silicide layer are removed. An adhesion layer is formed, which is located on the inner wall and bottom of the contact hole, and is located above and in contact with the inclined metal silicide layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of removing the residual silicon oxide layer from the upper surface of the sloped region includes: With the lower surface of the semiconductor substrate facing upwards, an etching solution is applied from the lower surface of the semiconductor substrate, and the etching solution flows to the upper surface of the semiconductor substrate; A purge gas is applied to the upper surface of the semiconductor substrate to purge the etching solution, thereby causing the etching solution to etch away the residual silicon oxide layer on the upper surface of the beveled region.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that: The etching solution is a hydrofluoric acid solution, and the purging gas is nitrogen.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that: The semiconductor substrate is a silicon substrate.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that: The metal layer includes at least one of a Ni layer, a Pt layer, and a NiPt layer.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that: The etching stop layer is made of silicon nitride, and the insulating dielectric layer is made of silicon oxide.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that: The adhesion layer comprises a stacked Ti layer and a TiN layer.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that: After forming the adhesion layer, the method further includes the step of forming a tungsten conductive layer in the contact hole.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that: The gate polysilicon has sidewalls formed on its sidewalls, and the source metal silicide layer, the drain metal silicide layer, the gate metal silicide layer, and the sloped metal silicide layer are formed using a self-aligned metal silicide process.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1-9.

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