Method of manufacturing through holes and semiconductor devices

Abstract

The application provides a via hole and a semiconductor device manufacturing method, and belongs to the semiconductor field. The via hole manufacturing method comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises an etching stop layer; coating a first photoresist on the surface of the semiconductor structure, and performing first PRB baking on the first photoresist to obtain a first photoresist layer; coating a second photoresist on the surface of the first photoresist layer, and performing second PRB baking on the second photoresist to obtain a second photoresist layer, wherein the static sensitivity of the second photoresist layer is lower than that of the first photoresist layer; performing exposure on the first photoresist layer and the second photoresist layer; performing development on the first photoresist layer and the second photoresist layer to form a via hole manufacturing area so as to expose the semiconductor structure at the bottom of the via hole manufacturing area; and etching the semiconductor structure at the bottom of the via hole manufacturing area until the etching stop layer is reached to form a via hole. The method can avoid the development residues caused by the static electricity of the photoresist, and ensure the appearance of the via hole.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor, and particularly relates to a via hole and a preparation method of a semiconductor device. BACKGROUND

[0002] A semiconductor device is structurally stacked by layers of films, including semiconductor layers, metal layers, etc. To ensure that signals can be transmitted between the films, vias are usually formed by photolithography and etching processes.

[0003] In the existing via hole preparation process, a photoresist layer (such as a photoresist layer) is first formed on the surface of the semiconductor layer, and then the photoresist layer is exposed and developed to image the photoresist layer (i.e. to form a pattern corresponding to the via hole). After etching the semiconductor layer under the blocking action of the patterned photoresist layer, the photoresist layer is removed, and the via hole formed in the semiconductor layer is obtained.

[0004] However, due to the photolithography process, the photoresist layer used in the via hole is generally an electrostatic photoresist layer. The core performance requirements of the photoresist layer are generally related to its insulating property (electrostatic property). Since the size of the via hole is extremely small (usually nanoscale), it requires the photoresist to have extremely high resolution. High-resolution photoresist layers usually require low molecular weight / narrow molecular weight distribution, high photosensitivity chemical structure. These characteristics essentially require high-resolution photoresist layers to be highly pure organic polymers, i.e. excellent insulators. In addition, the photoresist layer used in the via hole preparation process also needs to further require its etching resistance (to avoid the photoresist layer being etched simultaneously during the via hole etching process), which further requires the photoresist layer used in the via hole preparation process to have high cross-linking density, and the highly cross-linked dense structure will further hinder the migration of electric charges and aggravate the insulating property. The above characteristics show that the photoresist layer used in the via hole requires strong insulating property.

[0005] The stronger the insulation performance of the photoresist layer is, the stronger the ability to hinder the movement of charges is, which will cause the charges generated in the process of preparing the via to accumulate in the photoresist layer, thereby forming an electrostatic field (that is, the stronger the insulation performance is, the easier the electrostatic is generated). In addition, due to the low opening rate of the photoresist layer used in the process of preparing the via, the large specific surface area will cause the photoresist layer to be prone to electrostatic in the developing process. At the same time, the photoresist layer is affected by the developing process in the developing process, and the PH shock effect will occur, thereby causing the developing residue (that is, part of the photoresist layer is not developed, and the residue will be generated). In addition, under the action of the electrostatic generated in the developing process, the developing residue will inevitably adhere to the semiconductor layer in the via preparation area. The developing residue will cause the prepared via to be poor or the etching process to be unable to etch the semiconductor layer to form the via under the blocking action of the developing residue. SUMMARY

[0006] Therefore, the application provides a method for preparing a via and a semiconductor device, which aims to prepare a via with good appearance, and improve the performance and reliability of the semiconductor device including the via by preparing the via with good appearance.

[0007] In a first aspect, the application provides a method for preparing a via, comprising:

[0008] providing a semiconductor structure, wherein the semiconductor structure comprises an etching stop layer;

[0009] coating a first photoresist on the surface of the semiconductor structure, and performing first PRB baking on the first photoresist to obtain a first photoresist layer;

[0010] coating a second photoresist on the surface of the first photoresist layer, and performing second PRB baking on the second photoresist to obtain a second photoresist layer, wherein the electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer;

[0011] exposing the first photoresist layer and the second photoresist layer;

[0012] developing the first photoresist layer and the second photoresist layer to form a via preparation area to expose the semiconductor structure at the bottom of the via preparation area;

[0013] etching the semiconductor structure at the bottom of the via preparation area until the etching stop layer is reached to form a via.

[0014] Optionally, the PRB sensitivity of the second photoresist is higher than that of the first photoresist.

[0015] Optionally, the second photoresist comprises any one of I-line photoresist, krF photoresist, and ArF photoresist.

[0016] Optionally, the PRB baking temperature of the second photoresist is lower than the PRB baking temperature of the first photoresist.

[0017] Optionally, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8:9~10:11.

[0018] Optionally, the PRB baking time of the second photoresist is lower than the PRB baking time of the first photoresist.

[0019] Optionally, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 1:2~3:4.

[0020] Optionally, the opening width of the second photoresist layer at the via preparation area is smaller than the opening width of the first photoresist layer at the via preparation area.

[0021] Optionally, the thickness of the first photoresist layer is greater than the thickness of the etching stop layer.

[0022] Optionally, the thickness of the first photoresist layer is 1.2~1.8 times the thickness of the etching stop layer.

[0023] Optionally, the step of developing the first photoresist layer and the second photoresist layer comprises:

[0024] a developing step of developing the first photoresist layer and the second photoresist layer with a developing solution;

[0025] a deionized water cleaning step of cleaning the developed first photoresist layer and the second photoresist layer with deionized water;

[0026] a nitrogen blowing step of blowing the first photoresist layer and the second photoresist layer with nitrogen;

[0027] periodically performing the deionized water cleaning step and the nitrogen blowing step on the first photoresist layer and the second photoresist layer, and ending the developing.

[0028] Optionally, the step of etching the semiconductor structure of the via preparation area comprises:

[0029] etching the semiconductor structure at the bottom of the via preparation area and synchronously etching the second photoresist layer;

[0030] after the second photoresist layer is removed, continuing to etch the semiconductor structure at the bottom of the via preparation area under the blocking of the first photoresist layer until etching to the etching stop layer, forming a via.

[0031] Optionally, the plasma etching process is adopted, and the etching power is 100W-500W, the etching gas is fluorine-based gas, the temperature is 20-90℃, and the pressure is 5-10Pa.

[0032] In a second aspect, the application provides a method for manufacturing a semiconductor device, which comprises the method according to any one of the preceding aspects.

[0033] The technical scheme provided by the application has at least the following unexpected technical effects:

[0034] The second photoresist layer is made on the surface of the first photoresist layer, the second photoresist layer has lower insulation than the first photoresist layer, and the second photoresist layer covers the first photoresist layer. The unexpected technical effect is that the first photoresist layer is covered by the second photoresist layer with lower electrostatic sensitivity, which can avoid the accumulation of charges in the first photoresist layer during the development process. The second photoresist layer with lower electrostatic sensitivity has better charge migration ability than the first photoresist layer, and the second photoresist layer itself does not accumulate charges and is beneficial to release the accumulated charges in the first photoresist layer, thereby avoiding the accumulation of charges to generate an electrostatic field, i.e. avoiding the adhesion of development residues to the through-hole preparation area due to the effect of static electricity after development, and ensuring that the prepared through-hole is better. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical scheme in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0036] Figure 1 The flow chart of the method for manufacturing a through-hole is provided for an embodiment of the application.

[0037] Figure 2 The substrate structure schematic diagram provided in the manufacturing process of the semiconductor structure is provided for an embodiment of the application.

[0038] Figure 3 The schematic diagram of forming a first photoresist layer in the manufacturing process of the semiconductor structure is provided for an embodiment of the application.

[0039] Figure 4 The schematic diagram of forming a second photoresist layer in the manufacturing process of the semiconductor structure is provided for an embodiment of the application.

[0040] Figure 5 The schematic diagram of exposure in the manufacturing process of the semiconductor structure is provided for an embodiment of the application.

[0041] Figure 6 A schematic view of a semiconductor structure in an exposure area in a manufacturing process is provided.

[0042] Figure 7 A schematic view of a semiconductor structure in a via preparation area after development in a manufacturing process is provided.

[0043] Figure 8 A schematic view of a semiconductor structure after hard baking after development in a manufacturing process is provided.

[0044] Figure 9 A schematic view of a semiconductor structure in a via preparation area after etching the semiconductor structure at the bottom of the via preparation area in a manufacturing process is provided.

[0045] Figure 10 A schematic view of a semiconductor structure after the photoresist sacrificial layer is removed in a manufacturing process is provided.

[0046] Figure 11 A schematic view of a semiconductor structure after etching to the etch stop layer in a manufacturing process is provided.

[0047] Figure 12 A schematic view of a semiconductor structure in a via after removing the photoresist layer in a manufacturing process is provided.

[0048] Figure 13 A schematic view of a development process is provided.

[0049] Figure 14 A comparison view of a wafer after development is provided.

[0050] The reference signs are as follows:

[0051] 10: substrate; 100: etch stop layer; 11: first photoresist layer; 12: second photoresist layer; 13: mask plate; 14: exposure area; 15: via preparation area; 16: photoresist layer; 17: photoresist sacrificial layer; 18: via. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0053] Figure 1A flow chart of a method for manufacturing a via according to an embodiment of the present application is provided. Referring to Figure 1 The method comprises the following steps:

[0054] S101, providing a semiconductor structure, wherein the semiconductor structure comprises an etching stop layer.

[0055] In an example, the semiconductor structure can be any structure of a semiconductor device during manufacturing process, and the present application is not limited thereto.

[0056] For the convenience of understanding, the present application is described by taking a semiconductor structure as an example.

[0057] Referring to Figure 2 A schematic diagram of a semiconductor structure according to an embodiment of the present application is provided, wherein the semiconductor structure comprises a substrate 10, and the substrate 10 has an etching stop layer 100 inside.

[0058] S102, coating a first photoresist on the surface of the semiconductor structure, and performing a first PRB baking on the first photoresist to obtain a first photoresist layer.

[0059] In an example, the step S102 comprises:

[0060] Firstly, spin-coating the first photoresist on the surface of the semiconductor structure.

[0061] The first photoresist is a photoresist layer with good insulation performance, so as to ensure that the first photoresist layer formed subsequently has good etching performance when manufacturing the via. The resolution and fidelity of the photoresist pattern are ensured, thereby ensuring the morphology of the via manufactured. In addition, more accurate pattern transfer is also helpful to improve the electrical performance and reliability of the semiconductor device.

[0062] As an example, the first photoresist layer can be an EUV photoresist.

[0063] Secondly, performing a first PRB baking on the first photoresist at a first target temperature to form the first photoresist layer.

[0064] PRB (Post-Apply Bake) baking refers to a baking step performed after the photoresist is coated on the surface of the wafer and is uniformly spin-coated, but before exposure. The main purpose is to remove residual solvent, improve adhesion and stability, stabilize the photoresist film thickness, improve uniformity, and enhance exposure control.

[0065] In an example, the first target temperature is 90-110°C.

[0066] Exemplarily, the first target temperature is 100°C.

[0067] In an example, the baking time of the first photoresist layer is 60s-120s.

[0068] In an example, the baking time of the first photoresist layer is 80s.

[0069] In an example, the thickness of the first photoresist layer is greater than the thickness of the etching stop layer.

[0070] In an example, the thickness of the first photoresist layer is 1.2-1.8 times the thickness of the etching stop layer.

[0071] In an example, the thickness of the first photoresist layer is 1.5 times the thickness of the etching stop layer.

[0072] The first photoresist layer is used to protect the non-etching area during the via etching process, and the etching stop layer is used to ensure that the depth of each via is etched to the right position and does not appear to be etched too much during the via etching process.

[0073] In which, the depth of each via etched in the semiconductor structure meets the target depth, or is equal to the target depth.

[0074] In which, etching too much means that the depth of the via etched in the semiconductor structure exceeds the target depth, or the etched via not only exceeds the target depth, but also penetrates the semiconductor structure, resulting in damage to the semiconductor structure or the via connecting the semiconductor layers that should not be connected.

[0075] Since multiple vias need to be formed by etching in the semiconductor structure, it is impossible to ensure that the etching efficiency of each via is the same, so that some areas of the via will reach the target depth faster, while some areas of the via will reach the target depth slower. By setting the etching stop layer, when the via with faster etching speed meets the target depth, the etching stop layer can block the via with faster etching speed from continuing to extend downward, so that the depth of the via with faster etching speed no longer increases. Until the via with slower etching speed meets the target depth, the etching is stopped, which can ensure that the depth of the multiple vias formed in the semiconductor structure meets the target depth.

[0076] Referring to Figure 3 , a first photoresist layer 11 formed on the surface of the substrate 10 is specifically shown.

[0077] S103, coating a second photoresist on the surface of the first photoresist layer, and performing a second PRB baking on the second photoresist to obtain a second photoresist layer, the electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer.

[0078] In one example, step S103 comprises:

[0079] Firstly, coating a second photoresist on the surface of the first photoresist layer.

[0080] In one example, the PRB sensitivity of the second photoresist layer is higher than that of the first photoresist layer.

[0081] It should be noted that the PRB sensitivity (Post-Apply Bake Sensitivity) refers to the sensitivity of the final performance of the photoresist (especially the critical dimension of the pattern formed thereby) to the changes of the PRB (post-apply bake / pre-bake / soft bake) process parameters (mainly temperature and time).

[0082] More popularly, it measures how much the critical dimension of the photoresist pattern developed finally will deviate if the temperature of the PRB baking is slightly higher or lower, or the time is slightly longer or shorter; how much the slight fluctuation of the PRB baking parameters will "amplify" or affect the final pattern accuracy.

[0083] In one example, the solvent content of the second photoresist is 1.3 to 1.8 times that of the first photoresist.

[0084] For example, the solvent content of the second photoresist is 1.5 times that of the first photoresist.

[0085] In one example, the second photoresist comprises any one of I-line photoresist, krF photoresist, and ArF photoresist.

[0086] It should be noted that the types of the second photoresist described above are only some examples provided by the present application, and any photoresist that meets the PRB sensitivity and the subsequent electrostatic sensitivity can be used as the second photoresist of the present application.

[0087] Secondly, performing a second PRB baking on the second photoresist at a second target temperature to obtain a second photoresist layer, and the electrostatic sensitivity of the second photoresist layer is lower than that of the first photoresist layer.

[0088] It should be noted that the electrostatic sensitivity is used to characterize whether the photoresist layer is prone to static electricity. High electrostatic sensitivity indicates that the photoresist layer is prone to static electricity (or the migration ability of the electric charge in the photoresist layer is poor). Low electrostatic sensitivity indicates that the photoresist layer is difficult to produce static electricity or has a low possibility of producing static electricity (or the migration ability of the electric charge in the photoresist layer is relatively good).

[0089] In one example, the PRB baking temperature of the second photoresist is lower than that of the first photoresist.

[0090] In an example, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8-10:11, and more preferably 8:9-10:11.

[0091] For example, the ratio of the PRB baking temperature of the second photoresist to the PRB baking temperature of the first photoresist is 8.5:9.5.

[0092] In an example, the second target temperature is 80-100℃.

[0093] In an example, the PRB baking time of the second photoresist is lower than the baking time of the first photoresist.

[0094] In an example, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 1:2-3:4.

[0095] For example, the ratio of the PRB baking time of the second photoresist to the PRB baking time of the first photoresist is 2:3.

[0096] In an example, the PRB baking time of the second photoresist is 30-90s.

[0097] By adopting the first photoresist and the second photoresist with different properties, and by differentiating the baking of the first photoresist and the second photoresist, the first photoresist layer and the second photoresist layer are formed, so that the areas of the regions developed away after the exposure and development steps of the first photoresist layer and the second photoresist layer are different.

[0098] The area of the first photoresist layer developed away is greater than the second photoresist layer, that is, the opening width of the first photoresist layer is greater than the second photoresist layer, so as to ensure that the second photoresist layer can better cover the first photoresist layer, so as to ensure that the first photoresist layer is difficult to generate static electricity.

[0099] Referring to Figure 4 , it is specifically shown that the second photoresist layer 12 is formed on the surface of the first photoresist layer 11.

[0100] S104, the first photoresist layer 11 and the second photoresist layer 12 are exposed.

[0101] Wherein, the first photoresist layer 11 and the second photoresist layer 12 are exposed under the blocking action of the mask plate 13.

[0102] In an example, after the exposure is completed, the first photoresist layer 11 and the second photoresist layer 12 are subjected to post-exposure baking (PEB) at a third target temperature.

[0103] In an example, the third target temperature is 90-120 °C.

[0104] Referring to Figure 5 Under the shielding of the mask plate 13, the first photoresist layer 11 and the second photoresist layer 12 are subjected to exposure treatment.

[0105] Referring to Figure 6 After the first photoresist layer 11 and the second photoresist layer 12 are exposed, the exposure area 14 is formed. The exposure area 14 is an area formed after the first photoresist layer 11 and the second photoresist layer 12 react with light after the light is irradiated on the first photoresist layer 11 and the second photoresist layer 12 through the mask plate 13.

[0106] In an example, the exposure area 14 includes the first photoresist layer 11 and the second photoresist layer 12 after the reaction with light. The exposure area 14 is "convex", indicating that the area of the second photoresist layer 12 after the reaction with light is smaller than the area of the first photoresist layer 11 after the reaction with light.

[0107] S105, developing the first photoresist layer and the second photoresist layer to form a via preparation area to expose the semiconductor structure at the bottom of the via preparation area.

[0108] In an example, the step S105 includes:

[0109] Step 1, developing step: using a developing solution to develop the first photoresist layer and the second photoresist layer.

[0110] As an example, the developing solution is an alkaline developing solution, and the developing solution includes a TMAH solution with a proportion of 2.38%.

[0111] As an example, the PH value of the developing solution can be 11.8.

[0112] In other examples, the developing solution can be an acidic solution, and the application does not limit this. Those skilled in the art can select the type of developing solution as needed.

[0113] In an example, the area of the second photoresist layer developed away at the via preparation area is smaller than the area of the first photoresist layer developed away at the via preparation area, so as to ensure that the second photoresist layer can better cover the first photoresist layer.

[0114] Referring to Figure 7 Specifically, the via preparation area 15 is shown. The first photoresist layer 11 and the second photoresist layer 12 at the exposure area 14 are removed, thereby forming the via preparation area 15. The opening width of the second photoresist layer at the via preparation area is smaller than the opening width of the first photoresist layer at the via preparation area, so that the cross section of the remaining first photoresist layer 11 and the second photoresist layer 12 is T-shaped.

[0115] Step 2, deionized water cleaning step: deionized water is used to clean the first photoresist layer and the second photoresist layer after development.

[0116] The PH value of the deionized water is 7.

[0117] The deionized water cleaning is to clean the residual developing solution in the first photoresist layer, the second photoresist layer and the via preparation area, so as to avoid overdevelopment.

[0118] Step 3, nitrogen blowing step: nitrogen is used to blow the first photoresist layer and the second photoresist layer.

[0119] The nitrogen blowing refers to using nitrogen to blow the residual developing solution, deionized water and other liquids in the first photoresist layer, the second photoresist layer and the via preparation area.

[0120] Step 4, periodically performing the deionized water cleaning step and the nitrogen blowing step on the first photoresist layer and the second photoresist layer, and ending the development.

[0121] In an example, the cleaning time of the deionized water is 10s-30s in each cycle.

[0122] The cleaning time of the deionized water should not be too long, otherwise it will cause the PH value of the developing solution in the via preparation area to drop too fast, thereby causing the PH shock effect. If the cleaning time of the deionized water is too short, the cleaning efficiency of the developing solution in the via preparation area will be low.

[0123] In the process of cleaning the developing solution with deionized water, especially when cleaning the developing solution in the via preparation area, the PH shock effect is easy to occur, because the PH of the developing solution in the via preparation area is high and difficult to be removed (because the cross-sectional size of the via is small and the via is deep), and in the process of cleaning the developing solution in the via preparation area with deionized water, the PH of the developing solution in the via preparation area will quickly drop due to the cleaning of the deionized water. The rapid drop of the PH value will cause the photoresist that reacts with the developing solution to be developed to be precipitated, resulting in the formation of developing residues in the via preparation area.

[0124] The present application uses multiple rapid deionized water cleaning and nitrogen blowing steps to replace the residual developing solution in the via preparation area. Through multiple cleaning and multiple nitrogen blowing, the PH value of the developing solution can be gently lowered, the sudden drop of the PH of the developing solution can be avoided, the developing residues caused by the PH shock effect can be effectively avoided, and the morphology of the via prepared subsequently can be ensured.

[0125] In an example, after developing, the first photoresist layer and the second photoresist layer are subjected to hard bake, the first photoresist layer 11 becomes a photoresist layer 16, and the second photoresist layer 12 becomes a photoresist sacrificial layer 17.

[0126] Referring to Figure 8 , the photoresist layer 16 and the photoresist sacrificial layer 17 are specifically shown.

[0127] S106, etching the semiconductor structure at the bottom of the via preparation area until the etching stop layer is etched, to form a via.

[0128] In an example, the step S106 includes:

[0129] First, etching the semiconductor structure at the bottom of the via preparation area, and synchronously etching the second photoresist layer after hard bake (the second photoresist layer after hard bake becomes the etching photoresist sacrificial layer 17).

[0130] In an example, a plasma etching process is adopted, in an environment with a temperature of 20-90°C and a pressure of 5-10 Pa, an etching power of 100-500 W is adopted, and a fluorine-based gas is used as the etching gas.

[0131] For example, a plasma etching process is adopted, in an environment with a temperature of 40°C and a pressure of 8 Pa, an etching power of 200 W is adopted, and a fluorine-based gas is used as the etching gas.

[0132] As an example, the fluorine-based gas can include any one of , .

[0133] It should be noted that the above fluorine-based gas is only an example provided by the present application and is not used to limit the present application. Those skilled in the art should understand that as long as the gas can etch the semiconductor structure and the second photoresist layer, it can be used as the etching gas of the present application, and the etching gas of the present application is used to etch the photoresist sacrificial layer and the semiconductor structure.

[0134] Referring to Figure 9 , the etching direction of the plasma etching is specifically shown.

[0135] Second, after the second photoresist layer after hard bake is removed, the semiconductor structure at the bottom of the via preparation area is continuously etched under the blocking effect of the first photoresist layer after hard bake until the etching stop layer is etched, to form a via.

[0136] Referring to Figure 10 , after the photoresist sacrificial layer 17 is removed, a "T" shaped structure (i.e. the etched part of the semiconductor structure is "T-shaped") is formed at the bottom of the via preparation area 15.

[0137] Referring to Figure 11 , continue to etch the semiconductor structure at the bottom of the via preparation area 15, when etching to the surface of the etching stop layer 100, the semiconductor structure at the bottom of the via preparation area 15 is etched completely under the blocking effect of the etching stop layer 100, and a plane is formed at the bottom of the via preparation area, thereby obtaining a via 18 extending to the surface of the etching stop layer.

[0138] It should be noted that, for the sake of understanding, the substrate including the etching stop layer is described as a semiconductor structure in this application, while in the actual via preparation process, it is usually used to prepare a via for connecting a multi-layer structure, and the multi-layer structure is not equivalent to the substrate and the etching stop layer in this application.

[0139] Thirdly, after the via is formed, the photoresist layer is removed.

[0140] As an example, the photoresist layer 16 can be removed by a gray ash process.

[0141] Referring to Figure 12 , the structure formed after the photoresist layer 16 is removed is specifically shown.

[0142] Referring to Figure 13 For the sake of understanding, the developing process of this application is additionally described.

[0143] Firstly, a photoresist layer is prepared.

[0144] The first photoresist layer and the second photoresist layer of this application are formed in the first step.

[0145] Secondly, the photoresist layer is exposed to facilitate the formation of a pattern after subsequent development.

[0146] Thirdly, the exposed photoresist layer is developed by a developing solution to form a pattern.

[0147] As an example, the developing solution used is 2.38% TMAH (alkaline, PH value is 11.8).

[0148] It should be noted that during the developing process, the semiconductor structure is in a rotating state, thereby ensuring the developing efficiency.

[0149] Fourthly, the residual developing solution is cleaned by deionized water.

[0150] It should be noted that when the deionized water is used for cleaning, the semiconductor structure is in a rotating state to ensure the cleaning efficiency.

[0151] Fifthly, nitrogen is blown to remove the deionized water and the developing solution.

[0152] The residual liquid is removed by nitrogen blowing, and the developing process is completed.

[0153] In the fifth step, the semiconductor structure is also in a rotating state, and the residual developing liquid is quickly removed by nitrogen blowing and rotation of the substrate.

[0154] In the sixth step, the fourth step and the fifth step are periodically performed, and the developing is completed after the residual developing liquid is removed.

[0155] Referring to Figure 14 The wafer prepared by the via hole preparation method and the related via hole preparation method has a much lower developing residual on the surface than the wafer prepared by the related art, which is due to the use of the first photoresist layer and the second photoresist layer with different electrostatic sensitivities and the use of the periodic deionized water cleaning and nitrogen blowing steps for via hole preparation.

[0156] The application also provides a semiconductor device preparation method, which comprises Figure 1 The via hole preparation method.

[0157] Finally, it is worth noting that the technical method provided by the application has the following unexpected technical effects:

[0158] First, the second photoresist layer is made on the surface of the first photoresist layer, the second photoresist layer has lower insulation than the first photoresist layer, and the second photoresist layer covers the first photoresist layer. The unexpected technical effect is that the second photoresist layer with lower electrostatic sensitivity covers the first photoresist layer, which can avoid the accumulation of electric charge in the first photoresist layer during the developing process. The charge migration ability of the second photoresist layer with lower electrostatic sensitivity is better than that of the first photoresist layer, the second photoresist layer itself will not accumulate electric charge, and it is beneficial to release the accumulated electric charge in the first photoresist layer, so as to avoid the accumulation of electric charge to produce electrostatic field, that is, to avoid the adhesion of developing residual in the via hole preparation area due to the action of static electricity after developing, and to ensure the preparation of better via hole.

[0159] Second, the periodic deionized water and nitrogen blowing steps are used to clean the residual developing liquid in the via hole preparation area, which can avoid the PH shock effect, and avoid the precipitation of photoresist in the developing liquid when the deionized water is used to clean the developing liquid, that is, to avoid the developing residual caused by the PH shock effect.

[0160] The via hole is prepared by combining the above two methods to avoid developing residual and ensure the morphology of the via hole.

[0161] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of forming a via hole, characterized by, The application relates to a semiconductor device and a preparation method thereof. The application provides a semiconductor structure including an etching stop layer; A first photoresist is coated on the surface of the semiconductor structure, and the first photoresist is subjected to a first PRB baking to obtain a first photoresist layer; A second photoresist is coated on the surface of the first photoresist layer, and the second photoresist is subjected to a second PRB baking to obtain a second photoresist layer, wherein the second photoresist layer has a lower electrostatic sensitivity than the first photoresist layer; The first photoresist layer and the second photoresist layer are subjected to exposure; The first photoresist layer and the second photoresist layer are subjected to development to form a via preparation area to expose the semiconductor structure at the bottom of the via preparation area; The semiconductor structure at the bottom of the via preparation area is etched until the etching stop layer is reached to form a via.

2. The method of claim 1, wherein The PRB sensitivity of the second photoresist is higher than that of the first photoresist.

3. The method of claim 1, wherein the step of forming the via is performed by a method selected from the group consisting of mechanical drilling, laser drilling, and plasma etching. The PRB baking temperature of the second photoresist is lower than that of the first photoresist.

4. The method of claim 1, wherein The PRB baking time of the second photoresist is lower than that of the first photoresist.

5. The method of making a via according to any one of claims 1 to 4, wherein, The opening width of the second photoresist layer at the via preparation area is smaller than that of the first photoresist layer at the via preparation area.

6. The method of making a via according to any one of claims 1 to 4, wherein, The thickness of the first photoresist layer is greater than that of the etching stop layer.

7. The method of making a via according to any one of claims 1 to 4, wherein, The development of the first photoresist layer and the second photoresist layer includes: A development step: the first photoresist layer and the second photoresist layer are developed by using a developing solution; A deionized water cleaning step: the developed first photoresist layer and the second photoresist layer are cleaned by using deionized water; A nitrogen blowing step: the first photoresist layer and the second photoresist layer are blown by using nitrogen; The deionized water cleaning step and the nitrogen blowing step are periodically performed on the first photoresist layer and the second photoresist layer until the development is completed.

8. The method of making a via according to any one of claims 1 to 4, wherein, The etching of the semiconductor structure at the bottom of the via preparation area includes: The semiconductor structure at the bottom of the via preparation area is etched, and the second photoresist layer is etched at the same time; After the second photoresist layer is removed, the semiconductor structure at the bottom of the via preparation area is continuously etched under the blocking effect of the first photoresist layer until the etching stop layer is reached to form a via.

9. The method of claim 8, wherein the step of forming the via is performed by a method selected from the group consisting of mechanical drilling, laser drilling, and plasma etching. The etching is performed by using a plasma etching process under the condition that the temperature is 20-90 DEG C, the pressure is 5-10 Pa, the etching power is 100-500 W, and fluorine-based gas is used as the etching gas.

10. A method of manufacturing a semiconductor device, characterized by, The preparation method of the semiconductor device includes the preparation method of the via according to any one of claims 1-9.

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