Packaging structure and forming method thereof

Abstract

The invention discloses a packaging structure and a forming method thereof, and the forming method comprises the steps: providing a first wafer which comprises a plurality of first crystal grains; providing a second wafer, wherein the second wafer comprises a plurality of second crystal grains; etching a second bonding surface of the second wafer, and forming a first groove in a part of the second crystal grain; providing a third wafer, wherein the third wafer comprises a plurality of third crystal grains; bonding the second bonding surface of the second wafer with the first bonding surface of the first wafer, so that one part of the second crystal grains are bonded with the corresponding first crystal grains, and the other part of the second crystal grains are not bonded with the corresponding first crystal grains due to the existence of the first grooves; bonding the fourth bonding surface of the third wafer with the third bonding surface of the second wafer, so that at least part of the third crystal grains are bonded with the corresponding second crystal grains; and segmenting the bonded first wafer, second wafer and third wafer to form a plurality of discrete first chip stacking structures and second chip stacking structures. Wafer bonding of crystal grains with different sizes is realized, and the manufacturing efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of packaging technology, and in particular to a packaging structure and a method for forming the same. Background Technology

[0002] Wafer-to-wafer bonding is a process that tightly bonds two or more complete wafers (such as silicon wafers, glass wafers, or compound semiconductor wafers) together using physical or chemical methods. The bonded wafers form a multi-layered stacked structure, which is typically used to achieve 3D integration or the functional fusion of heterogeneous materials.

[0003] However, when the die sizes on the two wafers are different, the existing wafer-to-wafer bonding method is obviously no longer applicable, and only the existing die-to-wafer bonding method (that is, bonding each die to the wafer one by one) can be used, but this will seriously affect production efficiency. Summary of the Invention The purpose of this application is to provide a packaging structure and a method for forming the same, which enables the bonding of two wafers with different sized dies, thereby improving production efficiency. To achieve the above objectives, one embodiment of this application provides a method for forming an encapsulation structure, including: A first wafer is provided, the first wafer including opposing first bonding surfaces and first surfaces, the first wafer including a plurality of first grains; A second wafer is provided, the second wafer including opposing second bonding surfaces and third bonding surfaces, the second wafer including a plurality of second grains, the size of the first grains being larger than the size of the second grains; The second bonding surface is etched to form a first groove on a portion of the second grains; A third wafer is provided, the third wafer including opposing fourth bonding surfaces and fourth surfaces, the third wafer including a plurality of third grains, the size of the second grains being equal to or greater than the size of the third grains; The second bonding surface of the second wafer is bonded to the first bonding surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grain is bonded to the corresponding second grain; The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures and multiple discrete second chip stack structures.

[0004] In some embodiments, the first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; and the third wafer further includes a third dicing channel located between adjacent third dies.

[0005] In some embodiments, the size of the first groove is greater than or equal to the size of the second grain.

[0006] In some embodiments, the size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain; the size of the second groove is the sum of the size of the third grain and the size of the third kerf around the third grain.

[0007] In some embodiments, the size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the second wafer, the projection of the first dicing ditch onto the second bonding surface of the second wafer coincides with the projection of a portion of the first groove onto the second bonding surface, and the projection of the third dicing ditch onto the second bonding surface of the second wafer coincides with at least a portion of the projection of the second dicing ditch onto the second bonding surface.

[0008] In some embodiments, the size of the first grain being larger than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The second grain being larger than the third grain includes: the size of the second grain being an integer multiple of the size of the third grain.

[0009] In some embodiments, the projection of one of the first grains on the second bonding surface coincides with the projection of a plurality of the second grains on the second bonding surface.

[0010] In some embodiments, dividing the bonded first wafer, second wafer, and third wafer includes dividing the bonded first wafer, second wafer, and third wafer along the first dicing track, the second dicing track, and the third dicing track, respectively.

[0011] In some embodiments, bonding the fourth bonding surface of the third wafer to the third bonding surface of the second wafer, such that at least some of the third grains are bonded to the corresponding second grains, includes bonding all the third grains on the third wafer to the corresponding second grains.

[0012] In some embodiments, a first chip stack structure includes a first die, at least one second die bonded to a first die, and at least one third die bonded to at least one second die, and a second chip stack structure includes a second die and the third die bonded together.

[0013] In some embodiments, bonding the fourth bonding surface of the third wafer to the third bonding surface of the second wafer such that at least a portion of the third grains are bonded to the corresponding second grains includes: bonding a portion of the third grains to the corresponding second grains, while another portion of the third grains are not bonded to the corresponding second grains.

[0014] In some embodiments, the forming method further includes: etching a portion of the fourth bonding surface to form a second groove on a portion of the third grains; When the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, another portion of the third grains will not bond with the corresponding second grains due to the presence of the second groove.

[0015] In some embodiments, the bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures and second chip stack structures, while obtaining a number of separated third dies.

[0016] In some embodiments, a first chip stack structure includes a first die and at least one second die bonded to a first die, and a second chip stack structure includes a second die and a third die bonded together.

[0017] In some embodiments, a fourth wafer is provided, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, the size of the third grains being equal to or greater than the size of the fourth grains; The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain; The bonded first wafer, second wafer, third wafer, and fourth wafer are divided to form multiple discrete first chip stack structures and second chip stack structures, or to form multiple discrete first chip stack structures, second chip stack structures, and third chip stack structures.

[0018] In some embodiments, the first bonding surface has a first bonding layer, the second bonding surface has a second bonding layer, the third bonding surface has a third bonding layer, and the fourth bonding surface has a fourth bonding layer.

[0019] In some embodiments, the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer are all made of the same material.

[0020] In some embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer include dielectric materials, or a combination of dielectric layer materials and metallic materials, or solder.

[0021] In some embodiments, the dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

[0022] In some embodiments, after a plurality of first grains are formed on the first wafer, the first bonding layer is formed on the first bonding surface of the first wafer.

[0023] In some embodiments, after the second grain is formed on the second wafer, the second bonding layer is formed on the second bonding surface of the second wafer, and the third bonding layer is formed on the third bonding surface of the second wafer.

[0024] In some embodiments, the second bonding layer is etched to form the first groove in the second bonding layer.

[0025] In some embodiments, after the third grain is formed on the third wafer, the fourth bonding layer is formed on the fourth bonding surface of the third wafer.

[0026] In some embodiments, the fourth bonding layer is etched to form a second groove in the fourth bonding layer.

[0027] In some embodiments, a direct bonding process, a dielectric bonding process, an anodic bonding process, or a hybrid bonding process is used to bond the second bonding surface of the second wafer to the first bonding surface of the first wafer, and to bond the fourth bonding surface of the third wafer to the third bonding surface of the second wafer.

[0028] Another aspect of this application embodiment provides a packaging structure, including: The first wafer includes opposing first bonding surfaces and first surfaces, and the first wafer includes a plurality of first grains; The second wafer includes opposing second bonding surfaces and third bonding surfaces, and includes a plurality of second grains, wherein the size of the first grain is larger than the size of the second grain, and a portion of the second grains have a first groove penetrating the second bonding surface; The third wafer includes opposing fourth bonding surfaces and fourth surfaces, and the third wafer includes a plurality of third grains, wherein the size of the second grain is equal to or greater than the size of the third grain; The second bonding surface of the second wafer is bonded to the first bonding surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grain is bonded to the corresponding second grain.

[0029] In some embodiments, the first wafer further includes a first dicing channel located between adjacent first grains; the second wafer further includes a second dicing channel located between adjacent second grains; the third wafer further includes a third dicing channel located between adjacent third grains; and the size of the first groove is greater than or equal to the size of the second grain.

[0030] In some embodiments, the size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

[0031] In some embodiments, the size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the second wafer, the projection of the first dicing ditch onto the second bonding surface of the second wafer coincides with the projection of a portion of the first groove onto the second bonding surface, and the projection of the third dicing ditch onto the second bonding surface of the second wafer coincides with at least a portion of the projection of the second dicing ditch onto the second bonding surface.

[0032] In some embodiments, the size of the first grain being larger than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; and the projection of one of the first grains on the second bonding surface coinciding with the projections of multiple second grains on the second bonding surface. The second grain being larger than the third grain includes: the size of the second grain being an integer multiple of the size of the third grain; and the projection of one of the second grains on the second bonding surface coinciding with the projections of multiple third grains on the second bonding surface.

[0033] In some embodiments, the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least some of the third grains are bonded to the corresponding second grains, including: bonding all the third grains on the third wafer to the corresponding second grains.

[0034] In some embodiments, the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grains are bonded to the corresponding second grains, including: a portion of the third grains are bonded to the corresponding second grains, and another portion of the third grains are not bonded to the corresponding second grains.

[0035] In some embodiments, the packaging structure further includes: a portion of the third die having a second groove penetrating the fourth bonding surface; When the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, another portion of the third grains will not bond to the corresponding second grains due to the presence of the second groove.

[0036] In some embodiments, the size of the second groove is the sum of the size of the third grain and the size of the third kerf around the third grain.

[0037] In some embodiments, the first bonding surface has a first bonding layer, the second bonding surface has a second bonding layer, the third bonding surface has a third bonding layer, and the fourth bonding surface has a fourth bonding layer; the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer are all made of the same material.

[0038] In some embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer include a dielectric material, or a combination of a dielectric layer material and a metallic material, or a solder; the dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

[0039] In some embodiments, the packaging structure further includes: a fourth wafer, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, the size of the third grains being equal to or greater than the size of the fourth grains; The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain.

[0040] The beneficial effects of this application are: The packaging structure and its forming method of this application, wherein the forming method first forms a first groove on a portion of the second dies on a second wafer, and when bonding the second bonding surface of the second wafer to the first bonding surface of the first wafer, a portion of the second dies are bonded to the corresponding first dies, while another portion of the second dies will not be bonded to the corresponding first dies due to the presence of the first groove, and the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third dies on the third wafer are bonded to the corresponding second dies, and the bonded first wafer, second wafer and third wafer are divided to form multiple discrete chip stack structures and multiple discrete second chip stack structures. That is, the above steps in this application can realize the bonding of multiple wafers with different die sizes to mass-produce the first chip stack structure and the second chip stack structure, improve the manufacturing efficiency of the first chip stack structure and the second chip stack structure, and can simultaneously produce the first chip stack structure and the second chip stack structure with different functions. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort. In addition, in the following drawings, the components are not necessarily drawn to scale, and components with similar related characteristics or features may have the same or similar reference numerals.

[0042] Figure 1 This is a flowchart illustrating the method for forming the packaging structure provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure after the first wafer is formed in the method of forming the packaging structure provided in some embodiments of this application; Figure 3 This is a schematic diagram of the second wafer and the structure after forming the first groove in the method of forming the packaging structure provided in some embodiments of this application; Figure 4 This is a schematic diagram of the structure after providing a third wafer in the method of forming the packaging structure provided in some embodiments of this application; Figure 5 This is a schematic diagram of the structure formed by bonding the second wafer and the first wafer, and bonding the third wafer and the second wafer in the packaging structure formation method provided in some embodiments of this application; Figure 6This is a schematic diagram of the structure after dividing the bonded first wafer, second wafer, and third wafer in the method for forming the packaging structure provided in some embodiments of this application; Figure 7 This is a schematic diagram of the third wafer and the structure after forming the second groove in the method of forming the packaging structure provided in other embodiments of this application; Figure 8 This is a schematic diagram of the structure formed by bonding the second wafer and the first wafer, and bonding the third wafer and the second wafer in a method for forming a packaging structure provided in other embodiments of this application; Figure 9 This is a schematic diagram of the structure after dividing the bonded first wafer, second wafer, and third wafer in the method for forming the packaging structure provided in other embodiments of this application. Detailed Implementation

[0043] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0045] In the description of this application, it should be noted that the use of terms such as "first" and "second" to define objects (such as elements, components, regions, layers, doping types and / or parts) is merely for the purpose of distinguishing different objects and is not necessarily used to describe a specific order or sequence. Unless the context clearly indicates otherwise, it should be understood that such data can be used interchangeably where appropriate.

[0046] In the description of this application, it should be understood that the singular forms “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “compose” and / or “comprise” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0047] In the description of this application, it should also be noted that when a component is referred to as "on another component," "connected to another component," or "in contact with another component," it can mean not only that a component is directly on, directly connected to, or directly in contact with another component, but also that an intermediate component can be inserted between the two components. Furthermore, "connection" includes not only fixed connections but also detachable connections or integral connections. Similarly, when an element is referred to as "electrically connected," "electrically contacted," "electrically coupled," or "electrically coupled to" another element, the two elements can be in direct electrical contact or point coupling, or they can be in electrical contact or point coupling through an intermediate component.

[0048] In the description of this application, it should also be noted that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0049] Furthermore, in the description of this application, spatial relation terms such as "below," "under," "below," "below," "below," "above," "on the upper surface of," "above," etc., can be used to describe the spatial positional relationship between one element or feature shown in the figures and other elements or features. It should be understood that spatial relation terms, in addition to the orientation shown in the figures, also include different orientations of elements or features in use and operation. For example, if an element or feature in the figures is flipped or inverted, an element or feature described as "below" or "below" other elements or features will be oriented "above" other elements or features. Furthermore, elements may also include other orientations (e.g., rotated by an angle or other orientations).

[0050] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.

[0051] It is understood that in the accompanying drawings of this application, some adjacent membrane layers with the same processed membrane material are drawn as connected to make them resemble the actual structure.

[0052] This application first provides a method for forming an encapsulation structure. Figure 1 This is a flowchart illustrating the method for forming the encapsulation structure provided in some embodiments of this application. (Refer to...) Figure 1 The method for forming the encapsulation structure includes the following steps: Step S101: Provide a first wafer, the first wafer including opposing first bonding surfaces and first surfaces, the first wafer including a plurality of first grains; Step S102: Provide a second wafer, the second wafer including opposing second bonding surfaces and third bonding surfaces, the second wafer including a plurality of second grains, the size of the first grain being larger than the size of the second grain; Step S103: Etch a portion of the second bonding surface to form a first groove on a portion of the second grains; Step S104: Provide a third wafer, the third wafer including opposing fourth bonding surfaces and fourth surfaces, the third wafer including a plurality of third grains, the size of the second grains being equal to or greater than the size of the third grains; Step S105: Bond the second bonding surface of the second wafer to the first bonding surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove. Step S106: Bond the fourth bonding surface of the third wafer to the third bonding surface of the second wafer, such that at least a portion of the third grains are bonded to the corresponding second grains; Step S107: Divide the bonded first wafer, second wafer and third wafer to form multiple discrete first chip stack structures and multiple discrete second chip stack structures.

[0053] The method for forming the packaging structure is described in detail below with reference to the accompanying drawings in some embodiments.

[0054] First, refer to the reference Figure 1 and Figure 2 In step S101, a first wafer 101 is provided. The first wafer 101 includes opposing first bonding surfaces 11 and first surfaces 12. The first wafer 101 includes a plurality of first dies 102. The size of the first dies 102 is larger than that of the second dies 202 on the subsequently provided second wafer 201 (see reference). Figure 3 (size).

[0055] The first wafer 101 is subsequently bonded to the second wafer 201. The surface on which the first wafer 101 is subsequently bonded to the second wafer 201 is the first bonding surface 11, and the surface opposite to the first bonding surface 11 is the first surface 12.

[0056] The material of the first wafer 101 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In some embodiments, the material of the first wafer 101 can be the same as or different from the material of the second wafer 201, that is, wafer bonding of the same or different materials can be achieved.

[0057] The first wafer 101 has a plurality of first dies 102 and a first dicing channel 104 located between adjacent first dies 102. The plurality of first dies 102 can be arranged in rows and columns. One first die 102 can correspond to one semiconductor chip. The plurality of first dies 102 can be formed on the first wafer 101 by integrated circuit manufacturing process.

[0058] The first wafer 101 can be of different sizes. In specific examples, the first wafer 101 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes. In some embodiments, the size of the first wafer 101 is equal to the size of the subsequent second wafer 201. After the first wafer 101 and the second wafer 201 are subsequently bonded, the projection of the first dicing 104 onto the second bonding surface 21 of the second wafer 201 coincides with the projection of a portion of the first groove 205 onto the second bonding surface (see reference). Figure 5 The projection of the first dicing channel 104 on the second bonding surface of the second wafer 201 also coincides with the projection of part of the second dicing channel 204 on the second bonding surface. This facilitates the division of multiple bonded wafers into a chip stacking structure by using the second dicing channel 204 and the first dicing channel 104 during subsequent dicing.

[0059] In some embodiments, a first bonding layer (not shown) may be formed on the first bonding surface 11 of the first wafer 101. The first bonding layer serves as a bonding medium for subsequent bonding of the first wafer 101 and the second wafer 201 to improve the bonding strength. In some embodiments, after the first grain 102 is formed on the first wafer 101, the first bonding layer is formed on the first bonding surface 11 of the first wafer 101. In some embodiments, the material of the first bonding layer includes a dielectric material, and in one example, the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the first bonding layer includes a combination of a dielectric layer material and a metallic material, and in one example, the dielectric material includes silicon oxide or silicon carbide, and the metallic material includes copper. In still other embodiments, the material of the first bonding layer includes solder, and the solder material is tin or a tin alloy.

[0060] Next, refer to Figure 1 and Figure 3 In step S102, a second wafer 201 is provided. The second wafer 201 includes opposing second bonding surfaces 21 and third bonding surfaces 22. The second wafer 201 includes a plurality of second dies 202, the size of which is smaller than the size of the first die 102 or the size of the first die 102 is larger than the size of the second die 202. Continuing with reference to... Figure 1 and Figure 3 In step S102, a portion of the second bonding surface 21 is etched to form a first groove 205 on a portion of the second grains 202.

[0061] The second bonding surface 21 of the second wafer 201 subsequently connects to the first wafer 101 (see reference). Figure 2 The first bonding surface 11 of the second wafer 201, and the third bonding surface 22 of the second wafer 201 subsequently bonded to the third wafer 301 (see reference). Figure 4 The second wafer 201 is bonded to the fourth bonding surface 31 of the first wafer 101. The subsequent bonding surface of the second wafer 201 with the first wafer 101 is the second bonding surface 21, and the subsequent bonding surface of the second wafer 201 with the third wafer 301 is the third bonding surface 22.

[0062] The material of the second wafer 201 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. The second wafer 201 can be of different sizes. In a specific example, the second wafer 201 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes.

[0063] The second wafer 201 has a plurality of second dies 202 and a second dicing channel 204 located between adjacent second dies 202. The plurality of second dies 202 can be arranged in rows and columns, and one second die 202 can correspond to one semiconductor chip. The plurality of second dies 202 can be formed on the second wafer 201 by integrated circuit fabrication processes. In some embodiments, the second die 202 and the first die 102 are semiconductor chips with different functions. The semiconductor chips may include logic chips and / or memory chips. In some embodiments, the logic chip may include, but is not limited to, gate arrays, cell substrate arrays, embedded arrays, structured application integrated circuits (ASICs), field-programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), graphics processing units (GPUs), central processing units (CPUs), microprocessor units (MPUs), microcontroller units (MCUs), logic integrated circuits (ICs), application processors (APs), display driver ICs (DDIs), radio frequency (RF) chips, power supply chips, or complementary metal-oxide-semiconductor (CMOS) image sensors. In some embodiments, the memory chip may include, but is not limited to, Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Magnetoresistive Random Access Memory (MRAM), Phase-Change Memory (PRAM), Resistive Random Access Memory (RRAM), or non-volatile memory chips (such as flash memory). In a specific embodiment, the memory chip may include High Bandwidth Memory (HBM) containing DRAM chips.

[0064] The size of the second grain 202 is the same as that of the first grain 102 on the first wafer 101 (reference). Figure 2The sizes of the two dies are different. Specifically, the size of the second die 202 is smaller than the size of the first die 102 on the first wafer 101, or the size of the first die 102 on the first wafer 101 is larger than the size of the second die 202 on the second wafer 201. In a specific example, the size of the first die 102 can be an integer multiple of the size of the second die 202, such as 2, 3, 4 or more times. That is, after the first wafer 101 and the second wafer 201 are bonded, the projection of one first die 102 on the first wafer 101 on the second bonding surface can coincide with the projections of two, three, four or more second dies 202 on the second wafer on the second bonding surface, which facilitates wafer bonding and subsequent splitting after bonding.

[0065] A portion of the second dies 202 have a first groove 205 forming through the second bonding surface 21, while the other second dies 202 do not have the first groove formed. This will be achieved when the second bonding surface of the second wafer 201 is subsequently bonded to the first bonding surface of the first wafer 101 (see reference). Figure 5 This allows a portion of the second grains 202 to bond with the corresponding first grains 102, while another portion of the second grains 202 will not bond with the corresponding first grains 102 due to the presence of the first groove 205. In other words, in this application, the first groove 205 is formed on the second grains 202 that do not subsequently need to bond with the first grains 102, while the first groove is not formed on the second grains 202 that do subsequently need to bond with the first grains 102. The number of the first grooves 205 is equal to the number of the second grains 202 that do not need to bond with the first grains 102.

[0066] The size of the first groove 205 is greater than or equal to the size of the second grain 202. In some embodiments, the size of the first groove 205 is the sum of the size of the second grain 202 and the size of the second dicing 204 surrounding the second grain 202. When the second bonding surface of the second wafer 201 is subsequently bonded to the first bonding surface of the first wafer 101, there will be no bonding between the second grain 202 with the first groove 205 and the surrounding second dicing 204 and the corresponding first grain 102. This facilitates the separation of the second grain 202 from the corresponding first grain 102 during subsequent separation and prevents damage to the first grain 102 during separation.

[0067] In some embodiments, the depth of the first groove 205 is greater than or equal to 2 micrometers, so that there is a sufficient distance between the second grain 202 and the corresponding first grain 102. When the second bonding surface of the second wafer 201 is subsequently bonded to the first bonding surface of the first wafer 101, there will be no bonding between the second grain 202 and the corresponding first grain 102, and it is convenient to separate the two during dicing.

[0068] In some embodiments, a portion of the second bonding surface is etched to form a first groove 205 corresponding to the portion of the second grains 202. The process for forming the first groove 205 includes laser etching, chemical etching, or plasma etching.

[0069] In some embodiments, a second bonding surface 21 of the second wafer 201 may be formed with a second bonding layer (not shown in the figure), and a third bonding surface 22 of the second wafer 201 may be formed with a third bonding layer (not shown in the figure). The second bonding layer serves as the bonding medium when the second wafer 201 and the first wafer 101 are subsequently bonded, and the third bonding layer serves as the bonding medium when the second wafer 201 and the third wafer 301 (see reference) are subsequently bonded. Figure 4 The bonding medium used during bonding is adjusted to improve bonding strength. In some embodiments, after the second grain 202 is formed on the second wafer 201, the second bonding layer is formed on the second bonding surface 21 of the second wafer 201. In some embodiments, a portion of the second bonding layer is etched away, and the first groove 205 is formed in the second bonding layer on the second grain 202. In some embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer subsequently formed on the third wafer are all the same to improve bonding strength during subsequent bonding. In other embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer subsequently formed on the third wafer may be different or partially the same.

[0070] In some embodiments, the materials of the second and third bonding layers include a dielectric material, in one example, the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the second bonding layer includes a combination of a dielectric layer material and a metallic material, in one example, the dielectric material includes silicon oxide or silicon carbide, and the metallic material includes copper. In still other embodiments, the material of the second bonding layer includes solder, the solder being tin or a tin alloy.

[0071] Next, in conjunction with references Figure 1 and Figure 4In step S104, a third wafer 301 is provided, the third wafer 301 includes a fourth bonding surface 31 and a fourth surface 32, the third wafer 301 includes a plurality of third grains 302, and the size of the second grain 202 is equal to or greater than the size of the third grain 302.

[0072] The third wafer 301 is subsequently bonded to the second wafer 201. The surface on which the third wafer 301 is subsequently bonded to the second wafer 201 is the fourth bonding surface 31, and the surface opposite to the fourth bonding surface 31 is the fourth surface 32.

[0073] The material of the third wafer 301 can be a semiconductor material. In one example, the semiconductor material can be silicon (Si), germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other III-V compounds. In some embodiments, the material of the third wafer 301 can be the same as or different from the material of the second wafer 201, that is, bonding of multiple wafers of the same or different materials can be achieved.

[0074] The third wafer 301 has a plurality of third dies 302 and third dicing channels 304 located between adjacent third dies 302. The plurality of third dies 302 can be arranged in rows and columns, and one third die 302 can correspond to one semiconductor chip. The plurality of third dies 302 can be formed on the third wafer 301 by integrated circuit manufacturing processes. In some embodiments, the third dies 302 and the second dies 202 are semiconductor chips with different functions, and the semiconductor chips may include logic chips and / or memory chips. In other embodiments, the third dies 302 and the second dies 202 may also be semiconductor chips with the same function.

[0075] The third wafer 301 can be of different sizes. In a specific example, the third wafer 301 can be 6 inches, 8 inches, or 12 inches, or it can be other sizes. In some embodiments, reference continues to... Figure 4 The size of the third wafer 301 is equal to the size of the second wafer 201, the size of the third die 302 is the same as the size of the second die 202, and the size of the third dicing 304 is the same as the size of the second dicing 204, with corresponding positions. After the third wafer 301 and the second wafer 201 are subsequently bonded, the projection of the third die 302 onto the second bonding surface 21 coincides with the projection of the second die 202 onto the second bonding surface 21 (see reference). Figure 5The projection of the third dicing 304 onto the second bonding surface 21 of the second wafer 201 coincides with the projection of the second dicing 204 onto the second bonding surface 21 (see reference). Figure 5 This facilitates the alignment and bonding of the third wafer 301 and the second wafer 201, and also facilitates the subsequent segmentation of the third wafer 301, the second wafer 201, and the first wafer 101 after bonding.

[0076] In other embodiments, when the size of the second die 202 is larger than the size of the third die 302, the size of the second die 202 being larger than the size of the third die 302 includes: the size of the second die 202 being an integer multiple of the size of the third die 302, that is, the size of the second die 202 being 2, 3, 4 or more times the size of the third die 302. Subsequently, when the third wafer 301 is bonded to the second wafer 201, the projection of one second die 202 on the second bonding surface coincides with the projections of multiple third dies 302 on the second bonding surface. For example, the projection of one second die 202 on the second bonding surface coincides with the projections of two, three, four or more third dies 302 on the second bonding surface. The projection of the third dicing 304 on the second bonding surface 21 of the second wafer 201 coincides with at least a portion of the projections of the second dicing 204 on the second bonding surface 21. In some embodiments, when the size of the second grain 202 is an integer multiple of the size of the third grain 302, multiple third grains can be bonded to one second grain 202 simultaneously when the third wafer 301 is subsequently bonded to the second wafer 201. In other embodiments, a second groove penetrating the fourth bonding surface 31 can be formed on some of the third grains 302 (described in detail in subsequent embodiments), so that a portion of the third grains 302 are bonded to the corresponding second grains 202, while another portion of the third grains 302 will not be bonded to the corresponding second grains 202 due to the presence of the second groove.

[0077] In some embodiments, a fourth bonding layer (not shown) may be formed on the fourth bonding surface 31 of the third wafer 301. This fourth bonding layer serves as a bonding medium for subsequent bonding of the third wafer 301 and the second wafer 201, thereby improving the bonding strength. In some embodiments, the fourth bonding layer is formed on the fourth bonding surface 31 of the third wafer 301 after the third grain 302 is formed on the third wafer 301. In some embodiments, the material of the fourth bonding layer includes a dielectric material, in one example of which the dielectric material includes silicon oxide or silicon carbide. In other embodiments, the material of the fourth bonding layer includes a combination of a dielectric layer material and a metallic material, in one example of which the dielectric material includes silicon oxide or silicon carbide and the metallic material includes copper. In still other embodiments, the material of the fourth bonding layer includes solder, wherein the solder material is tin or a tin alloy.

[0078] Next, in conjunction with references Figure 1 and Figure 5 In step S105, the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, such that a portion of the second grains 202 are bonded to the corresponding first grains 102, while another portion of the second grains 202 will not be bonded to the corresponding first grains 102 due to the presence of the first groove 205; in step S106, the fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, such that at least a portion of the third grains 302 are bonded to the corresponding second grains 202.

[0079] In some embodiments, before bonding the second wafer 201 to the first wafer 101, and before bonding the third wafer 301 to the second wafer 201, the first bonding surface 11, the second bonding surface 21, the third bonding surface 22, and the fourth bonding surface 31 are cleaned and activated respectively to further improve the bonding strength between the second wafer 201 and the first wafer 101, and between the third wafer 301 and the second wafer 201.

[0080] In some embodiments, after aligning the second wafer 201 with the first wafer 101, the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101; after aligning the third wafer 301 with the second wafer 201, the fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201. In some embodiments, direct bonding, dielectric bonding, anodic bonding, or hybrid bonding processes can be used to bond the second bonding surface 21 of the second wafer 201 to the first bonding surface 11 of the first wafer 101, and to bond the fourth bonding surface 31 of the third wafer 301 to the third bonding surface 22 of the second wafer 201.

[0081] In some embodiments, when the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, a portion of the second dies 202 are bonded to the corresponding first dies 102, while another portion of the second dies 202 will not be bonded to the corresponding first dies 102 due to the presence of the first groove 205. In a specific example, refer to... Figure 5 After the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, when the projections of two second dies 202 on the second bonding surface 21 coincide with the projection of a corresponding first die 102 on the second bonding surface 21, only one of the second dies 202 will bond with the first die 102, while the other second die 202 will not bond with the first die 102 due to the presence of the first groove 205; bonding the fourth bonding surface 31 of the third wafer 301 to the third bonding surface 22 of the second wafer 201, such that at least some of the third dies 302 are bonded to the corresponding second dies 202, includes: all the third dies 302 on the third wafer 301 are bonded to the corresponding second dies 202.

[0082] This application implements multi-wafer bonding with dies of different sizes. Specifically, the size of the first die 102 on the first wafer 101 is larger than the size of the second die 202 on the second wafer 201, and the size of the third die 302 on the third wafer 301 is the same as the size of the second die 202 on the second wafer 201. In some embodiments, the size of the first die 102 is an integer multiple of the size of the second die 202, that is, the projection of one first die 102 on the second bonding surface 21 can coincide with the projection of multiple second dies 202 on the second bonding surface 21, and the projection of one third die 302 on the second bonding surface 21 can coincide with the projection of one first die 102 on the second bonding surface 21. The projections of two dies 202 on the second bonding surface 21 coincide. In a specific example, the size of the first die 102 can be 2, 3, 4 or more times the size of the second die 202, so that the projection of one first die 102 on the second bonding surface can coincide with the projections of two, three, four or more second dies 202 on the second bonding surface. Subsequently, after the second wafer 201 and the first wafer 101 are bonded, one first die 102 will only be bonded to a portion of the second dies 202 whose projections coincide, while the other portion of the second dies 202 whose projections coincide will not be bonded to the first die 102 due to the presence of the first groove 205. For example, if the projection of one first die 102 on the second bonding surface coincides with the projections of two second dies 202 on the second bonding surface, after the second wafer 201 and the first wafer 101 are bonded, one of the two second dies 202 will bond to the first die 102, while the other second die 202, which has a first groove 205, will not bond to the first die 102. As another example, if the projection of one first die 102 on the second bonding surface coincides with the projections of three second dies 202 on the second bonding surface, after the second wafer 201 and the first wafer 101 are bonded, one or two of the three second dies 202 will bond to the first die 102, while the remaining two or one second die 202, which has a first groove 205, will not bond to the first die 102.

[0083] Finally, referring to the references Figure 1 and Figure 6 In step S107, the bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete first chip stack structures 41 and multiple discrete second chip stack structures 42.

[0084] In some embodiments, continue to refer to Figure 6A first chip stack structure 41 includes a first die 102, at least one second die 202 bonded to the first die 102, and at least one third die 302 correspondingly bonded to the at least one second die 202. The second die 202 is electrically connected to the first die 102, and the third die 302 is electrically connected to the second die 202. For example, a first chip stack structure 41 may include a first die 102, a second die 202 bonded to and electrically connected to the first die 102, and a third die bonded to and electrically connected to the second die 202. As another example, a first chip stack structure 41 may include a first die 102, two or more second dies 202 bonded to and electrically connected to the first die 102, and two or more third dies 302 correspondingly bonded to and electrically connected to the two or more second dies 202. The other second dies 202 on the second wafer 201 will not bond to the first die 102 due to the presence of the first groove 205, but will instead bond to the other third dies 302 on the third wafer 302, forming a second chip stack structure 42. Each second chip stack structure 42 may include a second die 202 and a third die 302 bonded together and electrically connected. In this application, through the aforementioned steps, a first groove 205 is first formed on a portion of the second dies 202 on the second wafer 201. When the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, a portion of the second dies 202 are bonded to the corresponding first die 102, while another portion of the second dies 202 will not bond to the corresponding first die 102 due to the presence of the first groove 205. The fourth bonding surface 31 of the third wafer 301 is then bonded to the third bonding surface 22 of the second wafer 201, thus forming a second chip stack structure 42. All third dies 302 are bonded to corresponding second dies 202. The bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete chip stack structures 41 and multiple discrete second chip stack structures 42. That is, the above steps in this application can realize the bonding of multiple wafers with different die sizes to batch manufacture the first chip stack structure 41 and the second chip stack structure 42, improve the manufacturing efficiency of the first chip stack structure 41 and the second chip stack structure 42, and can simultaneously manufacture the first chip stack structure 41 and the second chip stack structure 42 with different functions.

[0085] In some embodiments, dividing the bonded first wafer 101, second wafer 201 and third wafer 301 includes dividing the bonded first wafer 101, second wafer 201 and third wafer 301 along the first dicing track 104, the second dicing track 204 and the third dicing track 304 respectively.

[0086] In some embodiments, blades are used to slit the bonded first wafer 101, second wafer 201, and third wafer 301.

[0087] Other embodiments of this application also provide a method for forming an encapsulation structure; please refer to the following for details. Figures 7-9 The main difference between this embodiment and the previous embodiments is that: (Refer to...) Figure 7 Etching a portion of the fourth bonding surface 31 of the third wafer 301 to form a second groove 305 on a portion of the third grains 302; Reference Figure 8 The second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, such that a portion of the second dies 202 are bonded to the corresponding first dies 102, while another portion of the second dies 202 will not be bonded to the corresponding first dies 102 due to the presence of the first groove 205; the fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, such that a portion of the third dies 302 are bonded to the corresponding second dies 202, while another portion of the third dies 302 will not be bonded to the corresponding second dies 102 due to the presence of the second groove 305; Reference Figure 9 The bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete first chip stack structures 41 and second chip stack structures 42, and at the same time, several separated third dies 302 are obtained.

[0088] In some embodiments, the size of the second groove 305 is greater than or equal to the size of the third grain 302. In some embodiments, the size of the second groove 305 is the sum of the size of the third grain 302 and the size of the third dicing channel 304 surrounding the third grain 302. When the fourth bonding surface of the third wafer 301 is subsequently bonded to the third bonding surface of the second wafer 201, no bonding is present between the third grain 302 with the second groove 305 and the surrounding third dicing channel 304 and the corresponding second grain 202. Subsequent separation facilitates the separation of the third grain 302 from the corresponding second grain 202 and prevents damage to the third grain 302 during separation.

[0089] In some embodiments, the depth of the second groove 305 is greater than or equal to 2 micrometers, so that there is a sufficient distance between the third grain 302 and the corresponding second grain 202. When the fourth bonding surface of the third wafer 301 is subsequently bonded to the third bonding surface of the second wafer 201, there will be no bonding between the third grain 302 and the corresponding second grain 202, and it is convenient to separate the two during cutting.

[0090] In some embodiments, a portion of the fourth bonding surface is etched to form a second groove 305 corresponding to a portion of the third grains 302. The process for forming the second groove 305 includes laser etching, chemical etching, or plasma etching.

[0091] In some embodiments, continue to refer to Figure 9 A first chip stack structure 41 includes a first die 102 and at least one second die 202 bonded and electrically connected to a first die 102, and a second chip stack structure 42 includes a second die 202 bonded together and electrically connected to a third die 302.

[0092] In this embodiment, through the aforementioned steps, a first groove 205 is first formed on a portion of the second dies 202 of the second wafer 201. When the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, a portion of the second dies 202 are bonded to the corresponding first dies 102, while another portion of the second dies 202 will not be bonded to the corresponding first dies 102 due to the presence of the first groove 205. A second groove 305 is formed on a portion of the third dies 302. When the fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, a portion of the third dies 302 are bonded to the corresponding second dies 202, while another portion of the third dies 302 will not be bonded to the corresponding second dies 202 due to the presence of the second groove 305. The corresponding second die 102 is bonded. After the bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete chip stack structures 41 and multiple discrete second chip stack structures 42, several separated third dies 302 can also be obtained. That is, the above-mentioned steps in this application can realize the bonding of multiple wafers with different die sizes to batch manufacture the first chip stack structure 41 and the second chip stack structure 42, improve the manufacturing efficiency of the first chip stack structure 41 and the second chip stack structure 42, and can simultaneously manufacture the first chip stack structure 41 and the second chip stack structure 42 with different functions. In addition, the excess third dies 302 during the manufacturing process can be easily and without damage separated. The separated third dies 302 can be used for other packaging processes, thereby saving manufacturing costs.

[0093] Other embodiments of this application also provide a method for forming a packaging structure. The main difference between this embodiment and the foregoing embodiments is that a fourth wafer is provided, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, and the size of the third grains being equal to or greater than the size of the fourth grains. The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain; The bonded first wafer, second wafer, third wafer, and fourth wafer are divided to form multiple discrete first chip stack structures and second chip stack structures, or to form multiple discrete first chip stack structures, second chip stack structures, and third chip stack structures.

[0094] In some embodiments, the specific structures of the first chip stack structure and the second chip stack structure are the same as those in the foregoing embodiments; please refer to the corresponding descriptions or limitations in the foregoing embodiments. In other embodiments, the first chip stack structure includes a first die, a second die, a third die, and a fourth die bonded sequentially. The second chip stack structure includes a second die, a third die, and a fourth die bonded sequentially.

[0095] In some embodiments, all the fourth grains on the fourth wafer are bonded to the corresponding third grains.

[0096] In some embodiments, a portion of the fourth grains on the fourth wafer are bonded to corresponding third grains. Specifically, a number of the fourth grains have a third groove penetrating the fifth bonding surface. When the fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grains are bonded to the corresponding third grains, a portion of the fourth grains are bonded to the corresponding third grains, while the other portion of the fourth grains will not be bonded to the corresponding third grains due to the presence of the third groove.

[0097] In this embodiment, the first chip stack structure, the second chip stack structure, and the third chip stack structure are manufactured in batches, improving the manufacturing efficiency of the first chip stack structure, the second chip stack structure, and the third chip stack structure. It can also simultaneously manufacture the first chip stack structure, the second chip stack structure, and the third chip stack structure with different functions. Furthermore, the excess fourth die can be easily and without damage separated during the manufacturing process. The separated fourth die can be used for other packaging processes, thereby saving manufacturing costs.

[0098] This application also provides a packaging structure, see reference. Figure 5 ,include: A first wafer 101 includes opposing first bonding surfaces 11 and first surfaces 12, and the first wafer 101 includes a plurality of first grains 102; The second wafer 201 includes a second bonding surface 21 and a third bonding surface 22 opposite to each other. The second wafer 201 includes a plurality of second dies 202. The size of the first die 102 is larger than the size of the second die 202, and a portion of the second dies 202 have a first groove 205 penetrating the second bonding surface 21. The third wafer 301 includes a fourth bonding surface 31 and a fourth surface 32, and the third wafer 301 includes a plurality of third grains 302, wherein the size of the second grain 202 is equal to or greater than the size of the third grain 302. The second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, such that a portion of the second grains 202 are bonded to the corresponding first grains 102, while another portion of the second grains 202 will not be bonded to the corresponding first grains 102 due to the presence of the first groove 205. The fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, such that at least a portion of the third grain 302 is bonded to the corresponding second grain 202.

[0099] In the packaging structure of this application, because a portion of the second dies 202 on the second wafer 201 have first grooves 205, when the second bonding surface 21 of the second wafer 201 is bonded to the first bonding surface 11 of the first wafer 101, a portion of the second dies 202 are bonded to the corresponding first dies 102, while the other portion of the second dies 202 will not be bonded to the corresponding first dies 102 due to the presence of the first grooves 205. The fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, so that all the third dies 302 on the third wafer 301 are bonded to the corresponding second dies 202. The bonded first wafer 101, second wafer 201 and third wafer 301 are divided to form multiple discrete chip stack structures 41 and multiple discrete second chip stack structures 42. That is, the above steps in this application can realize the bonding of multiple wafers with different die sizes to batch manufacture the first chip stack structure 41 and the second chip stack structure 42, improve the manufacturing efficiency of the first chip stack structure 41 and the second chip stack structure 42, and can simultaneously manufacture the first chip stack structure 41 and the second chip stack structure 42 with different functions.

[0100] In some embodiments, the first wafer 101 further includes a first dicing channel 104 located between adjacent first dies 102; the second wafer 201 further includes a second dicing channel 204 located between adjacent second dies 202; the third wafer 301 further includes a third dicing channel 304 located between adjacent third dies 302; the size of the first groove 205 is greater than or equal to the size of the second die 202. In some embodiments, the size of the first groove 205 is the sum of the size of the second die 202 and the size of the second dicing channel 204 surrounding the second die 202. When the second bonding surface of the second wafer 201 is bonded to the first bonding surface of the first wafer 101, there is no bonding between the second die 202 and the surrounding second dicing channel 204 and the corresponding first die 102, and it is easy to cut, separating the second die 202 from the corresponding first die 102.

[0101] In some embodiments, the depth of the first groove 205 is greater than or equal to 2 micrometers, so that there is a sufficient gap between the second grain 202 and the corresponding first grain 102. When the second bonding surface of the second wafer 201 is bonded to the first bonding surface of the first wafer 101, there will be no bonding between the second grain 202 and the corresponding first grain 102, and it is convenient to separate the two during cutting.

[0102] In some embodiments, the size of the first wafer 101 is equal to the size of the second wafer 201, the size of the third wafer 301 is equal to the size of the second wafer 201, the projection of the first dicing 104 onto the second bonding surface 21 of the second wafer 201 coincides with the projection of a portion of the first groove 205 onto the second bonding surface 21, and coincides with at least a portion of the projection of the second dicing 204 onto the second bonding surface 21, and the projection of the third dicing 304 onto the second bonding surface 21 of the second wafer 201 coincides with at least a portion of the projection of the second dicing 204 onto the second bonding surface 21.

[0103] In some embodiments, the size of the first grain 102 being larger than the size of the second grain 202 includes: the size of the first grain 102 being an integer multiple of the size of the second grain 202; and the projection of one of the first grains 102 on the second bonding surface 21 coinciding with the projections of multiple second grains 202 on the second bonding surface 21.

[0104] In some embodiments, continue to refer to Figure 5The fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, such that at least some of the third grains 302 are bonded to the corresponding second grains 202, including: bonding all the third grains 302 on the third wafer 301 to the corresponding second grains 202.

[0105] In some embodiments, reference Figure 8 The fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, such that at least a portion of the third grains 302 are bonded to the corresponding second grains 202, including: a portion of the third grains 302 are bonded to the corresponding second grains 202, and another portion of the third grains 302 are not bonded to the corresponding second grains 202. In some embodiments, reference continues to... Figure 9 The packaging structure further includes: a portion of the third dies 302 having a second groove 305 penetrating the fourth bonding surface 31; when the fourth bonding surface 31 of the third wafer 301 is bonded to the third bonding surface 22 of the second wafer 201, a portion of the third dies 302 are bonded to the corresponding second dies 202, and another portion of the third dies 302 will not be bonded to the corresponding second dies 202 due to the presence of the second groove 305.

[0106] In some embodiments, the size of the second groove 305 is the sum of the size of the third grain 302 and the size of the third kerf 304 surrounding the third grain 302.

[0107] In some embodiments, the first bonding surface 11 has a first bonding layer, the second bonding surface 21 has a second bonding layer, the third bonding surface 22 has a third bonding layer, and the fourth bonding surface 31 has a fourth bonding layer; the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer are all made of the same material to improve bonding strength.

[0108] In some embodiments, the materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer include a dielectric material, or a combination of a dielectric layer material and a metallic material, or solder. In some embodiments, the dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder material is tin or a tin alloy.

[0109] In some embodiments, the packaging structure further includes: a fourth wafer, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, the size of the third grains being equal to or greater than the size of the fourth grains; The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain.

[0110] It should be noted that the limitations or descriptions of the same or similar parts in this embodiment (encapsulation structure) and the foregoing embodiment (method of forming encapsulation structure) will not be repeated in this embodiment. Please refer to the limitations or descriptions of the corresponding parts in the foregoing embodiment for details.

[0111] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0112] It should be noted that, where there is no conflict, the features in the different embodiments of this application described above can be combined with each other. Furthermore, in each of the above embodiments, the focus is on describing the differences from other embodiments; other specific descriptions of the same / similar parts between the embodiments can be referred to (or referenced) interchangeably. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this application.

[0113] Although this application has been disclosed above with reference to preferred embodiments, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications to the technical solutions of this application by utilizing the methods and techniques disclosed above without departing from the spirit and scope of this application. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solutions of this application shall fall within the protection scope of the technical solutions of this application.

Claims

1. A method for forming an encapsulation structure, characterized in that, include: A first wafer is provided, the first wafer including opposing first bonding surfaces and first surfaces, the first wafer including a plurality of first grains; A second wafer is provided, the second wafer including opposing second bonding surfaces and third bonding surfaces, the second wafer including a plurality of second grains, the size of the first grains being larger than the size of the second grains; The second bonding surface is etched to form a first groove on a portion of the second grains; A third wafer is provided, the third wafer including opposing fourth bonding surfaces and fourth surfaces, the third wafer including a plurality of third grains, the size of the second grains being equal to or greater than the size of the third grains; The second bonding surface of the second wafer is bonded to the first bonding surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grain is bonded to the corresponding second grain; The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures and multiple discrete second chip stack structures.

2. The method for forming the packaging structure according to claim 1, characterized in that, The first wafer further includes a first dicing channel located between adjacent first dies; the second wafer further includes a second dicing channel located between adjacent second dies; and the third wafer further includes a third dicing channel located between adjacent third dies.

3. The method for forming the packaging structure according to claim 2, characterized in that, The size of the first groove is greater than or equal to the size of the second grain.

4. The method for forming the packaging structure according to claim 3, characterized in that, The size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain; the size of the second groove is the sum of the size of the third grain and the size of the third kerf around the third grain.

5. The method for forming the packaging structure according to claim 2, characterized in that, The size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the second wafer, the projection of the first dicing ditch onto the second bonding surface of the second wafer coincides with the projection of a portion of the first groove onto the second bonding surface, and the projection of the third dicing ditch onto the second bonding surface of the second wafer coincides with at least a portion of the projection of the second dicing ditch onto the second bonding surface.

6. The method for forming the packaging structure according to claim 5, characterized in that, The condition that the size of the first grain is greater than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; The second grain being larger than the third grain includes: the size of the second grain being an integer multiple of the size of the third grain.

7. The method for forming the packaging structure according to claim 6, characterized in that, The projection of one of the first grains on the second bonding surface coincides with the projections of multiple second grains on the second bonding surface.

8. The method for forming the packaging structure according to claim 7, characterized in that, Dividing the bonded first wafer, second wafer, and third wafer includes dividing the bonded first wafer, second wafer, and third wafer along the first dicing track, the second dicing track, and the third dicing track, respectively.

9. The method for forming the packaging structure according to claim 1, characterized in that, Bonding the fourth bonding surface of the third wafer to the third bonding surface of the second wafer, such that at least some of the third grains are bonded to the corresponding second grains, includes: bonding all the third grains on the third wafer to the corresponding second grains.

10. The method for forming the packaging structure according to claim 9, characterized in that, A first chip stack structure includes a first die, at least one second die bonded to the first die, and at least one third die bonded to the at least one second die. A second chip stack structure includes a second die and the third die bonded together.

11. The method for forming the packaging structure according to claim 1, characterized in that, Bonding the fourth bonding surface of the third wafer to the third bonding surface of the second wafer, such that at least a portion of the third grains are bonded to the corresponding second grains, includes: bonding a portion of the third grains to the corresponding second grains, while the remaining portion of the third grains are not bonded to the corresponding second grains.

12. The method for forming the packaging structure according to claim 11, characterized in that, The forming method further includes: etching a portion of the fourth bonding surface to form a second groove on a portion of the third grains; When the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, another portion of the third grains will not bond with the corresponding second grains due to the presence of the second groove.

13. The method for forming the packaging structure according to claim 12, characterized in that, The bonded first wafer, second wafer, and third wafer are divided to form multiple discrete first chip stack structures and second chip stack structures, while simultaneously obtaining several separated third dies.

14. The method for forming the packaging structure according to claim 13, characterized in that, A first chip stack structure includes a first die and at least one second die bonded to the first die, and a second chip stack structure includes a second die and a third die bonded together.

15. The method for forming the packaging structure according to claim 1, characterized in that, A fourth wafer is provided, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, the size of the third grains being equal to or greater than the size of the fourth grains; The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain; The bonded first wafer, second wafer, third wafer, and fourth wafer are divided to form multiple discrete first chip stack structures and second chip stack structures, or to form multiple discrete first chip stack structures, second chip stack structures, and third chip stack structures.

16. The method for forming the packaging structure according to claim 1, characterized in that, The first bonding surface has a first bonding layer, the second bonding surface has a second bonding layer, the third bonding surface has a third bonding layer, and the fourth bonding surface has a fourth bonding layer.

17. The method for forming the packaging structure according to claim 16, characterized in that, The first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer are all made of the same material.

18. The method for forming the packaging structure according to claim 17, characterized in that, The materials of the first bonding layer, the second bonding layer, the third bonding layer and the fourth bonding layer include dielectric materials, or a combination of dielectric layer materials and metallic materials, or solder.

19. The method for forming the packaging structure according to claim 18, characterized in that, The dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

20. The method for forming the packaging structure according to claim 16, characterized in that, After forming a plurality of first grains on the first wafer, the first bonding layer is formed on the first bonding surface of the first wafer.

21. The method for forming the packaging structure according to claim 16, characterized in that, After the second grain is formed on the second wafer, the second bonding layer is formed on the second bonding surface of the second wafer, and the third bonding layer is formed on the third bonding surface of the second wafer.

22. The method for forming the packaging structure according to claim 21, characterized in that, The second bonding layer is etched to form the first groove in the second bonding layer.

23. The method for forming the packaging structure according to claim 16, characterized in that, After the third grain is formed on the third wafer, the fourth bonding layer is formed on the fourth bonding surface of the third wafer.

24. The method for forming the packaging structure according to claim 23, characterized in that, The fourth bonding layer is etched to form a second groove in the fourth bonding layer.

25. The method for forming the packaging structure according to claim 16, characterized in that, The second bonding surface of the second wafer is bonded to the first bonding surface of the first wafer using a direct bonding process, a dielectric bonding process, an anodic bonding process, or a hybrid bonding process, and the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer.

26. A packaging structure, characterized in that, include: The first wafer includes opposing first bonding surfaces and first surfaces, and the first wafer includes a plurality of first grains; The second wafer includes opposing second bonding surfaces and third bonding surfaces, and includes a plurality of second grains, wherein the size of the first grain is larger than the size of the second grain, and a portion of the second grains have a first groove penetrating the second bonding surface; The third wafer includes opposing fourth bonding surfaces and fourth surfaces, and the third wafer includes a plurality of third grains, wherein the size of the second grain is equal to or greater than the size of the third grain; The second bonding surface of the second wafer is bonded to the first bonding surface of the first wafer, such that a portion of the second grains are bonded to the corresponding first grains, while another portion of the second grains will not be bonded to the corresponding first grains due to the presence of the first groove; The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grain is bonded to the corresponding second grain.

27. The packaging structure according to claim 26, characterized in that, The first wafer further includes a first dicing channel located between adjacent first grains; the second wafer further includes a second dicing channel located between adjacent second grains; the third wafer further includes a third dicing channel located between adjacent third grains; the size of the first groove is greater than or equal to the size of the second grain.

28. The packaging structure according to claim 27, characterized in that, The size of the first groove is the sum of the size of the second grain and the size of the second kerf around the second grain.

29. The packaging structure according to claim 27, characterized in that, The size of the first wafer is equal to the size of the second wafer, the size of the third wafer is equal to the size of the second wafer, the projection of the first dicing ditch onto the second bonding surface of the second wafer coincides with the projection of a portion of the first groove onto the second bonding surface, and the projection of the third dicing ditch onto the second bonding surface of the second wafer coincides with at least a portion of the projection of the second dicing ditch onto the second bonding surface.

30. The packaging structure according to claim 29, characterized in that, The size of the first grain being larger than the size of the second grain includes: the size of the first grain being an integer multiple of the size of the second grain; and the projection of one of the first grains on the second bonding surface coinciding with the projections of multiple second grains on the second bonding surface. The second grain being larger than the third grain includes: the size of the second grain being an integer multiple of the size of the third grain; and the projection of one of the second grains on the second bonding surface coinciding with the projections of multiple third grains on the second bonding surface.

31. The packaging structure according to claim 26, characterized in that, The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least some of the third grains are bonded to the corresponding second grains, including: bonding all the third grains on the third wafer to the corresponding second grains.

32. The packaging structure according to claim 26, characterized in that, The fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, such that at least a portion of the third grains are bonded to the corresponding second grains, including: a portion of the third grains are bonded to the corresponding second grains, and another portion of the third grains are not bonded to the corresponding second grains.

33. The packaging structure according to claim 32, characterized in that, The packaging structure further includes: a portion of the third grains having a second groove penetrating the fourth bonding surface; When the fourth bonding surface of the third wafer is bonded to the third bonding surface of the second wafer, another portion of the third grains will not bond to the corresponding second grains due to the presence of the second groove.

34. The packaging structure according to claim 33, characterized in that, The size of the second groove is the sum of the size of the third grain and the size of the third kerf around the third grain.

35. The packaging structure according to claim 26, characterized in that, The first bonding surface has a first bonding layer, the second bonding surface has a second bonding layer, the third bonding surface has a third bonding layer, and the fourth bonding surface has a fourth bonding layer; the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer are all made of the same material.

36. The packaging structure according to claim 35, characterized in that, The materials of the first bonding layer, the second bonding layer, the third bonding layer, and the fourth bonding layer include dielectric materials, or a combination of dielectric layer materials and metallic materials, or solder; the dielectric material includes silicon oxide or silicon carbide; the metallic material includes copper; and the solder includes tin or a tin alloy.

37. The packaging structure according to claim 26, characterized in that, The packaging structure further includes: a fourth wafer, the fourth wafer including opposing fifth bonding surfaces and fifth surfaces, the fourth wafer including a plurality of fourth grains, and the size of the third grains being equal to or greater than the size of the fourth grains; The fifth bonding surface of the fourth wafer is bonded to the fourth surface of the third wafer, such that at least a portion of the fourth grain is bonded to the corresponding third grain.

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