Chip stacking structure and chip stacking method
By introducing auxiliary components such as heat dissipation cavities and positioning slots into the chip packaging structure, the heat dissipation and positioning problems of chip packaging are solved, achieving efficient heat dissipation and precise packaging.
Patent Information
- Application Number
- CN202511044486.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-10-31
AI Technical Summary
Existing chip packaging structures lack effective heat dissipation structures and positioning calibration mechanisms, resulting in reduced heat dissipation and inconvenient packaging operations.
A chip stacking structure is designed, which achieves heat dissipation and positioning calibration by setting auxiliary components such as heat dissipation cavity, limiting groove and positioning slot on the bottom and top substrate of the package, and is fixed by adhesive and packaged by the cooperation of auxiliary components.
It improves the heat dissipation efficiency and ease of packaging operations, ensures packaging accuracy, and avoids packaging misalignment and heat accumulation.
Smart Images
Figure CN120878652A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip packaging technology, and in particular to a chip stacking structure and a chip stacking method. Background Technology
[0002] Chip packaging is the process of assembling integrated circuits into a final chip product. Simply put, it involves placing the bare integrated circuit dies produced by the foundry onto a substrate that serves as a support, bringing out the pins, and then fixing and packaging them into a whole.
[0003] For chip packaging, the chip body is generally pressed together by the bottom substrate and the top substrate, or fixed by adhesive. The chip body is then connected to the pins, which extend outwards. Existing stacked packaging structures lack corresponding heat dissipation structures to assist the overall heat dissipation function of the chip package. Generally, cooling paste or grease is added during packaging. However, the cooling effect of the cooling paste or grease will decrease over time. Therefore, a cooling structure is needed to assist cooling. Furthermore, when the bottom substrate and the top substrate are basically stacked and sealed, the calibration and positioning of the two are inconvenient and need to be improved and optimized.
[0004] To address these issues, this invention proposes a chip stacking structure and a chip stacking method. Summary of the Invention
[0005] The purpose of this invention is to provide a chip stacking structure and a chip stacking method to solve the problems mentioned in the background art.
[0006] To achieve the above objectives, the present invention provides the following technical solution: a chip stacking structure, comprising a bottom package substrate and a top package substrate, wherein a chip body is disposed at the center of the top surface of the bottom package substrate, and pins are disposed on the side of the chip body; A wrapping groove adapted to the chip body is provided on the bottom side of the top substrate of the package, a first auxiliary component is provided in the pin, and a second auxiliary component is provided in the top substrate of the package.
[0007] Preferably, the first auxiliary component includes a heat dissipation cavity, an auxiliary hole, a first auxiliary connecting groove, and a positioning slot; the heat dissipation cavity is disposed in the pin, and the bottom end of the pin is sealed.
[0008] Preferably, the auxiliary holes are evenly distributed on the side of the pin, and the auxiliary holes are connected to the heat dissipation cavity inside the pin.
[0009] Preferably, the first auxiliary connecting slot is disposed on the pin, and the first auxiliary connecting slot is also connected to the heat dissipation cavity. A positioning slot is provided at the slot opening of the first auxiliary connecting slot, and the number of sets of the first auxiliary connecting slot and the pin are the same.
[0010] Preferably, the second auxiliary component includes a limiting groove, a second auxiliary connecting groove, a positioning frame, a flow guiding cavity, and a bonding cavity; the limiting groove is equidistantly disposed on the bottom side of the top substrate of the package, and the limiting groove is disposed on the side of the wrapping groove, and the second auxiliary connecting groove is disposed in the limiting groove.
[0011] Preferably, the limiting groove and the pin are positioned correspondingly, have the same number of sets, and the width of the limiting groove is equal to the width of the pin.
[0012] Preferably, the second auxiliary connecting groove and the first auxiliary connecting groove are positioned correspondingly, have the same number of sets, and have the same shape and size of opening.
[0013] Preferably, a positioning frame is fixedly provided at the slot opening of the second auxiliary connecting slot, and the positioning frame and the positioning slot are positioned correspondingly and are compatible with each other.
[0014] Preferably, the second auxiliary connecting groove is connected to the flow guiding cavity, the flow guiding cavity is equidistantly disposed in the top substrate of the package, and the other end of the flow guiding cavity is connected to the bonding cavity, the bonding cavity is equidistantly disposed in the wrapping groove.
[0015] A chip stacking method for a chip stacking structure, the chip stacking method being as follows: S1: Position the chip body in the middle of the bottom substrate of the package; S2: Apply an appropriate amount of adhesive to the upper part of the bottom substrate of the package and the bottom side of the top substrate of the package, respectively. S3: Press the top substrate of the package onto the bottom substrate of the package. The wrapping groove on the bottom side of the top substrate of the package wraps the chip body. At the same time, the limiting groove on the bottom side of the top substrate of the package is locked onto the pins at the corresponding positions. The positioning card frame set at the slot of the second auxiliary communication slot is locked in the positioning card slot at the slot of the first auxiliary communication slot, so as to realize the rapid calibration and docking of the top substrate of the package and the bottom substrate of the package.
[0016] Compared with the prior art, the beneficial effects of the present invention are: The chip stacking structure designed in this invention includes a bottom packaging substrate and a top packaging substrate. A chip body is positioned at the center of the top surface of the bottom packaging substrate, and pins are arranged on the sides of the chip body. A wrapping groove adapted to the chip body is provided on the bottom side of the top packaging substrate. A first auxiliary component is arranged in the pins, and a second auxiliary component is arranged in the top packaging substrate. The chip stacking assembly in this solution mainly achieves encapsulation through the cooperation of the top and bottom packaging substrates. The first auxiliary component in the pins works in conjunction with the second auxiliary component in the top packaging substrate to provide a heat dissipation aid for the package formed by the top and bottom packaging substrates. Furthermore, the cooperation between the limiting groove and the pins, as well as the cooperation between the positioning frame and the positioning slot, provides a positioning and calibration function for the docking encapsulation of the bottom and top packaging substrates, improving the convenience of packaging operations and having a positive effect on improving chip packaging quality. Attached Figure Description
[0017] Figure 1 This is a top view of the chip stacking structure connection of the present invention; Figure 2 This is a bottom view of the chip stacking structure connection of the present invention; Figure 3 This is a side plan view of the chip stacking structure of the present invention; Figure 4 This is a schematic diagram of the connection of the bottom substrate structure of the package of the present invention; Figure 5 for Figure 4 Enlarged schematic diagram of the structural connection at point A; Figure 6 This is a schematic diagram of a partial structure connection of the top substrate of the package of the present invention; Figure 7 for Figure 6 Enlarged schematic diagram of the structural connection at point B.
[0018] In the figure: bottom substrate 1, chip body 2, pins 3, top substrate 4, wrapping groove 5, heat dissipation cavity 601, auxiliary hole 602, first auxiliary connecting groove 603, positioning slot 604, limiting groove 701, second auxiliary connecting groove 702, positioning frame 703, flow guiding cavity 704, bonding cavity 705. Detailed Implementation
[0019] The technical solutions in the embodiments of the present invention will be clearly and completely described below. All other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present invention.
[0020] Example 1: Please refer to Figures 1-7A chip stacking structure includes a bottom package substrate 1 and a top package substrate 4. A chip body 2 is disposed at the center of the top surface of the bottom package substrate 1, and pins 3 are disposed on the side of the chip body 2. A wrapping groove 5 adapted to the chip body 2 is disposed on the bottom side of the top package substrate 4. A first auxiliary component is disposed in the pins 3, and a second auxiliary component is disposed in the top package substrate 4.
[0021] The chip stacking assembly in this solution is mainly packaged by the cooperation of the top substrate 4 and the bottom substrate 1. A first auxiliary component in pin 3 works in conjunction with a second auxiliary component in the top substrate 4 to provide a heat dissipation aid for the package formed by the top substrate 4 and the bottom substrate 1. Furthermore, the cooperation between the limiting groove 701 and the pin 3, and the cooperation between the positioning frame 703 and the positioning slot 604, provides a positioning and calibration function for the docking of the bottom substrate 1 and the top substrate 4, improving the convenience of the packaging operation.
[0022] The chip body 2 is mounted and positioned at the center of the bottom substrate 1 of the package. Then, appropriate amounts of adhesive are applied to the upper part of the bottom substrate 1 and the bottom side of the top substrate 4. Next, the top substrate 4 and the bottom substrate 1 are joined together, and the top substrate 4 is pressed onto the bottom substrate 1. The encapsulation groove 5 on the bottom side of the top substrate 4 encapsulates the chip body 2. Simultaneously, the limiting groove 701 on the bottom side of the top substrate 4 engages with the corresponding pin 3. The positioning frame 703, located at the opening of the second auxiliary communication groove 702, engages with the positioning slot 604 at the opening of the first auxiliary communication groove 603, thus realizing the top substrate... 4. Rapid calibration and docking with the bottom substrate 1 of the package; wherein the first auxiliary component includes a heat dissipation cavity 601, an auxiliary hole 602, a first auxiliary connecting groove 603 and a positioning slot 604; the heat dissipation cavity 601 is disposed in the pin 3, and the bottom end of the pin 3 is sealed; the auxiliary hole 602 is evenly disposed on the side of the pin 3, and the auxiliary hole 602 is connected to the heat dissipation cavity 601 inside the pin 3; the first auxiliary connecting groove 603 is disposed on the pin 3, and the first auxiliary connecting groove 603 is also connected to the heat dissipation cavity 601, and a positioning slot 604 is provided at the opening of the first auxiliary connecting groove 603, and the number of sets of the first auxiliary connecting groove 603 and the pin 3 are the same.
[0023] When docking the bottom substrate 1 and the top substrate 4 of the package, the limiting groove 701 on the bottom side of the top substrate 4 is aligned with the corresponding pin 3, and the positioning frame 703 at the slot opening of the second auxiliary communication groove 702 in the limiting groove 701 is aligned with the positioning slot 604 at the slot opening of the first auxiliary communication groove 603 on the pin 3, and the two are inserted. At the same time, the top substrate 4 and the bottom substrate 1 of the package are aligned to avoid docking misalignment and improve the convenience of docking between the top substrate 4 and the bottom substrate 1 of the package. The second auxiliary component includes the limiting groove 701, the second auxiliary communication groove 702, the positioning frame 703, the flow guiding cavity 704, and the bonding cavity 705. The limiting grooves 701 are equidistantly arranged on the bottom side of the top substrate 4 of the package, and the limiting grooves 701 are arranged in the wrapping groove 5. On the side, a second auxiliary connecting groove 702 is provided in the limiting groove 701; the limiting groove 701 and the pin 3 are positioned correspondingly and have the same number of sets, and the width of the limiting groove 701 is equal to the width of the pin 3; the second auxiliary connecting groove 702 and the first auxiliary connecting groove 603 are positioned correspondingly and have the same number of sets, and the shape and size of their openings are the same; a positioning frame 703 is fixedly provided at the opening of the second auxiliary connecting groove 702, the positioning frame 703 and the positioning groove 604 are positioned correspondingly and are fitted together; the second auxiliary connecting groove 702 is connected to the flow guiding cavity 704, the flow guiding cavity 704 is equidistantly arranged in the top substrate 4 of the package, and the other end of the flow guiding cavity 704 is connected to the bonding cavity 705, the bonding cavity 705 is equidistantly arranged in the wrapping groove 5.
[0024] After the positioning card frame 703 is inserted into the positioning card slot 604, the openings of the first auxiliary connecting slot 603 and the second auxiliary connecting slot 702 are aligned. The heat generated by the chip body 2 can flow into the first auxiliary connecting slot 603 through the cooperation of the bonding cavity 705, the guiding cavity 704, and the second auxiliary connecting slot 702, and then flow out from the heat dissipation cavity 601 in the pin 3, that is, through the auxiliary hole 602. The auxiliary hole 602 not only provides heat dissipation, but also has a certain blocking and filtering effect on external impurities, preventing them from entering the interior of the package and avoiding contamination of the interior of the package and the chip body 2.
[0025] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A chip stacking structure, comprising a bottom package substrate (1) and a top package substrate (4), wherein a chip body (2) is disposed at the center of the top surface of the bottom package substrate (1), and pins (3) are disposed on the side of the chip body (2). Its features are: A wrapping groove (5) adapted to the chip body (2) is provided on the bottom side of the top substrate (4) of the package, a first auxiliary component is provided in the pin (3), and a second auxiliary component is provided in the top substrate (4) of the package.
2. The chip stacking structure according to claim 1, characterized in that: The first auxiliary component includes a heat dissipation cavity (601), an auxiliary hole (602), a first auxiliary connecting groove (603), and a positioning slot (604); the heat dissipation cavity (601) is disposed in the pin (3), and the bottom end of the pin (3) is sealed.
3. The chip stacking structure according to claim 2, characterized in that: The auxiliary holes (602) are evenly arranged on the side of the pin (3), and the auxiliary holes (602) are connected to the heat dissipation cavity (601) inside the pin (3).
4. The chip stacking structure according to claim 2, characterized in that: The first auxiliary communication slot (603) is set on the pin (3), and the first auxiliary communication slot (603) is also connected to the heat dissipation cavity (601). A positioning slot (604) is set at the slot opening of the first auxiliary communication slot (603). The first auxiliary communication slot (603) and the pin (3) have the same number of sets.
5. The chip stacking structure according to claim 1, characterized in that: The second auxiliary component includes a limiting groove (701), a second auxiliary connecting groove (702), a positioning frame (703), a flow guiding cavity (704), and a bonding cavity (705); the limiting groove (701) is equidistantly disposed on the bottom side of the top substrate (4) of the package, and the limiting groove (701) is disposed on the side of the wrapping groove (5), and the second auxiliary connecting groove (702) is disposed in the limiting groove (701).
6. The chip stacking structure according to claim 5, characterized in that: The limiting groove (701) and the pin (3) are positioned in the same way and have the same number of sets. The width of the limiting groove (701) is equal to the width of the pin (3).
7. The chip stacking structure according to claim 5, characterized in that: The second auxiliary connecting groove (702) and the first auxiliary connecting groove (603) are positioned in the same way, have the same number of sets, and have the same shape and size of opening.
8. The chip stacking structure according to claim 5, characterized in that: A positioning frame (703) is fixedly provided at the slot opening of the second auxiliary connecting groove (702). The positioning frame (703) and the positioning groove (604) are positioned correspondingly and are matched and engaged.
9. The chip stacking structure according to claim 5, characterized in that: The second auxiliary communication groove (702) is connected to the flow guiding cavity (704), the flow guiding cavity (704) is equidistantly arranged in the top substrate (4) of the package, and the other end of the flow guiding cavity (704) is connected to the bonding cavity (705), the bonding cavity (705) is equidistantly arranged in the wrapping groove (5).
10. A chip stacking method for a chip stacking structure as described in any one of claims 1-9, characterized in that, The chip stacking method is as follows: S1: Position the chip body (2) at the center of the bottom substrate (1) of the package; S2: Apply an appropriate amount of adhesive to the upper part of the bottom substrate (1) and the bottom side of the top substrate (4) of the package respectively; S3: Press the top substrate (4) of the package onto the bottom substrate (1) of the package. The wrapping groove (5) set on the bottom side of the top substrate (4) of the package wraps the chip body (2). At the same time, the limiting groove (701) set on the bottom side of the top substrate (4) of the package is locked onto the pin (3) at the corresponding position. The positioning card frame (703) set at the slot of the second auxiliary communication groove (702) is locked in the positioning card slot (604) at the slot of the first auxiliary communication groove (603), so as to realize the rapid calibration and docking of the top substrate (4) of the package and the bottom substrate (1) of the package.