Semiconductor element with filling layer and manufacturing method thereof

Abstract

The invention discloses a semiconductor element and a manufacturing method of the semiconductor element. The semiconductor device includes: a substrate; the conductive structure comprises a conductive concave layer which is arranged on the substrate; the conductive filling layer is arranged on the conductive concave layer, the conductive concave layer comprises a top surface, and the top surface is provided with a V-shaped section profile; and a top conductive layer disposed on the conductive structure. The conductive filling layer comprises germanium or silicon germanium.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 18 / 648,641 (priority date: April 29, 2024), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device having a filling layer and a method for manufacturing the same. Background Technology

[0004] Semiconductor components are used in a wide range of electronic applications, including personal computers, mobile phones, digital cameras, and other electronic devices. The size of semiconductor components continues to shrink to meet the ever-increasing demands for computing power. However, the challenges brought about by this shrinking size are becoming increasingly frequent and impactful. Therefore, challenges remain in improving quality, yield, performance, and reliability while reducing complexity.

[0005] The discussion in the Prior Art paragraph is provided for background information only. The statements in the Discussion in the Prior Art paragraph are not an admission that the content disclosed in this paragraph constitutes prior art to this disclosure, and nothing in the Discussion in the Prior Art paragraph shall be construed as an admission that any part of this application, including the part in the Discussion in the Prior Art paragraph, constitutes prior art to this disclosure. Summary of the Invention

[0006] One aspect of this disclosure is to provide a semiconductor device, comprising: a substrate; a conductive structure including: a conductive recess layer disposed on the substrate, wherein a top surface of the conductive recess layer has a V-shaped cross-sectional profile; a conductive fill layer disposed on the conductive recess layer; a first barrier layer covering the sidewalls of the conductive recess layer and the conductive fill layer, and covering a bottom surface of the conductive recess layer; and a top conductive layer disposed on the conductive structure. The conductive structure is disposed in the substrate and protrudes from the substrate. A surface of the conductive fill layer is recessed relative to the substrate. The conductive fill layer comprises germanium or silicon-germanium.

[0007] Another aspect of this disclosure is to provide a semiconductor device comprising: a stacked structure disposed on a semiconductor substrate; a first sidewall spacer and a second sidewall spacer covering one sidewall of the stacked structure; and a contact plug disposed between a pair of the stacked structures. An air gap is sealed between the first sidewall spacer and the second sidewall spacer. The top edges of the first sidewall spacer, the air gap, and the second sidewall spacer are coplanar with the top surface of the stack. A top portion of the air gap gradually tapers toward the top edge of the air gap.

[0008] Another aspect of this disclosure is to provide a method for manufacturing a semiconductor device, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a first dielectric layer on the epitaxial layer; forming a first opening in the dielectric layer, the epitaxial layer, and the substrate; forming a conductive recess in the first opening; forming a conductive filling layer on the conductive recess and in the first opening; and forming a top conductive layer on the conductive filling layer. A top surface of the conductive recess has a V-shaped cross-sectional profile. The conductive recess and the conductive filling layer together form a conductive structure; the conductive filling layer comprises germanium or silicon-germanium.

[0009] Due to the design of the semiconductor device disclosed herein, the resistance of the conductive structure can be reduced by employing a conductive filling layer containing germanium. This, in turn, improves the performance of the semiconductor device.

[0010] The technical features and advantages of this disclosure have been summarized quite extensively above, thus enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0011] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0012] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure;

[0013] Figures 2 to 10 This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to an embodiment of the present disclosure;

[0014] Figure 11 and Figure 12 This is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor device according to another embodiment of this disclosure;

[0015] Figures 13 to 16 This is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor device according to another embodiment of this disclosure;

[0016] Figure 17 and Figure 18This is a cross-sectional view illustrating a portion of the manufacturing process of semiconductor element 1B according to another embodiment of this disclosure;

[0017] Figures 19 to 25 This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 1A: Semiconductor components

[0020] 1B: Semiconductor components

[0021] 1C: Semiconductor components

[0022] 1D: Semiconductor components

[0023] 1E: Semiconductor components

[0024] 1F: Semiconductor components

[0025] 1G: Semiconductor components

[0026] 1H: Semiconductor components

[0027] 1I: Semiconductor components

[0028] 1J: Semiconductor components

[0029] 1K: Semiconductor components

[0030] 10: Method

[0031] 100: Semiconductor substrate

[0032] 101: Substrate

[0033] 102: Gate structure

[0034] 103: First dielectric layer

[0035] 103B: Bottom surface

[0036] 103O: First opening

[0037] 103O': Second opening

[0038] 103S1: Sidewall

[0039] 103S2: Sidewall

[0040] 103TS: Top surface

[0041] 104: Gate electrode

[0042] 105: Barrier Layer

[0043] 105CV: Protruding part

[0044] 105FP: Flat area

[0045] 106: Gate dielectric layer

[0046] 107: Top conductive layer

[0047] 108: Hard Mask

[0048] 108TS: Top surface

[0049] 109: Second dielectric layer

[0050] 110: Sidewall spacers

[0051] 110a: First sidewall spacer

[0052] 110b: Second sidewall spacer

[0053] 111: Bottom conductive layer

[0054] 112: Source / Drain Structure

[0055] 113: Epitaxial layer

[0056] 114: Dielectric layer

[0057] 116: Dielectric layer

[0058] 200: Conductive structure

[0059] 200SW: Sidewall

[0060] 201: Conductive recess

[0061] 201B: Bottom surface

[0062] 201R: concave part

[0063] 201S: Sidewall

[0064] 201TS: Top Surface

[0065] 201-1: Part One

[0066] 201-3: Part Two

[0067] 202: Isolation Structure

[0068] 203: Conductive filler layer

[0069] 203S: Sidewall

[0070] 203TS: Top Surface

[0071] 204: Contact plug

[0072] 205: Barrier Layer

[0073] 206: Conductive pattern

[0074] 208: Dielectric layer

[0075] 401: First conductive material

[0076] 401R: Dent

[0077] 403: Barrier Material

[0078] 405: Second conductive material

[0079] 501: First mask layer

[0080] 503: Second mask layer

[0081] 1102: Side boundary

[0082] 1103: Lateral boundary

[0083] AA: Active Zone

[0084] AG: Air gap

[0085] E1: Top

[0086] E2: Top

[0087] E3: Top

[0088] Gate: gate

[0089] S11: Steps

[0090] S13: Steps

[0091] S15: Steps

[0092] S17: Steps

[0093] SS: Sidewall

[0094] T1: First thickness

[0095] T2: Second thickness

[0096] VL1: Vertical horizontal plane

[0097] W1: Width

[0098] W2: Width

[0099] W3: Width Detailed Implementation

[0100] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations described below are provided to simplify this disclosure. Of course, these are merely illustrative and not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature can include embodiments in which the first and second features are formed in direct contact, or embodiments in which an additional feature is formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, element symbols and / or letters may be repeated in various examples in this disclosure. Such repetition is for simplicity and clarity and is not in itself a limitation on the relationship between the various embodiments and / or configurations discussed.

[0101] Furthermore, for ease of description, spatially related terms such as "below," "under," "lower part," "above," "upper part," or other similar terms may be used herein to describe the relative relationship between one element or feature and another shown in the accompanying drawings. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the element in use or operation. The element may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0102] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it may be directly connected to or coupled to the other component or layer, or there may be intermediate components or intermediate layers.

[0103] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one component from another. Thus, for example, the first component, first member, or first part discussed below may be referred to as the second component, second member, or second part without departing from the teachings of this disclosure.

[0104] Unless the context otherwise indicates, terms such as “identical,” “equal,” “plane,” or “coplanar” as used herein do not necessarily mean exactly identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures when referring to orientations, layouts, locations, shapes, dimensions, quantities, or other measures, but are intended to cover substantially identical orientations, layouts, locations, shapes, dimensions, quantities, or other measures within an acceptable range of possible variations (e.g., due to manufacturing processes). The term “substantially” may be used herein to reflect this meaning. For example, articles described as “substantially identical,” “substantially equal,” or “substantially coplanar” may be exactly identical, equal, or coplanar, or may be substantially identical, equal, or coplanar within an acceptable range of possible variations (e.g., due to manufacturing processes).

[0105] In this disclosure, semiconductor element generally refers to an element that can operate using semiconductor properties, and electro-optic elements, light-emitting display elements, semiconductor circuits and electronic components are all included in the category of semiconductor element.

[0106] It should be noted that, in the description of this disclosure, "above" (or "up") corresponds to the direction of the arrow in the Z direction, and "below" (or "down") corresponds to the opposite direction of the arrow in the Z direction.

[0107] Figure 1 This is a flowchart illustrating a method 10 for manufacturing a semiconductor element 1A according to an embodiment of the present disclosure. Figures 2 to 10 This is a cross-sectional view illustrating the manufacturing process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0108] See Figures 1 to 3 In step S11, a substrate 101 can be provided, a first dielectric layer 103 can be formed on the substrate 101, and a first opening 103O can be formed in the first dielectric layer 103.

[0109] See Figure 2 The substrate 101 may include a main semiconductor substrate composed entirely of at least one semiconductor material, a plurality of component assemblies (not shown for clarity), a plurality of dielectric layers (not shown for clarity), and a plurality of conductive features (not shown for clarity). The main semiconductor substrate may be formed of, for example, elemental semiconductors such as silicon or germanium; compound semiconductors such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors; or combinations thereof.

[0110] In some embodiments, substrate 101 may further include a semiconductor-on-insulator substrate, which comprises, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may be formed of the same material as the aforementioned main semiconductor substrate. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. For example, the insulating layer may be a dielectric oxide, such as silicon oxide. Another example is that the insulating layer may be a dielectric nitride, such as silicon nitride or boron nitride. Yet another example is that the insulating layer may comprise a stack of dielectric oxides and dielectric nitrides in any order, which is a stack of silicon oxide and either silicon nitride or boron nitride. The insulating layer may have a thickness between about 10 nm and 200 nm.

[0111] It should be noted that in the description of this disclosure, when the term "about" is used to modify the amount of an ingredient, component, or reactant of this disclosure, it refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0112] Multiple component assemblies can be formed on substrate 101. Some portions of the multiple component assemblies can be formed within substrate 101. The multiple component assemblies can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect transistors, other similar transistors, or combinations thereof.

[0113] Multiple dielectric layers can be formed on substrate 101 and cover multiple component assemblies. In some embodiments, the multiple dielectric layers can be formed of materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, other similar materials, or combinations thereof. Low-k dielectric materials can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, low-k dielectric materials can have a dielectric constant less than 2.0. The multiple dielectric layers can be formed by a deposition process, such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or other similar deposition processes. A planarization process can be performed after the deposition process to remove excess material and provide a substantially flat surface for subsequent process steps.

[0114] Multiple conductive features may include interconnect layers, conductive vias, and conductive pads. Interconnect layers may be separated from each other and may be horizontally disposed among multiple dielectric layers arranged along the Z-direction. In this embodiment, the topmost interconnect layer may be designated as a conductive pad. Conductive vias may connect interconnect layers adjacent to each other along the Z-direction, connect component assemblies to adjacent interconnect layers, and / or connect conductive pads to adjacent interconnect layers. In some embodiments, conductive vias may improve heat dissipation and provide structural support. In some embodiments, the multiple conductive features may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum compounds, or combinations thereof. The multiple conductive features may be formed during the formation of the multiple dielectric layers.

[0115] In some embodiments, multiple component assemblies and multiple conductive layers may together comprise a functional unit of semiconductor element 1A. In the description of this disclosure, a functional unit generally refers to a functionally related circuit that has been divided into different units for functional purposes. In some embodiments, the functional unit of semiconductor element 1A may include, for example, highly complex circuitry, such as a processor core, memory controller, accelerator unit, or other suitable functional circuitry.

[0116] See Figure 2 A first dielectric layer 103 can be formed on a substrate 101. In some embodiments, the first dielectric layer 103 may be part of a plurality of dielectric layers on the substrate 101. In some embodiments, the first dielectric layer 103 may be formed of a dielectric material comprising oxygen atoms and / or nitrogen atoms. In some embodiments, the first dielectric layer 103 may be formed of materials such as silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low dielectric constant dielectric materials (e.g., spin-coated low dielectric constant dielectric layers or chemical vapor deposition low dielectric constant dielectric layers) or combinations thereof. In some embodiments, the first dielectric layer 103 may include a self-planarizing material, such as spin-coated glass or spin-coated low dielectric constant dielectric materials, such as SiLK. TM The use of self-planarizing dielectric materials can eliminate the need for subsequent planarization steps. In some embodiments, the first dielectric layer 103 can be formed by deposition processes including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, or spin coating. In some embodiments, planarization processes, such as chemical mechanical polishing, can be performed to provide a substantially flat surface for subsequent process steps. In this embodiment, the first dielectric layer 103 is formed of silicon oxide. In some embodiments, the first dielectric layer 103 may be substantially composed of silicon oxide.

[0117] It should be noted that, in the description of this disclosure, the feature of "substantially composed of a particular material" includes more than 95%, more than 98%, more than 99%, or more than 99.5% of the material on an atomic basis.

[0118] See Figure 2 A first mask layer 501 can be formed on the first dielectric layer 103. The first mask layer 501 may have a pattern of a first opening 103O. In some embodiments, the first mask layer 501 may be a photoresist layer.

[0119] See Figure 3 An etching process, such as anisotropic dry etching, can be performed using the first mask layer 501 as a mask to remove portions of the first dielectric layer 103. In some embodiments, during the etching process, the ratio of the etching rate of the first dielectric layer 103 to the etching rate of the first mask layer 501 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the etching process, the ratio of the etching rate of the first dielectric layer 103 to the etching rate of the substrate 101 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the etching process, a first opening 103O can be formed in the first dielectric layer 103. A portion of the substrate 101 can be exposed through the first opening 103O. The first mask layer 501 can be removed after the first opening 103O is formed. In some embodiments, the sidewall of the first opening 103O may be substantially vertical.

[0120] It should be noted that, in the description of this disclosure, if there is a vertical plane and the root mean square roughness of a surface deviates from the vertical plane by no more than three times the root mean square roughness of the surface, then the surface is considered "substantially vertical".

[0121] See Figure 1 , Figure 4 and Figure 5 In step S13, a conductive recess 201 can be formed in the first opening 103O.

[0122] See Figure 4A first conductive material 401 can be formed to partially fill the first opening 103O, wherein this first conductive material 401 includes a recess 401R and covers the top surface 103TS of the first dielectric layer 103. In other words, this first conductive material 401 can extend along the top surface 103TS of the first dielectric layer 103 and can be immersed in the first opening 103O to contact the substrate 101. As the size of the semiconductor device decreases, the size of the first opening 103O becomes smaller, and this first conductive material 401 may not completely fill the first opening 103O, and may form a recess 401R, wherein the boundary of the recess 401R is recessed relative to the top surface 103TS of the first dielectric layer 103 (or relative to the substrate 101). A portion of this first conductive material 401 can be formed below the recess 401R, but this disclosure is not limited thereto.

[0123] In some embodiments, the first conductive material 401 may be a conductive material that does not contain oxygen atoms and / or nitrogen atoms. In some embodiments, the first conductive material 401 may be, for example, polycrystalline silicon, polycrystalline germanium, polycrystalline silicon-germanium, doped polycrystalline silicon, doped polycrystalline germanium, or doped polycrystalline silicon-germanium. In some embodiments, this first conductive material layer 401 may be formed by, for example, low-pressure chemical vapor deposition, high-density plasma chemical vapor deposition, or other suitable deposition processes.

[0124] In some embodiments, the first conductive material 401 can be deposited by low-pressure chemical vapor deposition. The process pressure for depositing the first conductive material 401 can be between about 0.1 Torr and about 50 Torr. The reaction gas for depositing the first conductive material 401 may include a silicon source gas (e.g., silane) and / or a dopant gas (e.g., phosphine).

[0125] In some embodiments, the first conductive material 401 can be deposited by high-density plasma chemical vapor deposition (PDCVD). PDCVD can employ a plasma having an ion density on the order of approximately 1E¹¹ ions / cm³ or higher. PDCVD can also have a ionization rate (ion / nucleus ratio) on the order of approximately 1E⁻⁴ or higher. PDCVD can include pretreatment and deposition operations.

[0126] In some embodiments, the pretreatment operation may include applying a hydrogen plasma to the first opening 103O. The deposition operation may include applying a silicon source plasma to deposit this layer of first conductive material 401. A bias voltage may be applied as needed during the deposition operation.

[0127] In some embodiments, during the pretreatment and deposition operations, the substrate temperature may be below or at about 500°C, below or at about 450°C, or below or at about 400°C. The substrate temperature can be controlled in various ways. For example, the substrate temperature can be increased by a front-side plasma and cooled by a rear-side helium flow.

[0128] In some embodiments, a hydrogen source can be used to generate hydrogen plasma. The hydrogen source can be, for example, hydrogen, ammonia, or hydrazine. In some embodiments, a silicon source can be used to generate silicon plasma. The silicon source can be, for example, silane, disilane, or other higher-order silanes.

[0129] In some embodiments, the hydrogen source and / or silicon source may be combined with an inert gas that helps stabilize the high-density plasma. The inert gas may include argon, neon, and / or helium.

[0130] In some embodiments, a dopant source may also be included during the deposition operation to integrate the dopant into the first conductive material 401 layer. The high-density plasma nature allows the dopant to be more tightly bound within the first conductive material 401 layer, thus eliminating the need for a separate thermal dopant activation step. In some embodiments, a boron-containing precursor (e.g., triethylborane, trimethylborane, borane, diborane, or higher boranes) may be used as the dopant source to set activated boron doping centers in the first conductive material 401 layer. In some embodiments, a phosphorus-containing precursor (e.g., phosphine) may be used as the dopant source to set activated phosphorus doping centers in the first conductive material 401 layer.

[0131] In some embodiments, the recess 401R may have a U-shaped or V-shaped profile. In other words, the top surface of the first conductive material 401 layer formed in the first opening 103O (which forms the recess 401R) may have a U-shaped or V-shaped profile.

[0132] See Figure 5An etch-back process can be performed to remove a portion of the first conductive material 401. In some embodiments, during the etch-back process, the ratio of the etch rate of the first conductive material 401 to the etch rate of the first dielectric layer 103 can be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the etch-back process, the remaining portion of the first conductive material 401 can be referred to as the conductive recess 201. The recess 401R can be transformed into a recess 201R of the conductive recess 201, wherein the recess 201R can be referred to as part of the top surface 201TS of the conductive recess 201. In some embodiments, the recess 201R can have a U-shaped cross-sectional profile or a V-shaped cross-sectional profile. In other words, the top surface 201TS of the conductive recess 201 forming the recess 201R can have a U-shaped cross-sectional profile or a V-shaped cross-sectional profile. The top surface 201TS of the conductive recess 201 may be located at a vertical horizontal plane VL1 below the top surface 103TS of the first dielectric layer 103. A portion of the top surface 201TS (i.e., the recess 201R) may be recessed relative to the substrate 101.

[0133] See Figure 1 , Figure 6 and Figure 7 In step S15, a conductive filling layer 203 may be deposited on the conductive recess 201 to form a conductive structure 200.

[0134] See Figure 6 A conductive filler layer 203 can be selectively deposited on the conductive recess 201. At this stage, the top surface 203TS of the conductive filler layer 203 can protrude from the top surface 103TS of the first dielectric layer 103. In other words, the top surface 203TS of the conductive filler layer 203 can protrude relative to the top surface 103TS of the first dielectric layer 103 (or relative to the substrate 101).

[0135] In some embodiments, the conductive filler layer 203 may be formed of, for example, germanium. In some embodiments, the conductive filler layer 203 may include germanium with an atomic percentage greater than or equal to 50%. In this respect, the conductive filler layer 203 may be described as a "germanium-rich layer." In some embodiments, the atomic percentage of germanium in the conductive filler layer 203 may be greater than or equal to 60%, greater than or equal to 70%, greater than or equal to 80%, greater than or equal to 90%, greater than or equal to 95%, greater than or equal to 98%, greater than or equal to 99%, or greater than or equal to 99.5%. In other words, in some embodiments, the conductive filler layer 203 is substantially composed of germanium. In some embodiments, the conductive filler layer 203 may include silicon and germanium. In other words, in some embodiments, the conductive filler layer 203 may include silicon and germanium.

[0136] In some embodiments, a conductive filler layer 203 may be formed by a deposition process. In some embodiments, the deposition process may include a reaction gas comprising a germanium precursor and / or hydrogen. In some embodiments, the germanium precursor may be substantially composed of germanane. In some embodiments, the germanium precursor may include one or more of germanane, digerane, isobutylgerane, chlorogerane, or dichlorogerane. In some embodiments, hydrogen may be used as a carrier or diluent for the germanium precursor. In some embodiments, the reaction gas may be substantially composed of germanane and hydrogen. In some embodiments, the molar percentage of germanane in the reaction gas may be in the range of about 1% to about 50%, about 2% to about 30%, or about 5% to about 20%.

[0137] Alternatively, in some embodiments, the reactant gas may also include a silicon-containing precursor. In some embodiments, the silicon-containing precursor may include one or more of silanes, polysilanes, or halosilanes. As used herein, "polysilane" is a substance having the general formula Si. n H 2n+2 The substance in which n is between 2 and 6. Furthermore, "halosilanes" are substances with the general formula Si. a X b H 2a+2-b The substance, wherein X is a halogen, a is between 1 and 6, and b is between 1 and 2a+2. In some embodiments, the silicon-containing precursor comprises SiH4, Si2H6, Si3H8, Si4H 10 One or more of SiCl4 or SiH2Cl2.

[0138] In some embodiments, the temperature of the intermediate semiconductor device to be deposited can be maintained during the deposition process. This temperature may be referred to as the substrate temperature. In some embodiments, the substrate temperature may be between about 300°C and about 800°C, between about 400°C and about 800°C, between about 500°C and about 800°C, between about 250°C and about 600°C, between about 400°C and about 600°C, or between about 500°C and about 600°C. In some embodiments, the substrate temperature may be about 540°C.

[0139] In some embodiments, the pressure of the processing chamber used to deposit the conductive filler layer 203 can be maintained during the deposition process. In some embodiments, the pressure is maintained in the range of about 1 Torr to about 300 Torr, about 10 Torr to about 300 Torr, about 50 Torr to about 300 Torr, about 100 Torr to about 300 Torr, about 200 Torr to about 300 Torr, and about 1 Torr to about 20 Torr. In some embodiments, the pressure can be maintained at about 13 Torr.

[0140] In some embodiments, the deposition selectivity may be greater than or equal to 5, greater than or equal to 10, greater than or equal to 20, greater than or equal to 30, or greater than or equal to 50. In some embodiments, the conductive filling layer 203 may be deposited on the conductive recess 201 until deposition is observed on the first dielectric layer 103.

[0141] It should be noted that in the description of this disclosure, the term "selectively depositing a layer higher on a first feature than on a second feature" or similar terms means that a first amount of the layer is deposited on the first feature and a second amount of the layer is deposited on the second feature, wherein the first amount of the layer is greater than the second amount of the layer, or no layer is deposited on the second feature. The selectivity of the deposition process can be expressed as a multiple of the growth rate. For example, if the deposition rate on one surface is 25 times faster than the deposition rate on another surface, the process can be described as having a selectivity of 25:1, or simply a selectivity of 25. In this respect, a higher ratio represents a more selective deposition process.

[0142] The term "superior" used in this context does not imply a physical orientation of one feature above another, but rather indicates a relative thermodynamic or kinetic property of the chemical reaction with one feature relative to the other. For example, selectively depositing germanium layers on silicon surfaces more readily than on dielectric surfaces means that germanium layers are deposited faster on silicon surfaces and slower or not at all on dielectric surfaces; or that forming germanium layers on silicon surfaces is thermodynamically or kinetically more advantageous than forming germanium layers on dielectric surfaces.

[0143] See Figure 7 The conductive filler layer 203 can be planarized, for example, by chemical mechanical polishing, to remove excess material and provide a substantially flat surface for subsequent processing steps. At this stage, the top surface 203TS of the conductive filler layer 203 can be substantially coplanar with the top surface 103TS of the first dielectric layer 103. In some embodiments, the width W1 of the conductive recess 201 and the width W2 of the conductive filler layer 203 can be substantially the same.

[0144] See Figure 1 and Figures 8 to 10 In step S17, a barrier layer 105 may be formed on the conductive structure 200, a top conductive layer 107 may be formed on the barrier layer 105, and a second dielectric layer 109 may be formed on the first dielectric layer 103.

[0145] See Figure 8 A barrier material 403 can be formed on the first dielectric layer 103 and the conductive structure 200. In some embodiments, the barrier material 403 can be formed of materials such as titanium, titanium nitride, tantalum, tantalum nitride, or combinations thereof. In some embodiments, this barrier material 403 can be a multilayer structure. For example, this barrier material 403 can be a titanium / titanium nitride bilayer or a tantalum / tantalum nitride bilayer. In some embodiments, this barrier material 403 can be formed by, for example, chemical vapor deposition, atomic layer deposition, or other suitable deposition processes.

[0146] For example, when the barrier material 403 is titanium nitride, this barrier material 403 can be formed by chemical vapor deposition. In some embodiments, the formation of this barrier material 403 may include: a source gas introduction step, a first purging step, a reactant flow step, and a second purging step. The source gas introduction step, the first purging step, the reactant flow step, and the second purging step may be referred to as a cycle. Multiple cycles may be performed to obtain the desired thickness of this barrier material layer 403.

[0147] In some embodiments, such as Figure 7 The intermediate semiconductor element shown can be loaded into a reaction chamber. In the source gas introduction step, a source gas containing precursors and reactants can be introduced into the reaction chamber containing the intermediate semiconductor element. The precursors and reactants can diffuse and reach the surface of the intermediate semiconductor element (i.e., the top surface 103TS of the first dielectric layer 103 and the top surface 203TS of the conductive filling layer 203). The precursors and reactants can be adsorbed onto the surface of the intermediate semiconductor element and subsequently migrate on the surface of the intermediate semiconductor element. The adsorbed precursors and adsorbed reactants can react on the surface and form solid byproducts. The solid byproducts can form nuclei on the surface. The nuclei can grow into islands and the islands can merge on the surface into a continuous thin film. In the first purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge gaseous byproducts, unreacted precursors, and unreacted reactants.

[0148] In the reactant flow step, reactants can be introduced individually into the reaction chamber to transform the continuous film into this barrier material 403. In the second purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge gaseous byproducts and unreacted reactants.

[0149] In some embodiments, the barrier material 403 can be formed using chemical vapor deposition with the assistance of plasma. The plasma source can be, for example, argon, hydrogen, or a combination thereof.

[0150] For example, the precursor can be titanium tetrachloride. The reactant can be ammonia. Due to the incomplete reaction between titanium tetrachloride and ammonia, titanium tetrachloride and ammonia may react on the surface of the intermediate semiconductor device and form a titanium nitride film containing high chloride contamination. The ammonia in the reactant flow step can reduce the chloride content of the titanium nitride film. After ammonia treatment, the titanium nitride film can be referred to as this layer barrier material 403.

[0151] See Figure 8 In some other embodiments, this barrier material 403 can be formed by atomic layer deposition, such as photo-assisted atomic layer deposition or liquid-injection atomic layer deposition. In some embodiments, the formation of this barrier material 403 may include: a first precursor introduction step, a first purging step, a second precursor introduction step, and a second purging step. The first precursor introduction step, the first purging step, the second precursor introduction step, and the second purging step may be referred to as a cycle. Multiple cycles may be performed to obtain the desired thickness of this barrier material layer 403.

[0152] In some embodiments, such as Figure 7 The intermediate semiconductor element shown can be loaded into a reaction chamber. In the first precursor introduction step, a first precursor can be introduced into the reaction chamber. The first precursor can diffuse and reach the surface of the intermediate semiconductor element (i.e., the top surface 103TS of the first dielectric layer 103 and the top surface 203TS of the conductive filling layer 203). The first precursor can adsorb onto the surface of the intermediate semiconductor element to form a monolayer at the single atomic layer level. In the first purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge unreacted first precursor.

[0153] In the second precursor introduction step, a second precursor can be introduced into the reaction chamber. The second precursor can react with the monolayer and transform the monolayer into the barrier material 403. In the second purging step, a purging gas (e.g., argon) can be injected into the reaction chamber to purge unreacted second precursor and gaseous byproducts. Compared to chemical vapor deposition, atomic layer deposition can suppress particle generation caused by gas-phase reactions because the first and second precursors are introduced separately.

[0154] In some embodiments, the first precursor may be titanium tetrachloride. The second precursor may be ammonia. The adsorbed titanium tetrachloride may form a titanium nitride monolayer. The ammonia introduced in the second precursor introduction step may react with the titanium nitride monolayer and convert the titanium nitride monolayer into this barrier material 403.

[0155] In some embodiments, the barrier material 403, formed using atomic layer deposition, can be formed with the assistance of plasma. The plasma source can be, for example, argon, hydrogen, oxygen, or a combination thereof. In some embodiments, the oxygen source can be, for example, water, oxygen, or ozone. In some embodiments, co-reactants can be introduced into the reaction chamber. The co-reactants can be selected from the group consisting of hydrogen, hydrogen plasma, oxygen, air, water, ammonia, hydrazine, alkylhydrazine, borane, silane, ozone, and combinations thereof.

[0156] In some embodiments, the formation of this barrier material 403 can be performed using the following process conditions: The substrate temperature can be between about 160°C and about 300°C. The evaporator temperature can be about 175°C. The pressure in the reaction chamber can be about 5 mbar. The solvent for the first and second precursors can be toluene.

[0157] See Figure 8 A second conductive material 405 can be formed on this barrier material 403. In some embodiments, the second conductive material 405 may be, for example, aluminum, tungsten, copper, or a combination thereof. In some embodiments, the second conductive material layer 405 may be formed by, for example, chemical vapor deposition, physical vapor deposition, electroplating, electroless plating, or other suitable deposition processes.

[0158] See Figure 8 A second mask layer 503 can be formed on this second conductive material 405. The second mask layer 503 may include the pattern of the top conductive layer 107. In some embodiments, the second mask layer 503 may be a photoresist layer.

[0159] See Figure 9An etching process can be performed using a second mask layer 503 as a mask to remove portions of the barrier material 403 and the second conductive material 405. After the etching process, the remaining portion of the barrier material 403 may be referred to as the barrier layer 105. The remaining portion of the second conductive material 405 may be referred to as the top conductive layer 107. In some embodiments, the etching process may be a multi-stage etching process. For example, the etching process may be a two-stage etching process. In some embodiments, during the etching process, the ratio of the etching rate of the second conductive material 405 to the etching rate of the second mask layer 503 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the etching process, the ratio of the etching rate of the second conductive material 405 to the etching rate of the barrier material 403 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. In some embodiments, during the first etching process, the ratio of the etching rate of the barrier material 403 to the etching rate of the first dielectric layer 103 may be between about 100:1 and about 1.05:1, between about 15:1 and about 2:1, or between about 10:1 and about 2:1. After the etching process, the second mask layer 503 may be removed.

[0160] See Figure 9 The width W3 of the barrier layer 105 or the top conductive layer 107 can be greater than the width W1 of the conductive recess 201 or greater than the width W2 of the conductive fill layer 203.

[0161] See Figure 10 A second dielectric layer 109 can be formed on the first dielectric layer 103, and a top conductive layer 107 can be formed. A planarization process, such as chemical mechanical polishing, can be performed until the top surface of the top conductive layer 107 is exposed to remove excess material and provide a substantially flat surface for subsequent process steps. In some embodiments, the second dielectric layer 109 can be formed of materials such as silicon dioxide, undoped silicate glass, fluorosilicate glass, borophosphosilicate glass, spin-coated low-dielectric-constant dielectric layer, chemical vapor deposition low-dielectric-constant dielectric layer, or combinations thereof. In some embodiments, the second dielectric layer 109 can be formed by a deposition process, including, for example, chemical vapor deposition, plasma-enhanced chemical vapor deposition, evaporation, spin coating, or other suitable deposition processes. In some embodiments, the second dielectric layer 109 and the first dielectric layer 103 can be formed of the same material. In some embodiments, the second dielectric layer 109 and the first dielectric layer 103 can be formed of different materials.

[0162] The conductive filling layer 203 reduces the resistance of the conductive structure 200, thereby improving the performance of the semiconductor device 1A.

[0163] Figure 11 and Figure 12 This is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor element 1B according to another embodiment of this disclosure.

[0164] See Figure 11 It can utilize similar Figures 2 to 6 The intermediate semiconductor device is manufactured using the process shown, and its description will not be repeated here. It should be noted that during the manufacturing process of semiconductor device 1B, the conductive filling layer 203 is not planarized. Therefore, the top surface 203TS of the conductive filling layer 203 protrudes relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101. This can be achieved through a process similar to... Figure 8 The process shown directly forms the barrier material 403 on the conductive fill layer 203 and the first dielectric layer 103, which will not be described again here. Since no planarization process is performed on the conductive fill layer 203, a portion of the barrier material 403 formed on the conductive fill layer 203 may protrude relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101.

[0165] See Figure 11 It can utilize similar Figure 8 The process shown forms the second conductive material 405 on top of the barrier material 403, and will not be described again here. A planarization process, such as chemical mechanical polishing, can be performed on the second conductive material layer 405 to remove excess material and provide a substantially flat surface for subsequent process steps. Similar to... Figure 8 The process shown forms a second mask layer 503 on the second conductive material layer 405, which will not be described again here.

[0166] See Figure 12 It can utilize similar Figure 9 The process shown forms the barrier layer 105 and the top conductive layer 107, which will not be described again here. A similar process can be used... Figure 10 The process shown forms the second dielectric layer 109, which will not be described again here.

[0167] See Figure 12The top surface 203TS of the conductive fill layer 203 may protrude relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101. The barrier layer 105 may include a protruding portion 105CV and two flat portions 105FP. The protruding portion 105CV may be compliantly formed on the top surface 203TS of the conductive fill layer 203. The two flat portions 105FP may extend from both ends of the protruding portion 105CV and may be compliantly formed on the top surface 103TS of the first dielectric layer 103.

[0168] Figures 13 to 16 This is a cross-sectional view illustrating a part of the manufacturing process of a semiconductor device 1C according to another embodiment of the present disclosure.

[0169] See Figure 13 It can utilize similar Figures 2 to 6 The process shown manufactures intermediate semiconductor devices, and its description will not be repeated here. A planarization process can be performed until the top surface 103TS of the first dielectric layer 103 is exposed. After the planarization process, the recess 201R can remain in the conductive recess 201, and a first portion 201-1 of the top surface 201TS of the conductive recess 201 can be formed around the recess 201R and adjacent to the first dielectric layer 103. The first portion 201-1 of the top surface 201TS of the conductive recess 201 can have a protruding surface relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101. In other words, the first portion 201-1 of the top surface 201TS of the conductive recess 201 can protrude from the top surface 103TS of the first dielectric layer 103. The surface of the recess 201R can correspond to a second portion 201-3 of the top surface 201TS of the conductive recess 201. The second portion 201-3 of the top surface 201TS of the conductive recess 201 can extend from the first portion 201-1 of the top surface 201TS of the conductive recess 201 and has a recessed shape relative to the top surface 103TS of the conductive recess 201 (or relative to the substrate 101).

[0170] See Figure 14 It can utilize similar Figure 6 The process shown forms a conductive filling layer 203 on the conductive recess 201, which will not be described again here. At this stage, the top surface 203TS of the conductive filling layer 203 can protrude from the top surface 103TS of the first dielectric layer 103. In other words, the top surface 203TS of the conductive filling layer 203 can protrude relative to the top surface 103TS of the first dielectric layer 103 (or relative to the substrate 101).

[0171] See Figure 15A planarization process, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent processing steps. After the planarization process, the top surface 203TS of the conductive filler layer 203 may be substantially coplanar with the top surface 103TS of the first dielectric layer 103. In some embodiments, the top surface 201TS of the conductive recess 201 may be substantially coplanar with the top surface 203TS of the conductive filler layer 203. In some embodiments, the width W1 of the conductive recess 201 may be greater than the width W2 of the conductive filler layer 203.

[0172] See Figure 16 It can utilize similar Figures 8 to 10 The process shown forms a barrier layer 105, a top conductive layer 107, and a second dielectric layer 109, which will not be described again here.

[0173] Figure 17 and Figure 18 This is a cross-sectional view illustrating a portion of the manufacturing process of a semiconductor element 1D according to another embodiment of the present disclosure.

[0174] See Figure 17 It can utilize similar Figure 13 and Figure 14 The process shown is used to fabricate intermediate semiconductor devices, and will not be described again here. It should be noted that a planarization process is not performed on the conductive filling layer 203. Therefore, the top surface 203TS of the conductive filling layer 203 protrudes relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101. A similar process can be used... Figure 8 The process shown directly forms this barrier material 403 on the conductive fill layer 203 and the first dielectric layer 103, and will not be described again here. Since no planarization process is performed on the conductive fill layer 203, a portion of this barrier material 403 formed on the conductive fill layer 203 may protrude relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101.

[0175] See Figure 17 It can utilize similar Figure 8 The process shown forms the second conductive material 405 on top of the barrier material 403, and will not be described again here. Planarization processes, such as chemical mechanical polishing, can be performed to remove excess material and provide a substantially flat surface for subsequent process steps. Similar to... Figure 8 The process shown forms a second mask layer 503 on the second conductive material 405, which will not be described again here.

[0176] See Figure 18 It can utilize similar Figure 9The process shown forms the barrier layer 105 and the top conductive layer 107, which will not be described again here. A similar process can be used... Figure 10 The process shown forms the second dielectric layer 109, which will not be described again here.

[0177] See Figure 18 The barrier layer 105 may include a protruding portion 105CV and two flat portions 105FP. The protruding portion 105CV may be compliantly formed on the top surface 203TS of the conductive fill layer 203. The conductive fill layer 203 may protrude relative to the top surface 103TS of the first dielectric layer 103 or relative to the substrate 101. The two flat portions 105FP may extend from both ends of the protruding portion 105CV and may be compliantly formed on the top surface 103TS of the first dielectric layer 103. In some embodiments, the width W3 of the barrier layer 105 or the top conductive layer 107 may be greater than the width W1 of the conductive recess 201 or greater than the width W2 of the conductive fill layer 203. In some embodiments, the width W1 of the conductive recess 201 and the width W2 of the conductive fill layer 203 may be substantially the same.

[0178] Figures 19 to 23 This is a cross-sectional view illustrating semiconductor elements 1E, 1F, 1G, 1H and 1I according to some embodiments of the present disclosure.

[0179] See Figure 19 Semiconductor element 1E can have the same characteristics as... Figure 10 The structure shown is similar to the one described. Figure 19 The components in and in Figure 10 Identical or similar elements are marked with similar element symbols, and repeated descriptions are omitted.

[0180] See Figure 19 Semiconductor device 1E may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed in substrate 101. In some embodiments, the bottom conductive layer 111 may be an impurity region configured as a source / drain. In some embodiments, the bottom conductive layer 111 may be a metal wire, a conductive via, a conductive plug, or a conductive pad. A conductive structure 200 is disposed on the bottom conductive layer 111. In some embodiments, the bottom conductive layer 111 may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0181] See Figure 20 Semiconductor element 1F can have similar characteristics to Figure 12 The structure shown. In Figure 20 The components in and in Figure 12Identical or similar elements are marked with similar element symbols, and repeated descriptions are omitted.

[0182] See Figure 20 The semiconductor device 1F may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed in the substrate 101. In some embodiments, the bottom conductive layer 111 may be an impurity region configured as a source / drain. In some embodiments, the bottom conductive layer 111 may be a metal wire, a conductive via, a conductive plug, or a conductive pad. A conductive structure 200 is disposed on the bottom conductive layer 111. In some embodiments, the bottom conductive layer 111 may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0183] See Figure 21 Semiconductor element 1G can have similar characteristics to Figure 16 The structure shown. In Figure 21 The components in and in Figure 16 Identical or similar elements are marked with similar element symbols, and repeated descriptions are omitted.

[0184] See Figure 21 The semiconductor device 1G may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed in the substrate 101. In some embodiments, the bottom conductive layer 111 may be an impurity region configured as a source / drain. In some embodiments, the bottom conductive layer 111 may be a metal wire, a conductive via, a conductive plug, or a conductive pad. A conductive structure 200 is disposed on the bottom conductive layer 111. In some embodiments, the bottom conductive layer 111 may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0185] See Figure 22 Semiconductor element 1H can have similar characteristics to Figure 18 The structure shown. In Figure 22 The components in and in Figure 18 Identical or similar elements are marked with similar element symbols, and repeated descriptions are omitted.

[0186] See Figure 22The semiconductor device 1H may include a bottom conductive layer 111. The bottom conductive layer 111 may be disposed in the substrate 101. In some embodiments, the bottom conductive layer 111 may be an impurity region configured as a source / drain. In some embodiments, the bottom conductive layer 111 may be a metal wire, a conductive via, a conductive plug, or a conductive pad. A conductive structure 200 is disposed on the bottom conductive layer 111. In some embodiments, the bottom conductive layer 111 may be formed of materials such as tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, or magnesium tantalum carbide), metal nitrides (e.g., titanium nitride), transition metal aluminum nitrides, or combinations thereof.

[0187] See Figure 23 Semiconductor element 1I can have similar characteristics to Figure 10 The structure shown. In Figure 23 The components in and in Figure 10 Identical or similar elements are marked with similar element symbols, and redundant descriptions are omitted. In semiconductor element 1I, the sidewalls 200SW of the conductive structure 200 may be tapered.

[0188] See Figure 24 Semiconductor element 1J can have similar characteristics to Figure 10 The structure of semiconductor device 1A is shown. Figure 24 The components in and in Figure 10 Identical or similar elements are marked with similar element symbols, and repeated descriptions are omitted.

[0189] See Figure 24 The semiconductor device 1J may include an epitaxial layer 113, which is disposed on a substrate 101 and sandwiched between the first dielectric layer 103 and the substrate 101. The epitaxial layer 113 may include conductive regions serving as source / drain regions of the semiconductor device 1J. In some embodiments, the epitaxial layer 113 includes silicon (Si). In some embodiments, the epitaxial layer 113 may be formed by an epitaxial growth method, which may include metal-organic chemical vapor deposition (MOCVD), vapor-phase epitaxy (VPE), molecular-beam epitaxy (MPE), liquid-phase epitaxy (LPE), or other suitable processes.

[0190] See Figure 24The conductive structure 200 of the semiconductor element 1J may further include a barrier layer 205 disposed on the sidewalls 103S1 and 103S2 of the second opening 103O' and the bottom surface 103B, wherein the second opening 103O' and Figure 10 Similar to the first opening 103O, the difference is that the second opening 103O' can penetrate the first dielectric layer 103 and the epitaxial layer 113, and can extend into the substrate 101. In other words, the conductive structure 200 includes a conductive filling layer 203, a conductive recessed layer 201, and a barrier layer 205 surrounding the conductive filling layer 203 and the conductive recessed layer 201. In some embodiments, the barrier layer 205 includes titanium (Ti), titanium nitride (TiN), or a combination thereof. In some embodiments, the conductive filling layer 203 and the conductive recessed layer 201 are separated from the first dielectric layer 103, the epitaxial layer 113, and the substrate 101 by the barrier layer 205.

[0191] It should be noted that the barrier layer 205 has a first thickness T1 on the sidewalls 201S and 203S of the conductive recessed layer 201 and the conductive filling layer 203, and the barrier layer 205 has a second thickness T2 below the bottom surface 201B of the conductive recessed layer 201. In some embodiments, the barrier layer 205 is formed through an anisotropic deposition process, such that the first thickness T1 is less than the second thickness T2. In some embodiments, this anisotropic deposition process includes physical vapor deposition (PCVD).

[0192] See Figure 25 According to some embodiments of this disclosure, the semiconductor device 1K may include a contact plug 204, which includes a conductive structure 200, a barrier layer 105, and a top conductive layer 107. The conductive structure 200, the barrier layer 105, and the top conductive layer 107 are connected to... Figure 10 The same or similar items shown will not be described again here.

[0193] See Figure 25The semiconductor element 1K can be a unit cell in a memory element. In some embodiments, the memory element is a dynamic random-access memory (DRAM) element. In such embodiments, each unit cell (i.e., semiconductor element 1K) may include two field-effect transistors (FETs) having the same conductivity type and sharing a common source / drain node. These FETs include two gate structures 102, as described below. The gate structures 102 are embedded in a dielectric layer stack (e.g., including dielectric layers 114 and 116) and stand independently on the active region AA. The active region AA of the semiconductor substrate 100 may be defined by an isolation structure 202. In some embodiments, the isolation structure 202 is a trench isolation structure extending from the top surface of the semiconductor substrate 100 into the semiconductor substrate 100 and laterally surrounding the active region AA. The isolation structure 202 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, etc., or combinations thereof.

[0194] Gate structure 102 includes a gate electrode 104 and a gate dielectric layer 106. The gate electrode 104 is disposed on an active region AA spanning a shallow region of the semiconductor substrate 100. The gate dielectric layer 106 is located between the gate electrode 104 and the semiconductor substrate 100, such that the gate electrode 104 is capacitively coupled to the active region AA through the gate dielectric layer 106. Although not shown, the gate electrode 104 may be formed in a line pattern and extend along the bottom surface of the upper gate electrode 104 with the gate dielectric layer 106. The gate electrode 104 is formed of a conductive material, while the gate dielectric layer 106 is formed of a dielectric material. In some embodiments, the gate electrode 104 is formed of polysilicon, and the gate dielectric layer 106 is formed of silicon oxide. In other embodiments, the gate electrode 104 is formed of a metallic material, and the gate dielectric layer 106 is formed of a high-dielectric-constant dielectric material (e.g., a dielectric material having a dielectric constant greater than 3.9 or 7). In some embodiments, the metallic material may include tungsten, titanium, titanium nitride, aluminum, or combinations thereof, and the high dielectric constant dielectric material may include hafnium oxide, hafnium aluminate, hafnium silicate, tantalum oxide, aluminum oxide, zirconium oxide, similar materials, or combinations thereof.

[0195] In some embodiments, the gate structure 102 further includes a hard mask 108. The hard mask 108 is disposed on the gate electrode 104 (also referred to as the gate). In some embodiments, the hard mask 108 serves as a shadow mask during one or more etching processes used to form the gate electrode 104 and the gate dielectric layer 106. In such embodiments, the hard mask 108 extends along the top surface of the gate electrode 104, and the sidewalls SS of the hard mask 108 may be substantially coplanar with the sidewalls of the gate electrode 104 and the gate dielectric layer 106. For use as a shadow mask, the hard mask 108 may be formed of a material having sufficient etch selectivity relative to the gate electrode 104 and the gate dielectric layer 106. Alternatively, the hard mask 108 may be at least partially consumed during the etching process used to form the gate dielectric layer 106, and the material of the hard mask 108 may have low or no etch selectivity relative to the gate dielectric layer 106. In some embodiments, the hard mask 108 is formed of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, similar materials, or combinations thereof.

[0196] The gate structure 102 also includes a plurality of sidewall spacers 110 covering the sidewalls of the gate electrode 104. In embodiments where the gate electrode 104 is formed as a line, each sidewall spacer 110 may include portions located on opposite sides of the gate electrode 104. Furthermore, in embodiments where the gate electrode 104 is covered by a hard mask 108, the sidewall spacers 110 may also cover the sidewalls of the hard mask 108. Additionally, in some embodiments, the sidewall spacers 110 also cover the sidewalls of the gate dielectric layer 106 located beneath the gate electrode 104.

[0197] The sidewall spacers 110 may include a first sidewall spacer 110a and a second sidewall spacer 110b. The sidewall spacer 110a is located between the second sidewall spacer 110b and a stacked structure including a gate electrode 104 (and a hard mask 108 and / or a gate dielectric layer 106). An air gap AG is sealed between the first sidewall spacer 110a and the second sidewall spacer 110b. Specifically, the sidewall of the first sidewall spacer 110a facing away from the gate electrode 104 defines one side boundary 1102 of the air gap AG, and the sidewall of the second sidewall spacer 110b facing the gate electrode 104 defines the other side boundary 1103 of the air gap AG. The top surface of the portion of the semiconductor substrate 100 located between the first sidewall spacer 110a and the second sidewall spacer 110b may define the bottom boundary of the air gap AG. Additionally, the tip E3 of the air gap AG may be substantially aligned with the tips E1 and E2 of the first sidewall spacer 110a and the second sidewall spacer 110b. Furthermore, in some embodiments, the tip of the air gap AG is defined by a dielectric layer (e.g., dielectric layer 116, which will be described further) located above the gate structure 102. In embodiments where each sidewall spacer 110a / 110b has portions located on opposite sides of the gate electrode 104, the air gap AG may also have portions located on opposite sides of the gate electrode 104.

[0198] The air gap AG, in terms of structure and shape, is similar to one of the sidewall spacers (e.g., the first sidewall spacer 110a or the second sidewall spacer 110b) and may be referred to as an air sidewall spacer or an air gate spacer. In some embodiments, the top portion of each sidewall spacer (i.e., the first sidewall spacer 110a or the second sidewall spacer 110b) tapers towards its tip. In other words, the lateral width of each sidewall spacer (i.e., the first sidewall spacer 110a or the second sidewall spacer 110b) may decrease towards its tip. In such embodiments, the top portion AGT of the air gap AG may also taper towards its tip, and the lateral width of the air gap AG may decrease towards its tip.

[0199] The first sidewall spacer 110a and the second sidewall spacer 110b may each be formed of an insulating material. In some embodiments, the insulating material is a carbon-containing insulating material. The carbon-containing insulating material may include high-density carbon (HDC), silicon carbide (SiC), silicon carbonitride (SiCN), or similar materials. In some embodiments, the first sidewall spacer 110a may be formed of HDC or SiC, while the second sidewall spacer 110b may be formed of HDC, SiC, or SiCN.

[0200] In some embodiments, a plurality of dielectric layers are stacked on a semiconductor substrate 100. In some embodiments, the dielectric layers may include a dielectric layer 114 laterally surrounding a gate structure 102 and a dielectric layer 116 situated on the dielectric layer 114. The top surface of the dielectric layer 114 may be substantially aligned with the top tip of the sidewall spacers 110 of the gate structure 102. Accordingly, the top surface of the dielectric layer 114 may also be substantially aligned with the top tip of the air gap AG sealed between adjacent sidewall spacers 110 (e.g., first sidewall spacers 110a and second sidewall spacers 110b). In embodiments where the gate structure 102 includes a hard mask 108, the top surface of the dielectric layer 116 may be substantially aligned with the top surface 108TS of the hard mask 108. Additionally, the dielectric layer 116 situated on the dielectric layer 114 covers the gate structure 102, and the dielectric layer 116 may contact the top tip of the sidewall spacers 110. In embodiments where the top portion of each sidewall spacer 110 tapers towards its tip, the air gap AG defined between adjacent sidewall spacers 110 may also have a tapering top portion. In this way, the tip of the air gap AG is quite narrow, and the dielectric layer 116 may not be able to enter the air gap AG through its narrow tip when forming the dielectric layer 116. Therefore, the narrow tip of the air gap AG can be sealed by the dielectric layer 116. Dielectric layers 114 and 116 may be formed of dielectric materials, respectively. In some embodiments, the dielectric material may include silicon oxide, silicon nitride, silicon carbonitride, silicon boron nitride (SiBN), silicon oxycarbonitride (SiOCN), silicon oxynitride, silicon carbonitride, silicon carbide, similar materials, or combinations thereof.

[0201] As described above, the air gap AG is sealed between adjacent sidewall spacers 110 covering the opposing sidewalls of the gate electrode 104. The dielectric constant of air is approximately the same as that of a vacuum, which is likely the lowest dielectric constant for a material. Therefore, the gate electrode 104 is adjacent to any possible conductive components (e.g., contact plugs similar to the contact plug 204 described below, see...) Figure 25 The parasitic capacitance between the gate electrode 104 and adjacent electronic components 110 can be reduced due to the air gap AG sealed between them. Therefore, the resistive-capacitive (RC) delay of signal transmission through the gate electrode 104 and adjacent electronic components can be effectively minimized.

[0202] Three source / drain structures 112 can be disposed in the active region AA. Gate structures 102 are respectively located between adjacent source / drain structures 112 of the three source / drain structures 112. One of the source / drain structures 112 is located between the gate structures 102 and serves as the common source / drain node of the FET. In some embodiments, the source / drain structure 112 serving as the common source / drain node of the FET can be coupled to a bit line, as will be further described later. The other two source / drain structures 112 are located on opposite sides of the gate structure 102 and can be coupled to a storage capacitor, as will also be further described later.

[0203] Contact plugs 204 extend through dielectric layers 114 and 116 respectively to one of the source / drain structures 112 to establish electrical contact with the source / drain structure 112. The contact plugs 204, positioned on the source / drain structures 112 between the gate structures 102, can be configured to connect such source / drain structures 112 to bit lines (described further below) and can be referred to as bit line contacts. These contact plugs 204 (i.e., bit line contacts) are laterally separated from the gate electrode 104 of the gate structure 102 by sidewall spacers 110 of the gate structure 102. An air gap AG with an ultra-low dielectric constant is sealed between adjacent sidewall spacers 110, thereby reducing the parasitic capacitance between the gate electrode 104 and the contact plugs 204. Therefore, the RC delay of signal transmission through the gate electrode 104 and the contact plugs 204 (i.e., bit line contacts) can be effectively minimized. Additionally, two other source / drain structures 112 located on opposite sides of the gate structure 102 can be connected to a storage capacitor (not shown) via contact plugs 204 located on these source / drain structures 112, and such contact plugs 204 can be referred to as capacitive contacts. Similar to bit line contacts, each capacitive contact is laterally separated from the gate electrode 104 of one of the gate structures 102 by sidewall spacers 110 of the gate structure 102, and can effectively minimize the RC delay of signal transmission through the gate electrode 104 and the contact plugs 204 (i.e., capacitive contacts) due to the air gap AG sealed between adjacent sidewall spacers 110. The contact plugs 204 are formed of a conductive material. In some embodiments, the conductive material may include tungsten, titanium, titanium nitride, similar materials, or combinations thereof.

[0204] Conductive patterns 206 may be located on one of the contact plugs 204. Each conductive pattern 206 is electrically connected to the source / drain structure 112 below it via the contact plug 204 located therebetween. In some embodiments, the conductive pattern 206 located on and electrically connected to the source / drain structure 112 between the gate structures 102 may be a bit line. Although not shown, this conductive pattern 206 may be formed as a line. Two other conductive patterns 206 located on opposite sides of the gate structures 102, located on the source / drain structures 112 and electrically connected to these two source / drain structures 112, may be bonding pads, and storage capacitors (not shown) may be disposed thereon. The area occupied by each of these conductive patterns 206 (i.e., bonding pads) may be larger than the area occupied by the contact plug 204 below it, thus effectively minimizing the coverage problem of the storage capacitor. The conductive patterns 206 are formed of a conductive material. In some embodiments, the conductive material may include copper, titanium, titanium nitride, similar materials, or combinations thereof. In some embodiments, the conductive pattern 206 is formed in an additional dielectric layer 208. In such embodiments, the conductive pattern 206 may be laterally surrounded by the additional dielectric layer 208. This additional dielectric layer 208 may be formed of the dielectric material used to form dielectric layers 114 and 116. Alternatively, the dielectric material used to form the additional dielectric layer 208 may be different from the dielectric material used to form dielectric layers 114 and 116. The dielectric material used to form the additional dielectric layer 208 may include, for example, silicon oxide, silicon nitride, silicon carbonitride, silicon boron nitride (SiBN), silicon oxycarbonitride (SiOCN), silicon oxynitride, silicon carbonitride, silicon carbide, similar materials, or combinations thereof.

[0205] One aspect of this disclosure is to provide a semiconductor device, comprising: a substrate; a conductive structure including: a conductive recess layer disposed on the substrate and including a top surface having a V-shaped cross-sectional profile; a conductive filling layer disposed on the conductive recess layer; a first barrier layer covering the sidewalls of the conductive recess layer and the conductive filling layer, and covering a bottom surface of the conductive recess layer; and a top conductive layer disposed on the conductive structure. The conductive structure is disposed in the substrate and protrudes from the substrate. One surface of the conductive filling layer is recessed relative to the substrate. The conductive filling layer comprises germanium or silicon-germanium.

[0206] Another aspect of this disclosure is to provide a semiconductor device comprising: a stacked structure disposed on a semiconductor substrate; a first sidewall spacer and a second sidewall spacer covering one sidewall of the stacked structure; and a contact plug disposed between a pair of the stacked structures. An air gap is sealed between the first sidewall spacer and the second sidewall spacer. The top edges of the first sidewall spacer, the air gap, and the second sidewall spacer are coplanar with the top surface of the stack. A top portion of the air gap gradually tapers toward the top edge of the air gap.

[0207] Another aspect of this disclosure is to provide a method for manufacturing a semiconductor device, comprising: providing a substrate; forming an epitaxial layer on the substrate; forming a first dielectric layer on the epitaxial layer; forming a first opening in the dielectric layer, the epitaxial layer, and the substrate; forming a conductive recess in the first opening; forming a conductive filling layer on the conductive recess and in the first opening; and forming a top conductive layer on the conductive filling layer. A top surface of the conductive recess has a V-shaped cross-sectional profile. The conductive recess and the conductive filling layer together form a conductive structure; the conductive filling layer comprises germanium or silicon-germanium.

[0208] Due to the design of the semiconductor device disclosed herein, the resistance of the conductive structure can be reduced by employing a conductive filling layer containing germanium. This, in turn, improves the performance of the semiconductor device.

[0209] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0210] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of protection of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A conductive structure is disposed in the substrate and protrudes from the substrate, comprising: A conductive recess is disposed on the substrate and includes a top surface having a V-shaped cross-sectional profile. A conductive filler layer is disposed on the conductive recessed layer, wherein one surface of the conductive filler layer is recessed relative to the substrate; and A first barrier layer covers the sidewalls of the conductive recess and the conductive filler layer, and covers a bottom surface of the conductive recess; and A top conductive layer is disposed on the conductive structure. The conductive filling layer includes germanium or silicon germanium.

2. The semiconductor device of claim 1, wherein the conductive recess comprises substantially oxygen-free and nitrogen-free silicon and / or germanium.

3. The semiconductor device of claim 2, further comprising: A first dielectric layer is disposed on the substrate, wherein the conductive structure penetrates the first dielectric layer.

4. The semiconductor device of claim 3, further comprising: An epitaxial layer is disposed between the substrate and the first dielectric layer.

5. The semiconductor device of claim 4, further comprising: A second barrier layer is disposed between the conductive structure and the top conductive layer.

6. The semiconductor device of claim 5, wherein the first dielectric layer comprises a dielectric material, wherein the dielectric material contains oxygen atoms and / or nitrogen atoms.

7. The semiconductor device of claim 6, wherein the second barrier layer comprises titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof.

8. The semiconductor device of claim 7, wherein the top conductive layer comprises aluminum, tungsten, copper, or a combination thereof.

9. The semiconductor device of claim 8, wherein the width of the conductive recess is substantially equal to the width of the conductive fill layer.

10. The semiconductor device of claim 9, wherein a top surface of the conductive filling layer and a top surface of the first dielectric layer are substantially coplanar.

11. The semiconductor device of claim 10, wherein the conductive filling layer and the conductive recess layer are separated from the first dielectric layer, the epitaxial layer and the substrate by the first barrier layer.

12. The semiconductor device of claim 1, wherein the first barrier layer comprises titanium (Ti), titanium nitride (TiN), or a combination thereof.

13. The semiconductor device of claim 12, wherein the thickness of the first barrier layer on the sidewalls of the conductive recess and the conductive fill layer is less than the thickness of the first barrier layer below the bottom surface of the conductive recess.

14. The semiconductor device of claim 13, wherein the first barrier layer is formed by an anisotropic deposition process.

15. The semiconductor device of claim 14, further comprising: A first dielectric layer is disposed on the substrate; as well as A second dielectric layer is disposed on the first dielectric layer and covers the top conductive layer.

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