Semiconductor device, circuit board assembly, electric control box and electrical equipment

Abstract

The invention discloses a semiconductor device, a circuit board assembly, an electric control box and electrical equipment. The semiconductor device comprises a plastic package body; a substrate; the driving side pin frame is used for setting one transverse side of the first inversion low-side driving chip as a first inversion low-side driving chip boundary, one transverse side of the first inversion high-side driving chip as a first inversion high-side driving chip boundary and one transverse side of the second inversion low-side driving chip as a second inversion low-side driving chip boundary; and the transverse side of the second inversion high-side driving chip is the boundary of the second inversion high-side driving chip. Therefore, the distance between the boundary of the first inversion high-side driving chip and the boundary of the first inversion low-side driving chip in the transverse direction is smaller than the distance between the boundary of the second inversion high-side driving chip and the boundary of the second inversion low-side driving chip in the transverse direction, so that the area of the substrate occupied by the first inversion power bonding pad part can be reduced; the area, occupied by the second inverter power bonding pad part, of the substrate is increased, and the heat dissipation performance of the second inverter power bonding pad part is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, circuit board assembly, electrical control box, and electrical equipment. Background Technology

[0002] Electronic control boards for devices such as air conditioners and washing machines can be equipped with semiconductor devices such as intelligent power modules. However, existing intelligent power modules (IPMs) have limited functionality, only having an inverter function. Furthermore, the inverter power pads in some intelligent power modules have a small area on the substrate. Since the inverter current carrying capacity of the inverter area is large, it may lead to insufficient heat dissipation in the inverter area. This can cause the devices in the inverter area and its surrounding area to malfunction due to excessive temperature, resulting in the air conditioner electronic control board failing to operate normally. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a semiconductor device that can increase the area of ​​the second inverter power pad portion and improve the heat dissipation performance of the second inverter power pad portion.

[0004] The present invention further proposes a circuit board assembly.

[0005] The present invention further proposes an electrical control box.

[0006] The present invention further proposes an electrical device.

[0007] According to a semiconductor device of the present invention, the semiconductor device has a lateral direction, a longitudinal direction, and a vertical direction, the lateral direction, the longitudinal direction, and the vertical direction being perpendicular to each other. The semiconductor device includes: a molding compound; a substrate, the substrate being at least partially disposed within the molding compound, the substrate including a first inverter power pad portion, a second inverter power pad portion, and a PFC (Power Factor Correction) power pad portion spaced apart in the lateral direction, the first inverter power pad portion having a first inverter low-side power chip and a first inverter high-side power chip spaced apart in the lateral direction, the second inverter power pad portion having a second inverter low-side power chip and a second inverter high-side power chip spaced apart in the lateral direction; and a drive-side pin frame, the drive-side... A pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame extends at least partially from the molding compound. The drive-side pin frame includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart laterally. The first inverter drive pin frame corresponds at least partially to the first inverter power pad portion in the longitudinal direction. The second inverter drive pin frame corresponds at least partially to the second inverter power pad portion in the longitudinal direction. The PFC drive pin frame corresponds at least partially to the PFC (Power Factor Correction) power pad portion in the longitudinal direction. The rack is equipped with a first inverter high-side driver chip and a first inverter low-side driver chip spaced apart from each other. The first inverter high-side driver chip is electrically connected to the first inverter high-side power chip, and the first inverter low-side driver chip is electrically connected to the first inverter low-side power chip. The second inverter drive pin frame is equipped with a second inverter high-side driver chip and a second inverter low-side driver chip spaced apart from each other. The second inverter high-side driver chip is electrically connected to the second inverter high-side power chip, and the second inverter low-side driver chip is electrically connected to the second inverter low-side power chip. The side of the first inverter low-side driver chip that is laterally adjacent to the first inverter high-side driver chip is defined as the boundary of the first inverter low-side driver chip. The side of the first inverter high-side driver chip that is laterally adjacent to the first inverter low-side driver chip is defined as the boundary of the first inverter high-side driver chip, and the lateral distance between the boundary of the first inverter low-side driver chip and the boundary of the first inverter high-side driver chip is L1. The side of the second inverter low-side driver chip that is laterally away from the second inverter high-side driver chip is defined as the boundary of the second inverter low-side driver chip, and the side of the second inverter high-side driver chip that is laterally adjacent to the second inverter low-side driver chip is defined as the boundary of the second inverter high-side driver chip, and the lateral distance between the boundary of the second inverter low-side driver chip and the boundary of the second inverter high-side driver chip is L2. L1 and L2 satisfy the relationship: L1 < L2.

[0008] The specific advantages or beneficial effects of the above scheme are as follows: By making the lateral distance between the boundary of the first inverter high-side drive chip and the boundary of the first inverter low-side drive chip smaller than the lateral distance between the boundary of the second inverter high-side drive chip and the boundary of the second inverter low-side drive chip, the area of ​​the substrate occupied by the first inverter power pad portion can be reduced, the area of ​​the substrate occupied by the second inverter power pad portion can be increased, and the heat dissipation performance of the second inverter power pad portion can be improved.

[0009] In some examples of the present invention, there are three of each of the first inverter high-side power chip and the first inverter low-side power chip. The three first inverter low-side power chips are respectively a first inverter low-side power first chip, a first inverter low-side power second chip, and a first inverter low-side power third chip. Similarly, there are three first inverter high-side power chips, each being a first inverter low-side power first chip, a first inverter low-side power second chip, and a first inverter low-side power third chip. These chips are arranged sequentially and alternately in the horizontal direction. Compared to the first inverter low-side power chip, the first inverter high-side power chip is more horizontally adjacent to the second inverter power pad portion. There is also one of each of the first inverter high-side drive chip and the first inverter low-side drive chip. These chips are arranged sequentially and alternately in the horizontal direction. Compared to the first inverter low-side drive chip, the first inverter high-side drive chip is more horizontally adjacent to the second inverter power pad portion. The moving chip is laterally closer to the second inverter drive pin frame; a plane perpendicular to the vertical direction is set as the first projection plane, and the longitudinal extension region of the orthographic projection of the first inverter low-side drive chip on the first projection plane is laterally spaced between the orthographic projections of the first inverter low-side power first chip and the first inverter low-side power third chip on the first projection plane, and the longitudinal extension region of the orthographic projection of the first inverter low-side drive chip on the first projection plane at least partially overlaps with the orthographic projection of the first inverter low-side power second chip on the first projection plane; the longitudinal extension region of the orthographic projection of the first inverter high-side drive chip on the first projection plane is spaced apart from the side of the orthographic projection of the first inverter low-side power first chip on the first projection plane that is laterally away from the first inverter low-side drive chip, and the longitudinal extension region of the orthographic projection of the first inverter high-side drive chip on the first projection plane at least partially overlaps with the orthographic projections of the first inverter low-side power second chip and / or the first inverter low-side power third chip on the first projection plane.

[0010] The specific advantages or beneficial effects of the above scheme are as follows: it can optimize the structural layout of the semiconductor device, and make the wire connections between the first inverter low-side drive chip and the first inverter low-side power chip, as well as between the first inverter high-side drive chip and the first inverter high-side power chip, suitable for the semiconductor device manufacturing process and meet the reliability requirements of the semiconductor device.

[0011] In some embodiments of the present invention, the first inverter drive pin frame includes a first inverter drive chip ground pin, which protrudes at least partially toward the side longitudinally away from the substrate to form a first inverter low-side drive chip pad and a first inverter high-side drive chip pad spaced apart in the lateral direction. The first inverter low-side drive chip and the first inverter high-side drive chip pad are respectively disposed on the first inverter low-side drive chip pad and the first inverter high-side drive chip pad. The first inverter low-side drive chip pad and the first inverter high-side drive chip pad are respectively spaced apart on both sides of the lateral center of the first inverter drive pin frame. The center of the first inverter low-side drive chip is offset in the lateral direction relative to the center of the first inverter low-side drive chip pad toward the side closer to the first inverter high-side drive chip, and the center of the first inverter high-side drive chip is offset in the lateral direction relative to the center of the first inverter high-side drive chip pad toward the side away from the first inverter low-side drive chip.

[0012] The specific advantages or beneficial effects of the above scheme are as follows: it can optimize the structural layout of the semiconductor device, and make the wire connections between the first inverter low-side drive chip and the first inverter low-side power chip, as well as between the first inverter high-side drive chip and the first inverter high-side power chip, suitable for the semiconductor device manufacturing process and meet the reliability requirements of the semiconductor device.

[0013] In some embodiments of the present invention, there are three of each of the second inverter low-side power chip and the second inverter low-side power chip. The three second inverter low-side power chips are respectively a first second inverter low-side power chip, a second second inverter low-side power chip, and a third second inverter low-side power chip. The three second inverter high-side power chips are respectively a first second inverter high-side power chip, a second second inverter high-side power chip, and a third second inverter high-side power chip. These chips are arranged sequentially and spaced apart laterally. Compared to the second inverter low-side power chip, the second inverter high-side power chip is more laterally adjacent to the PFC power pad portion. There is one of each of the second inverter high-side drive chip and the second inverter low-side drive chip. These chips are arranged sequentially and spaced apart laterally. Compared to the second inverter low-side power chip, the second inverter high-side power chip is more laterally adjacent to the PFC power pad portion. The second inverter high-side driver chip is laterally closer to the PFC driver pin frame; the longitudinal extension region of the orthographic projection of the second inverter low-side driver chip on the first projection plane is laterally spaced between the orthographic projections of the second inverter low-side power first chip and the second inverter low-side power third chip on the first projection plane, and the longitudinal extension region of the orthographic projection of the second inverter low-side power second chip on the first projection plane at least partially overlaps with each other; the longitudinal extension region of the orthographic projection of the second inverter high-side driver chip on the first projection plane is spaced apart from the side of the orthographic projection of the second inverter high-side power first chip on the first projection plane that is laterally away from the second inverter low-side driver chip, and the longitudinal extension region of the orthographic projection of the second inverter high-side driver chip on the first projection plane at least partially overlaps with each other.

[0014] The specific advantages or beneficial effects of the above scheme are as follows: it can optimize the structural layout of the semiconductor device, and make the wire connections between the second inverter low-side drive chip and the second inverter low-side power chip, as well as between the second inverter high-side drive chip and the second inverter high-side power chip, suitable for the semiconductor device manufacturing process and meet the reliability requirements of the semiconductor device.

[0015] In some examples of the present invention, the second inverter drive pin frame includes a second inverter drive chip ground pin, which is at least partially protruding toward the side longitudinally away from the substrate to form a second inverter low-side drive chip pad and a second inverter high-side drive chip pad spaced apart in the lateral direction. The second inverter low-side drive chip and the second inverter high-side drive chip pad are respectively disposed on the second inverter low-side drive chip pad and the second inverter high-side drive chip pad. The second inverter low-side drive chip is located in the middle of the second inverter low-side drive chip pad in the lateral direction; or the second inverter low-side drive chip is located to the right of the middle of the second inverter low-side drive chip pad in the lateral direction. The center of the second inverter high-side drive chip is offset in the lateral direction relative to the center of the second inverter high-side drive chip pad toward the side closer to the second inverter low-side drive chip.

[0016] The specific advantages or beneficial effects of the above scheme are as follows: it can optimize the structural layout of the semiconductor device, and make the wire connections between the second inverter low-side drive chip and the second inverter low-side power chip, as well as between the second inverter high-side drive chip and the second inverter high-side power chip, suitable for the semiconductor device manufacturing process and meet the reliability requirements of the semiconductor device.

[0017] In some examples of the present invention, the lateral dimension of the first inverter power pad portion is smaller than the lateral dimension of the second inverter power pad portion.

[0018] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and increase the area of ​​the substrate occupied by the second inverter power pad, which can help dissipate heat in the area of ​​the second inverter power pad.

[0019] In some examples of the present invention, the side of the first inverter low-side driver chip pad that is laterally adjacent to the first inverter high-side driver chip pad is defined as the boundary of the first inverter low-side driver pad. The boundary of the first inverter low-side driver pad extends longitudinally. The side of the first inverter high-side driver chip pad that is laterally adjacent to the first inverter low-side driver chip pad is defined as the boundary of the first inverter high-side driver first pad. The boundary of the first inverter high-side driver first pad extends longitudinally. The lateral distance between the boundary of the first inverter high-side driver first pad and the boundary of the first inverter low-side driver pad is L3. The side of the second inverter low-side driver chip pad that is laterally adjacent to the second inverter high-side driver chip pad is defined as the boundary of the second inverter low-side driver pad. The boundary of the second inverter low-side driver pad extends longitudinally. The side of the second inverter high-side driver chip pad that is laterally adjacent to the second inverter low-side driver chip pad is defined as the boundary of the second inverter high-side driver first pad. The second inverter high-side driver first pad extends longitudinally. The lateral distance between the boundary of the second inverter high-side driver first pad and the boundary of the second inverter low-side driver pad is L4. L3 and L4 satisfy the relationship: L3 < L4.

[0020] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and increase the area of ​​the substrate occupied by the second inverter power pad, which can help dissipate heat in the area of ​​the second inverter power pad.

[0021] In some examples of the present invention, the side of the first inverter drive pin frame that is laterally adjacent to the pad of the first inverter low-side drive chip is defined as the boundary of the first inverter pin frame, and the boundary of the first inverter pin frame extends longitudinally. The side of the first inverter high-side drive chip pad that is laterally away from the pad of the first inverter low-side drive chip is defined as the boundary of the first inverter high-side drive second pad, and the boundary of the first inverter high-side drive second pad extends longitudinally. The lateral distance between the boundary of the first inverter pin frame and the boundary of the first inverter high-side drive second pad is L5. The second inverter drive pin frame boundary is defined as the side of the second inverter low-side drive chip pad that is laterally adjacent to it. The second inverter pin frame boundary extends longitudinally. The side of the second inverter high-side drive chip pad that is laterally away from the second inverter low-side drive chip pad is defined as the second inverter high-side drive second pad boundary. The second inverter high-side drive second pad boundary extends longitudinally. The lateral distance between the second inverter pin frame boundary and the second inverter high-side drive second pad boundary is L6. L5 and L6 satisfy the relationship: L5 > L6.

[0022] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and the second inverter power pad, and increase the area of ​​the substrate occupied by the PFC power pad, which can help dissipate heat in the PFC power pad area.

[0023] In some examples of the present invention, the lateral dimension of the first inverter drive pin frame is equal to the lateral dimension of the second inverter drive pin frame.

[0024] The specific advantages or beneficial effects of the above scheme are as follows: it can ensure the overall stability and reliability of the first inverter drive pin frame and the second inverter drive pin frame, and make the structure of the first inverter drive pin frame and the second inverter drive pin frame suitable for the semiconductor device manufacturing process and meet the reliability requirements of the semiconductor device.

[0025] In some examples of the present invention, the substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC (power factor correction) power pad portion. A plurality of rectifier chips are disposed on the rectifier bridge pad portion. The drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially longitudinally aligned with the rectifier bridge pad portion. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to it. The lateral dimension of the rectifier bridge pad portion is larger than the lateral dimension of the PFC (power factor correction) power pad portion.

[0026] The specific advantages or beneficial effects of the above scheme are as follows: it can facilitate the layout of rectifier chips and other modules on the rectifier bridge pad area, can help optimize the layout design of the rectifier bridge pad area, and can help improve the heat dissipation performance of the rectifier bridge pad area.

[0027] The circuit board assembly according to an embodiment of the present invention includes the semiconductor device described above.

[0028] The specific advantages or beneficial effects of the above solution are as follows: it can prevent local overheating of the circuit board assembly, reduce the wear and tear of the circuit board assembly, and improve the working performance of the circuit board assembly.

[0029] The electrical control box according to an embodiment of the present invention includes: the circuit board assembly described above.

[0030] The specific advantages or beneficial effects of the above solution are as follows: it can improve the working performance of the electrical control box and extend its service life.

[0031] An electrical device according to an embodiment of the present invention includes: the electrical control box described above.

[0032] The specific advantages or beneficial effects of the above solution are as follows: it can improve the working performance and quality of electrical equipment.

[0033] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0034] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 4 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 5 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 6 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 7 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 8 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0035] Figure label: 100. Semiconductor devices; 1. Plastic encapsulation; 2. Substrate; 201, First inverter power pad section; 2011, First inverter low-side power chip; 20111, First inverter low-side power first chip; 20112, First inverter low-side power second chip; 20113, First inverter low-side power third chip; 2012, First inverter high-side power chip; 20121, First inverter high-side power first chip; 20122, First inverter high-side power second chip; 20123, First inverter high-side power third chip; 202. Second inverter power pad section; 2021. Second inverter low-side power chip; 20211. Second inverter low-side power first chip; 20212. Second inverter low-side power second chip; 20213. Second inverter low-side power third chip; 2022. Second inverter high-side power chip; 20221. Second inverter high-side power first chip; 20222. Second inverter high-side power second chip; 20223. Second inverter high-side power third chip; 203. PFC (Power Factor Correction) power pad section; 2031. PFC power chip; 204, Rectifier bridge pads; 2041, Rectifier chip; 3. Driver-side pin frame; 301. First inverter drive pin frame; 3011, First inverter low-side driver chip pad; 30111, First inverter low-side driver chip; 3012, First inverter high-side driver chip pad; 30121, First inverter high-side driver chip; 3013, Ground pin of the first inverter driver chip; 30141, Boundary of the first inverter low-side driver chip; 30142, Boundary of the first inverter high-side driver chip; 30143, Boundary of the first inverter low-side driver pad; 30144, Boundary of the first inverter high-side driver first pad; 30145, Boundary of the first inverter high-side driver second pad; 30146, Boundary of the first inverter pin frame; 302. Second inverter drive pin frame; 3021, Pad for the low-side driver chip of the second inverter; 30211, Low-side driver chip of the second inverter; 3022, Pad for the high-side driver chip of the second inverter; 30221, High-side driver chip of the second inverter; 3023, Ground pin of the second inverter driver chip; 30241, Boundary of the second inverter low-side driver chip; 30242, Boundary of the second inverter high-side driver chip; 30243, Boundary of the second inverter low-side driver pad; 30244, Boundary of the second inverter high-side driver first pad; 30245, Boundary of the second inverter high-side driver second pad; 30246, Boundary of the second inverter pin frame; 303, PFC driver pin frame; 3031, PFC driver pad section; 304. Rectifier bridge driver pin frame. Detailed Implementation

[0036] The following is for reference. Figures 1-8A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 can be applied to a circuit board assembly, the circuit board assembly can be applied to an electrical control box, and the electrical control box can be applied to an electrical device. It should be noted that the semiconductor device 100 has a horizontal, a vertical, and a longitudinal dimension, which are perpendicular to each other.

[0037] Combination Figures 1-8 As shown, the semiconductor device 100 according to the present invention mainly includes: a molding compound 1, a substrate 2, and a drive-side pin frame 3. The substrate 2 is at least partially disposed within the molding compound 1. The substrate 2 can be completely encapsulated by the molding compound 1, or it can be partially encapsulated and partially exposed on the surface of the molding compound 1. The drive-side pin frame 3 is at least partially disposed within the molding compound 1, and partially extends out of the molding compound 1 for electrical connection with external components. The molding compound 1 protects the substrate 2 and the drive-side pin frame 3 within the semiconductor device 100, ensuring their stable placement and providing electrical insulation from the outside, thus guaranteeing the structural reliability of the semiconductor device 100. It should be noted that the pins of the drive-side pin frame 3 are spaced apart to ensure electrical isolation between them, and the longitudinal dimensions of the portions of the pins extending out of the molding compound 1 are inconsistent; this will not be elaborated further here.

[0038] Furthermore, the substrate 2 includes a first inverter power pad 201, a second inverter power pad 202, and a PFC (power factor correction) power pad 203 arranged laterally at intervals. This ensures that the first inverter power pad 201, the second inverter power pad 202, and the PFC (power factor correction) power pad 203 are all relatively independently arranged on the substrate 2, preventing mutual interference between them. This not only ensures the normal working performance of the first inverter power pad 201, the second inverter power pad 202, and the PFC (power factor correction) power pad 203, but also facilitates their installation, testing, and maintenance.

[0039] Furthermore, the first inverter power pad portion 201 is provided with first inverter low-side power chips 2011 and first inverter high-side power chips 2012 arranged horizontally at intervals, and the second inverter power pad portion 202 is provided with second inverter low-side power chips 2021 and second inverter high-side power chips 2022 arranged horizontally at intervals. Specifically, in the embodiment of the present invention, the first inverter power pad portion 201 is provided with a plurality of first inverter low-side power chips 2011 and a plurality of first inverter high-side power chips 2012. The plurality of first inverter low-side power chips 2011 are respectively disposed on a plurality of first inverter power pad portions 201 arranged horizontally at intervals, and the plurality of first inverter high-side power chips 2012 are arranged horizontally at intervals on the same first inverter power pad portion 201. This can ensure good working performance of each first inverter low-side power chip 2011 and each first inverter high-side power chip 2012. The second inverter power pad section 202 is provided with a plurality of second inverter low-side power chips 2021 and a plurality of second inverter high-side power chips 2022. The plurality of second inverter low-side power chips 2021 are respectively disposed on a plurality of second inverter power pad sections 202 that are spaced apart laterally. The plurality of second inverter high-side power chips 2022 are spaced apart laterally on the same second inverter power pad section 202. This ensures good working performance of each second inverter low-side power chip 2021 and each second inverter high-side power chip 2022. In addition, the PFC (Power Factor Correction) power pad section 203 is provided with a PFC power chip 2031. The PFC power chip 2031 includes a PFC power switch chip and a PFC diode chip. The PFC power switch chip and the PFC diode chip are some of the components in the PFC circuit. The PFC circuit adjusts the power factor of the DC power and outputs the adjusted DC power. The PFC power switch chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT. It should be noted that the RC-IGBT is a reverse-conducting IGBT that integrates the IGBT and the freewheeling diode into a single chip.

[0040] The first inverter power chip includes a first inverter low-side power chip 2011 and a first inverter high-side power chip 2012. Multiple first inverter power chips are used to form a first inverter circuit; for example, six first inverter power chips can form a first three-phase inverter bridge circuit. The first three-phase inverter bridge circuit includes a first three-phase upper bridge arm inverter power chip and a first three-phase lower bridge arm inverter power chip. The first inverter power chip can be composed of an insulated-gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be a reverse-conducting IGBT that integrates the IGBT and freewheeling diode into a single chip, etc.

[0041] Furthermore, the second inverter power chip includes a second inverter low-side power chip 2021 and a second inverter high-side power chip 2022, and there are multiple second inverter power chips. Multiple second inverter power chips form a second inverter circuit; for example, six second inverter power chips can form a second three-phase inverter bridge circuit. The second three-phase inverter bridge circuit includes second three-phase upper bridge arm inverter power chips and second three-phase lower bridge arm inverter power chips. The second inverter power chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be a reverse-conducting IGBT that integrates the IGBT and freewheeling diode into a single chip, etc.

[0042] Furthermore, the drive-side pin frame 3 is at least partially disposed within the molding compound 1 and spaced apart on one side of the longitudinal direction of the substrate 2. The drive-side pin frame extends at least partially from the molding compound. This not only allows the drive-side pin frame 3 and the substrate 2 to be designed separately to reduce the mutual influence between the devices on the drive-side pin frame 3 and the devices on the substrate 2, but also allows the drive-side pin frame 3 to be disposed adjacent to the substrate 2 to facilitate the electrical connection between the devices on the drive-side pin frame 3 and the devices on the substrate 2. In addition, it also facilitates the electrical connection between the drive-side pin frame 3 and external devices, which can ensure the rationality of the structural layout of the semiconductor device 100 and improve the integration of the semiconductor device 100 structure. In this invention, a driver chip is mounted on the driver-side pin frame 3. The driver-side pin frame 3 can be completely spaced apart from the substrate 2 in the vertical direction, thereby reducing the impact of heat transferred from the substrate 2 on the driver chip and ensuring the working performance of each driver chip. Alternatively, the driver-side pin frame 3 can be partially protruding in the vertical direction to form a connecting rod and connect to the substrate 2, thereby improving the stability of the substrate 2. At the same time, most of the driver-side pin frame 3 is spaced apart from the substrate 2 in the second direction, thus balancing the improvement of the stability of the substrate 2 and the reduction of the impact of heat transferred from the substrate 2 on the driver chip. In addition, in some embodiments of the present invention, the substrate 2 and the driver-side pin frame 3 can be constructed as a single frame. This not only facilitates the packaging of the semiconductor device 100 and improves the assembly efficiency of the semiconductor device 100, but also improves the overall structural strength of the semiconductor device 100 and extends the service life of the semiconductor device 100.

[0043] Furthermore, the drive-side pin frame 3 includes a first inverter drive pin frame 301, a second inverter drive pin frame 302, and a PFC drive pin frame 303 spaced apart in the horizontal direction. The first inverter drive pin frame 301 corresponds at least partially to the first inverter power pad portion 201 in the vertical direction. This facilitates the electrical connection between the first inverter drive pin frame 301 and the first inverter power chip on the first inverter power pad portion 201, and makes the wire connection between the first inverter drive pin frame 301 and the first inverter power pad portion 201 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. The second inverter drive pin frame 302 and the second inverter power pad portion 202 are at least partially corresponding in the longitudinal direction. This facilitates the electrical connection between the second inverter drive pin frame 302 and the second inverter power chip on the second inverter power pad portion 202, and makes the wire connection between the second inverter drive pin frame 302 and the second inverter power pad portion 202 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. The PFC drive pin frame 303 and the PFC (Power Factor Correction) power pad portion 203 are at least partially corresponding in the longitudinal direction. This facilitates the electrical connection between the PFC drive pin frame 303 and the PFC (Power Factor Correction) power chip 2031 on the PFC (Power Factor Correction) power pad portion 203, and makes the wire connection between the PFC drive pin frame 303 and the PFC (Power Factor Correction) power pad portion 203 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100.

[0044] Furthermore, the first inverter drive pin frame 301 is provided with a first inverter high-side drive chip 30121 and a first inverter low-side drive chip 30111 spaced apart from each other. The first inverter high-side drive chip 30121 is electrically connected to the first inverter high-side power chip 2012, and the first inverter low-side drive chip 30111 is electrically connected to the first inverter low-side power chip 2011. This allows the first inverter low-side drive chip 30111 to drive the first inverter low-side power chip 2011 to work normally, and allows the first inverter high-side drive chip 30121 to drive the first inverter high-side power chip 2012 to work normally. Operation: The second inverter drive pin frame 302 is provided with a second inverter high-side drive chip 30221 and a second inverter low-side drive chip 30211 that are spaced apart from each other. The second inverter high-side drive chip 30221 and the second inverter high-side power chip 2022 are electrically connected, and the second inverter low-side drive chip 30211 and the second inverter low-side power chip 2021 are electrically connected. This allows the second inverter low-side drive chip 30211 to drive the second inverter low-side power chip 2021 to work normally, and the second inverter high-side drive chip 30221 to drive the second inverter high-side power chip 2022 to work normally.

[0045] Furthermore, the side of the first inverter low-side drive chip 30111 that is laterally adjacent to the first inverter high-side drive chip 30121 is defined as the first inverter low-side drive chip boundary 30141, and the side of the first inverter high-side drive chip 30121 that is laterally adjacent to the first inverter low-side drive chip 30111 is defined as the first inverter high-side drive chip boundary 30142. The lateral distance between the first inverter low-side drive chip boundary 30141 and the first inverter high-side drive chip boundary 30142 is L1. Specifically, both the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141 extend vertically. Setting the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141 can help to reasonably set the horizontal distance between the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141. This can help to optimize the layout of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 while ensuring the stable performance of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111.

[0046] Furthermore, the side of the second inverter low-side drive chip 30211 that is laterally away from the second inverter high-side drive chip 30221 is defined as the second inverter low-side drive chip boundary 30241, and the side of the second inverter high-side drive chip 30221 that is laterally adjacent to the second inverter low-side drive chip 30211 is defined as the second inverter high-side drive chip boundary 30242. The lateral distance between the second inverter low-side drive chip boundary 30241 and the second inverter high-side drive chip boundary 30242 is L2. Specifically, the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241 are both extended vertically. Setting the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241 can help to reasonably set the lateral distance between the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241. This can help to optimize the layout of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211 while ensuring the stable performance of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211.

[0047] Furthermore, L1 and L2 satisfy the relationship: L1 < L2. That is, the lateral distance between the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141 is less than the lateral distance between the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241. Specifically, the first inverter drive pin frame 301 and the first inverter power pad portion 201 are mostly vertically aligned, and the second inverter drive pin frame 302 and the second inverter power pad portion 202 are also mostly vertically aligned. By making the lateral distance between the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141 smaller than the lateral distance between the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241, the first inverter drive pin frame 301 can be recessed to the side away from the PFC drive pin frame 303. This ensures that the first inverter power pad portion 201 and the second inverter power pad portion 202 are aligned. Under the premise of stable performance of the pad portion 202, the first inverter power pad portion 201 is correspondingly recessed to the side away from the PFC (Power Factor Correction) power pad portion 203. This reduces the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increases the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 area is usually greater than that of the first inverter power pad portion 201 area, this is beneficial for heat dissipation of the second inverter power pad portion 202 area, can prevent the devices in the second inverter power pad portion 202 area from malfunctioning due to excessive temperature, and can improve the stability and reliability of the semiconductor device 100.

[0048] Therefore, by making the lateral distance between the first inverter high-side drive chip boundary 30142 and the first inverter low-side drive chip boundary 30141 smaller than the lateral distance between the second inverter high-side drive chip boundary 30242 and the second inverter low-side drive chip boundary 30241, the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 can be reduced, the area of ​​the substrate 2 occupied by the second inverter power pad portion 202 can be increased, and the heat dissipation performance of the second inverter power pad portion 202 can be improved.

[0049] Combination Figure 2 , Figure 3 and Figure 4As shown, there are three first inverter high-side power chips 2012 and three first inverter low-side power chips 2011. The three first inverter low-side power chips 2011 are respectively first inverter low-side power first chip 20111, first inverter low-side power second chip 20112, and first inverter low-side power third chip 20113. The three first inverter high-side power chips 2012 are respectively first inverter high-side power first chip 20121, first inverter high-side power second chip 20122, and first inverter high-side power third chip 20122. In the first inverter low-side power first chip 20111, first inverter low-side power second chip 20112, first inverter low-side power third chip 20113, first inverter high-side power first chip 20121, first inverter high-side power second chip 20122, and first inverter high-side power third chip 20123 are arranged sequentially at intervals in the horizontal direction. Compared with the first inverter low-side power chip 2011, the first inverter high-side power chip 2012 is closer to the second inverter power pad portion 202 in the horizontal direction. Specifically, the first inverter low-side power first chip 20111, the first inverter low-side power second chip 20112, the first inverter low-side power third chip 20113, the first inverter high-side power first chip 20121, the first inverter high-side power second chip 20122, and the first inverter high-side power third chip 20123 are arranged sequentially and spaced apart in the horizontal direction. This not only facilitates the electrical connection between the three first inverter low-side power chips 2011 and the first inverter low-side drive chip 30111, but also facilitates the connection between the three first inverter high-side power chips 2012 and... The electrical connection of the first inverter high-side drive chip 30121 can also prevent mutual interference between the first inverter low-side power first chip 20111, the first inverter low-side power second chip 20112, the first inverter low-side power third chip 20113, the first inverter high-side power first chip 20121, the first inverter high-side power second chip 20122, and the first inverter high-side power third chip 20123, thus ensuring good working performance of each first inverter low-side power chip 2011 and each first inverter high-side power chip 2012. Compared to the first inverter low-side power chip 2011, the first inverter high-side power chip 2012 is laterally closer to the second inverter power pad portion 202. This can shorten the distance between the first inverter high-side power chip 2012 and the first inverter low-side power chip 2011 and other devices on the semiconductor device 100, thereby shortening the electrical connection length between the first inverter high-side power chip 2012 and the first inverter low-side power chip 2011 and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100 and optimize the structural layout of the semiconductor device 100.

[0050] Furthermore, there is only one first inverter high-side driver chip 30121 and one first inverter low-side driver chip 30111. The first low-side driver chip 30111 and the first high-side driver chip 30121 are arranged laterally at a distance. Compared to the first low-side driver chip 30111, the first high-side driver chip 30121 is laterally closer to the second inverter driver pin frame 302. Specifically, the lateral spacing between the first low-side driver chip 30111 and the first high-side driver chip 30121 prevents mutual interference between them and ensures good operating performance. One first inverter high-side drive chip 30121 corresponds to three first inverter high-side power chips 2012, and one first inverter low-side drive chip 30111 corresponds to three first inverter low-side power chips 2011. This can help optimize the circuit design of the semiconductor device 100, reduce the driving cost of the semiconductor device 100, and simplify the control system of the semiconductor device 100. Compared to the first inverter low-side drive chip 30111, the first inverter high-side drive chip 30121 is laterally closer to the second inverter drive pin frame 302. This shortens the distance between the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 and other devices on the semiconductor device 100, thereby shortening the electrical connection length between the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100 and optimize the structural layout of the semiconductor device 100.

[0051] With this configuration, compared to the first inverter low-side power chip 2011, the first inverter high-side power chip 2012 is laterally closer to the second inverter power pad portion 202, and compared to the first inverter low-side driver chip 30111, the first inverter high-side driver chip 30121 is laterally closer to the second inverter driver pin frame 302. This helps to make the first inverter high-side driver chip 30121 and the first inverter high-side power chip 2012 correspond in the vertical direction, facilitating the electrical connection between the first inverter high-side driver chip 30121 and the first inverter low-side driver chip 2011. This also helps to make the first inverter low-side driver chip 30111 and the first inverter low-side power chip 2011 correspond in the vertical direction, facilitating the electrical connection between the first inverter low-side driver chip 30111 and the first inverter low-side power chip 2011. This simplifies the layout of the devices on the semiconductor device 100 and simplifies the wiring design on the semiconductor device 100.

[0052] Furthermore, a plane perpendicular to the vertical direction is defined as the first projection plane. The longitudinal extension region of the orthographic projection of the first inverter low-side drive chip 30111 on the first projection plane is laterally spaced between the orthographic projections of the first inverter low-side power first chip 20111 and the first inverter low-side power third chip 20113 on the first projection plane. The longitudinal extension region of the orthographic projection of the first inverter low-side drive chip 30111 on the first projection plane at least partially overlaps with the orthographic projection of the first inverter low-side power second chip 20112 on the first projection plane. Specifically, the side of the first inverter low-side power first chip 20111 away from the first inverter low-side power second chip 20112 is defined as the left boundary of the first inverter low-side power first chip 20111, and the side of the first inverter low-side power third chip 20113 away from the first inverter low-side power second chip 20112 is defined as the right boundary of the first inverter low-side power third chip 20113. The orthographic projection of the first inverter low-side drive chip 30111 on the first projection plane is located between the extension line of the orthographic projection of the left boundary of the first inverter low-side power first chip 20111 on the first projection plane and the extension line of the orthographic projection of the right boundary of the first inverter low-side power third chip 20113 on the first projection plane. Furthermore, the longitudinal extension area of ​​the orthographic projection of the first inverter low-side drive chip 30111 on the first projection plane is adjacent to the first inverter low-side power second chip 20112. 12 The orthographic projections on the first projection plane at least partially overlap with each other. This allows the orthographic projection of the first inverter low-side drive chip 30111 on the first projection plane to be positioned in the middle of the horizontal direction of the orthographic projection of the three first inverter low-side power chips 2011 on the first projection plane. This facilitates the electrical connection between the first inverter low-side drive chip 30111 and the three first inverter low-side power chips 2011, preventing the electrical connection line between one of the first inverter low-side power chips 2011 and the first inverter low-side drive chip 30111 from being too long. This also ensures that the wire connection between the first inverter low-side drive chip 30111 and the first inverter low-side power chips 2011 is suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. This can help optimize the circuit design and layout design of the semiconductor device 100.

[0053] Furthermore, the longitudinally extending region of the orthographic projection of the first inverter high-side drive chip 30121 on the first projection plane is spaced apart from the side of the orthographic projection of the first inverter low-side power chip 20111 on the first projection plane that is laterally away from the first inverter low-side drive chip 30111. The longitudinally extending region of the orthographic projection of the first inverter high-side drive chip 30121 on the first projection plane at least partially overlaps with the orthographic projections of the first inverter low-side power chip 20112 and / or the first inverter low-side power chip 20113 on the first projection plane. This allows the orthographic projection of the first inverter high-side drive chip 30121 on the first projection plane to be at least partially overlapping with each other. The three adjacent first inverter high-side power chips 2012 are positioned in the middle of the horizontal direction of the orthographic projection on the first projection plane. This facilitates the electrical connection between the first inverter high-side drive chip 30121 and the three first inverter high-side power chips 2012, preventing the electrical connection line between one of the first inverter high-side power chips 2012 and the first inverter high-side drive chip 30121 from being too long. This also ensures that the wire connection between the first inverter high-side drive chip 30121 and the first inverter high-side power chips 2012 is suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. This can help optimize the circuit design and layout design of the semiconductor device 100.

[0054] Combination Figure 4 , Figure 5 and Figure 6As shown, the first inverter drive pin frame 301 includes a first inverter drive chip ground pin 3013. The first inverter drive chip ground pin 3013 is at least partially protruding toward the side that is longitudinally away from the substrate 2 to form a first inverter low-side drive chip pad 3011 and a first inverter high-side drive chip pad 3012 that are spaced apart in the lateral direction. The first inverter low-side drive chip 30111 and the first inverter high-side drive chip 3012 are respectively provided on the first inverter low-side drive chip pad 3011 and the first inverter high-side drive chip pad 3012. Specifically, by making the ground pin 3013 of the first inverter driver chip protrude at least partially toward the side that is longitudinally away from the substrate 2 when it extends laterally, the first inverter low-side driver chip pad 3011 and the first inverter high-side driver chip pad 3012 are formed and spaced apart laterally. This not only provides a placement position for the first inverter low-side driver chip 30111 and the first inverter high-side driver chip 30121, but also increases the size of the ground pin 3013 of the first inverter driver chip in both the lateral and longitudinal directions, so as to shorten the distance between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100, thereby shortening the length of the electrical connection between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100. The first inverter low-side driver chip 30111 and the first inverter high-side driver chip 30121 are respectively set on the first inverter low-side driver chip pad 3011 and the first inverter high-side driver chip pad 3012. This can ensure the rationality of the structural setting of the first inverter low-side driver chip 30111 and the first inverter high-side driver chip 30121, and can ensure the normal operation of the first inverter low-side driver chip 30111 and the first inverter high-side driver chip 30121.

[0055] Furthermore, the first inverter low-side driver chip pad 3011 and the first inverter high-side driver chip pad 3012 are respectively spaced apart on both sides of the horizontal middle of the first inverter driver pin frame 301. This not only facilitates the electrical connection between the first inverter low-side driver chip pad 3011 and the first inverter high-side driver chip pad 3012 and other components, but also improves the rationality and compactness of the layout of the driver-side pin frame 3 and enhances the stability of the driver-side pin frame 3 structure.

[0056] Furthermore, the center of the first inverter low-side driver chip 30111 is offset laterally relative to the center of the first inverter low-side driver chip pad 3011 towards the side closer to the first inverter high-side driver chip 30121, and the center of the first inverter high-side driver chip 30121 is offset laterally relative to the center of the first inverter high-side driver chip pad 3012 towards the side farther away from the first inverter low-side driver chip 30111. Specifically, the center of the first inverter low-side drive chip pad 3011 is offset laterally from the center of the three first inverter low-side power chips 2011 as a whole, away from the first inverter high-side drive chip 30121. The first inverter low-side drive chip 30111 is disposed on the first inverter low-side drive chip pad 3011. By offsetting the center of the first inverter low-side drive chip 30111 laterally from the center of the first inverter low-side drive chip pad 3011 towards the side closer to the first inverter high-side drive chip 30121, the center of the first inverter low-side drive chip 30111 is positioned laterally close to the center of the three first inverter low-side power chips 2011 as a whole. This facilitates the electrical connection between the first inverter low-side drive chip 30111 and the three first inverter low-side power chips 2011, and optimizes the layout design of the semiconductor device 100. Furthermore, by offsetting the center of the first inverter high-side driver chip 30121 laterally relative to the center of the first inverter high-side driver chip pad 3012, away from the first inverter low-side driver chip 30111, the system prevents interference between the first inverter high-side driver chip 30121 and the first inverter low-side driver chip 30111 due to excessive proximity, thus improving the stability of the semiconductor device 100. This configuration also ensures that the wiring connections between the first inverter low-side driver chip 30111 and the first inverter low-side power chip 2011, as well as between the first inverter high-side driver chip 30121 and the first inverter high-side power chip 2012, are suitable for the manufacturing process of the semiconductor device 100 and meet its reliability requirements. This optimizes the layout of the first inverter driver pin frame 301 and the circuit and layout design of the semiconductor device 100.

[0057] Combination Figure 2 , Figure 3 and Figure 4As shown, there are three second inverter low-side power chips 2021 and three second inverter low-side power chips 2021. These three second inverter low-side power chips 2021 are respectively second inverter low-side power first chip 20211, second inverter low-side power second chip 20212, and second inverter low-side power third chip 20213. Similarly, the three second inverter high-side power chips 2022 are respectively second inverter high-side power first chip 20221, second inverter high-side power second chip 20222, and second inverter high-side power third chip 20213. Chip 20223, second inverter low-side power first chip 20211, second inverter low-side power second chip 20212, second inverter low-side power third chip 20213, second inverter high-side power first chip 20221, second inverter high-side power second chip 20222, and second inverter high-side power third chip 20223 are arranged sequentially and alternately in the horizontal direction. Compared with the second inverter low-side power chip 2021, the second inverter high-side power chip 2022 is closer to the PFC power pad in the horizontal direction. Specifically, the second inverter low-side power first chip 20211, second inverter low-side power second chip 20212, second inverter low-side power third chip 20213, second inverter high-side power first chip 20221, second inverter high-side power second chip 20222, and second inverter high-side power third chip 20223 are arranged sequentially and spaced apart in the horizontal direction. This not only facilitates the electrical connection between the three second inverter low-side power chips 2021 and the second inverter low-side driver chip 30211, but also facilitates the connection between the three second inverter high-side power chips 2022 and... The electrical connection of the second inverter high-side drive chip 30221 can also prevent mutual interference between the second inverter low-side power first chip 20211, the second inverter low-side power second chip 20212, the second inverter low-side power third chip 20213, the second inverter high-side power first chip 20221, the second inverter high-side power second chip 20222, and the second inverter high-side power third chip 20223, thus ensuring good working performance of each second inverter low-side power chip 2021 and each second inverter high-side power chip 2022. Compared to the second inverter low-side power chip 2021, the second inverter high-side power chip 2022 is laterally closer to the PFC power pad. This shortens the distance between the second inverter high-side power chip 2022 and the second inverter low-side power chip 2021 and other devices on the semiconductor device 100. Consequently, it shortens the electrical connection length between the second inverter high-side power chip 2022 and the second inverter low-side power chip 2021 and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100 and optimize the structural layout of the semiconductor device 100.

[0058] Furthermore, there is only one second inverter high-side driver chip 30221 and one second inverter low-side driver chip 30211. The two second inverter low-side driver chips 30211 and 30221 are arranged laterally at a distance. Compared to the second inverter low-side driver chip 30211, the second inverter high-side driver chip 30221 is laterally closer to the PFC driver pin frame 303. Specifically, the lateral spacing between the two second inverter low-side driver chips 30211 and 30221 prevents mutual interference and ensures good operating performance for both chips. One second inverter high-side drive chip 30221 corresponds to three second inverter high-side power chips 2022, and one second inverter low-side drive chip 30211 corresponds to three second inverter low-side power chips 2021. This can help optimize the circuit design of the semiconductor device 100, reduce the driving cost of the semiconductor device 100, and simplify the control system of the semiconductor device 100. Compared to the second inverter low-side driver chip 30211, the second inverter high-side driver chip 30221 is laterally closer to the PFC driver pin frame 303. This shortens the distance between the second inverter high-side driver chip 30221 and the second inverter low-side driver chip 30211 and other devices on the semiconductor device 100, thereby shortening the electrical connection length between the second inverter high-side driver chip 30221 and the second inverter low-side driver chip 30211 and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100 and optimize the structural layout of the semiconductor device 100.

[0059] With this configuration, compared to the second inverter low-side power chip 2021, the second inverter high-side power chip 2022 is laterally closer to the second inverter power pad portion 202, and compared to the second inverter low-side driver chip 30211, the second inverter high-side driver chip 30221 is laterally closer to the second inverter driver pin frame 302. This helps to align the positions of the second inverter high-side driver chip 30221 and the second inverter high-side power chip 2022 vertically, facilitating the electrical connection between them. Similarly, it helps to align the positions of the second inverter low-side driver chip 30211 and the second inverter low-side power chip 2021 vertically, facilitating the electrical connection between them. This simplifies the layout of the devices on the semiconductor device 100 and simplifies the wiring design on the semiconductor device 100.

[0060] Furthermore, the longitudinal extension region of the orthographic projection of the second inverter low-side drive chip 30211 on the first projection plane is laterally spaced between the orthographic projection of the second inverter low-side power first chip 20211 on the first projection plane and the orthographic projection of the second inverter low-side power third chip 20213 on the first projection plane. The longitudinal extension region of the orthographic projection of the second inverter low-side drive chip 30211 on the first projection plane at least partially overlaps with the orthographic projection of the second inverter low-side power second chip 20212 on the first projection plane. Specifically, the side of the second inverter low-side power first chip 20211 away from the second inverter low-side power second chip 20212 is defined as the left boundary of the second inverter low-side power first chip 20211, and the side of the second inverter low-side power third chip 20213 away from the second inverter low-side power second chip 20212 is defined as the right boundary of the second inverter low-side power third chip 20213. The orthographic projection of the second inverter low-side drive chip 30211 on the first projection plane is located between the extension line of the orthographic projection of the left boundary of the second inverter low-side power first chip 20211 on the first projection plane and the extension line of the orthographic projection of the right boundary of the second inverter low-side power third chip 20213 on the first projection plane. Furthermore, the longitudinal extension area of ​​the orthographic projection of the second inverter low-side drive chip 30211 on the first projection plane intersects with the orthographic projection of the second inverter low-side power second chip 20212. 12 The orthographic projections on the first projection plane at least partially overlap with each other. This allows the orthographic projection of the second inverter low-side drive chip 30211 on the first projection plane to be positioned in the middle of the horizontal direction of the orthographic projection of the three second inverter low-side power chips 2021 on the first projection plane. This facilitates the electrical connection between the second inverter low-side drive chip 30211 and the three second inverter low-side power chips 2021, and prevents the electrical connection line between one of the second inverter low-side power chips 2021 and the second inverter low-side drive chip 30211 from being too long. This also makes the wire connection between the second inverter low-side drive chip 30211 and the second inverter low-side power chip 2021 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. This can help optimize the circuit design and layout design of the semiconductor device 100.

[0061] Furthermore, the longitudinally extending region of the orthographic projection of the second inverter high-side drive chip 30221 on the first projection plane is spaced apart from the side of the orthographic projection of the second inverter high-side power first chip 20221 on the first projection plane that is laterally away from the second inverter low-side drive chip 30211. The longitudinally extending region of the orthographic projection of the second inverter high-side drive chip 30221 on the first projection plane at least partially overlaps with the orthographic projections of the second inverter high-side power second chip 20222 and / or the second inverter high-side power third chip 20223 on the first projection plane. This allows the orthographic projection of the second inverter high-side drive chip 30221 on the first projection plane to be at least partially overlapping with each other. The three adjacent second inverter high-side power chips 2022 are positioned in the middle of the horizontal direction of the orthographic projection on the first projection plane. This facilitates the electrical connection between the second inverter high-side driver chip 30221 and the three second inverter high-side power chips 2022, preventing the electrical connection line between one of the second inverter high-side power chips 2022 and the second inverter high-side driver chip 30221 from being too long. This also ensures that the wire connection between the second inverter high-side driver chip 30221 and the second inverter high-side power chips 2022 is suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. This can help optimize the circuit design and layout design of the semiconductor device 100.

[0062] Combination Figure 4 , Figure 5 and Figure 6As shown, the second inverter drive pin frame 302 includes a second inverter drive chip ground pin 3023. The second inverter drive chip ground pin 3023 is at least partially protruding toward the side that is longitudinally away from the substrate 2 to form a second inverter low-side drive chip pad 3021 and a second inverter high-side drive chip pad 3022 that are spaced apart in the lateral direction. A second inverter low-side drive chip 30211 and a second inverter high-side drive chip 30221 are respectively disposed on the second inverter low-side drive chip pad 3021 and the second inverter high-side drive chip pad 3022. Specifically, by making the ground pin 3023 of the second inverter driver chip protrude at least partially toward the side of the longitudinal direction away from the substrate 2 when extending laterally, a second inverter low-side driver chip pad 3021 and a second inverter high-side driver chip pad 3022 are formed. This not only provides a placement position for the second inverter high-side driver chip 30221 and the second inverter low-side driver chip 30211, but also increases the size of the ground pin 3023 of the second inverter driver chip in both the lateral and longitudinal directions, thereby shortening the distance between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This further shortens the length of the electrical connection between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100. The second inverter low-side driver chip 30211 and the second inverter high-side driver chip 3022 are respectively set on the second inverter low-side driver chip pad 3021 and the second inverter high-side driver chip pad 3022. This can ensure the rationality of the structural setting of the second inverter low-side driver chip 30211 and the second inverter high-side driver chip 30221, and can ensure the normal operation of the second inverter low-side driver chip 30211 and the second inverter high-side driver chip 30221.

[0063] Furthermore, the second inverter low-side driver chip 30211 is located in the middle of the second inverter low-side driver chip pad 3021 in the lateral direction; or the second inverter low-side driver chip 30211 is located to the right of the middle of the second inverter low-side driver chip pad 3021 in the lateral direction; the center of the second inverter high-side driver chip 30221 is offset in the lateral direction relative to the center of the second inverter high-side driver chip pad 3012 towards the side closer to the second inverter low-side driver chip 30111. Specifically, the second inverter low-side driver chip 30211 is located in the middle of the second inverter low-side driver chip pad 3021 in the horizontal direction, or the second inverter low-side driver chip 30211 is located to the right of the middle of the second inverter low-side driver chip pad 3021 in the horizontal direction. This ensures a reasonable distance between the second inverter low-side driver chip 30211 and the first inverter high-side driver chip 30121, while also making the center of the second inverter low-side driver chip 30211 horizontally adjacent to the center of the three second inverter low-side power chips 2021 as a whole, so as to facilitate the electrical connection between the second inverter low-side driver chip 30211 and the second inverter low-side power chips 2021. Furthermore, the center of the second inverter high-side driver chip 30221 is offset laterally relative to the center of the first inverter high-side driver chip pad 3012, towards the side closer to the first inverter low-side driver chip 30111. This allows the center of the second inverter high-side driver chip 30221 to be laterally adjacent to the center of the three second inverter high-side power chips 2022 as a whole, facilitating electrical connections between the second inverter high-side driver chip 30221 and the second inverter high-side power chips 2022. This arrangement ensures that the wiring connections between the second inverter low-side driver chip 30211 and the second inverter low-side power chip 2021, and between the second inverter high-side driver chip 30221 and the second inverter high-side power chip 2022, are suitable for the manufacturing process of the semiconductor device 100 and meet the reliability requirements of the semiconductor device 100. It also optimizes the layout of the second inverter driver pin frame 302, optimizes the circuit design and layout design of the semiconductor device 100, and improves the stability of the semiconductor device 100.

[0064] Combination Figure 2 , Figure 4 and Figure 8As shown, the lateral dimension of the first inverter power pad portion 201 is smaller than the lateral dimension of the second inverter power pad portion 202. Specifically, by making the lateral dimension of the first inverter power pad portion 201 smaller than the lateral dimension of the second inverter power pad portion 202, the first inverter power pad portion 201 can be recessed as a whole away from the PFC (Power Factor Correction) power pad portion 203, while ensuring the stable performance of the first and second inverter power pad portions 201 and 202. This reduces the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increases the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 is usually greater than that of the first inverter power pad portion 201, this is beneficial for heat dissipation in the second inverter power pad portion 202, preventing the devices in the second inverter power pad portion 202 from malfunctioning due to excessive temperature, and improving the stability and reliability of the semiconductor device 100.

[0065] It should be noted that, Figure 8 In this context, L7 represents the lateral dimension of the first inverter power pad portion 201, and L8 represents the lateral dimension of the second inverter power pad portion 202.

[0066] Combination Figure 2 , Figure 4 and Figure 8 As shown, the side of the first inverter low-side driver chip pad 3011 that is laterally adjacent to the first inverter high-side driver chip pad 3012 is defined as the first inverter low-side driver pad boundary 30143. The first inverter low-side driver pad boundary 30143 extends longitudinally. The side of the first inverter high-side driver chip pad 3012 that is laterally adjacent to the first inverter low-side driver chip pad 3011 is defined as the first inverter high-side driver first pad boundary 30144. The first inverter high-side driver first pad boundary 30144 extends longitudinally. The lateral distance between the first inverter high-side driver first pad boundary 30144 and the first inverter low-side driver pad boundary 30143 is L3. Specifically, setting the first inverter high-side drive first pad boundary 30144 and the first inverter low-side drive pad boundary 30143 can help to reasonably set the lateral distance between the first inverter high-side drive first pad boundary 30144 and the first inverter low-side drive pad boundary 30143. This can help to optimize the layout of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 while ensuring the stable performance of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111.

[0067] Furthermore, a triangular region can extend from the side of the first inverter low-side driver chip pad 3011 near the first inverter high-side driver chip pad 3012. This not only optimizes the structural design and layout of the first inverter low-side driver chip pad 3011, facilitating the electrical connection between the first inverter low-side driver chip 30111 and the first inverter low-side power chip 2011, but also enhances the structural strength of the first inverter low-side driver chip pad 3011, improving the stability and reliability of the first inverter driver pin frame 301 structure. In this case, the position of the boundary 30143 of the first inverter low-side driver pad remains unchanged, with the longitudinally extending portion of the first inverter low-side driver chip pad 3011 near the first inverter high-side driver chip pad 3012 serving as a reference.

[0068] Furthermore, the side of the second inverter low-side driver chip pad 3021 that is laterally adjacent to the second inverter high-side driver chip pad 3022 is defined as the second inverter low-side driver pad boundary 30243. The second inverter low-side driver pad boundary 30243 extends longitudinally. The side of the second inverter high-side driver chip pad 3022 that is laterally adjacent to the second inverter low-side driver chip pad 3021 is defined as the second inverter high-side driver first pad boundary 30244. The second inverter high-side driver first pad extends longitudinally. The lateral distance between the second inverter high-side driver first pad boundary 30244 and the second inverter low-side driver pad boundary 30243 is L4. Specifically, setting the boundary 30244 of the first pad of the second inverter high-side drive and the boundary 30243 of the second inverter low-side drive can help to reasonably set the lateral distance between the boundary 30244 of the first pad of the second inverter high-side drive and the boundary 30243 of the second inverter low-side drive. This can help to optimize the layout of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211 while ensuring the stable performance of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211.

[0069] Furthermore, L3 and L4 satisfy the relationship: L3 < L4, that is, the lateral distance between the first inverter high-side drive first pad boundary 30144 and the first inverter low-side drive pad boundary 30143 is less than the lateral distance between the second inverter high-side drive first pad boundary 30244 and the second inverter low-side drive pad boundary 30243. Specifically, the first inverter drive pin frame 301 and the first inverter power pad portion 201 are mostly vertically aligned, and the second inverter drive pin frame 302 and the second inverter power pad portion 202 are mostly vertically aligned. By making the lateral distance between the first inverter high-side drive first pad boundary 30144 and the first inverter low-side drive pad boundary 30143 smaller than the lateral distance between the second inverter high-side drive first pad boundary 30244 and the second inverter low-side drive pad boundary 30243, it is possible to ensure the stable performance of the first inverter power pad portion 201 and the second inverter power pad portion 202 while achieving... The first inverter power pad portion 201 is recessed to the side away from the PFC (Power Factor Correction) power pad portion 203, thereby reducing the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increasing the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 is usually greater than that of the first inverter power pad portion 201, this is beneficial for heat dissipation of the second inverter power pad portion 202, preventing the devices in the second inverter power pad portion 202 from malfunctioning due to excessive temperature, and improving the stability and reliability of the semiconductor device 100.

[0070] Combination Figure 2 , Figure 4 and Figure 8As shown, the side of the first inverter drive pin frame 301 that is laterally adjacent to the first inverter low-side drive chip pad 3011 is defined as the first inverter pin frame boundary 30146. The first inverter pin frame boundary 30146 extends longitudinally. The side of the first inverter high-side drive chip pad 3012 that is laterally away from the first inverter low-side drive chip pad 3011 is defined as the first inverter high-side drive second pad boundary 30145. The first inverter high-side drive second pad boundary 30145 extends longitudinally. The lateral distance between the first inverter pin frame boundary 30146 and the first inverter high-side drive second pad boundary 30145 is L5. Specifically, setting the boundary 30146 of the first inverter pin frame and the boundary 30145 of the second pad for the first inverter high-side drive can help to reasonably set the lateral distance between the boundary 30146 and the second pad for the first inverter high-side drive. This can help to optimize the layout of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 while ensuring their stable performance. The first inverter drive pin frame 301 includes a plurality of horizontally spaced first inverter drive pins. Among the first inverter drive pins located on both sides of the lateral edges, the one closer to the first inverter low-side drive pad is the first inverter drive boundary pin. The side edge of the first inverter drive boundary pin that extends vertically out of the molding compound 1 and is laterally away from the first inverter low-side drive pad is the first inverter pin frame boundary 30146.

[0071] Furthermore, the side of the second inverter drive pin frame 302 that is laterally adjacent to the second inverter low-side drive chip pad 3021 is defined as the second inverter pin frame boundary 30246, and the second inverter pin frame boundary 30246 extends longitudinally. The side of the second inverter high-side drive chip pad 3022 that is laterally away from the second inverter low-side drive chip pad 3021 is defined as the second inverter high-side drive second pad boundary 30245, and the second inverter high-side drive second pad boundary 30245 extends longitudinally. The lateral distance between the second inverter pin frame boundary 30246 and the second inverter high-side drive second pad boundary 30245 is L6. Specifically, setting the boundary 30246 of the second inverter pin frame and the boundary 30245 of the second inverter high-side drive second pad can help to reasonably set the lateral distance between the boundary 30246 of the second inverter pin frame and the boundary 30245 of the second inverter high-side drive second pad. This can help to optimize the layout of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211 while ensuring the stable performance of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211. The second inverter drive pin frame 302 includes a plurality of second inverter drive pins arranged laterally at intervals. Among the second inverter drive pins located on both lateral edges of the plurality of second inverter drive pins, the one closer to the second inverter low-side drive pad is the second inverter drive boundary pin. The edge of the second inverter drive boundary pin that extends longitudinally out of the molding compound 1 and is laterally away from the second inverter low-side drive pad is the second inverter pin frame boundary 30246.

[0072] Furthermore, L5 and L6 satisfy the relationship: L5 > L6, that is, the lateral distance between the first inverter pin frame boundary 30146 and the first inverter high-side drive second pad boundary 30145 is greater than the lateral distance between the second inverter pin frame boundary 30246 and the second inverter high-side drive second pad boundary 30245. Specifically, the first inverter drive pin frame 301 and the first inverter power pad portion 201 are mostly vertically aligned, and the second inverter drive pin frame 302 and the second inverter power pad portion 202 are mostly vertically aligned. By making the lateral distance between the first inverter pin frame boundary 30146 and the first inverter high-side drive second pad boundary 30145 greater than the lateral distance between the second inverter pin frame boundary 30246 and the second inverter high-side drive second pad boundary 30245, the second inverter power pad portion 202 can be recessed towards the side closer to the first inverter pin frame boundary 30146, while ensuring the stable performance of the first inverter power pad portion 201 and the second inverter power pad portion 202. In other words, the first inverter power pad portion 201 can be recessed towards the side closer to the first inverter pin frame boundary 30146. The first and second inverter power pad portions 201 and 202 are recessed towards the boundary 30146 of the first inverter pin frame to reduce the area of ​​the substrate 2 occupied by the first and second inverter power pad portions 201 and 202. This increases the area of ​​the substrate 2 occupied by the PFC (Power Factor Correction) power pad portion 203. Since the PFC (Power Factor Correction) power pad portion 203 is a high-temperature, high-frequency operating region, the increased area of ​​the substrate 2 occupied by the PFC (Power Factor Correction) power pad portion 203 facilitates heat dissipation in the PFC (Power Factor Correction) power pad portion 203, preventing device failure due to excessive temperature and improving the stability and reliability of the semiconductor device 100. Furthermore, it optimizes the heat dissipation performance of the drive-side pin frame 3, preventing fatigue problems such as material performance degradation or structural failure caused by heat concentration, thus improving the structural reliability of the drive-side pin frame 3. In addition, making the lateral distance between the first inverter pin frame boundary 30146 and the first inverter high-side drive first pad boundary 30144 greater than the lateral distance between the second inverter pin frame boundary 30246 and the second inverter high-side drive first pad boundary 30244 can optimize the heat dissipation performance of the drive-side pin frame 3, avoid fatigue problems such as material performance degradation or structural failure caused by heat concentration in the drive-side pin frame 3, and improve the structural reliability of the drive-side pin frame 3.

[0073] It should be noted that the boundary 30146 of the first inverter pin frame and the boundary 30246 of the second inverter pin frame are referenced to the portion of the drive-side pin frame 3 that extends longitudinally out of the encapsulation body 1.

[0074] Combination Figure 2 , Figure 4 and Figure 8 As shown, the lateral dimension of the first inverter drive pin frame 301 is equal to the lateral dimension of the second inverter drive pin frame 302. Specifically, by making the lateral dimension of the first inverter drive pin frame 301 equal to the lateral dimension of the second inverter drive pin frame 302, not only can the overall stability and reliability of the first inverter drive pin frame 301 and the second inverter drive pin frame 302 be ensured, and the rationality of the device layout in the two regions of the first inverter drive pin frame 301 and the second inverter drive pin frame 302 be ensured, but also the structure of the first inverter drive pin frame 301 and the second inverter drive pin frame 302 can be made suitable for the manufacturing process of the semiconductor device 100 and meet the reliability requirements of the semiconductor device 100.

[0075] It should be noted that, Figure 8 In this context, L9 represents the lateral dimension of the first inverter drive pin frame 301, and L10 represents the lateral dimension of the second inverter drive pin frame 302.

[0076] The first inverter drive pin frame 301 has two horizontal edges, one on each side, which are the first inverter over-temperature protection pin and the first inverter drive chip ground pin 3013; the second inverter drive pin frame 302 has two horizontal edges, which are the second inverter over-temperature protection pin and the second inverter drive chip ground pin 3023; and the PFC drive pin frame 303 has two horizontal edges, which are the PFC drive chip power supply voltage pin and the temperature sensor connector pin near the rectifier bridge drive pin frame 304.

[0077] Furthermore, the lateral dimensions of the first inverter drive pin frame 301 and the lateral dimensions of the second inverter drive pin frame 302 are both referenced to the portion of the drive-side pin frame 3 that extends longitudinally out of the encapsulation body 1. Specifically, the edge of the first inverter over-temperature protection pin extending longitudinally out of the molding compound 1 and laterally away from the first inverter low-side drive pad is defined as the first inverter pin frame boundary 30146. The edge of the first inverter driver chip ground pin 3013 extending longitudinally out of the molding compound 1 and laterally away from the first inverter high-side drive pad is defined as the right boundary of the first inverter pin frame. The lateral dimension of the first inverter driver pin frame 301 is the distance between the first inverter pin frame boundary 30146 and the right boundary of the first inverter pin frame. The edge of the second inverter over-temperature protection pin extending longitudinally out of the molding compound 1 and laterally away from the second inverter low-side drive pad is defined as the second inverter pin frame boundary 30246. The edge of the second inverter driver chip ground pin 3023 extending longitudinally out of the molding compound 1 and laterally away from the second inverter high-side drive pad is defined as the right boundary of the second inverter pin frame. The lateral dimension of the second inverter driver pin frame 302 is the distance between the second inverter pin frame boundary 30246 and the right boundary of the second inverter pin frame.

[0078] Combination Figure 1 , Figure 2 and Figure 4 As shown, the substrate 2 also includes a rectifier bridge pad portion 204, which is laterally spaced from the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC (power factor correction) power pad portion 203. A plurality of rectifier chips 2041 are disposed on the rectifier bridge pad portion 204. The drive-side pin frame 3 also includes a rectifier bridge drive pin frame 304, which is at least partially corresponding to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge drive pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. The lateral dimension of the rectifier bridge pad portion 204 is larger than the lateral dimension of the PFC (power factor correction) power pad portion 203.

[0079] Specifically, the rectifier bridge pad 204 is spaced laterally from the first inverter power pad 201, the second inverter power pad 202, and the PFC (power factor correction) power pad 203. This ensures that the rectifier bridge pad 204, the first inverter power pad 201, the second inverter power pad 202, and the PFC (power factor correction) power pad 203 are independently arranged on the semiconductor device 100. This prevents mutual interference between the rectifier bridge pad 204 and the first inverter power pad 201, the second inverter power pad 202, and the PFC (power factor correction) power pad 203, ensuring good working performance of the rectifier bridge pad 204 and improving the anti-interference capability of the semiconductor device 100.

[0080] Furthermore, a rectifier chip 2041 is provided on the rectifier bridge pad section 204, so that the rectifier bridge pad section 204 can provide a setting position for the rectifier chip 2041 to ensure the reasonable layout and working stability of the rectifier chip 2041.

[0081] Furthermore, the drive-side pin frame 3 also includes a rectifier bridge drive pin frame 304, which corresponds at least partially to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge drive pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. This allows the establishment of an electrical connection point at the edge of the rectifier bridge drive pin frame 304 that is electrically connected to the rectifier bridge pad portion 204, thereby facilitating the electrical connection between the rectifier chip 2041 on the rectifier bridge pad portion 204 and external circuits or other devices. It also facilitates the input of AC signals to the rectifier chip 2041 on the rectifier bridge pad portion 204 to realize the rectification function of the semiconductor device 100.

[0082] Furthermore, the lateral dimension of the rectifier bridge pad portion 204 is larger than the lateral dimension of the PFC (Power Factor Correction) power pad portion 203. Specifically, since the rectifier chip 2041 disposed on the rectifier bridge pad portion 204 is more numerous than the PFC power chip 2031 on the PFC (Power Factor Correction) power pad portion 203, and the rectifier bridge pad portion 204 is compatible with modules of various current specifications, by making the lateral dimension of the rectifier bridge pad portion 204 larger than that of the PFC (Power Factor Correction) power pad portion 203, it is not only easier to arrange the rectifier chip 2041 and other modules on the rectifier bridge pad portion 204, which helps to optimize the layout design of the rectifier bridge pad portion 204, but also helps to improve the heat dissipation performance of the rectifier bridge pad portion 204, thereby improving the stability and reliability of the semiconductor device 100.

[0083] The rectifier chip 2041 can be a rectifier diode, and a rectifier bridge can be formed by multiple rectifier diodes. For example, it can be implemented by combining four rectifier diodes arranged at intervals. The rectifier bridge composed of four rectifier diodes converts the input AC power into DC power and outputs it.

[0084] In embodiments of the present invention, the first inverter drive pin frame 301 and the first inverter power pad portion 201 together constitute the first inverter intelligent module; the second inverter drive pin frame 302 and the second inverter power pad portion 202 together constitute the second inverter intelligent module; and the PFC drive pin frame 303 and the PFC power pad portion together constitute the PFC intelligent module. The rectifier bridge, PFC intelligent module, second inverter intelligent module, and first inverter intelligent module can be integrated on the semiconductor device 100. Compared to setting multiple independent components, this reduces the size of the semiconductor device 100 and eliminates the need for multiple component insertions during production, resulting in a simpler and more compact structure and easier manufacturing of the semiconductor device 100. In some embodiments of the present invention, one of the first inverter intelligent module and the second inverter intelligent module is a fan intelligent module, and the other is a compressor intelligent module. In other embodiments of the present invention, both the first inverter intelligent module and the second inverter intelligent module are motor intelligent modules. No specific limitations are imposed here.

[0085] In some embodiments of the present invention, the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad 203, and the rectifier bridge pad 204 are all formed of a copper layer on the substrate 2. The pins on the side of the molding compound 1 away from the drive-side pin frame 3 are power-side pins. Preferably, each power-side pin is correspondingly soldered to the first inverter power pad 201, the second inverter power pad 202, and the PFC (Power Factor Correction) power pad 203. The first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad 203, and the rectifier bridge pad 204 can also be electrically connected to their respective power side pins via wires; and / or the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad 203, and the rectifier bridge pad 204 are integrally formed with their respective power side pins.

[0086] In some embodiments of the present invention, the substrate 2 may include pads and an insulating heat dissipation layer disposed below the pads. The insulating heat dissipation layer is mainly formed by sequentially stacking an insulating resin sheet and a copper layer, or by sequentially stacking an insulating resin sheet and an aluminum layer. The main material of the pads is copper or aluminum. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the copper layer or the outer surface of the aluminum layer in the insulating heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads, an insulating layer, and a heat dissipation layer formed by sequentially stacking. The main material of the pads is a copper layer or an aluminum layer, the main material of the insulating layer is an ALN, or AL2O3, or Si3N4, or a combination of several materials, and the main material of the heat dissipation layer is a copper layer or an aluminum layer. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads and an insulating layer disposed below the pads. The main material of the insulating layer is an ALN ​​ceramic insulating layer or AL2O3. The substrate 2 may be constructed with a ceramic insulating layer or a Si3N4 ceramic insulating layer. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the insulating layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may be formed solely of solder pads. In this case, the substrate 2 is disposed within the molding compound 1, and the molding compound 1 completely encapsulates the substrate 2. The specific structural form of the substrate 2 can be adjusted according to the specific requirements and application environment of the semiconductor device 100.

[0087] The circuit board assembly according to the present invention may mainly include the semiconductor device 100 described above. Specifically, since the semiconductor device 100 has a more reliable structure and good heat dissipation and operating performance, applying the semiconductor device 100 to the circuit board assembly can prevent the circuit board assembly from generating local overheating problems and improve the operating performance of the circuit board assembly.

[0088] The electrical control box according to the present invention may mainly include the aforementioned circuit board assembly. Specifically, since the circuit board assembly has a more reliable structure and good working performance, applying the circuit board assembly to the electrical control box can improve the working performance of the electrical control box and extend its service life.

[0089] The electrical device according to the present invention may mainly include: the aforementioned electrical control box. Specifically, since the electrical control box has a more reliable structure and good working performance, applying the electrical control box to the electrical device can improve the working performance and quality of the electrical device.

[0090] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0091] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0092] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a lateral direction, a longitudinal direction, and a vertical direction, wherein the lateral direction, the longitudinal direction, and the vertical direction are perpendicular to each other, and the semiconductor device includes: Plastic encapsulation; A substrate, at least partially disposed within the molding compound, the substrate comprising a first inverter power pad portion, a second inverter power pad portion, and a PFC (power factor correction) power pad portion spaced apart laterally, a first inverter low-side power chip and a first inverter high-side power chip spaced apart on the first inverter power pad portion, and a second inverter low-side power chip and a second inverter high-side power chip spaced apart on the second inverter power pad portion; A drive-side pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame extends at least partially from the molding compound. The drive-side pin frame includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart laterally. The first inverter drive pin frame corresponds at least partially to a first inverter power pad portion in the longitudinal direction. The second inverter drive pin frame corresponds at least partially to a second inverter power pad portion in the longitudinal direction. The PFC drive pin frame corresponds to the PFC (Power Factor Correction) pad portion. The power pads are at least partially corresponding in the vertical direction. The first inverter drive pin frame is provided with a first inverter high-side drive chip and a first inverter low-side drive chip spaced apart from each other. The first inverter high-side drive chip is electrically connected to the first inverter high-side power chip, and the first inverter low-side drive chip is electrically connected to the first inverter low-side power chip. The second inverter drive pin frame is provided with a second inverter high-side drive chip and a second inverter low-side drive chip spaced apart from each other. The second inverter high-side drive chip is electrically connected to the second inverter high-side power chip, and the second inverter low-side drive chip is electrically connected to the second inverter low-side power chip. The side of the first inverter low-side drive chip that is laterally adjacent to the first inverter high-side drive chip is defined as the boundary of the first inverter low-side drive chip, and the side of the first inverter high-side drive chip that is laterally adjacent to the first inverter low-side drive chip is defined as the boundary of the first inverter high-side drive chip. The lateral distance between the boundary of the first inverter low-side drive chip and the boundary of the first inverter high-side drive chip is L1. The side of the second inverter low-side drive chip that is laterally away from the second inverter high-side drive chip is defined as the boundary of the second inverter low-side drive chip. The side of the second inverter high-side drive chip that is laterally adjacent to the second inverter low-side drive chip is defined as the boundary of the second inverter high-side drive chip. The lateral distance between the boundary of the second inverter low-side drive chip and the boundary of the second inverter high-side drive chip is L2. L1 and L2 satisfy the relationship: L1 < L2.

2. The semiconductor device according to claim 1, characterized in that, There are three of each of the first inverter high-side power chips and the first inverter low-side power chips. The three first inverter low-side power chips are respectively a first inverter low-side power first chip, a first inverter low-side power second chip, and a first inverter low-side power third chip. The three first inverter high-side power chips are respectively a first inverter high-side power first chip, a first inverter high-side power second chip, and a first inverter high-side power third chip. The first inverter low-side power first chip, the first inverter low-side power second chip, the first inverter low-side power third chip, the first inverter high-side power first chip, the first inverter high-side power second chip, and the first inverter high-side power third chip are arranged in a horizontally spaced manner. Compared with the first inverter low-side power chips, the first inverter high-side power chips are more closely adjacent to the second inverter power pad portion in the horizontal direction. There is one first inverter high-side drive chip and one first inverter low-side drive chip. The first inverter low-side drive chip and the first inverter high-side drive chip are arranged horizontally at intervals. Compared with the first inverter low-side drive chip, the first inverter high-side drive chip is more horizontally adjacent to the second inverter drive pin frame. A plane perpendicular to the vertical direction is defined as the first projection plane. The longitudinal extension region of the orthographic projection of the first inverter low-side drive chip on the first projection plane is laterally spaced between the orthographic projection of the first inverter low-side power first chip on the first projection plane and the orthographic projection of the first inverter low-side power third chip on the first projection plane. The longitudinal extension region of the orthographic projection of the first inverter low-side drive chip on the first projection plane at least partially overlaps with the orthographic projection of the first inverter low-side power second chip on the first projection plane. The longitudinal extension region of the orthographic projection of the first inverter high-side drive chip on the first projection surface is spaced apart from the side of the orthographic projection of the first inverter low-side power first chip on the first projection surface that is laterally away from the first inverter low-side drive chip. The longitudinal extension region of the orthographic projection of the first inverter high-side drive chip on the first projection surface at least partially overlaps with the orthographic projection of the first inverter low-side power second chip on the first projection surface and / or the orthographic projection of the first inverter low-side power third chip on the first projection surface.

3. The semiconductor device according to claim 1, characterized in that, The first inverter drive pin frame includes a ground pin of a first inverter drive chip. The ground pin of the first inverter drive chip protrudes at least partially toward the side that is longitudinally away from the substrate to form a first inverter low-side drive chip pad and a first inverter high-side drive chip pad that are spaced apart in the lateral direction. The first inverter low-side drive chip and the first inverter high-side drive chip pad are respectively disposed on the first inverter low-side drive chip pad and the first inverter high-side drive chip pad. The first inverter low-side driver chip pad and the first inverter high-side driver chip pad are respectively disposed on both sides of the horizontal middle part of the first inverter driver pin frame; The center of the first inverter low-side driver chip is offset laterally relative to the center of the first inverter low-side driver chip pad towards the side closer to the first inverter high-side driver chip, and the center of the first inverter high-side driver chip is offset laterally relative to the center of the first inverter high-side driver chip pad towards the side farther away from the first inverter low-side driver chip.

4. The semiconductor device according to claim 2, characterized in that, There are three of each of the second inverter low-side power chips. The three second inverter low-side power chips are respectively a second inverter low-side power first chip, a second inverter low-side power second chip, and a second inverter low-side power third chip. The three second inverter high-side power chips are respectively a second inverter high-side power first chip, a second inverter high-side power second chip, and a second inverter high-side power third chip. The second inverter low-side power first chip, the second inverter low-side power second chip, the second inverter low-side power third chip, the second inverter high-side power first chip, the second inverter high-side power second chip, and the second inverter high-side power third chip are arranged sequentially at intervals in the horizontal direction. Compared with the second inverter low-side power chips, the second inverter high-side power chips are more closely adjacent to the PFC power pad portion in the horizontal direction. There is one second inverter high-side driver chip and one second inverter low-side driver chip. The second inverter low-side driver chip and the second inverter high-side driver chip are arranged horizontally at intervals. Compared with the second inverter low-side driver chip, the second inverter high-side driver chip is more horizontally adjacent to the PFC driver pin frame. The longitudinal extension region of the orthographic projection of the second inverter low-side drive chip on the first projection surface is laterally spaced between the orthographic projection of the second inverter low-side power first chip on the first projection surface and the orthographic projection of the second inverter low-side power third chip on the first projection surface. The longitudinal extension region of the orthographic projection of the second inverter low-side drive chip on the first projection surface at least partially overlaps with the orthographic projection of the second inverter low-side power second chip on the first projection surface. The longitudinally extending region of the orthographic projection of the second inverter high-side drive chip on the first projection plane is spaced apart from the side of the orthographic projection of the second inverter high-side power first chip on the first projection plane that is laterally away from the second inverter low-side drive chip. The longitudinally extending region of the orthographic projection of the second inverter high-side drive chip on the first projection plane and the orthographic projection of the second inverter high-side power second chip on the first projection plane and / or the orthographic projection of the second inverter high-side power third chip on the first projection plane all at least partially overlap with each other.

5. The semiconductor device according to claim 1, characterized in that, The second inverter drive pin frame includes a second inverter drive chip ground pin, which is at least partially protruding toward the side longitudinally away from the substrate to form a second inverter low-side drive chip pad and a second inverter high-side drive chip pad spaced apart laterally. The second inverter low-side drive chip and the second inverter high-side drive chip pad are respectively disposed on the second inverter low-side drive chip pad and the second inverter high-side drive chip pad. The second inverter low-side driver chip is located laterally in the middle of the pads of the second inverter low-side driver chip; or The second inverter low-side driver chip is located horizontally in the middle right of the pad of the second inverter low-side driver chip; The center of the second inverter high-side driver chip is offset laterally relative to the center of the pad of the second inverter high-side driver chip towards the side closer to the second inverter low-side driver chip.

6. The semiconductor device according to claim 1, characterized in that, The lateral dimension of the first inverter power pad is smaller than the lateral dimension of the second inverter power pad.

7. The semiconductor device according to claim 1, characterized in that, The side of the first inverter low-side driver chip pad that is horizontally adjacent to the first inverter high-side driver chip pad is defined as the boundary of the first inverter low-side driver pad. The boundary of the first inverter low-side driver pad extends vertically. The side of the first inverter high-side driver chip pad that is horizontally adjacent to the first inverter low-side driver chip pad is defined as the boundary of the first inverter high-side driver first pad. The boundary of the first inverter high-side driver first pad extends vertically. The horizontal distance between the boundary of the first inverter high-side driver first pad and the boundary of the first inverter low-side driver pad is L3. The side of the second inverter low-side driver chip pad that is laterally adjacent to the second inverter high-side driver chip pad is defined as the boundary of the second inverter low-side driver pad. The boundary of the second inverter low-side driver pad extends longitudinally. The side of the second inverter high-side driver chip pad that is laterally adjacent to the second inverter low-side driver chip pad is defined as the boundary of the second inverter high-side driver first pad. The boundary of the second inverter high-side driver first pad extends longitudinally. The lateral distance between the boundary of the second inverter high-side driver first pad and the boundary of the second inverter low-side driver pad is L4. L3 and L4 satisfy the relationship: L3 < L4.

8. The semiconductor device according to claim 1, characterized in that, The first inverter drive pin frame is defined as the side of the first inverter low-side drive chip pad that is laterally adjacent to it. The first inverter pin frame boundary extends longitudinally. The first inverter high-side drive chip pad is defined as the side of the first inverter high-side drive second pad that is laterally away from it. The first inverter high-side drive second pad boundary extends longitudinally. The lateral distance between the first inverter pin frame boundary and the first inverter high-side drive second pad boundary is L5. The second inverter drive pin frame is defined as the side of the second inverter low-side drive chip pad that is laterally adjacent to it. The second inverter pin frame boundary extends longitudinally. The second inverter high-side drive chip pad is defined as the side of the second inverter high-side drive second pad that is laterally away from it. The second inverter high-side drive second pad boundary extends longitudinally. The lateral distance between the second inverter pin frame boundary and the second inverter high-side drive second pad boundary is L6. L5 and L6 satisfy the relationship: L5 > L6.

9. The semiconductor device according to claim 1, characterized in that, The lateral dimension of the first inverter drive pin frame is equal to the lateral dimension of the second inverter drive pin frame.

10. The semiconductor device according to claim 1, characterized in that, The substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC (power factor correction) power pad portion. A plurality of rectifier chips are disposed on the rectifier bridge pad portion. The drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially corresponding to the rectifier bridge pad portion in the longitudinal direction. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion. The lateral dimension of the rectifier bridge pad is larger than the lateral dimension of the PFC (Power Factor Correction) power pad.

11. A circuit board assembly, characterized in that... The semiconductor device included in any one of claims 1-10.

12. An electrical control box, characterized in that, Includes the circuit board assembly as described in claim 11.

13. An electrical appliance, characterized in that, Includes the electrical control box as described in claim 12.

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