Semiconductor device, circuit board assembly, electric control box and electrical equipment

Abstract

The invention discloses a semiconductor device, a circuit board assembly, an electric control box and electrical equipment, the semiconductor device comprises a driving side pin frame, the driving side pin frame comprises a first inversion driving pin frame, a second inversion driving pin frame and a PFC driving pin frame, and the first inversion driving pin frame, the second inversion driving pin frame and the PFC driving pin frame are arranged at intervals in the transverse direction; the first inversion driving pin frame comprises a first inversion driving chip power supply voltage pin, the second inversion driving pin frame comprises a second inversion driving chip power supply voltage pin, and the PFC driving pin frame comprises a PFC driving chip power supply voltage pin. The first inversion driving chip power supply voltage pin, the second inversion driving chip power supply voltage pin and the PFC driving chip power supply voltage pin are mutually independent and are arranged at intervals in the transverse direction. Therefore, mutual interference among the functional parts can be reduced, and the anti-interference capability of the semiconductor device can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, circuit board assembly, electrical control box, and electrical equipment. Background Technology

[0002] Electronic control boards for equipment such as air conditioners and washing machines can be equipped with semiconductor devices such as intelligent power modules. However, existing intelligent power modules (IPMs) have limited functionality, only having an inverter function. Furthermore, the PFC in intelligent power modules operates at a very high frequency (typically 50K-100K), the compressor inverter has a relatively large operating current (typically 15A-30A), and the fan inverter has a relatively small operating current (typically 5A-15A). This makes the fan inverter susceptible to interference from the compressor inverter, PFC, and rectifier bridge, which have high current-carrying capacity. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a semiconductor device with enhanced anti-interference capability.

[0004] Another object of the present invention is to provide a circuit board assembly.

[0005] Another object of the present invention is to provide an electrical control box.

[0006] Another object of the present invention is to provide an electrical device.

[0007] A semiconductor device according to an embodiment of the present invention has a lateral direction, a longitudinal direction, and a vertical direction, wherein the lateral direction, the longitudinal direction, and the vertical direction are perpendicular to each other, and includes: a molding compound; a substrate, wherein the substrate is at least partially disposed within the molding compound, the substrate including a first inverter power pad portion, a second inverter power pad portion, and a PFC (Power Factor Correction) power pad portion disposed laterally at intervals in the lateral direction, wherein a first inverter power chip, a second inverter power chip, and a PFC power chip are respectively disposed on the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion. A drive-side pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart laterally. The first inverter drive pin frame at least partially corresponds to a first inverter power pad portion in the longitudinal direction. The second inverter drive pin frame and the second inverter power pad portion at least partially correspond to each other in the longitudinal direction. The PFC power pad portion and the PFC drive pin frame... The components are at least partially corresponding in the vertical direction; a first inverter driver chip, a second inverter driver chip, and a PFC driver chip are respectively disposed on the first inverter driver pin frame, the second inverter driver pin frame, and the PFC driver pin frame. The first inverter driver chip is electrically connected to the first inverter power chip, the second inverter driver chip is electrically connected to the second inverter power chip, and the PFC driver chip is electrically connected to the PFC power chip. The first inverter driver pin frame includes a first inverter driver chip power supply voltage pin, which is electrically connected to the first inverter driver chip. The second inverter driver pin frame includes a second inverter driver chip power supply voltage pin, which is electrically connected to the second inverter driver chip. The PFC driver pin frame includes a PFC driver chip power supply voltage pin, which is electrically connected to the PFC driver chip. The first inverter driver chip power supply voltage pin, the second inverter driver chip power supply voltage pin, and the PFC driver chip power supply voltage pin are independent of each other and spaced apart in the horizontal direction.

[0008] Therefore, by arranging the power supply voltage pins of the first inverter driver chip, the second inverter driver chip, and the PFC driver chip separately on the driver-side pin frame, mutual interference between the various functional units can be reduced, thereby improving the anti-interference capability of the semiconductor device.

[0009] In some examples of the present invention, the second inverter driver chip includes a second inverter high-side driver chip and a second inverter low-side driver chip, which are laterally spaced. The power supply voltage pins of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin and a second inverter low-side gate drive power supply voltage pin, which are independent of each other and laterally spaced. The second inverter high-side gate drive power supply voltage pin is electrically connected to the second inverter high-side driver chip, and the second inverter low-side gate drive power supply voltage pin is electrically connected to the second inverter low-side driver chip.

[0010] In some examples of the present invention, the second inverter high-side gate drive supply voltage pin includes a second inverter first high-side supply voltage pin portion, a second inverter second high-side supply voltage pin portion, and a second inverter third high-side supply voltage pin portion. The second inverter first high-side supply voltage pin portion extends laterally. The second inverter second high-side supply voltage pin portion and the second inverter third high-side supply voltage pin portion are respectively disposed at both ends of the second inverter first high-side supply voltage pin portion laterally. Both the second inverter second high-side supply voltage pin portion and the second inverter third high-side supply voltage pin portion extend longitudinally away from the substrate. The second inverter second high-side supply voltage pin portion is laterally closer to the PFC drive pin frame than the second inverter third high-side supply voltage pin portion. The PFC drive chip supply voltage pin extends longitudinally and is spaced apart from the second inverter second high-side supply voltage pin portion on the side laterally away from the first inverter drive pin frame. The second inverter low-side gate drive supply voltage pin is spaced apart from the second inverter third high-side supply voltage pin portion on the side laterally away from the PFC drive pin frame.

[0011] In some examples of the present invention, the second inverter drive pin frame includes a second inverter drive chip ground pin, the second inverter drive chip ground pin including a second inverter first ground pin portion, a second inverter second ground pin portion and a second inverter third ground pin portion, the second inverter first ground pin portion extending laterally and at least partially protruding along a longitudinal direction away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad spaced apart laterally, the second inverter high-side drive chip disposed on the second inverter high-side drive pad, the second inverter low-side drive chip disposed on the second inverter low-side drive pad; the second inverter first ground pin portion spaced apart from the second inverter first high-side power supply voltage pin portion along a longitudinal direction towards the substrate, the second inverter first ground pin portion extending laterally, the second inverter second ground pin portion and the... The second inverter third ground pin is respectively disposed at both ends of the second inverter first ground pin and extends longitudinally away from the substrate. The second inverter second ground pin is horizontally spaced between the second inverter second high-side power supply voltage pin and the PFC driver chip power supply voltage pin. The second inverter third ground pin is vertically spaced between the second inverter third high-side power supply voltage pin and the first inverter drive pin frame. The second inverter driver chip ground pin also includes a second inverter separator pin. One end of the second inverter separator pin is connected to the second inverter first ground pin, and the other end extends longitudinally away from the substrate. The second inverter separator pin is horizontally spaced between the second inverter high-side gate drive power supply voltage pin and the second inverter low-side gate drive power supply voltage pin.

[0012] In some examples of the present invention, the first inverter driver chip includes a first inverter high-side driver chip and a first inverter low-side driver chip, which are laterally spaced. The first inverter driver chip power supply voltage pins include a first inverter high-side gate drive power supply voltage pin and a first inverter low-side gate drive power supply voltage pin, which are independent of each other and laterally spaced. The first inverter high-side gate drive power supply voltage pin is electrically connected to the first inverter high-side driver chip, and the first inverter low-side gate drive power supply voltage pin is electrically connected to the first inverter low-side driver chip.

[0013] In some examples of the present invention, the first inverter high-side gate drive supply voltage pin includes a first inverter first high-side supply voltage pin portion, a first inverter second high-side supply voltage pin portion, and a first inverter third high-side supply voltage pin portion. The first inverter first high-side supply voltage pin portion extends laterally. The first inverter second high-side supply voltage pin portion and the first inverter third high-side supply voltage pin portion are respectively disposed at both ends of the first inverter first high-side supply voltage pin portion laterally. The first inverter second high-side supply voltage pin portion and the first inverter third high-side supply voltage pin portion both extend longitudinally away from the substrate. The first inverter second high-side supply voltage pin portion is laterally closer to the second inverter drive pin frame than the first inverter third high-side supply voltage pin portion. The second inverter drive chip supply voltage pin is spaced apart from the first inverter second high-side supply voltage pin portion on the side laterally away from the first inverter third high-side supply voltage pin portion. The first inverter low-side gate drive supply voltage pin is spaced apart from the first inverter third high-side supply voltage pin portion on the side laterally away from the second inverter drive pin frame.

[0014] In some embodiments of the present invention, the first inverter drive pin frame includes a first inverter drive chip ground pin, the first inverter drive chip ground pin including a first inverter first ground pin portion, a first inverter second ground pin portion, and a first inverter third ground pin portion. The first inverter first ground pin portion extends laterally and at least partially protrudes along a longitudinal direction away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad that are laterally spaced apart. The first inverter high-side drive chip is disposed on the first inverter high-side drive pad, and the first inverter low-side drive chip is disposed on the first inverter low-side drive pad. The first inverter first ground pin portion is spaced apart from the first inverter first high-side power supply voltage pin portion along a longitudinal direction towards the substrate. The first inverter second ground pin portion and the first inverter third ground pin portion are respectively... The first inverter first ground pin is disposed at both ends laterally and extends toward the side facing away from the substrate. The first inverter second ground pin is disposed laterally between the first inverter second high-side power supply voltage pin and the second inverter driver chip power supply voltage pin. The first inverter third ground pin is disposed laterally between the first inverter third high-side power supply voltage pin and the side facing away from the second inverter driver pin frame. The first inverter driver chip ground pin also includes a first inverter separator pin. One end of the first inverter separator pin is connected to the first inverter first ground pin, and the other end extends toward the side facing away from the substrate. The first inverter separator pin is disposed laterally between the first inverter high-side gate drive power supply voltage pin and the first inverter low-side gate drive power supply voltage pin.

[0015] In some examples of the present invention, the second inverter driver chip includes a second inverter high-side driver chip and a second inverter low-side driver chip, which are spaced apart laterally. The power supply voltage pins of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin and a second inverter low-side gate drive power supply voltage pin. The second inverter high-side gate drive power supply voltage pin and the second inverter low-side gate drive power supply voltage pin are interconnected. The second inverter high-side gate drive power supply voltage pin is electrically connected to the second inverter high-side driver chip, and the second inverter low-side gate drive power supply voltage pin is electrically connected to the second inverter low-side driver chip.

[0016] In some embodiments of the present invention, the second inverter high-side gate drive supply voltage pin includes a second inverter first high-side supply voltage pin portion and a second inverter second high-side supply voltage pin portion. The second inverter first high-side supply voltage pin portion extends laterally, and the second inverter second high-side supply voltage pin portion is disposed at one end of the second inverter first high-side supply voltage pin portion that is laterally closer to the PFC drive pin frame. The second inverter second high-side supply voltage pin portion extends longitudinally away from the substrate. The PFC drive chip supply voltage pins extend longitudinally and are spaced apart from the second inverter second high-side supply voltage pin portion. The second inverter low-side gate drive supply voltage pin includes a second inverter first low-side supply voltage pin portion and a second inverter second low-side supply voltage pin portion. The second inverter first low-side supply voltage pin portion extends longitudinally. One end of the second inverter second low-side supply voltage pin portion is connected to the end of the second inverter first low-side supply voltage pin portion that is longitudinally adjacent to the substrate and extends laterally. The other end of the second inverter second low-side supply voltage pin portion is connected to the end of the second inverter first high-side supply voltage pin portion that is laterally away from the PFC drive pin frame.

[0017] In some examples of the present invention, the second inverter drive pin frame further includes a second inverter power supply support pin, one end of which is connected to the connection between the second inverter first high-side power supply voltage pin portion and the second inverter second low-side power supply voltage pin portion, and the other end of which extends longitudinally away from the substrate.

[0018] In some embodiments of the present invention, the second inverter drive pin frame includes a second inverter drive chip ground pin, the second inverter drive chip ground pin including a second inverter first ground pin portion, a second inverter second ground pin portion, and a second inverter third ground pin portion, the second inverter first ground pin portion extending laterally and at least partially protruding along a side longitudinally away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad spaced laterally apart, the second inverter high-side drive chip disposed on the second inverter high-side drive pad, and the second inverter low-side drive chip disposed on the second inverter low-side drive pad; the second inverter The first ground pin extends laterally. The second inverter second ground pin and the second inverter third ground pin are respectively disposed at both ends of the second inverter first ground pin and both extend toward the side facing away from the substrate in the longitudinal direction. The second inverter second low-side power supply voltage pin and the second inverter first high-side power supply voltage pin are spaced apart on the side of the second inverter first ground pin facing away from the substrate in the longitudinal direction. The second inverter third ground pin, the second inverter first low-side power supply voltage pin, the second inverter power supply support pin, and the second inverter second high-side power supply voltage pin are arranged in a laterally spaced manner.

[0019] In some examples of the present invention, the second inverter drive pin frame further includes a second inverter ground support pin, one end of which is connected to the second inverter first ground pin portion and extends longitudinally toward the substrate. The second inverter ground support pin is connected to the second inverter power pad portion. A plane perpendicular to the vertical direction is set as a first projection plane. The orthographic projection of the second inverter ground support pin on the first projection plane is laterally spaced between the orthographic projection of the second inverter high-side drive chip on the first projection plane and the orthographic projection of the second inverter low-side drive chip on the first projection plane.

[0020] In some examples of the present invention, the first inverter driver chip includes a first inverter high-side driver chip and a first inverter low-side driver chip, which are spaced apart laterally. The power supply voltage pins of the first inverter driver chip include a first inverter high-side gate drive power supply voltage pin and a first inverter low-side gate drive power supply voltage pin, which are interconnected. The first inverter high-side gate drive power supply voltage pin is electrically connected to the first inverter high-side driver chip, and the first inverter low-side gate drive power supply voltage pin is electrically connected to the first inverter low-side driver chip.

[0021] In some examples of the present invention, the first inverter high-side gate drive supply voltage pin includes a first inverter first high-side supply voltage pin portion and a first inverter second high-side supply voltage pin portion. The first inverter first high-side supply voltage pin portion extends laterally, and the first inverter second high-side supply voltage pin portion is disposed at one end of the first inverter first high-side supply voltage pin portion laterally adjacent to one end of the second inverter drive pin frame. The first inverter second high-side supply voltage pin portion extends longitudinally away from the substrate. The second inverter drive chip supply voltage pin and the first inverter second high-side supply voltage pin portion are laterally spaced apart. The first inverter low-side gate drive supply voltage pin also includes a first inverter first low-side supply voltage pin portion and a first inverter second low-side supply voltage pin portion. The first inverter first low-side supply voltage pin portion extends longitudinally, and one end of the first inverter second low-side supply voltage pin portion is connected to the end of the first inverter first low-side supply voltage pin portion longitudinally adjacent to the substrate and extends laterally. The other end of the first inverter second low-side supply voltage pin portion is connected to the first inverter first high-side supply voltage pin portion.

[0022] In some examples of the present invention, the first inverter drive pin frame further includes a first inverter power supply support pin, one end of which is connected to the connection between the first inverter first high-side power supply voltage pin portion and the first inverter second low-side power supply voltage pin portion, and the other end of which extends longitudinally away from the substrate.

[0023] In some embodiments of the present invention, the first inverter drive pin frame includes a first inverter drive chip ground pin, the first inverter drive chip ground pin including a first inverter first ground pin portion, a first inverter second ground pin portion and a first inverter third ground pin portion, the first inverter first ground pin portion extending laterally and at least partially protruding along a side longitudinally away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad spaced apart laterally, the first inverter high-side drive chip disposed on the first inverter high-side drive pad, and the first inverter low-side drive chip disposed on the first inverter low-side drive pad; the first inverter The first ground pin extends laterally. The first inverter second ground pin and the first inverter third ground pin are respectively disposed at both ends of the first inverter first ground pin and both extend toward the side facing away from the substrate in the longitudinal direction. The first inverter second low-side power supply voltage pin and the first inverter first high-side power supply voltage pin are spaced apart on the side of the first inverter first ground pin facing away from the substrate in the longitudinal direction. The first inverter third ground pin, the first inverter first low-side power supply voltage pin, the first inverter power supply support pin and the first inverter second high-side power supply voltage pin are arranged in a sequentially spaced manner in the lateral direction.

[0024] In some embodiments of the present invention, the PFC driver pin frame further includes a PFC driver chip ground pin. The PFC driver chip ground pin includes a PFC ground pin portion and a PFC driver pad portion. The PFC ground pin portion extends longitudinally, and the PFC driver pad portion is disposed at one end of the PFC ground pin portion longitudinally adjacent to the substrate. The PFC driver pad portion protrudes laterally from the PFC ground pin portion toward the side adjacent to the second inverter driver pin frame. The PFC driver chip is disposed on the PFC driver pad portion, and the PFC driver chip power supply voltage pin is... The PFC driver chip power supply voltage pins are arranged longitudinally and laterally at intervals on the side of the PFC driver pad portion facing the PFC driver pad portion, and the PFC driver pad portion is arranged longitudinally at intervals on the side of the PFC driver pad portion away from the substrate. The side of the PFC driver pad portion laterally away from the PFC driver pin portion is provided with a clearance notch. The clearance notch is located at one end of the PFC driver pad portion longitudinally adjacent to the PFC driver chip power supply voltage pins. The clearance notch is adapted to avoid at least a portion of the PFC driver chip power supply voltage pins longitudinally adjacent to the end of the substrate.

[0025] In some examples of the present invention, the substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion, and a rectifier chip is disposed on the rectifier bridge pad portion; the drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially corresponding to the rectifier bridge pad portion in the longitudinal direction, and the rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion.

[0026] In some examples of the present invention, the lateral direction includes a first direction and a second direction, the first direction and the second direction are arranged in opposite directions, and the first inverter power pad, the second inverter power pad, the PFC power pad and the rectifier bridge pad are arranged sequentially in the first direction; or the rectifier bridge pad, the PFC power pad, the first inverter power pad and the second inverter power pad are arranged sequentially in the first direction; or the first inverter power pad, the second inverter power pad, the rectifier bridge pad and the PFC power pad are arranged sequentially in the first direction.

[0027] The circuit board assembly according to an embodiment of the present invention includes the semiconductor device described above.

[0028] The electrical control box according to an embodiment of the present invention includes the circuit board assembly described above.

[0029] The electrical equipment according to an embodiment of the present invention includes the electrical control box described above.

[0030] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0031] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 4 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 5 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 6 This is a partial schematic diagram of a semiconductor device according to other embodiments of the present invention; Figure 7 This is a partial schematic diagram of a semiconductor device according to some embodiments of the present invention; Figure 8 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0032] Figure label: 100. Semiconductor devices; 1. Plastic encapsulation; 2. Substrate; 201. First inverter power pad; 2011. First inverter power chip; 202. Second inverter power pad; 2021. Second inverter power chip; 203. PFC power pad; 2031. PFC power chip; 204. Rectifier bridge pad; 2041. Rectifier chip; 3. Driver-side pin frame; 301, First inverter drive pin frame; 3011, First inverter drive chip; 30111, First inverter high-side drive chip; 30112, First inverter low-side drive chip; 3012, First inverter driver chip power supply voltage pin; 30121, First inverter high-side gate drive power supply voltage pin; 301211, First inverter first high-side power supply voltage pin section; 301212, First inverter second high-side power supply voltage pin section; 301213, First inverter third high-side power supply voltage pin section; 30122, First inverter low-side gate drive power supply voltage pin; 301221, First inverter first low-side power supply voltage pin section; 301222, First inverter second low-side power supply voltage pin section; 3013, Ground pin of the first inverter driver chip; 30131, First ground pin of the first inverter; 301311, High-side drive pad of the first inverter; 301312, Low-side drive pad of the first inverter; 30132, Second ground pin of the first inverter; 30133, Third ground pin of the first inverter; 30134, Separator pin of the first inverter; 3014, First inverter power supply support pin; 302, Second inverter drive pin frame; 3021, Second inverter drive chip; 30211, Second inverter high-side drive chip; 30212, Second inverter low-side drive chip; 3022, Power supply voltage pin of the second inverter driver chip; 30221, Second inverter high-side gate drive power supply voltage pin; 302211, Second inverter first high-side power supply voltage pin section; 302212, Second inverter second high-side power supply voltage pin section; 302213, Second inverter third high-side power supply voltage pin section; 30222, Second inverter low-side gate drive power supply voltage pin; 302221, Second inverter first low-side power supply voltage pin section; 302222, Second inverter second low-side power supply voltage pin section; 3023, Ground pin of the second inverter driver chip; 30231, First ground pin of the second inverter; 302311, High-side drive pad of the second inverter; 302312, Low-side drive pad of the second inverter; 30232, Second ground pin of the second inverter; 30233, Third ground pin of the second inverter; 30234, Separator pin of the second inverter; 3024, Second inverter power supply support pin; 3025, Second inverter ground support pin; 303, PFC driver pin frame; 3031, PFC driver chip; 3032, PFC driver chip power supply voltage pin; 3033, PFC driver chip ground pin; 30331, PFC ground pin section; 30332, PFC driver pad section; 303321, clearance notch; 304. Rectifier bridge driver pin frame. Detailed Implementation

[0033] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0034] The following is for reference. Figures 1-8 A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 has a lateral direction, a longitudinal direction, and a vertical direction, and the lateral direction, the longitudinal direction, and the vertical direction are perpendicular to each other.

[0035] In some embodiments of the present invention, combined with Figures 1-5 As shown, the semiconductor device 100 according to the present invention may mainly include: a molding compound 1, a substrate 2, and a drive-side pin frame 3. The substrate 2 is at least partially disposed within the molding compound 1. Specifically, the substrate 2 can be encapsulated by the molding compound 1, or the substrate 2 may be partially included by the molding compound 1 and partially exposed on the surface of the molding compound 1. The drive-side pin frame 3 is at least partially disposed within the molding compound 1 and partially extends out of the molding compound 1 for electrical connection with external components. The molding compound 1 can protect the stability of the substrate 2 and the drive-side pin frame 3 within the semiconductor device 100 and provide electrical insulation from the outside, thus ensuring the structural reliability of the semiconductor device 100.

[0036] In some embodiments of the present invention, the substrate 2 may include pads and an insulating heat dissipation layer disposed below the pads. The insulating heat dissipation layer is mainly formed by sequentially stacking an insulating resin sheet and a copper layer, or by sequentially stacking an insulating resin sheet and an aluminum layer. The main material of the pads is copper or aluminum. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the copper layer or the outer surface of the aluminum layer in the insulating heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads, an insulating layer, and a heat dissipation layer sequentially stacked. The main material of the pads is a copper layer or an aluminum layer, and the main material of the insulating layer is AlN, Al2O3, or Si3N. 4. A ceramic insulating layer composed of one or more materials, with the main material of the heat dissipation layer being a copper or aluminum layer. In this case, the substrate 2 is mostly encapsulated by the molding compound 1, and the outer surface of the heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads and an insulating layer disposed below the pads, wherein the main material of the insulating layer is an AlN ceramic insulating layer, an Al2O3 ceramic insulating layer, or a Si3N4 ceramic insulating layer. In this case, the substrate 2 is mostly encapsulated by the molding compound 1, and the outer surface of the insulating layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may be formed solely of pads. In this case, the substrate 2 is disposed within the molding compound 1, and the molding compound 1 completely encapsulates the substrate 2. The specific structural form of the substrate 2 can be adjusted according to the specific requirements and application environment of the semiconductor device 100.

[0037] It should be noted that, in some embodiments of the present invention, the substrate 2, the drive-side pin frame 3, and the power-side pins can also be constructed as a single integrated frame. This configuration, on the one hand, makes the substrate 2, drive-side pin frame 3, and power-side pins integral, which facilitates the packaging of the integrated frame with other components, thereby improving the assembly efficiency of the semiconductor device 100. On the other hand, it improves the overall structural strength of the substrate 2, drive-side pin frame 3, and power-side pins, thereby extending the service life of the semiconductor device 100.

[0038] Furthermore, the substrate 2 includes a first inverter power pad portion 201, a second inverter power pad portion 202, and a PFC power pad portion 203 arranged laterally at intervals. This ensures that the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203 are arranged relatively independently on the substrate 2. The first inverter power pad portion 201 is provided with a first inverter power chip 2011, the second inverter power pad portion 202 is provided with a second inverter power chip 2021, and the PFC power pad portion 203 is provided with a PFC power chip 2031.

[0039] In some embodiments of the present invention, one of the first inverter power pad portion 201 and the second inverter power pad portion 202 is a fan power pad portion and the other is a compressor power pad portion.

[0040] In some other embodiments of the present invention, the first inverter power pad portion 201 and the second inverter power pad portion 202 are both motor power pad portions.

[0041] In embodiments of the present invention, multiple inverter power chips constitute an inverter circuit, for example, a three-phase inverter bridge circuit can be composed of six inverter power chips. The three-phase inverter bridge circuit includes three-phase upper bridge arm inverter power chips and three-phase lower bridge arm inverter power chips. The inverter power chips can be composed of insulated gate bipolar transistors (IGBTs) and freewheeling diodes (FRDs), or they can be metal-oxide-semiconductor field-effect transistors (MOS), or they can be RC-IGBTs (reverse-conducting IGBTs that integrate the IGBT and freewheeling diode into a single chip).

[0042] Furthermore, the drive-side pin frame 3 is spaced apart on one side of the longitudinal direction of the substrate 2, so that the drive-side pin frame 3 can be disposed adjacent to the substrate 2 to facilitate the electrical connection between the drive-side pin frame 3 and the substrate 2.

[0043] Furthermore, the drive-side pin frame 3 can be completely spaced apart from the substrate 2 in the vertical direction, thereby reducing the impact of heat transferred from the substrate 2 on the drive chip; the drive-side pin frame 3 can also be partially protruded in the vertical direction to form a connecting rod and connect with the substrate 2, thereby improving the stability of the substrate 2. At the same time, most of the drive-side pin frame 3 is spaced apart from the substrate 2 in the vertical direction, thereby balancing the improvement of the stability of the substrate 2 and the reduction of the impact of heat transferred from the substrate 2 on the drive chip.

[0044] Furthermore, the drive-side pin frame 3 includes a first inverter drive pin frame 301, a second inverter drive pin frame 302, and a PFC drive pin frame 303, which are spaced apart laterally. The first inverter drive pin frame 301 corresponds at least partially to the first inverter power pad portion 201 in the vertical direction, thus facilitating electrical connection between the first inverter drive pin frame 301 and the first inverter power chip 2011 on the first inverter power pad portion 201. The second inverter drive pin frame 302 corresponds at least partially to the second inverter power pad portion 202 in the vertical direction, thus facilitating electrical connection between the second inverter drive pin frame 302 and the second inverter power chip 2021 on the second inverter power pad portion 202. The PFC power pad portion 203 corresponds at least partially to the PFC drive pin frame 303 in the vertical direction, thus facilitating electrical connection between the PFC drive pin frame 303 and the PFC power chip 2031 on the PFC power pad portion 203.

[0045] Furthermore, a first inverter driver chip 3011, a second inverter driver chip 3021, and a PFC driver chip 3031 are respectively disposed on the first inverter driver pin frame 301, the second inverter driver pin frame 302, and the PFC driver pin frame 303. The first inverter driver chip 3011 is electrically connected to the first inverter power chip 2011, enabling the first inverter driver chip 3011 to drive the first inverter power chip 2011 to operate normally. The second inverter driver chip 3021 is electrically connected to the second inverter power chip 2021, enabling the second inverter driver chip 3021 to drive the second inverter power chip 2021 to operate normally. The PFC driver chip 3031 is electrically connected to the PFC power chip 2031, enabling the PFC driver chip 3031 to drive the PFC power chip 2031 to operate normally.

[0046] In an embodiment of the present invention, the PFC power chip 2031 includes a PFC power switch chip and a PFC diode. The PFC power switch and PFC diode are components of the PFC circuit, which adjusts the power factor of the DC power supply and outputs the adjusted DC power. The PFC power switch chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT (a reverse-conducting IGBT that integrates the IGBT and freewheeling diode onto a single chip).

[0047] Furthermore, the first inverter drive pin frame 301 includes a first inverter drive chip power supply voltage pin 3012, which is electrically connected to the first inverter drive chip 3011. Thus, the first inverter drive pin frame 301, the first inverter drive chip 3011, and the first inverter power chip 2011 are electrically connected, and the first inverter power pad portion 201 has a relatively small operating current in the semiconductor device 100.

[0048] The second inverter drive pin frame 302 includes a second inverter drive chip power supply voltage pin 3022, which is electrically connected to the second inverter drive chip 3021. Thus, the second inverter drive pin frame 302, the second inverter drive chip 3021, and the second inverter power chip 2021 are electrically connected, and the second inverter power pad portion 202 has a large operating current in the semiconductor device 100.

[0049] The PFC driver pin frame 303 includes a PFC driver chip power supply voltage pin 3032, which is electrically connected to the PFC driver chip 3031. Thus, the PFC driver pin frame 303, the PFC driver chip 3031, and the PFC power chip 2031 are electrically connected, and the PFC power pad portion 203 has a large operating current in the semiconductor device 100.

[0050] In the prior art, the power supply and ground of the first inverter power pad section 201, the second inverter power pad section 202 and the PFC power pad section 203 are in a common terminal frame structure. The EMC (electromagnetic compatibility) interference path is mainly coupled through the power supply and ground. The higher frequency PFC power pad section 203 and the second inverter power pad section 202 are more likely to affect the lower frequency first inverter power pad section 201.

[0051] In an embodiment of the present invention, by setting the first inverter driver chip power supply voltage pin 3012, the second inverter driver chip power supply voltage pin 3022, and the PFC driver chip power supply voltage pin 3032 to be independent of each other and spaced apart in the lateral direction, the first inverter driver chip power supply voltage pin 3012, the second inverter driver chip power supply voltage pin 3022, and the PFC driver chip power supply voltage pin 3032 can be separated, thereby effectively disconnecting the coupling interference path and improving the anti-interference capability of the semiconductor device 100.

[0052] In embodiments of the present invention, combined with Figure 4 As shown, the second inverter driver chip 3021 includes a second inverter high-side driver chip 30211 and a second inverter low-side driver chip 30212. The second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212 are arranged horizontally at a distance. The power supply voltage pins 3022 of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin 30221 and a second inverter low-side gate drive power supply voltage pin 30222. The second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222 are independent of each other and are arranged horizontally at a distance. The second inverter high-side gate drive power supply voltage pin 30221 is electrically connected to the second inverter high-side driver chip 30211, and the second inverter low-side gate drive power supply voltage pin 30222 is electrically connected to the second inverter low-side driver chip 30212.

[0053] This configuration allows the second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222 to be set separately, which can reduce the mutual interference between the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212, thereby improving the anti-interference capability of the semiconductor device 100.

[0054] In embodiments of the present invention, combined with Figure 4 As shown, the second inverter high-side gate drive power supply voltage pin 30221 includes a second inverter first high-side power supply voltage pin portion 302211, a second inverter second high-side power supply voltage pin portion 302212, and a second inverter third high-side power supply voltage pin portion 302213. The second inverter first high-side power supply voltage pin portion 302211 extends laterally. The second inverter second high-side power supply voltage pin portion 302212 and the second inverter third high-side power supply voltage pin portion 302213 are respectively disposed at both ends of the second inverter first high-side power supply voltage pin portion 302211 laterally. The second inverter second high-side power supply voltage pin portion 302212 and the second inverter third high-side power supply voltage pin portion 302213 both extend longitudinally away from the substrate 2.

[0055] Specifically, the first high-side power supply voltage pin portion 302211 of the second inverter extends laterally to increase the lateral dimension of the second high-side gate drive power supply voltage pin 30221. This facilitates the connection of laterally arranged devices to the second high-side gate drive power supply voltage pin 30221, thereby shortening the wire length and reducing line resistance. In the semiconductor device 100, reduced line resistance improves device operating speed, reduces power consumption and heat generation, improves signal integrity, and enhances the reliability of the semiconductor device 100.

[0056] Furthermore, the second high-side power supply voltage pin portion 302212 and the third high-side power supply voltage pin portion 302213 of the second inverter are respectively disposed at the two lateral ends of the first high-side power supply voltage pin portion 302211 of the second inverter, and extend longitudinally toward the side away from the substrate 2. This not only increases the longitudinal dimension of the second high-side gate drive power supply voltage pin 30221, but also facilitates the connection of devices arranged longitudinally with the second high-side gate drive power supply voltage pin 30221. This not only shortens the wire length and improves the device integration, but also helps to reduce the line resistance of the device. In addition, it enables the second high-side gate drive power supply voltage pin 30221 to be connected to the power supply to supply power to the second inverter drive chip 3021.

[0057] Furthermore, the PFC driver chip power supply voltage pin 3032 extends vertically to increase its vertical dimension. This allows the PFC driver chip power supply voltage pin 3032 to be closer to other devices on the semiconductor device 100, thereby shortening the conductor length of the electrical connection, reducing line resistance, and also enabling the PFC driver chip power supply voltage pin 3032 to be connected to a power source to supply power to the PFC driver chip 3031.

[0058] Furthermore, the second inverter second high-side power supply voltage pin portion 302212 is laterally closer to the PFC drive pin frame 303 than the second inverter third high-side power supply voltage pin portion 302213. The PFC drive chip power supply voltage pin 3032 is spaced apart on the side of the second inverter second high-side power supply voltage pin portion 302212 that is laterally away from the first inverter drive pin frame 301. In this way, the second inverter second high-side power supply voltage pin portion 302212 and the PFC drive chip power supply voltage pin 3032 are spaced apart laterally, so that the second inverter high-side gate drive power supply voltage pin 30221 and the PFC drive chip power supply voltage pin 3032 are arranged separately on the drive-side pin frame 3. This can reduce electromagnetic interference between the PFC power pad portion 203 and the second inverter power pad portion 202, thereby improving the anti-interference capability of the semiconductor device 100.

[0059] Furthermore, the second inverter low-side gate drive supply voltage pin 30222 is spaced apart from the second inverter third high-side supply voltage pin portion 302213 on the side laterally away from the PFC drive pin frame 303. Specifically, the second inverter third high-side power supply voltage pin portion 302213 is laterally further away from the PFC drive pin frame 303 than the second inverter second high-side power supply voltage pin portion 302212. The second inverter low-side gate drive power supply voltage pin 30222 is located on the side of the second inverter third high-side power supply voltage pin portion 302213 that is further away from the PFC drive pin frame 303, and is spaced apart from the second inverter third high-side power supply voltage pin portion 302213. This allows the second inverter low-side gate drive power supply voltage pin 30222 to be further away from the PFC drive pin frame 303. This not only reduces the mutual interference between the second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222, but also further reduces the mutual interference between the PFC drive pin frame 303 and the second inverter low-side gate drive power supply voltage pin 30222, thereby improving the anti-interference capability of the semiconductor device 100.

[0060] In embodiments of the present invention, combined with Figure 3 and Figure 4As shown, the second inverter drive pin frame 302 includes a second inverter drive chip ground pin 3023. The second inverter drive chip ground pin 3023 includes a second inverter first ground pin portion 30231, a second inverter second ground pin portion 30232, and a second inverter third ground pin portion 30233. The second inverter first ground pin portion 30231 extends laterally and protrudes at least partially along the side longitudinally away from the substrate 2 to form a second inverter high-side drive pad 302311 and a second inverter low-side drive pad 302312 that are spaced apart laterally. The second inverter high-side drive chip 30211 is disposed on the second inverter high-side drive pad 302311, and the second inverter low-side drive chip 30212 is disposed on the second inverter low-side drive pad 302312.

[0061] Specifically, the ground pin 3023 of the second inverter driver chip can provide a mounting position for the second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212. The second inverter first ground pin portion 30231 extends laterally and protrudes at least partially along the side facing away from the substrate 2 in the longitudinal direction. This not only provides a mounting position for the second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212, but also increases the lateral dimension of the ground pin 3023 of the second inverter driver chip to shorten the distance between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This can shorten the length of the electrical connection between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0062] Furthermore, a second inverter high-side drive pad 302311 and a second inverter low-side drive pad 302312 are laterally spaced on the second inverter first ground pin portion 30231. This ensures that the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212 are arranged laterally at intervals to reduce mutual interference between the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212.

[0063] Furthermore, the second inverter first ground pin portion 30231 is spaced apart from the second inverter first high-side power supply voltage pin portion 302211 on the side facing the substrate 2 longitudinally. This allows the second inverter first ground pin portion 30231, which extends laterally, and the second inverter first high-side power supply voltage pin portion 302211, which also extends laterally, to be spaced apart longitudinally, ensuring that the second inverter first ground pin portion 30231 is adjacent to the substrate 2. This facilitates the placement of the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212 on the second inverter first ground pin portion 30231 adjacent to the second inverter power chip 2021 on the second inverter power pad portion 202, so that both the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212 are connected to the second inverter power chip 2021.

[0064] Furthermore, the second inverter first ground pin portion 30231 extends laterally, and the second inverter second ground pin portion 30232 and the second inverter third ground pin portion 30233 are respectively disposed at both ends of the second inverter first ground pin portion 30231 laterally, and both extend toward the side facing away from the substrate 2 in the longitudinal direction. This can increase the size of the second inverter driver chip ground pin 3023 in the longitudinal direction, so that the second inverter driver chip ground pin 3023 can be grounded normally.

[0065] Furthermore, the second inverter second ground pin portion 30232 is laterally spaced between the second inverter second high-side power supply voltage pin portion 302212 and the PFC driver chip power supply voltage pin 3032. This ensures that the second inverter high-side gate drive power supply voltage pin 30221 is laterally separated from the PFC driver chip power supply voltage pin 3032, thereby eliminating the frame structure of the second inverter high-side gate drive power supply voltage pin 30221 and the PFC driver chip power supply voltage pin 3032 in the prior art. This reduces the mutual interference between the functional part of the second inverter on the semiconductor device 100 and the functional part of the PFC on the semiconductor device 100, thereby improving the anti-interference capability of the semiconductor device 100.

[0066] Furthermore, the second inverter third ground pin portion 30233 is longitudinally spaced between the second inverter third high-side power supply voltage pin portion 302213 and the first inverter drive pin frame 301. This ensures that the second inverter high-side gate drive power supply voltage pin 30221 is laterally separated from the first inverter drive pin frame 301, thereby eliminating the frame structure of the second inverter high-side gate drive power supply voltage pin 30221 and the first inverter drive pin frame 301 power supply terminals in the prior art. This reduces the mutual interference between the functional part of the second inverter on the semiconductor device 100 and the functional part of the first inverter on the semiconductor device 100, thereby improving the anti-interference capability of the semiconductor device 100.

[0067] Furthermore, the ground pin 3023 of the second inverter driver chip also includes a second inverter separation pin portion 30234. One end of the second inverter separation pin portion 30234 is connected to the second inverter first ground pin portion 30231, and the other end extends toward the side facing away from the substrate 2. The second inverter separation pin portion 30234 is laterally spaced between the second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222. With this arrangement, the second inverter separation pin portion 30234 can separate the second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222 to reduce mutual interference between the second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222, thereby improving the anti-interference capability of the semiconductor device 100.

[0068] In embodiments of the present invention, combined with Figure 5 As shown, the first inverter driver chip 3011 includes a first inverter high-side driver chip 30111 and a first inverter low-side driver chip 30112. The first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112 are arranged horizontally at a distance. The first inverter driver chip power supply voltage pin 3012 includes a first inverter high-side gate drive power supply voltage pin 30121 and a first inverter low-side gate drive power supply voltage pin 30122. The first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 are independent of each other and are arranged horizontally at a distance. The first inverter high-side gate drive power supply voltage pin 30121 is electrically connected to the first inverter high-side driver chip 30111, and the first inverter low-side gate drive power supply voltage pin 30122 is electrically connected to the first inverter low-side driver chip 30112.

[0069] This configuration allows the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 to be set separately, which can reduce the mutual interference between the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112, thereby improving the anti-interference capability of the semiconductor device 100.

[0070] In embodiments of the present invention, combined with Figure 5 As shown, the first inverter high-side gate drive power supply voltage pin 30121 includes a first inverter first high-side power supply voltage pin portion 301211, a first inverter second high-side power supply voltage pin portion 301212, and a first inverter third high-side power supply voltage pin portion 301213, with the first inverter first high-side power supply voltage pin portion 301211 extending laterally.

[0071] Specifically, the first inverter first high-side power supply voltage pin portion 301211 extends laterally to increase the lateral size of the first inverter high-side gate drive power supply voltage pin 30121, thereby facilitating the connection of devices arranged laterally with the first inverter high-side gate drive power supply voltage pin 30121. This shortens the wire length and helps reduce line resistance.

[0072] Furthermore, the first inverter second high-side power supply voltage pin portion 301212 and the first inverter third high-side power supply voltage pin portion 301213 are respectively disposed at the two lateral ends of the first inverter first high-side power supply voltage pin portion 301211 and extend longitudinally toward the side away from the substrate 2. This not only increases the longitudinal dimension of the first inverter high-side gate drive power supply voltage pin 30121, but also facilitates the connection of longitudinally arranged devices with the first inverter high-side gate drive power supply voltage pin 30121. This not only shortens the wire length and improves the device integration, but also helps to reduce the line resistance of the device. In addition, it enables the first inverter high-side gate drive power supply voltage pin 30121 to be connected to the power supply to supply power to the first inverter drive chip 3011.

[0073] Furthermore, the first inverter second high-side power supply voltage pin portion 301212 is laterally closer to the second inverter drive pin frame 302 than the first inverter third high-side power supply voltage pin portion 301213. The second inverter drive chip power supply voltage pin 3022 is spaced apart from the first inverter second high-side power supply voltage pin portion 301212 on the side laterally away from the first inverter third high-side power supply voltage pin portion 301213. In this way, the first inverter second high-side power supply voltage pin portion 301212 and the second inverter drive chip power supply voltage pin 3022 are spaced apart laterally, so that the first inverter high-side gate drive power supply voltage pin 30121 and the second inverter second inverter drive chip power supply voltage pin 3022 are arranged separately on the drive-side pin frame 3. This can reduce electromagnetic interference between the first inverter power pad portion 201 and the second inverter power pad portion 202, thereby improving the anti-interference capability of the semiconductor device 100.

[0074] Furthermore, the first inverter low-side gate drive supply voltage pin 30122 is spaced apart from the first inverter third high-side supply voltage pin portion 301213 on the side laterally away from the second inverter drive pin frame 302. Specifically, the first inverter third high-side power supply voltage pin portion 301213 is laterally further away from the second inverter drive pin frame 302 compared to the first inverter second high-side power supply voltage pin portion 301212. The first inverter low-side gate drive power supply voltage pin 30122 is located on the side of the first inverter third high-side power supply voltage pin portion 301213 that is further away from the second inverter drive pin frame 302, and is spaced apart from the first inverter third high-side power supply voltage pin portion 301213. This allows the first inverter low-side gate drive power supply voltage pin 30122 to be further away from the second inverter drive pin frame 302. This not only reduces the mutual interference between the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122, but also further reduces the mutual interference between the second inverter drive pin frame 302 and the first inverter low-side gate drive power supply voltage pin 30122, thereby improving the anti-interference capability of the semiconductor device 100.

[0075] In embodiments of the present invention, combined with Figure 3 and Figure 5As shown, the first inverter drive pin frame 301 includes a first inverter drive chip ground pin 3013. The first inverter drive chip ground pin 3013 includes a first inverter first ground pin portion 30131, a first inverter second ground pin portion 30132, and a first inverter third ground pin portion 30133. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side longitudinally away from the substrate 2 to form a first inverter high-side drive pad 301311 and a first inverter low-side drive pad 301312 that are spaced apart laterally. The first inverter high-side drive chip 30111 is disposed on the first inverter high-side drive pad 301311, and the first inverter low-side drive chip 30112 is disposed on the first inverter low-side drive pad 301312.

[0076] Specifically, the ground pin 3013 of the first inverter driver chip can provide a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side facing away from the substrate 2 in the longitudinal direction. This not only provides a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112, but also increases the lateral dimension of the ground pin 3013 of the first inverter driver chip, thereby shortening the distance between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100. This can further shorten the electrical connection length between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100, which not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0077] Furthermore, a first inverter high-side drive pad 301311 and a first inverter low-side drive pad 301312 are laterally spaced on the first inverter first ground pin portion 30131. This ensures that the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 are arranged laterally at intervals to reduce mutual interference between the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112.

[0078] Furthermore, the first inverter first ground pin portion 30131 is spaced apart from the first inverter first high-side power supply voltage pin portion 301211 on the side facing the substrate 2 longitudinally. This allows the first inverter first ground pin portion 30131 extending laterally and the first inverter first high-side power supply voltage pin portion 301211 extending laterally to be spaced apart longitudinally, ensuring that the first inverter first ground pin portion 30131 is adjacent to the substrate 2. This facilitates the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 on the first inverter first ground pin portion 30131 to be adjacent to the first inverter power chip 2011 on the first inverter power pad portion 201, so that both the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 are connected to the first inverter power chip 2011.

[0079] Furthermore, the first inverter second ground pin portion 30132 extends laterally, and the first inverter second ground pin portion 30132 and the first inverter third ground pin portion 30133 are respectively disposed at both ends of the first inverter first ground pin portion 30131 laterally, and both extend toward the side facing away from the substrate 2 in the vertical direction. This can increase the size of the first inverter driver chip ground pin 3013 in the vertical direction, so that the first inverter driver chip ground pin 3013 can be grounded normally.

[0080] Furthermore, the first inverter second ground pin portion 30132 is laterally spaced between the first inverter second high-side power supply voltage pin portion 301212 and the second inverter driver chip power supply voltage pin 3022. This ensures that the first inverter high-side gate drive power supply voltage pin 30121 is laterally separated from the second inverter driver chip power supply voltage pin 3022, thereby eliminating the frame structure of the first inverter high-side gate drive power supply voltage pin 30121 and the second inverter driver chip power supply voltage pin 3022 in the prior art. This reduces the mutual interference between the functional part of the first inverter on the semiconductor device 100 and the functional part of the second inverter on the semiconductor device 100, thereby improving the anti-interference capability of the semiconductor device 100.

[0081] Furthermore, the third ground pin portion 30133 of the first inverter is laterally spaced from the side of the third high-side power supply voltage pin portion 301213 of the first inverter that is away from the second inverter drive pin frame 302. This ensures that the ground pin 3013 of the first inverter drive chip is laterally separated from the second inverter drive pin frame 302, which can reduce the mutual interference between the functional part of the first inverter on the semiconductor device 100 and the functional part of the second inverter on the semiconductor device 100, thereby improving the anti-interference capability of the semiconductor device 100.

[0082] Furthermore, the ground pin 3013 of the first inverter drive chip also includes a first inverter separation pin portion 30134. One end of the first inverter separation pin portion 30134 is connected to the first inverter first ground pin portion 30131, and the other end extends toward the side facing away from the substrate 2. The first inverter separation pin portion 30134 is laterally spaced between the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122. With this arrangement, the first inverter separation pin portion 30134 can separate the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 to reduce mutual interference between the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122, thereby improving the anti-interference capability of the semiconductor device 100.

[0083] According to other embodiments of the present invention, in combination Figure 6 As shown, the second inverter driver chip 3021 includes a second inverter high-side driver chip 30211 and a second inverter low-side driver chip 30212. The second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212 are arranged horizontally at intervals. The power supply voltage pins 3022 of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin 30221 and a second inverter low-side gate drive power supply voltage pin 30222. The second inverter high-side gate drive power supply voltage pin 30221 and the second inverter low-side gate drive power supply voltage pin 30222 are interconnected. The second inverter high-side gate drive power supply voltage pin 30221 is electrically connected to the second inverter high-side driver chip 30211, and the second inverter low-side gate drive power supply voltage pin 30222 is electrically connected to the second inverter low-side driver chip 30212.

[0084] This configuration simplifies the design of the second inverter high-side gate drive supply voltage pin 30221 and the second inverter low-side gate drive supply voltage pin 30222 on the semiconductor device 100, reduces the pin design difficulty on the semiconductor device 100, and reduces the number of pins on the semiconductor device 100, thereby reducing the device manufacturing cost.

[0085] In embodiments of the present invention, combined with Figure 6 As shown, the second inverter high-side gate drive power supply voltage pin 30221 includes a second inverter first high-side power supply voltage pin portion 302211 and a second inverter second high-side power supply voltage pin portion 302212, with the second inverter first high-side power supply voltage pin portion 302211 extending laterally.

[0086] Specifically, the first high-side power supply voltage pin portion 302211 of the second inverter extends laterally to increase the lateral dimension of the second high-side gate drive power supply voltage pin 30221, thereby facilitating the connection of devices arranged laterally with the second high-side gate drive power supply voltage pin 30221. This shortens the wire length and helps to reduce line resistance.

[0087] Furthermore, the second high-side power supply voltage pin portion 302212 of the second inverter is disposed laterally closer to one end of the first high-side power supply voltage pin portion 302211 of the second inverter and closer to the PFC drive pin frame 303. The second high-side power supply voltage pin portion 302212 of the second inverter extends longitudinally away from the substrate 2. This not only increases the longitudinal dimension of the second high-side gate drive power supply voltage pin 30221, but also facilitates the connection of devices arranged longitudinally to the second high-side gate drive power supply voltage pin 30221. This not only shortens the wire length and improves the device integration, but also helps to reduce the line resistance of the device. In addition, it enables the second high-side gate drive power supply voltage pin 30221 to be connected to the power supply to supply power to the second inverter drive chip 3021.

[0088] Furthermore, the PFC driver chip power supply voltage pin 3032 extends vertically to increase its vertical dimension. This allows the PFC driver chip power supply voltage pin 3032 to be closer to other devices on the semiconductor device 100, thereby shortening the conductor length of the electrical connection, reducing line resistance, and also enabling the PFC driver chip power supply voltage pin 3032 to be connected to a power source to supply power to the PFC driver chip 3031.

[0089] Furthermore, the PFC driver chip power supply voltage pin 3032 is spaced apart on the side of the second inverter second high-side power supply voltage pin portion 302212 that is laterally away from the first inverter drive pin frame 301. In this way, the second inverter high-side gate drive power supply voltage pin 30221 and the PFC driver chip power supply voltage pin 3032 can be arranged separately on the drive-side pin frame 3. This can reduce electromagnetic interference between the PFC power pad portion 203 and the second inverter power pad portion 202, thereby improving the anti-interference capability of the semiconductor device 100.

[0090] Furthermore, the second inverter low-side gate drive supply voltage pin 30222 includes a second inverter first low-side supply voltage pin portion 302221 and a second inverter second low-side supply voltage pin portion 302222. The second inverter first low-side supply voltage pin portion 302221 extends vertically to increase the vertical dimension of the second inverter low-side gate drive supply voltage pin 30222. This can shorten the vertical distance between the second inverter low-side gate drive supply voltage pin 30222 and other devices, thereby shortening the wire length, improving device integration, and helping to reduce the line resistance of the device.

[0091] Furthermore, one end of the second low-side power supply voltage pin portion 302222 of the second inverter is connected to the end of the first low-side power supply voltage pin portion 302221 of the second inverter that is longitudinally adjacent to the substrate 2 and extends laterally, so that the other end of the second low-side power supply voltage pin portion 302222 of the second inverter is laterally closer to the first high-side power supply voltage pin portion 302211 of the second inverter, and the other end of the second low-side power supply voltage pin portion 302222 of the second inverter is connected to the end of the first high-side power supply voltage pin portion 302211 of the second inverter that is laterally away from the PFC drive pin frame 303. In this way, the second high-side gate drive power supply voltage pin 30221 and the second low-side gate drive power supply voltage pin 30222 of the second inverter can be interconnected, thereby simplifying the pin design difficulty on the semiconductor device 100, reducing the number of pins on the semiconductor device 100, and thus reducing the device manufacturing cost.

[0092] In embodiments of the present invention, combined with Figure 6 As shown, the second inverter drive pin frame 302 also includes a second inverter power supply support pin 3024. One end of the second inverter power supply support pin 3024 is connected to the connection point of the second inverter first high-side power supply voltage pin portion 302211 and the second inverter second low-side power supply voltage pin portion 302222. The other end of the second inverter power supply support pin 3024 extends longitudinally away from the substrate 2.

[0093] This configuration enhances the connection strength between the first high-side power supply voltage pin 302211 of the second inverter and the second low-side power supply voltage pin 302222 of the second inverter, thereby improving the structural stability of the first high-side power supply voltage pin 302211 of the second inverter and the second low-side power supply voltage pin 302222 of the second inverter in the semiconductor device 100.

[0094] In embodiments of the present invention, combined with Figure 6As shown, the second inverter drive pin frame 302 includes a second inverter drive chip ground pin 3023. The second inverter drive chip ground pin 3023 includes a second inverter first ground pin portion 30231, a second inverter second ground pin portion 30232, and a second inverter third ground pin portion 30233. The second inverter first ground pin portion 30231 extends laterally and protrudes at least partially along the side longitudinally away from the substrate 2 to form a second inverter high-side drive pad 302311 and a second inverter low-side drive pad 302312 that are spaced apart laterally. The second inverter high-side drive chip 30211 is disposed on the second inverter high-side drive pad 302311, and the second inverter low-side drive chip 30212 is disposed on the second inverter low-side drive pad 302312.

[0095] Specifically, the ground pin 3023 of the second inverter driver chip can provide a mounting position for the second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212. The second inverter first ground pin portion 30231 extends laterally and protrudes at least partially along the side facing away from the substrate 2 in the longitudinal direction. This not only provides a mounting position for the second inverter high-side driver chip 30211 and the second inverter low-side driver chip 30212, but also increases the lateral dimension of the ground pin 3023 of the second inverter driver chip to shorten the distance between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This can shorten the length of the electrical connection between the ground pin 3023 of the second inverter driver chip and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0096] Furthermore, the second inverter first ground pin portion 30231 extends laterally, and the second inverter second ground pin portion 30232 and the second inverter third ground pin portion 30233 are respectively disposed at both ends of the second inverter first ground pin portion 30231 laterally, and both extend toward the side facing away from the substrate 2 in the longitudinal direction. This can increase the size of the second inverter driver chip ground pin 3023 in the longitudinal direction, so that the second inverter driver chip ground pin 3023 can be grounded normally.

[0097] Furthermore, the second inverter second low-side power supply voltage pin portion 302222 and the second inverter first high-side power supply voltage pin portion 302211 are both spaced apart on the side of the second inverter first ground pin portion 30231 that is longitudinally away from the substrate 2. This allows the second inverter first ground pin portion 30231, which extends laterally, and the second inverter first high-side power supply voltage pin portion 302211, which also extends laterally, to be spaced apart longitudinally, while ensuring that the second inverter first ground pin portion 30231 is adjacent to the substrate 2. This facilitates the placement of the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212 on the second inverter first ground pin portion 30231 adjacent to the second inverter power chip 2021 on the second inverter power pad portion 202, so that both the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212 are connected to the second inverter power chip 2021.

[0098] In an embodiment of the present invention, the second inverter third ground pin 30233, the second inverter first low-side power supply voltage pin 302221, the second inverter power supply support pin 3024, and the second inverter second high-side power supply voltage pin 302212 are arranged sequentially and spaced apart in the lateral direction. This allows the second inverter driver chip ground pin 3023, the second inverter low-side gate drive power supply voltage pin 30222, the second inverter power supply support pin 3024, and the second inverter high-side gate drive power supply voltage pin 30221 to be arranged separately in the second inverter driver pin frame 302, thereby reducing mutual interference between the pins and improving the anti-interference capability of the semiconductor device 100.

[0099] In embodiments of the present invention, combined with Figure 6 As shown, the second inverter drive pin frame 302 also includes a second inverter ground support pin 3025. One end of the second inverter ground support pin 3025 is connected to the second inverter first ground pin portion 30231 and extends longitudinally toward the substrate 2. The second inverter ground support pin 3025 is connected to the second inverter power pad portion 202. The plane perpendicular to the vertical is set as the first projection plane. The orthographic projection of the second inverter ground support pin 3025 on the first projection plane is laterally spaced between the orthographic projection of the second inverter high-side drive chip 30211 on the first projection plane and the orthographic projection of the second inverter low-side drive chip 30212 on the first projection plane. With this configuration, the second inverter ground support pin 3025 can support the second inverter first ground pin portion 30231 corresponding to the second inverter high-side drive chip 30211 and the second inverter low-side drive chip 30212, which can ensure the structural stability of the second inverter first ground pin portion 30231 on the semiconductor device 100.

[0100] According to further embodiments of the present invention, in combination with Figure 7 As shown, the first inverter driver chip 3011 includes a first inverter high-side driver chip 30111 and a first inverter low-side driver chip 30112. The first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112 are arranged horizontally at intervals. The first inverter driver chip power supply voltage pin 3012 includes a first inverter high-side gate drive power supply voltage pin 30121 and a first inverter low-side gate drive power supply voltage pin 30122. The first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 are interconnected. The first inverter high-side gate drive power supply voltage pin 30121 is electrically connected to the first inverter high-side driver chip 30111, and the first inverter low-side gate drive power supply voltage pin 30122 is electrically connected to the first inverter low-side driver chip 30112.

[0101] This configuration simplifies the design of the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 on the semiconductor device 100, reduces the pin design difficulty on the semiconductor device 100, and reduces the number of pins on the semiconductor device 100, thereby reducing the device manufacturing cost.

[0102] In embodiments of the present invention, combined with Figure 2 As shown, the first inverter high-side gate drive power supply voltage pin 30121 includes a first inverter first high-side power supply voltage pin portion 301211 and a first inverter second high-side power supply voltage pin portion 301212, with the first inverter first high-side power supply voltage pin portion 301211 extending laterally.

[0103] Specifically, the first inverter first high-side power supply voltage pin portion 301211 extends laterally to increase the lateral size of the first inverter high-side gate drive power supply voltage pin 30121, thereby facilitating the connection of devices arranged laterally with the first inverter high-side gate drive power supply voltage pin 30121. This shortens the wire length and helps reduce line resistance.

[0104] Furthermore, the first inverter second high-side power supply voltage pin portion 301212 is disposed at one end of the first inverter first high-side power supply voltage pin portion 301211 that is laterally adjacent to the second inverter drive pin frame 302. The first inverter second high-side power supply voltage pin portion 301212 extends longitudinally away from the substrate 2. This not only increases the longitudinal dimension of the first inverter high-side gate drive power supply voltage pin 30121, but also facilitates the connection of longitudinally arranged devices to the first inverter high-side gate drive power supply voltage pin 30121. This not only shortens the wire length and improves the device integration, but also helps to reduce the line resistance of the device. In addition, it enables the first inverter high-side gate drive power supply voltage pin 30121 to be connected to the power supply to supply power to the first inverter drive chip 3011.

[0105] Furthermore, the second inverter driver chip power supply voltage pin 3022 and the first inverter second high-side power supply voltage pin portion 301212 are arranged laterally at a distance. In this way, the first inverter high-side gate drive power supply voltage pin 30121 and the second inverter driver chip power supply voltage pin 3022 can be arranged separately on the drive-side pin frame 3. This can reduce electromagnetic interference between the first inverter power pad portion 201 and the second inverter power pad portion 202, thereby improving the anti-interference capability of the semiconductor device 100.

[0106] In embodiments of the present invention, combined with Figure 7 As shown, the first inverter drive pin frame 301 also includes a first inverter power supply support pin 3014. One end of the first inverter power supply support pin 3014 is connected to the connection point of the first inverter first high-side power supply voltage pin portion 301211 and the first inverter second low-side power supply voltage pin portion 301222. The other end of the first inverter power supply support pin 3014 extends longitudinally away from the substrate 2.

[0107] This configuration enhances the connection strength between the first high-side power supply voltage pin 301211 and the second low-side power supply voltage pin 301222 of the first inverter, thereby improving the structural stability of the first high-side power supply voltage pin 301211 and the second low-side power supply voltage pin 301222 of the first inverter in the semiconductor device 100.

[0108] Furthermore, the first inverter low-side gate drive supply voltage pin 30122 also includes a first inverter first low-side supply voltage pin portion 301221 and a first inverter second low-side supply voltage pin portion 301222. The first inverter first low-side supply voltage pin portion 301221 extends vertically to increase the vertical dimension of the first inverter low-side gate drive supply voltage pin 30122. This can shorten the vertical distance between the first inverter low-side gate drive supply voltage pin 30122 and other devices, thereby shortening the wire length, improving device integration, and helping to reduce the line resistance of the device.

[0109] Furthermore, one end of the first inverter second low-side power supply voltage pin portion 301222 is connected to the end of the first inverter first low-side power supply voltage pin portion 301221 adjacent to the substrate 2 in the longitudinal direction, and is provided in the transverse direction so that the other end of the first inverter second low-side power supply voltage pin portion 301222 is closer to the first inverter first high-side power supply voltage pin portion 301211 in the transverse direction, and the other end of the first inverter second low-side power supply voltage pin portion 301222 is connected to the end of the first inverter first high-side power supply voltage pin portion 301211 away from the second inverter drive pin frame 302 in the transverse direction. In this way, the first inverter high-side gate drive power supply voltage pin 30121 and the first inverter low-side gate drive power supply voltage pin 30122 can be interconnected, thereby simplifying the pin design difficulty on the semiconductor device 100, reducing the number of pins on the semiconductor device 100, and thus reducing the device manufacturing cost.

[0110] In embodiments of the present invention, combined with Figure 7 As shown, the first inverter drive pin frame 301 includes a first inverter drive chip ground pin 3013. The first inverter drive chip ground pin 3013 includes a first inverter first ground pin portion 30131, a first inverter second ground pin portion 30132, and a first inverter third ground pin portion 30133. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side longitudinally away from the substrate 2 to form a first inverter high-side drive pad 301311 and a first inverter low-side drive pad 301312 that are spaced apart laterally. The first inverter high-side drive chip 30111 is disposed on the first inverter high-side drive pad 301311, and the first inverter low-side drive chip 30112 is disposed on the first inverter low-side drive pad 301312.

[0111] Specifically, the ground pin 3013 of the first inverter driver chip can provide a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side facing away from the substrate 2 in the longitudinal direction. This not only provides a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112, but also increases the lateral dimension of the ground pin 3013 of the first inverter driver chip, thereby shortening the distance between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100. This can further shorten the electrical connection length between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100, which not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0112] Furthermore, the first inverter first ground pin portion 30131 extends laterally, and the first inverter second ground pin portion 30132 and the first inverter third ground pin portion 30133 are respectively disposed at both ends of the first inverter first ground pin portion 30131 laterally, and both extend toward the side facing away from the substrate 2 in the vertical direction. This can increase the size of the first inverter driver chip ground pin 3013 in the vertical direction, so that the first inverter driver chip ground pin 3013 can be grounded normally.

[0113] Furthermore, the first inverter second low-side power supply voltage pin portion 301222 and the first inverter first high-side power supply voltage pin portion 301211 are both spaced apart on the side of the first inverter first ground pin portion 30131 that is longitudinally away from the substrate 2. This allows the first inverter first ground pin portion 30131, which extends laterally, and the first inverter first high-side power supply voltage pin portion 301211, which also extends laterally, to be spaced apart longitudinally, while ensuring that the first inverter first ground pin portion 30131 is adjacent to the substrate 2. This facilitates the placement of the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 on the first inverter first ground pin portion 30131 adjacent to the first inverter power chip 2011 on the first inverter power pad portion 201, so that the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 are both connected to the first inverter power chip 2011.

[0114] In an embodiment of the present invention, the first inverter third ground pin 30133, the first inverter first low-side power supply voltage pin 301221, the first inverter power supply support pin 3014, and the first inverter second high-side power supply voltage pin 301212 are arranged sequentially and spaced apart in the horizontal direction. This allows the first inverter driver chip ground pin 3013, the first inverter low-side gate drive power supply voltage pin 30122, the first inverter power supply support pin 3014, and the first inverter high-side gate drive power supply voltage pin 30121 to be arranged separately in the first inverter driver pin frame 301, thereby reducing mutual interference between the pins and improving the anti-interference capability of the semiconductor device 100.

[0115] In embodiments of the present invention, combined with Figure 7 As shown, the first inverter drive pin frame 301 includes a first inverter drive chip ground pin 3013. The first inverter drive chip ground pin 3013 includes a first inverter first ground pin portion 30131, a first inverter second ground pin portion 30132, and a first inverter third ground pin portion 30133. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side longitudinally away from the substrate 2 to form a first inverter high-side drive pad 301311 and a first inverter low-side drive pad 301312 that are spaced apart laterally. The first inverter high-side drive chip 30111 is disposed on the first inverter high-side drive pad 301311, and the first inverter low-side drive chip 30112 is disposed on the first inverter low-side drive pad 301312.

[0116] Specifically, the ground pin 3013 of the first inverter driver chip can provide a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112. The first inverter first ground pin portion 30131 extends laterally and protrudes at least partially along the side facing away from the substrate 2 in the longitudinal direction. This not only provides a mounting position for the first inverter high-side driver chip 30111 and the first inverter low-side driver chip 30112, but also increases the lateral dimension of the ground pin 3013 of the first inverter driver chip, thereby shortening the distance between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100. This can further shorten the electrical connection length between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100, which not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0117] Furthermore, the first inverter first ground pin portion 30131 extends laterally, and the first inverter second ground pin portion 30132 and the first inverter third ground pin portion 30133 are respectively disposed at both ends of the first inverter first ground pin portion 30131 laterally, and both extend toward the side facing away from the substrate 2 in the vertical direction. This can increase the size of the first inverter driver chip ground pin 3013 in the vertical direction, so that the first inverter driver chip ground pin 3013 can be grounded normally.

[0118] Furthermore, the first inverter second low-side power supply voltage pin portion 301222 and the first inverter first high-side power supply voltage pin portion 301211 are both spaced apart on the side of the first inverter first ground pin portion 30131 that is longitudinally away from the substrate 2. This allows the first inverter first ground pin portion 30131, which extends laterally, and the first inverter first high-side power supply voltage pin portion 301211, which also extends laterally, to be spaced apart longitudinally, while ensuring that the first inverter first ground pin portion 30131 is adjacent to the substrate 2. This facilitates the placement of the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 on the first inverter first ground pin portion 30131 adjacent to the first inverter power chip 2011 on the first inverter power pad portion 201, so that the first inverter high-side drive chip 30111 and the first inverter low-side drive chip 30112 are both connected to the first inverter power chip 2011.

[0119] In an embodiment of the present invention, the first inverter third ground pin 30133, the first inverter first low-side power supply voltage pin 301221, the first inverter power supply support pin 3014, and the first inverter second high-side power supply voltage pin 301212 are arranged sequentially and spaced apart in the horizontal direction. This allows the first inverter driver chip ground pin 3013, the first inverter low-side gate drive power supply voltage pin 30122, the first inverter power supply support pin 3014, and the first inverter high-side gate drive power supply voltage pin 30121 to be arranged separately in the first inverter driver pin frame 301, thereby reducing mutual interference between the pins and improving the anti-interference capability of the semiconductor device 100.

[0120] According to an embodiment of the present invention, in combination Figure 8As shown, the PFC driver pin frame 303 also includes a PFC driver chip ground pin 3033. The PFC driver chip ground pin 3033 includes a PFC ground pin portion 30331 and a PFC driver pad portion 30332. The PFC ground pin portion 30331 extends vertically, and the PFC driver pad portion 30332 is disposed at one end of the PFC ground pin portion 30331 that is vertically adjacent to the substrate 2. The PFC driver pad portion 30332 protrudes from the PFC ground pin portion 30331 toward the side that is laterally adjacent to the second inverter driver pin frame 302. The PFC driver chip 3031 is disposed on the PFC driver pad portion 30332.

[0121] Specifically, the vertical extension of the PFC driver chip ground pin 3033 can increase the vertical dimension of the PFC driver chip ground pin 30333, so that the PFC driver pad portion 30332 is located at one end of the PFC ground pin portion 30331 that is vertically adjacent to the substrate 2. This allows the PFC power pad portion 203 located on the substrate 2 adjacent to the PFC driver pad portion 30332 to shorten the connection distance between the PFC driver pad portion 30332 and the PFC power chip 2031.

[0122] Furthermore, the PFC drive pad portion 30332 protrudes towards the side adjacent to the second inverter drive pin frame 302 relative to the PFC ground pin portion 30331, which increases the area of ​​the PFC drive pad portion 30332 and provides space for the PFC drive chip 3031 to be mounted on the PFC drive pad portion 30332.

[0123] Furthermore, the PFC driver chip power supply voltage pin 3032 extends vertically and is spaced laterally on the side of the PFC ground pin portion 30331 facing the PFC driver pad portion 30332. This allows the PFC driver chip power supply voltage pin 3032 to be positioned adjacent to the PFC driver pad portion 30332, facilitating electrical connection between the PFC driver chip power supply voltage pin 3032 and the PFC driver chip 3031. The PFC driver chip power supply voltage pin 3032 is also spaced vertically on the side of the PFC driver pad portion 30332 away from the substrate 2. This allows the PFC driver chip power supply voltage pin 3032 and the PFC driver pad portion 30332 to be spaced apart within the PFC driver pin frame 303, thereby reducing mutual interference between the PFC driver chip power supply voltage pin 3032 and the PFC driver pad portion 30332 and improving the anti-winding capability of the semiconductor device 100.

[0124] Furthermore, a clearance notch 303321 is provided on the side of the PFC driver pad portion 30332 that is laterally opposite to the PFC ground pin portion 30331. The clearance notch 303321 is located at one end of the PFC driver pad portion 30332 that is longitudinally adjacent to the PFC driver chip power supply voltage pin 3032. The clearance notch 303321 is adapted to avoid at least a portion of the PFC driver chip power supply voltage pin 3032 that is longitudinally adjacent to the substrate 2. This arrangement not only ensures the structural integrity of the PFC driver pad and the PFC driver chip power supply voltage pin 3032 in the PFC driver pin frame 303, but also makes the arrangement of the PFC driver pad and the PFC driver chip power supply voltage pin 3032 on the semiconductor device 100 more compact, which is beneficial to improving the structural compactness of the semiconductor device 100.

[0125] According to an embodiment of the present invention, in combination Figure 2 and Figure 3 As shown, the substrate 2 also includes a rectifier bridge pad portion 204. The rectifier bridge pad portion 204 is spaced apart from the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203 in the lateral direction. A rectifier chip 2041 is provided on the rectifier bridge pad portion 204. This arrangement ensures that the rectifier bridge pad portion 204, the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203 are independently arranged on the semiconductor device 100. This can reduce electromagnetic interference between the rectifier bridge pad portion 204, the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203, thereby improving the anti-interference capability of the semiconductor device 100.

[0126] In an embodiment of the present invention, a rectifier bridge is formed by multiple rectifier diodes, for example, by combining four spaced rectifier diodes. The rectifier bridge composed of the four rectifier diodes converts the input AC power into DC power and outputs it.

[0127] Furthermore, the driver-side pin frame 3 also includes a rectifier bridge driver pin frame 304, which corresponds at least partially to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge driver pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. This ensures the structural integrity of the semiconductor device 100 and guarantees the normal function of the rectifier module.

[0128] According to an embodiment of the present invention, in combination Figures 1-3 As shown, the lateral direction of the semiconductor device 100 includes a first direction and a second direction, which are opposite to each other.

[0129] In some embodiments of the present invention, the first inverter power pad 201, the second inverter power pad 202, the PFC power pad 203, and the rectifier bridge pad 204 are arranged sequentially in a first direction.

[0130] In some other embodiments of the present invention, the rectifier bridge pad 204, the PFC power pad 203, the first inverter power pad 201, and the second inverter power pad 202 are arranged sequentially in a first direction.

[0131] In some other embodiments of the present invention, the first inverter power pad 201, the second inverter power pad 202, the rectifier bridge pad 204 and the PFC power pad 203 are arranged sequentially in a first direction.

[0132] With this configuration, in this embodiment of the invention, the first inverter power pad section 201, the second inverter power pad section 202, and the PFC power pad section 203 can be arranged at intervals in the horizontal direction, and the order in which the first inverter power pad section 201, the second inverter power pad section 202, and the PFC power pad section 203 are arranged in the horizontal direction can be changed, wherein the pad section and the PFC power pad section 203 are arranged adjacent to each other.

[0133] According to an embodiment of the present invention, the semiconductor device 100 can be applied to a circuit board assembly, the circuit assembly configured with the semiconductor device 100 in the embodiment of the present invention can be applied to an electrical control box, and the electrical control box configured with the circuit assembly using the semiconductor device 100 of the present invention can be applied to electrical equipment.

[0134] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "circumferential," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0135] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0136] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a lateral direction, a longitudinal direction, and a vertical direction, wherein the lateral direction, the longitudinal direction, and the vertical direction are perpendicular to each other, and the semiconductor device includes: Plastic encapsulation; A substrate, at least partially disposed within the molding compound, the substrate comprising a first inverter power pad portion, a second inverter power pad portion, and a PFC (power factor correction) power pad portion disposed laterally at intervals, wherein a first inverter power chip, a second inverter power chip, and a PFC power chip are respectively disposed on the first inverter power pad portion, the second inverter power pad portion, and the PFC power pad portion; A drive-side pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart in the transverse direction. The first inverter drive pin frame corresponds at least partially to the first inverter power pad portion in the longitudinal direction. The second inverter drive pin frame and the second inverter power pad portion correspond at least partially in the longitudinal direction. The PFC power pad portion corresponds at least partially in the longitudinal direction to the PFC drive pin frame. A first inverter driver chip, a second inverter driver chip, and a PFC driver chip are respectively disposed on the first inverter driver pin frame, the second inverter driver pin frame, and the PFC driver pin frame. The first inverter driver chip is electrically connected to the first inverter power chip, the second inverter driver chip is electrically connected to the second inverter power chip, and the PFC driver chip is electrically connected to the PFC power chip. The first inverter drive pin frame includes a first inverter drive chip power supply voltage pin, which is electrically connected to the first inverter drive chip. The second inverter drive pin frame includes a second inverter drive chip power supply voltage pin, which is electrically connected to the second inverter drive chip. The PFC drive pin frame includes a PFC drive chip power supply voltage pin, which is electrically connected to the PFC drive chip. The first inverter drive chip power supply voltage pin, the second inverter drive chip power supply voltage pin, and the PFC drive chip power supply voltage pin are independent of each other and are spaced apart in the horizontal direction.

2. The semiconductor device according to claim 1, characterized in that, The second inverter driver chip includes a second inverter high-side driver chip and a second inverter low-side driver chip, which are arranged laterally at intervals. The power supply voltage pins of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin and a second inverter low-side gate drive power supply voltage pin, which are independent of each other and arranged laterally at intervals. The second inverter high-side gate drive power supply voltage pin is electrically connected to the second inverter high-side driver chip, and the second inverter low-side gate drive power supply voltage pin is electrically connected to the second inverter low-side driver chip.

3. The semiconductor device according to claim 2, characterized in that, The second inverter high-side gate drive supply voltage pin includes a second inverter first high-side supply voltage pin portion, a second inverter second high-side supply voltage pin portion, and a second inverter third high-side supply voltage pin portion. The second inverter first high-side supply voltage pin portion extends laterally. The second inverter second high-side supply voltage pin portion and the second inverter third high-side supply voltage pin portion are respectively disposed at both ends of the second inverter first high-side supply voltage pin portion laterally. Both the second inverter second high-side supply voltage pin portion and the second inverter third high-side supply voltage pin portion extend longitudinally away from the substrate. The second inverter second high-side supply voltage pin portion is laterally closer to the PFC drive pin frame than the second inverter third high-side supply voltage pin portion. The PFC drive chip supply voltage pin extends longitudinally and is spaced apart from the second inverter second high-side supply voltage pin portion on the side laterally away from the first inverter drive pin frame. The second inverter low-side gate drive supply voltage pin is spaced apart from the second inverter third high-side supply voltage pin portion on the side laterally away from the PFC drive pin frame.

4. The semiconductor device according to claim 3, characterized in that, The second inverter drive pin frame includes a second inverter drive chip ground pin, the second inverter drive chip ground pin includes a second inverter first ground pin portion, a second inverter second ground pin portion and a second inverter third ground pin portion, the second inverter first ground pin portion extends laterally and at least partially protrudes along the side of the longitudinal direction away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad that are spaced apart laterally, the second inverter high-side drive chip is disposed on the second inverter high-side drive pad, and the second inverter low-side drive chip is disposed on the second inverter low-side drive pad; The second inverter first ground pin portion is spaced apart from the second inverter first high-side power supply voltage pin portion on the side facing the substrate in the longitudinal direction. The second inverter first ground pin portion extends in the lateral direction. The second inverter second ground pin portion and the second inverter third ground pin portion are respectively disposed at both ends of the second inverter first ground pin portion in the lateral direction and both extend in the longitudinal direction away from the substrate. The second inverter second ground pin portion is spaced apart in the lateral direction between the second inverter second high-side power supply voltage pin portion and the PFC driver chip power supply voltage pin. The second inverter third ground pin portion is spaced apart in the longitudinal direction between the second inverter third high-side power supply voltage pin portion and the first inverter drive pin frame. The ground pin of the second inverter driver chip also includes a second inverter separator pin portion. One end of the second inverter separator pin portion is connected to the first ground pin portion of the second inverter, and the other end extends toward the side that is longitudinally away from the substrate. The second inverter separator pin portion is laterally spaced between the high-side gate drive power supply voltage pin and the low-side gate drive power supply voltage pin of the second inverter.

5. The semiconductor device according to claim 1, characterized in that, The first inverter driver chip includes a first inverter high-side driver chip and a first inverter low-side driver chip, which are arranged laterally at intervals. The power supply voltage pins of the first inverter driver chip include a first inverter high-side gate drive power supply voltage pin and a first inverter low-side gate drive power supply voltage pin, which are independent of each other and arranged laterally at intervals. The first inverter high-side gate drive power supply voltage pin is electrically connected to the first inverter high-side driver chip, and the first inverter low-side gate drive power supply voltage pin is electrically connected to the first inverter low-side driver chip.

6. The semiconductor device according to claim 5, characterized in that, The first inverter high-side gate drive supply voltage pin includes a first inverter first high-side supply voltage pin portion, a first inverter second high-side supply voltage pin portion, and a first inverter third high-side supply voltage pin portion. The first inverter first high-side supply voltage pin portion extends laterally. The first inverter second high-side supply voltage pin portion and the first inverter third high-side supply voltage pin portion are respectively disposed at both ends of the first inverter first high-side supply voltage pin portion laterally. Both the first inverter second high-side supply voltage pin portion and the first inverter third high-side supply voltage pin portion extend longitudinally away from the substrate. The first inverter second high-side supply voltage pin portion is laterally closer to the second inverter drive pin frame than the first inverter third high-side supply voltage pin portion. The second inverter drive chip supply voltage pin is spaced apart from the first inverter second high-side supply voltage pin portion on the side laterally away from the first inverter third high-side supply voltage pin portion. The first inverter low-side gate drive supply voltage pin is spaced apart from the first inverter third high-side supply voltage pin portion on the side laterally away from the second inverter drive pin frame.

7. The semiconductor device according to claim 6, characterized in that, The first inverter drive pin frame includes a ground pin of a first inverter drive chip. The first inverter drive chip ground pin includes a first inverter first ground pin portion, a first inverter second ground pin portion, and a first inverter third ground pin portion. The first inverter first ground pin portion extends laterally and protrudes at least partially along the longitudinal side away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad that are spaced apart laterally. The first inverter high-side drive chip is disposed on the first inverter high-side drive pad, and the first inverter low-side drive chip is disposed on the first inverter low-side drive pad. The first inverter first ground pin portion is spaced apart from the first inverter first high-side power supply voltage pin portion on the side facing the substrate in the longitudinal direction. The first inverter second ground pin portion and the first inverter third ground pin portion are respectively disposed at both ends of the first inverter first ground pin portion in the lateral direction and both extend towards the side facing away from the substrate in the longitudinal direction. The first inverter second ground pin portion is spaced apart in the lateral direction between the first inverter second high-side power supply voltage pin portion and the second inverter driver chip power supply voltage pin. The first inverter third ground pin portion is spaced apart in the lateral direction on the side of the first inverter third high-side power supply voltage pin portion away from the second inverter driver pin frame. The ground pin of the first inverter driver chip also includes a first inverter separator pin portion. One end of the first inverter separator pin portion is connected to the first inverter first ground pin portion, and the other end extends toward the side that is longitudinally away from the substrate. The first inverter separator pin portion is laterally spaced between the first inverter high-side gate drive power supply voltage pin and the first inverter low-side gate drive power supply voltage pin.

8. The semiconductor device according to claim 1, characterized in that, The second inverter driver chip includes a second inverter high-side driver chip and a second inverter low-side driver chip, which are arranged horizontally at intervals. The power supply voltage pins of the second inverter driver chip include a second inverter high-side gate drive power supply voltage pin and a second inverter low-side gate drive power supply voltage pin, which are interconnected. The second inverter high-side gate drive power supply voltage pin is electrically connected to the second inverter high-side driver chip, and the second inverter low-side gate drive power supply voltage pin is electrically connected to the second inverter low-side driver chip.

9. The semiconductor device according to claim 8, characterized in that, The second inverter high-side gate drive power supply voltage pin includes a second inverter first high-side power supply voltage pin portion and a second inverter second high-side power supply voltage pin portion. The second inverter first high-side power supply voltage pin portion extends laterally, and the second inverter second high-side power supply voltage pin portion is disposed at one end of the second inverter first high-side power supply voltage pin portion that is laterally closer to the PFC drive pin frame. The second inverter second high-side power supply voltage pin portion extends longitudinally away from the substrate. The PFC drive chip power supply voltage pin extends longitudinally and is spaced apart from the second inverter second high-side power supply voltage pin portion on the side laterally away from the first inverter drive pin frame. The second inverter low-side gate drive supply voltage pin includes a second inverter first low-side supply voltage pin portion and a second inverter second low-side supply voltage pin portion. The second inverter first low-side supply voltage pin portion extends vertically. One end of the second inverter second low-side supply voltage pin portion is connected to the end of the second inverter first low-side supply voltage pin portion that is vertically adjacent to the substrate and extends horizontally. The other end of the second inverter second low-side supply voltage pin portion is connected to one end of the second inverter first high-side supply voltage pin portion that is horizontally away from the PFC drive pin frame.

10. The semiconductor device according to claim 9, characterized in that, The second inverter drive pin frame also includes a second inverter power supply support pin. One end of the second inverter power supply support pin is connected to the connection point of the first high-side power supply voltage pin and the second low-side power supply voltage pin of the second inverter. The other end of the second inverter power supply support pin extends longitudinally away from the substrate.

11. The semiconductor device according to claim 10, characterized in that, The second inverter drive pin frame includes a second inverter drive chip ground pin, the second inverter drive chip ground pin includes a second inverter first ground pin portion, a second inverter second ground pin portion and a second inverter third ground pin portion, the second inverter first ground pin portion extends laterally and at least partially protrudes along the side of the longitudinal direction away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad that are spaced apart laterally, the second inverter high-side drive chip is disposed on the second inverter high-side drive pad, and the second inverter low-side drive chip is disposed on the second inverter low-side drive pad; The second inverter first ground pin extends laterally. The second inverter second ground pin and the second inverter third ground pin are respectively disposed at both ends of the second inverter first ground pin and both extend toward the side facing away from the substrate in the longitudinal direction. The second inverter second low-side power supply voltage pin and the second inverter first high-side power supply voltage pin are spaced apart on the side of the second inverter first ground pin facing away from the substrate in the longitudinal direction. The second inverter third ground pin, the second inverter first low-side power supply voltage pin, the second inverter power supply support pin, and the second inverter second high-side power supply voltage pin are arranged in a sequentially spaced manner in the lateral direction.

12. The semiconductor device according to claim 11, characterized in that, The second inverter drive pin frame also includes a second inverter ground support pin. One end of the second inverter ground support pin is connected to the second inverter first ground pin portion and extends longitudinally toward the substrate. The second inverter ground support pin is connected to the second inverter power pad portion. The plane perpendicular to the vertical direction is set as the first projection plane. The orthographic projection of the second inverter ground support pin on the first projection plane is laterally spaced between the orthographic projection of the second inverter high-side drive chip on the first projection plane and the orthographic projection of the second inverter low-side drive chip on the first projection plane.

13. The semiconductor device according to claim 1, characterized in that, The first inverter driver chip includes a first inverter high-side driver chip and a first inverter low-side driver chip, which are spaced apart laterally. The power supply voltage pins of the first inverter driver chip include a first inverter high-side gate drive power supply voltage pin and a first inverter low-side gate drive power supply voltage pin, which are interconnected. The first inverter high-side gate drive power supply voltage pin is electrically connected to the first inverter high-side driver chip, and the first inverter low-side gate drive power supply voltage pin is electrically connected to the first inverter low-side driver chip.

14. The semiconductor device according to claim 13, characterized in that, The first inverter high-side gate drive power supply voltage pin includes a first inverter first high-side power supply voltage pin portion and a first inverter second high-side power supply voltage pin portion. The first inverter first high-side power supply voltage pin portion extends laterally. The first inverter second high-side power supply voltage pin portion is disposed at one end of the first inverter first high-side power supply voltage pin portion laterally adjacent to one end of the second inverter drive pin frame. The first inverter second high-side power supply voltage pin portion extends longitudinally away from the substrate. The second inverter drive chip power supply voltage pin and the first inverter second high-side power supply voltage pin portion are spaced apart laterally. The first inverter low-side gate drive power supply voltage pin further includes a first inverter first low-side power supply voltage pin portion and a first inverter second low-side power supply voltage pin portion. The first inverter first low-side power supply voltage pin portion extends in the longitudinal direction. One end of the first inverter second low-side power supply voltage pin portion is connected to the end of the first inverter first low-side power supply voltage pin portion adjacent to the substrate in the longitudinal direction and extends in the transverse direction. The other end of the first inverter second low-side power supply voltage pin portion is connected to the first inverter first high-side power supply voltage pin portion.

15. The semiconductor device according to claim 14, characterized in that, The first inverter drive pin frame also includes a first inverter power supply support pin. One end of the first inverter power supply support pin is connected to the connection point of the first inverter first high-side power supply voltage pin and the first inverter second low-side power supply voltage pin. The other end of the first inverter power supply support pin extends longitudinally away from the substrate.

16. The semiconductor device according to claim 15, characterized in that, The first inverter drive pin frame includes a ground pin of a first inverter drive chip. The first inverter drive chip ground pin includes a first inverter first ground pin portion, a first inverter second ground pin portion, and a first inverter third ground pin portion. The first inverter first ground pin portion extends laterally and protrudes at least partially along the longitudinal side away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad that are spaced apart laterally. The first inverter high-side drive chip is disposed on the first inverter high-side drive pad, and the first inverter low-side drive chip is disposed on the first inverter low-side drive pad. The first inverter first ground pin extends laterally. The first inverter second ground pin and the first inverter third ground pin are respectively disposed at both ends of the first inverter first ground pin and both extend toward the side facing away from the substrate in the longitudinal direction. The first inverter second low-side power supply voltage pin and the first inverter first high-side power supply voltage pin are spaced apart on the side of the first inverter first ground pin facing away from the substrate in the longitudinal direction. The first inverter third ground pin, the first inverter first low-side power supply voltage pin, the first inverter power supply support pin, and the first inverter second high-side power supply voltage pin are arranged in a sequentially spaced manner in the lateral direction.

17. The semiconductor device according to claim 1, characterized in that, The PFC driver pin frame also includes a PFC driver chip ground pin. The PFC driver chip ground pin includes a PFC ground pin portion and a PFC driver pad portion. The PFC ground pin portion extends vertically. The PFC driver pad portion is disposed at one end of the PFC ground pin portion that is vertically adjacent to the substrate. The PFC driver pad portion protrudes from the PFC ground pin portion toward the side that is laterally adjacent to the second inverter driver pin frame. The PFC driver chip is disposed on the PFC driver pad portion. The PFC driver chip power supply voltage pins extend vertically and are spaced laterally at the side of the PFC ground pin portion facing the PFC driver pad portion. The PFC driver chip power supply voltage pins are also spaced vertically at the side of the PFC driver pad portion away from the substrate. The PFC driver pad portion is provided with a clearance notch on the side that is laterally opposite to the PFC ground pin portion. The clearance notch is located at one end of the PFC driver pad portion that is longitudinally adjacent to the power supply voltage pin of the PFC driver chip. The clearance notch is adapted to avoid at least a portion of the power supply voltage pin of the PFC driver chip that is longitudinally adjacent to one end of the substrate.

18. The semiconductor device according to claim 1, characterized in that, The substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion and the PFC power pad portion, and a rectifier chip is disposed on the rectifier bridge pad portion; The drive-side pin frame also includes a rectifier bridge drive pin frame, which corresponds at least partially in the longitudinal direction to the rectifier bridge pad portion. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion.

19. The semiconductor device according to claim 18, characterized in that, The lateral direction includes a first direction and a second direction, which are arranged in opposite directions. The first inverter power pad, the second inverter power pad, the PFC power pad, and the rectifier bridge pad are arranged sequentially in the first direction; or The rectifier bridge pads, the PFC power pads, the first inverter power pads, and the second inverter power pads are arranged sequentially in a first direction; or The first inverter power pad, the second inverter power pad, the rectifier bridge pad, and the PFC power pad are arranged sequentially in a first direction.

20. A circuit board assembly, characterized in that, The semiconductor device included in any one of claims 1-19.

21. An electrical control box, characterized in that, Includes the circuit board assembly as described in claim 20.

22. An electrical appliance, characterized in that, Includes the electrical control box as described in claim 21.

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