Chip module and manufacturing method thereof
By employing an insulating metal substrate, heat sink, sintered layer, and metal connector in the chip module, the problems of parasitic inductance and overheating during high-frequency switching are solved, resulting in a reduction in resistance and thermal resistance, improved reliability and product yield, and reduced manufacturing costs.
Patent Information
- Application Number
- CN202410526685.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-29
- Publication Date
- 2025-10-31
Smart Images
Figure CN120878701A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a chip module and its manufacturing method. Background Technology
[0002] Currently, most chip modules use wire bonding to electrically connect the chips to the circuit board. However, chip modules containing power chips may need to be used in products with high-frequency switching, but the aforementioned wire bonding packaging method is prone to parasitic inductance, which cannot meet the requirements of high-frequency switching, and is also prone to overheating problems. In addition, the ceramic substrates and silver sintered materials used in general chip modules are expensive, which increases manufacturing costs. Summary of the Invention
[0003] At least one embodiment of the present invention provides a chip module that can avoid the generation of parasitic inductance, reduce resistance and thermal resistance, improve reliability and product yield and reduce manufacturing costs.
[0004] At least another embodiment of the present invention provides a method for manufacturing the above-described chip module, which helps to improve the reliability and product yield of the chip module and reduce manufacturing costs.
[0005] A chip module according to at least one embodiment of the present invention includes a circuit board and multiple chips. The circuit board includes an insulating metal substrate, multiple heat sinks, multiple sintered layers, multiple metal connectors, and a connection layer. The heat sinks are disposed on and thermally coupled to the insulating metal substrate. The sintered layers are respectively disposed on and thermally coupled to the heat sinks. The metal connectors are respectively disposed on and thermally coupled to the sintered layers. The connection layer is disposed on the metal connectors. The chips are respectively disposed on the metal connectors and located between the metal connectors and the connection layer. Each chip includes a body, a first electrode, a second electrode, and a third electrode. The body has opposing upper and lower surfaces, with the upper surface being closer to the connection layer than the lower surface. The first electrode is disposed on the lower surface and electrically connected to one of the metal connectors. One of the metal connectors extends from the lower surface to the upper surface and is electrically connected to the connection layer. The second electrode is disposed on the upper surface and electrically connected to the connection layer. The third electrode is disposed on the upper surface and electrically connected to the connection layer.
[0006] In at least one embodiment of the present invention, the first electrode of one of the plurality of chips is electrically connected to the second electrode of another of the plurality of chips through the connection line layer.
[0007] In at least one embodiment of the present invention, the circuit board further includes a plurality of insulating layers disposed between the insulating metal substrate and the connection line layer.
[0008] In at least one embodiment of the present invention, the glass transition temperature of each insulating layer is not less than 230°C.
[0009] In at least one embodiment of the present invention, the circuit board further includes a plurality of filling resins, which surround the plurality of heat sinks and the plurality of chips respectively.
[0010] In at least one embodiment of the present invention, the material of each sintered layer is copper paste, and the thermal conductivity of each sintered layer is 250 to 393 W / mK.
[0011] A method for manufacturing a chip module according to at least one embodiment of the present invention includes a patterned first core board having opposing first and second sides. A metal layer is formed on the first side. A plurality of first slots are formed, penetrating the first core board and the metal layer. A first release layer is attached to the second side. A plurality of chips are respectively disposed in the first slots and attached to the first release layer. A first resin is filled into the first slots to surround the chips. The first release layer is removed to expose the second side. A circuit layer is formed on the second side. A plurality of second slots are formed on the second core board, penetrating the second core board. After forming the second slots, a second release layer is attached to one side of the second core board. A plurality of heat sinks are respectively disposed in the second slots and attached to the second release layer. A second resin is filled into the second slots to surround the heat sinks. The second release layer is removed. A plurality of sintered layers are formed on the heat sinks. An insulating layer is disposed between the second side of the first core board and the second core board. A first core board, an insulating layer, and a second core board are laminated together, with the chips located on these sintered layers. After laminating the first core board, the insulating layer, and the second core board, the first core board, the insulating layer, and the second core board are placed on an insulating metal substrate and laminated together.
[0012] In at least one embodiment of the present invention, the width of each of the first slots is 0.4 to 0.6 mm larger than the width of each of the chips.
[0013] In at least one embodiment of the present invention, before forming the metal layer on the first side, the method of manufacturing the chip module further includes patterning an insulating layer of the first core board to form a plurality of openings, and the step of forming the metal layer on the first side includes forming the metal layer on the first side and filling the openings to electrically connect the metal layer of the first core board having the second side, wherein the metal layer, the metal layer of the first core board having the second side, and the circuit layer form a plurality of metal connections.
[0014] In at least one embodiment of the present invention, the step of disposing and laminating the first core board, the insulating layer, and the second core board on the insulating metal substrate includes providing the insulating metal substrate, a bottom circuit material layer, another insulating layer, and a connecting circuit material layer, wherein the insulating metal substrate is located between the bottom circuit material layer and the second core board, and the other insulating layer is located between the first core board and the connecting circuit material layer. The connecting circuit material layer, the other insulating layer, the first core board, the insulating layer, the second core board, the insulating metal substrate, and the bottom circuit material layer are then laminated. The connecting circuit material layer and the bottom circuit material layer are patterned to form the connecting circuit layer and the bottom circuit layer. Attached Figure Description
[0015] Figure 1 This is a partial cross-sectional schematic diagram of a chip module according to at least one embodiment of the present invention.
[0016] Figures 2A to 2L yes Figure 1 Partial cross-sectional views of the chip module at different process stages. Detailed Implementation
[0017] In the following text, to clearly present the technical features of the present invention, the dimensions (e.g., length, width, thickness, and depth) of the elements (e.g., layers, films, substrates, and regions) in the accompanying drawings will be enlarged proportionally, and the number of some elements may be reduced. Therefore, the description and explanation of the embodiments below are not limited to the number of elements in the drawings or the size and shape of the elements, but should cover deviations in size, shape, and both caused by actual manufacturing processes and / or tolerances. For example, a flat surface shown in the drawings may have rough and / or non-linear characteristics, and an acute angle shown in the drawings may be rounded. Therefore, the elements presented in the accompanying drawings of the present invention are primarily for illustration and are not intended to precisely depict the actual shape of the elements, nor are they intended to limit the claims of the present invention.
[0018] Secondly, the terms "approximately," "about," or "substantially" used in this invention not only cover explicitly stated numerical values and ranges, but also the permissible deviation range understood by those skilled in the art. This deviation range can be determined by errors generated during measurement, which may arise from limitations of the measurement system or process conditions. For example, two objects (e.g., planes or traces of a substrate) are "substantially parallel" or "substantially perpendicular," where "substantially parallel" and "substantially perpendicular" respectively represent that the parallelism and perpendicularity between the two objects can include non-parallelism and non-perpendicularity caused by the permissible deviation range.
[0019] The spatial relative terms used in this invention, such as "below," "under," "above," and "above," are for the convenience of describing the relative relationship between one element or feature and another, as illustrated in the figures. The true meaning of these spatial relative terms includes other orientations. For example, when the figures are rotated 180 degrees vertically, the relationship between one element and another may change from "below" or "under" to "above" or "above." Furthermore, the spatial relative descriptions used in this invention should be interpreted in the same way.
[0020] It should be understood that although the present invention may use terms such as "first," "second," and "third" to describe various elements or features, these elements or features should not be limited by these terms. These terms are primarily used to distinguish one element from another, or one feature from another. Furthermore, the term "or" as used in the present invention may, as appropriate, include any combination of one or more of the associated listed items.
[0021] Although this invention uses a series of operations or steps to illustrate the manufacturing method, the order in which these operations or steps are shown should not be construed as a limitation of the invention. For example, some operations or steps may be performed in a different order and / or simultaneously with other steps. Furthermore, each operation or step described herein may comprise multiple sub-steps or actions.
[0022] Furthermore, the present invention can be implemented or applied through other different specific embodiments, and the details of the present invention can also be combined, modified and changed in various embodiments based on different viewpoints and applications without departing from the concept of the present invention.
[0023] Figure 1 This is a partial cross-sectional schematic diagram of a chip module according to at least one embodiment of the present invention. Please refer to... Figure 1 The chip module 10 includes a circuit board 100 and multiple chips 200. The circuit board 100 includes an insulated metal substrate (IMS) 101, multiple heat sinks 102, multiple sintered layers 103, multiple metal connectors 104, and a connection line layer 105.
[0024] These heat sinks 102 are disposed on and thermally coupled to the insulating metal substrate 101. These sintered layers 103 are disposed on and thermally coupled to the heat sinks 102 respectively. These metal connection portions 104 are disposed on and thermally coupled to the sintered layers 103 respectively. The connection line layer 105 is disposed on the metal connection portions 104.
[0025] In some embodiments, the heat sink 102, the sintered layer 103, and the metal connection portion 104 can directly contact the insulating metal substrate 101, the heat sink 102, and the sintered layer 103 respectively to thermally couple the insulating metal substrate 101, the heat sink 102, and the sintered layer 103 respectively, or they can be thermally coupled to the insulating metal substrate 101, the heat sink 102, and the sintered layer 103 respectively through a thermally conductive layer disposed between the heat sink 102 and the insulating metal substrate 101, a thermally conductive layer disposed between the sintered layer 103 and the heat sink 102, and a thermally conductive layer disposed between the metal connection portion 104 and the sintered layer 103 respectively.
[0026] These chips 200 are respectively disposed on these metal connection portions 104 and located between these metal connection portions 104 and the connection line layer 105. Each chip 200 includes a body BD, a first electrode DE, a second electrode SE, and a third electrode GE that are separated from each other.
[0027] The chip 200 body BD has an upper surface US and a lower surface LS. The upper surface US is closer to the connection line layer 105 than the lower surface LS. The first electrode DE is disposed on the lower surface LS and electrically connected to one of the metal connection portions 104. One of the metal connection portions 104 extends from the lower surface LS to the upper surface US and is electrically connected to the connection line layer 105. The second electrode SE is disposed on the upper surface US and electrically connected to the connection line layer 105. The third electrode GE is disposed on the upper surface US and electrically connected to the connection line layer 105.
[0028] Heat dissipation is aided by thermally coupling the first electrode DE of the chip 200 to the metal connection portion 104, sintered layer 103, heat sink 102, and insulating metal substrate 101. The metal connection portion 104 then transfers the first electrode DE, located on the lower surface LS, to the upper surface US, placing it on the same side as the second electrode SE and the third electrode GE. This reduces resistance and facilitates electrical testing. Replacing wire bonding or through-hole connection with the metal connection portion 104 and the connection layer 105 avoids parasitic inductance and reduces resistance and thermal resistance, thereby improving reliability and product yield. Furthermore, replacing the ceramic substrate with an insulating metal substrate reduces manufacturing costs.
[0029] Please continue reading. Figure 1 The first electrode DE of one of these chips 200 is electrically connected to the second electrode SE of another of these chips 200 via a connection layer 105. In detail, Figure 1 The first electrode DE of the chip 200 on the right side is connected to the connection line layer 105 through the metal connection portion 104, while Figure 1 The second electrode SE of the chip 200 on the left side is connected to the connection line layer 105 through the metal connection portion 104, thereby achieving electrical connection. Figure 1The first electrode DE of chip 200 on the right side of the middle is shown. The aforementioned electrical connection enables a half-bridge circuit, effectively reducing resistance.
[0030] Furthermore, the first electrode DE, the second electrode SE, and the third electrode GE of the same chip 200 are electrically connected to a portion of the connection line layer 105, which is separated from each other. That is, the first electrode DE, the second electrode SE, and the third electrode GE of the same chip 200 are not electrically connected to the connection line layer 105.
[0031] The circuit board 100 has a first surface S1 and a second surface S2 opposite to each other. The connection line layer 105 has a first surface S1. The circuit board 100 also includes a bottom line layer 113. An insulating metal substrate 101 is located between the bottom line layer 113 and the heat sink 102. The bottom line layer 113 has a second surface S2.
[0032] like Figure 1 As shown, the circuit board 100 further includes multiple insulating layers 106, 107, 108, and 109 disposed between the insulating metal substrate 101 and the interconnect layer 105. Specifically, insulating layer 106 is located between the heat sink 102 and the metal connection portion 104 and surrounds the sintered layer 103. Insulating layer 107 is located between the chip 200 and the interconnect layer 105, and the interconnect layer 105 passes through insulating layer 107 to electrically connect to the chip 200. Insulating layer 108 is located between the insulating metal substrate 101 and the sintered layer 103 and surrounds the heat sink 102; that is, the heat sink 102 passes through insulating layer 108 to thermally couple the sintered layer 103 and the insulating metal substrate 101. The insulating layer 109 is located between the sintered layer 103 and the connection line layer 105 and surrounds the chip 200 and the metal connection portion 104. That is, the metal connection portion 104 passes through the insulating layer 109 to be electrically connected to the connection line layer 105 and the thermally coupled sintered layer 103.
[0033] The circuit board 100 also includes multiple filling resins 110, 111, and 112. The filling resins 110 and 111 surround the chip 200 and the heat sink 102 respectively, while the filling resin 112 is located between the second electrode SE and the third electrode GE of the chip 200.
[0034] Specifically, the filling resin 111 is located in the gap between the insulating layer 108 and the heat sink 102, that is, the filling resin 111 surrounds the heat sink 102, and the insulating layer 108 surrounds the filling resin 111. The filling resin 110 is located in the gap between the insulating layer 109 and the chip 200, that is, the filling resin 110 surrounds the chip 200, and the insulating layer 109 surrounds the filling resin 110. Furthermore, in the vertical direction of the insulating metal substrate 101, the insulating metal substrate 101, the heat sink 102, the sintering layer 103, and the chip 200 are sequentially stacked.
[0035] In some embodiments, the materials of the heat sink 102, metal connector 104, connection layer 105, and bottom circuit layer 113 may include copper. The insulating layers 106, 107, 108, and 109 may be prepreg, with a glass transition temperature of not less than 230°C and a coefficient of thermal expansion of 9 to 10 ppm / °C. The sintered layer 103 may be made of copper paste, with a thermal conductivity of 250 to 393 W / mK and a coefficient of thermal expansion of 3 to 17 ppm / °C. The aforementioned material selection and physical properties aid in heat dissipation, thereby improving reliability and product yield.
[0036] In some embodiments, chip 200 may be a power chip, such as a power semiconductor device. For example, chip 200 may be a silicon carbide power device, and the first electrode DE, the second electrode SE, and the third electrode GE may be the drain, source, and gate of chip 200, respectively. Furthermore, chip module 10 may be applied to products such as power inverters (DC-AC inverters) or power modules.
[0037] Figures 2A to 2L yes Figure 1 Partial cross-sectional views of the chip module at different process stages. Please refer to... Figures 2A to 2B A patterned first core board C1 has a first side E1 and a second side E2. The first core board C1 includes an insulating layer 109, a metal layer (unlabeled) having the first side E1, and a metal layer (unlabeled) having the second side E2.
[0038] In detail, firstly, such as Figure 2A As shown, a metal layer with a first side E1 is patterned. Next, as... Figure 2B As shown, the insulating layer 109 is patterned to form a plurality of openings O. In some embodiments, the metal layer having the first side E1 may be patterned by an etching process, and the insulating layer 109 may be patterned by a laser process or a milling process to form these openings O.
[0039] Please see Figure 2C A metal layer M is formed on the first side E1. In addition to being formed on the first side E1, the metal layer M also fills the openings O to electrically connect the metal layer on the second side E2 of the first core plate C1. In some embodiments, the material of the metal layer M may include copper, and the metal layer M may be formed by electroplating.
[0040] Please see Figure 2DMultiple first slots T1 are formed, penetrating the first core plate C1 and the metal layer M. After forming these first slots T1, a first release layer R1 is attached to the second side E2. In some embodiments, these first slots T1 may be formed by a milling process, and the first release layer R1 may comprise polyester tape.
[0041] Please see Figure 2E After attaching the first release layer R1, multiple chips 200 are respectively disposed in these first slots T1 and attached to the first release layer R1. In some embodiments, the width W1 of the first slot T1 is 0.4 to 0.6 mm larger than the width W2 of the chip 200, that is, there is a gap between the chip 200 and the first slot T1.
[0042] Please see Figure 2F After the chips 200 are respectively disposed in the first slots T1 and attached to the first release layer R1, a first resin F1 is filled into the first slots T1 to surround the chips 200. Specifically, the first resin F1 is filled in the gaps and between the second electrode SE and the third electrode GE of the chip 200. In some embodiments, the first resin F1 may be filled by a printing process.
[0043] Please see Figure 2G After filling the first resin F1 to surround the chips 200, the first release layer R1 is removed to expose the second side E2. After removing the first release layer R1, a circuit layer WL is formed on the second side E2. Specifically, the first resin F1 can be cured first to form filling resins 110 and 112 before removing the first release layer R1. Next, a circuit layer WL is formed on the second side E2. The circuit layer WL is electrically connected to the metal layer of the first core board C1 having the second side E2. The metal layer M, the metal layer of the first core board C1 having the second side E2, and the circuit layer WL form a plurality of metal connection portions 104. In addition, other circuits can also be formed on the metal layer M, the metal layer of the first core board C1 having the second side E2, and the circuit layer WL.
[0044] In some embodiments, in addition to forming a circuit layer WL on the second side E2, another metal layer (not labeled) may be formed on the metal layer M. The materials of the circuit layer WL and the other metal layer may include copper, and the circuit layer WL and the other metal layer may be formed by an electroplating process. Furthermore, the first resin F1 may be cured by a baking process.
[0045] Please see Figure 2HMultiple second slots T2 are formed on the second core board C2, and these second slots T2 penetrate the second core board C2. After forming these second slots T2, a second release layer R2 is attached to one side of the second core board C2. After attaching the second release layer R2 to one side of the second core board C2, multiple heat sinks 102 are respectively disposed in these second slots T2 and attached to the second release layer R2.
[0046] like Figure 2H As shown, the second core board C2 includes an insulating layer 108 and two metal layers (not labeled) located on opposite sides of the insulating layer 108. The width of the second slot T2 is greater than the width of the heat sink 102, i.e., there is a gap between the heat sink 102 and the second slot T2. In some embodiments, these second slots T2 can be formed by a milling process, and the second release layer R2 may include polyester tape.
[0047] Please see Figure 2I After the heat sinks 102 are respectively disposed in the second slots T2 and attached to the second release layer R2, the second resin F2 is filled into the second slots T2 to surround the heat sinks 102. After filling the heat sinks 102 with the second resin F2, the second release layer R2 is removed. Specifically, the second resin F2 is filled in the aforementioned gaps, and before removing the second release layer R2, the second resin F2 can be cured to form a filling resin 111. In some embodiments, the second resin F2 can be cured by a baking process.
[0048] Please see Figure 2J After removing the second release layer R2, a plurality of sintered layers 103 are formed on these heat sinks 102. After forming these sintered layers 103, an insulating layer 106 is disposed between the second side E2 of the first core plate C1 and the second core plate C2. In some embodiments, these sintered layers 103 may be formed by a printing process and a baking process.
[0049] Please see Figure 2K The first core board C1, the insulating layer 106, and the second core board C2 are laminated together, and these chips 200 are respectively located on these sintered layers 103. Please refer to [link / reference]. Figure 2L After pressing the first core plate C1, the insulating layer 106 and the second core plate C2, the first core plate C1, the insulating layer 106 and the second core plate C2 are disposed on the insulating metal substrate 101 and pressed together.
[0050] In detail, an insulating metal substrate 101, a bottom circuit material layer 113', an insulating layer 107, and a connecting circuit material layer 105' are provided. The insulating metal substrate 101 is located between the bottom circuit material layer 113' and the second core board C2, and the insulating layer 107 is located between the first core board C1 and the connecting circuit material layer 105'. The connecting circuit material layer 105', the insulating layer 107, the first core board C1, the insulating layer 106, the second core board C2, the insulating metal substrate 101, and the bottom circuit material layer 113' are laminated together.
[0051] Next, the connecting circuit material layer 105' and the bottom circuit material layer 113' are patterned to form the connecting circuit layer 105 and the bottom circuit layer 113, such as Figure 1 As shown. In some embodiments, the connecting line material layer 105' and the bottom line material layer 113' can be patterned by an etching process, and a plurality of conductive blind vias (not labeled) can be formed in the insulating layer 107 by a laser process and an electroplating process, through which the connecting line layer 105 can electrically connect the metal connection portions 104. In addition, the materials of the connecting line layer 105 and the bottom line layer 113 may include copper.
[0052] In summary, the chip module and its manufacturing method according to at least one embodiment of the present invention, through the thermal coupling of the chip's electrodes to the metal connection portion, sintered layer, heat sink, and insulating metal substrate, can aid in heat dissipation. Furthermore, the metal connection portion transfers the electrodes located on the lower surface of the chip to the upper surface, placing them on the same side as the other electrodes of the chip. This not only reduces resistance but also facilitates electrical testing. Using metal connection portions and interconnection layers instead of wire bonding or through-hole conduction avoids parasitic inductance and reduces resistance and thermal resistance, thereby improving reliability and product yield. In addition, using an insulating metal substrate instead of a ceramic substrate reduces manufacturing costs.
[0053] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.
[0054] [Symbol Explanation]
[0055] 10: Chip Module
[0056] 100: Circuit board
[0057] 101: Insulating metal substrate
[0058] 102: Heat sink
[0059] 103: Sintered layer
[0060] 104: Metal connection part
[0061] 105: Connection Line Layer
[0062] 105': Connecting line material layer
[0063] 106, 107, 108, 109: Insulation layer
[0064] 110, 111, 112: Filler resin
[0065] 113: Bottom Circuit Layer
[0066] 113': Bottom circuit material layer
[0067] 200: Chip
[0068] BD: Ontology
[0069] C1: First Core Board
[0070] C2: Second Core Board
[0071] DE: First electrode
[0072] E1: First side
[0073] E2: Second side
[0074] F1: First Resin
[0075] F2: Second resin
[0076] GE: Third electrode
[0077] LS: Lower surface
[0078] M: Metal layer
[0079] O: Opening
[0080] R1: First release layer
[0081] R2: Second release layer
[0082] SE: Second electrode
[0083] S1: First surface
[0084] S2: Second surface
[0085] T1: First slot
[0086] T2: Second slot
[0087] US: Upper surface
[0088] WL: Line Layer
[0089] W1, W2: Width.
Claims
1. A chip module, characterized in that, include: Circuit board, including: Insulating metal substrate; Multiple heat sinks are disposed on the insulating metal substrate and thermally coupled to the insulating metal substrate; Multiple sintered layers are respectively disposed on the multiple heat sinks and thermally coupled to the multiple heat sinks; Multiple metal connectors are respectively disposed on the multiple sintered layers and thermally coupled to the multiple sintered layers; and A connection layer is disposed on the plurality of metal connectors; and Multiple chips are respectively disposed on the multiple metal connectors and located between the multiple metal connectors and the connection line layer, each chip comprising: The body has opposing upper and lower surfaces, wherein the upper surface is closer to the connection layer than the lower surface; and A first electrode is disposed on the lower surface and electrically connected to one of the plurality of metal connection portions, wherein one of the plurality of metal connection portions extends from the lower surface to the upper surface and is electrically connected to the connection line layer; A second electrode is disposed on the upper surface and electrically connected to the connection line layer; and The third electrode is disposed on the upper surface and electrically connected to the connection line layer.
2. The chip module according to claim 1, characterized in that, The first electrode of one of the plurality of chips is electrically connected to the second electrode of another of the plurality of chips through the connection layer.
3. The chip module according to claim 1, characterized in that, The circuit board also includes multiple insulating layers disposed between the insulating metal substrate and the connection line layer.
4. The chip module according to claim 3, characterized in that, The glass transition temperature of each insulating layer is not less than 230°C.
5. The chip module according to claim 1, characterized in that, The circuit board also includes multiple filling resins, which surround the multiple heat sinks and the multiple chips respectively.
6. The chip module according to claim 1, characterized in that, The material of each sintered layer is copper paste, and the thermal conductivity of each sintered layer is 250 to 393 W / mK.
7. A method for manufacturing a chip module, characterized in that, include: A patterned first core plate, wherein the first core plate has opposing first and second sides; A metal layer is formed on the first side; Multiple first slots are formed, penetrating the first core plate and the metal layer; The first release layer is attached to the second side; Multiple chips are respectively disposed in the multiple first slots and attached to the first release layer; A first resin is filled into the plurality of first slots to surround the plurality of chips; Remove the first release layer to expose the second side; A circuit layer is formed on the second side; Multiple second slots are formed in the second core plate, and the multiple second slots penetrate the second core plate; After the plurality of second slots are formed, a second release layer is attached to one side of the second core plate; Multiple heat sinks are respectively disposed in the multiple second slots and attached to the second release layer; A second resin is filled into the plurality of second slots to surround the plurality of heat sinks; Remove the second release layer; Multiple sintered layers are formed on the plurality of heat sinks respectively; An insulating layer is disposed between the second side of the first core plate and the second core plate; The first core board, the insulating layer, and the second core board are laminated together, wherein the plurality of chips are respectively located on the plurality of sintered layers; and After pressing the first core plate, the insulating layer and the second core plate together, the first core plate, the insulating layer and the second core plate are disposed on the insulating metal substrate and pressed together.
8. The method for manufacturing a chip module according to claim 7, characterized in that, The width of each of the first slots is 0.4 to 0.6 mm larger than the width of each of the chips.
9. The method for manufacturing a chip module according to claim 7, characterized in that, Before forming the metal layer on the first side, the step further includes patterning an insulating layer of the first core plate to form a plurality of openings, and the step of forming the metal layer on the first side includes: The metal layer is formed on the first side and the plurality of openings are filled to electrically connect the metal layer on the second side of the first core board, wherein the metal layer, the metal layer on the second side of the first core board and the circuit layer form a plurality of metal connections.
10. The method for manufacturing a chip module according to claim 7, characterized in that, The step of depositing the first core plate, the insulating layer, and the second core plate onto the insulating metal substrate and then laminating them includes: The facility provides an insulating metal substrate, a bottom circuit material layer, another insulating layer, and a connecting circuit material layer, wherein the insulating metal substrate is located between the bottom circuit material layer and the second core board, and the other insulating layer is located between the first core board and the connecting circuit material layer; The bonding process involves laminating the connecting circuit material layer, the other insulating layer, the first core board, the insulating layer, the second core board, the insulating metal substrate, and the bottom circuit material layer; and The connecting line material layer and the bottom line material layer are patterned to form the connecting line layer and the bottom line layer.