Semiconductor element and manufacturing method thereof

Abstract

The invention provides a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a first active region, a second active region, a first test module and a second test module. The second active area is separated from the first active area by a cutting line. The cutting line extends along a first direction. The first test module is adjacent to the first active area and is arranged in the cutting line. The second test module is adjacent to the second active area and is arranged in the cutting line. The first test module and the second test module are arranged along a second direction substantially orthogonal to the first direction.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 650,416 (i.e., priority date "April 30, 2024"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for manufacturing the same, and more specifically, to a semiconductor device comprising a test module and a method for manufacturing the same. Background Technology

[0003] When performing dicing techniques, cutting metal material within the dicing line can generate debris that may damage the device cavity. This is especially true when cutting conductive vias with relatively large heights, as this produces a significant amount of debris. To address these issues, new semiconductor devices and manufacturing methods are needed.

[0004] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in this paragraph constitutes prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts discussed in the preceding technical paragraphs, constitutes prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a first active region, a second active region, a first test module, and a second test module. The second active region is separated from the first active region by a dicing line. The dicing line extends along a first direction. The first test module is adjacent to the first active region and disposed within the dicing line. The second test module is adjacent to the second active region and disposed within the dicing line. The first test module and the second test module are arranged along a second direction substantially orthogonal to the first direction.

[0006] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a first active region, a second active region, and a first test module. The second active region is separated from the first active region by a dicing line. The dicing line extends along a first direction. The first test module is adjacent to the first active region and disposed within the dicing line. The first test module includes a test pad, a test circuit, and a via structure. The via structure connects to the test pad. The via structure is closer to the first active region than the first test circuit.

[0007] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: forming a plurality of active regions, including a first active region and a second active region, the second active region being separated from the first active region by a dicing line extending along a first direction; and forming a first test module and a second test module within the dicing line, wherein the first test module and the second test module are arranged along a second direction substantially perpendicular to the first direction.

[0008] Embodiments of this disclosure provide a semiconductor device including a plurality of test modules located within a dicing line extending along a first direction. A first test module and a second test module are arranged along a second direction substantially perpendicular to the first direction. A dicing region is located between the first test module and the second test module. This arrangement avoids cutting conductive components (e.g., traces and / or vias) of the first and second test modules, thereby preventing metal fragments from damaging the device cavity.

[0009] The technical features and advantages of this disclosure have been summarized quite extensively above to provide a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims of this disclosure will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily used to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art to which this disclosure pertains will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0010] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings in conjunction with the embodiments and claims, wherein the same element symbols represent similar elements in all the drawings, and:

[0011] Figure 1 This is a top view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0012] Figure 2 Examples of some embodiments of this disclosure Figure 1 An enlarged view of the area shown by the dashed line.

[0013] Figure 3 Examples of some embodiments of this disclosure are illustrated along the lines of Figure 2 The sectional view intercepted by section line A-A' in the diagram.

[0014] Figure 4 Examples of some embodiments of this disclosure are illustrated along the lines of Figure 2 The sectional view taken by section line B-B' in the diagram.

[0015] Figure 5 This is a top view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0016] Figure 6 This is a top view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0017] Figure 7 This is a top view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0018] Figure 8 This disclosure illustrates one or more stages of an example of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0019] Figure 9 This disclosure illustrates one or more stages of an example of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0020] Figure 10 This is a flowchart illustrating a method for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 1a: Semiconductor element

[0023] 1b: Semiconductor components

[0024] 1c: Semiconductor components

[0025] 1d: Semiconductor element

[0026] 2: Method

[0027] 10: Wafers

[0028] 20: Active Zone

[0029] 20-1: Active Zone

[0030] 20-2: Active Zone

[0031] 22: Grain

[0032] 24: Grain

[0033] 30: Cutting line

[0034] 30c: Cutting area

[0035] 40-1: Test Module

[0036] 40-2: Test Module

[0037] 40-3: Test Module

[0038] 40-4: Test Module

[0039] 41-1: Test Circuit

[0040] 41-2: Test Circuit

[0041] 41-3: Test Circuit

[0042] 41-4: Test Circuit

[0043] 42-1: Test pad

[0044] 42-2: Test pad

[0045] 42-3: Test pad

[0046] 42-4: Test pad

[0047] 43-1: Internal Wiring Structure

[0048] 43-2: Internal Wiring Structure

[0049] 43-3: Internal Wiring Structure

[0050] 43-4: Internal Wiring Structure

[0051] 45: Wiring

[0052] 46: Through hole

[0053] 51: Substrate

[0054] 52: Integrated Circuit Area

[0055] 53: Dielectric Structure

[0056] 54: Redistribution Structure

[0057] 56: Passivation layer

[0058] 57: Terminal

[0059] 202: Operation

[0060] 204: Operation

[0061] 206: Operation

[0062] 208: Operation

[0063] P1: Segmentation Techniques

[0064] R: Region

[0065] W1: Width Detailed Implementation

[0066] The embodiments or exemplary cases of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.

[0067] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0068] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context otherwise requires. It should be further understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.

[0069] See Figure 1 , Figure 1 This is a top view illustrating a semiconductor element 1a according to some embodiments of the present disclosure. The semiconductor element 1a may include a wafer 10 and a plurality of active regions 20 located on the wafer 10. Each active region 20 may be separated by dicing lines 30.

[0070] Active region 20 (or die region) may include integrated circuits. Active region 20 may include active components, such as memory circuits (e.g., dynamic random-access memory (DRAM) circuits, static random-access memory (SRAM) circuits, etc.), power management circuits (e.g., power management integrated circuit (PMIC) circuits), logic circuits (e.g., central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) circuits, sensor circuits, micro-electro-mechanical system (MEMS) circuits, signal processing circuits (e.g., digital signal processing (DSP) circuits), front-end circuits (e.g., analog front-end (AFE) circuits), or other active components. Active region 20 may also include passive components, such as resistors, inductors, or other passive components.

[0071] The cutting line 30 can extend along both the X and Y directions. In some embodiments, the cutting line 30 can be configured to separate the active region 20. In some embodiments, the cutting line 30 can be a region where a test module is formed, and the test module is used to test the performance of the active region 20. In some embodiments, the cutting line 30 is a region that can be cut or sawn using a segmentation technique.

[0072] Although not shown Figure 1 However, it should be noted that the semiconductor element 1a may include other regions as needed. For example, a sealing region including multiple gaskets and vias located within the substrate may be located between the active region 20 and the dicing line 30, and the sealing region is used to prevent breakage during the dicing process.

[0073] Figure 2 Examples of some embodiments of this disclosure Figure 1 An enlarged view of the dashed area R shown.

[0074] Semiconductor device 1a may include an active region 20-1 and an active region 20-2 adjacent to the active region 20-1. The active regions 20-1 and 20-2 may be arranged along the Y direction. The active regions 20-1 and 20-2 may be separated by a dicing line 30.

[0075] The cutting line 30 may extend along the X direction. The cutting line 30 may be positioned between active region 20-1 and active region 20-2. In some embodiments, the cutting line 30 may define a cutting region 30c. In some embodiments, the cutting region 30c may be a region on which a segmentation technique is performed. In some embodiments, the cutting region 30c may be removed or cut by laser grooving, laser drilling, or other suitable techniques. In some embodiments, the width W1 of the cutting region 30c along the Y direction may be between 1µm and 30µm. The cutting region 30c may extend along a first direction. In some embodiments, after the segmentation technique is performed, the remaining area of ​​the cutting line, excluding the cutting region 30c, may remain connected to active region 20-1 or active region 20-2.

[0076] In some embodiments, semiconductor element 1a may include test modules 40-1, 40-2, 40-3, and 40-4. Test modules 40-1, 40-2, 40-3, and 40-4 may be located within the dicing line 30. In some embodiments, test modules 40-1 and 40-2 may be arranged along the Y direction. In some embodiments, test modules 40-1 and 40-3 may be arranged along the X direction. In some embodiments, test modules 40-2 and 40-4 may be arranged along the X direction.

[0077] In some embodiments, test module 40-1 may include test circuit 41-1, test pad 42-1, and internal interconnect structure 43-1. Test module 40-2 may include test circuit 41-2, test pad 42-2, and internal interconnect structure 43-2. ​​Test module 40-3 may include test circuit 41-3, test pad 42-3, and internal interconnect structure 43-3. Test module 40-4 may include test circuit 41-4, test pad 42-4, and internal interconnect structure 43-4. In some embodiments, cutting area 30c may be disposed between test module 40-1 and test module 40-2. In some embodiments, cutting area 30c may be disposed between test module 40-3 and test module 40-4.

[0078] Each of test circuits 41-1 to 41-4 can be configured to be tested to obtain the electrical characteristics of active region 20-1 or active region 20-2. In some embodiments, each of test circuits 41-1 to 41-4 may include active elements, such as memory circuits (e.g., dynamic random access memory circuits and static random access memory circuits), power management circuits (e.g., power management integrated circuit circuits), logic circuits (e.g., central processing unit, graphics processing unit, application processor, microcontroller, etc.), radio frequency circuits, sensor circuits, microelectromechanical systems (MEMS) circuits, signal processing circuits (e.g., digital signal processing circuits), front-end circuits (e.g., analog front-end circuits), or other active elements. Each of test circuits 41-1 to 41-4 may include passive elements, such as resistors, inductors, or other passive elements.

[0079] In some embodiments, test circuits 41-1 and 41-3 may be arranged or aligned along the X direction. In some embodiments, test circuits 41-1 and 41-2 may be arranged or aligned along the Y direction. In some embodiments, each of test circuits 41-1 to 41-4 may not overlap with the cutting area 30c along the Z direction. In some embodiments, the cutting area 30c may be disposed between test circuits 41-1 and 41-2. In some embodiments, the cutting area 30c may be disposed between test circuits 41-3 and 41-4. Each of test circuits 41-1 to 41-4 may be disposed outside the cutting area 30c.

[0080] Each of test pads 42-1 to 42-4 may be exposed via the surface of wafer 10. Each of test pads 42-1 to 42-4 may be electrically connected to test circuits 41-1 to 41-4, respectively. Each of test pads 42-1 to 42-4 may be configured to connect to external components (not shown) to measure the electrical characteristics of test circuits 41-1 to 41-4. In some embodiments, test circuit 41-1 and test pad 42-1 may be arranged along the X direction from the top view. In some embodiments, test pads 42-1 and 42-2 may be arranged or aligned along the Y direction. In some embodiments, test pads 42-1 and 42-3 may be arranged or aligned along the X direction. In some embodiments, each of test pads 42-1 to 42-4 may not overlap with the cut area 30c along the Z direction. In some embodiments, the cut area 30c may be disposed between test pads 42-1 and 42-2. In some embodiments, the cutting area 30c may be disposed between test pad 42-3 and test pad 42-4.

[0081] Each of the interconnect structures 43-1 to 43-4 can be disposed on the substrate ( Figure 2 (Unless otherwise noted). Interconnect structure 43-1 can electrically connect test circuit 41-1 and test pad 42-1. Interconnect structure 43-2 can electrically connect test circuit 41-2 and test pad 42-2. Interconnect structure 43-3 can electrically connect test circuit 41-3 and test pad 42-3. Interconnect structure 43-4 can electrically connect test circuit 41-4 and test pad 42-4. Each of interconnect structures 43-1 to 43-4 may include a redistribution structure. The redistribution structure may include conductive traces and vias embedded within the dielectric structure. In some embodiments, each of interconnect structures 43-1 to 43-4 may not overlap with the cut area 30c along the Z direction. In some embodiments, the cut area 30c may be disposed between interconnect structures 43-1 and 43-2. In some embodiments, the cutting area 30c may be disposed between the interconnect structure 43-3 and the interconnect structure 43-4.

[0082] See Figure 3 and Figure 4 , Figure 3 Examples of some embodiments of this disclosure are illustrated along the lines of Figure 2 The sectional view intercepted by section line A-A' in the diagram, and Figure 4 Examples of some embodiments of this disclosure are illustrated along the lines of Figure 2 The sectional view taken by section line B-B' in the diagram.

[0083] Semiconductor element 1a may include substrate 51. Substrate 51 may be a semiconductor substrate, such as a host semiconductor, semiconductor-on-insulator (SOI) substrate, or similar substrate. Substrate 51 may include elemental semiconductors, including monocrystalline, polycrystalline, or amorphous silicon or germanium; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of silicon, silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, gallium aluminum arsenide, indium gallium arsenide, indium gallium phosphide, and indium gallium arsenide phosphide; any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a silicon-germanium alloy having a gradient silicon characteristic structure, wherein the silicon and germanium composition changes from one ratio at one location of the gradient silicon-germanium characteristic structure to another ratio at another location. In another embodiment, the silicon-germanium alloy is formed on a silicon substrate. In some embodiments, the silicon-germanium alloy may be mechanically strained by another material in contact with the silicon-germanium alloy. In some embodiments, substrate 51 may have a multilayer structure, or substrate 51 may include a multilayer compound semiconductor structure.

[0084] like Figure 3 and Figure 4 As shown, the test circuit 41-1 may be formed at least partially within or on the substrate 51.

[0085] Semiconductor element 1a may include integrated circuit region 52. Integrated circuit region 52 may be at least partially formed within or on substrate 51. Integrated circuit region 52 may include integrated circuits, which may include transistors and / or other suitable components.

[0086] Semiconductor element 1a may include a dielectric structure 53. The dielectric structure 53 may be disposed on or above a substrate 51. An interconnect structure 43-1, including traces 45 and vias 46, may be disposed within the dielectric structure 53. In some embodiments, the dielectric structure 53 may be disposed in an active region 20-1. In some embodiments, a portion of the dielectric structure 53 may be disposed in a dicing line 30. In some embodiments, the dielectric structure 53 may be disposed outside a dicing region 30c. In some embodiments, the dicing region 30c may be defined by the sidewalls of the dielectric structure 53. The dielectric structure 53 may include an oxygen-containing dielectric material, which may include silicon oxide-based materials, such as tetraethyl orthosilicate (TEOS), phospho-silicate glass (PSG), borosilicate glass (BSG), boron-doped phospho-silicate glass (BPSG), or other suitable materials.

[0087] Semiconductor element 1a may include a redistribution structure 54. The redistribution structure 54 may be located within the active region 20-1. The redistribution structure 54 may be disposed within the dielectric structure 53. The redistribution structure 54 may include multiple traces and vias. The redistribution structure 54 may be electrically connected to the integrated circuit region 52.

[0088] Semiconductor device 1a may include a passivation layer 56. Passivation layer 56 may be disposed on or above redistribution structure 54. Test pad 42-1 may be exposed via passivation layer 56. Passivation layer 56 may include a monolayer structure or a stacked structure comprising multiple material layers. Passivation layer 56 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or other suitable materials.

[0089] Semiconductor element 1a may include terminal 57. Terminal 57 may be disposed on or above redistribution structure 54. Terminal 57 may be electrically connected to integrated circuit region 52. Terminal 57 may be exposed by passivation layer 56. Terminal 57 may be configured to connect to external components (not shown). Terminal 57 may include one or more layers, such as metal pads, under bump metallization (UBM), and other suitable layers. Metal pads may include copper, tungsten, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, tantalum, alloys thereof, and combinations thereof.

[0090] like Figure 4 As shown, the test circuit 41-1 can be at least partially formed within or on the substrate 51. The interconnect structure 43-1 may include traces 45 and vias 46. The thickness (or aspect ratio) of the via 46 along the Y direction may be greater than the thickness (or aspect ratio) of the trace 45 along the Y direction. The via 46 can connect traces 45 located at different height levels.

[0091] In this embodiment, at least two test modules (e.g., test module 40-1 and test module 40-2) are disposed within active regions 20-1 and 20-2. For example, active regions 20-1 and 20-2, test modules 40-1 and 40-2 may be at least partially aligned along the Y direction. The density of the test modules is greater than the density of the relative semiconductor elements, at least along the Y direction. In this embodiment, the test modules (e.g., test modules 40-1 to 40-4) are disposed outside the dicing region 30c. This prevents damage to the equipment chamber caused by metal fragments generated by the dicing technique.

[0092] Figure 5 This is a top view illustrating a semiconductor element 1b according to some embodiments of the present disclosure. Semiconductor element 1b has a similar structure to semiconductor element 1a, but with the following differences.

[0093] In some embodiments, test pad 42-1 may be misaligned with test pad 42-2 along the Y direction. In some embodiments, test pad 42-3 may be misaligned with test pad 42-4 along the Y direction. In some embodiments, test pad 42-1 may be at least partially aligned with test circuit 41-2 along the Y direction from a top view. In some embodiments, test circuit 41-1 may be at least partially aligned with test pad 42-2 along the Y direction from a top view. In some embodiments, test pad 42-3 may be at least partially aligned with test circuit 41-4 along the Y direction from a top view. In some embodiments, test circuit 41-3 may be at least partially aligned with test pad 42-4 along the Y direction from a top view.

[0094] Figure 6This is a top view illustrating a semiconductor element 1c according to some embodiments of the present disclosure. Semiconductor element 1c has a similar structure to semiconductor element 1a, but with the following differences.

[0095] Interconnect structure 43-1 may include via structure 44-1. Interconnect structure 43-2 may include via structure 44-2. Interconnect structure 43-3 may include via structure 44-3. Interconnect structure 43-4 may include via structure 44-4. Each of via structures 44-1 to 44-4 may include a conductive via located within each of the plurality of dielectric layers of dielectric structure 53.

[0096] In some embodiments, the via structure 44-1 may be disposed at the edge of the interconnect structure 43-1. In some embodiments, the via structure 44-1 may be closer to the active region 20-1 than the test circuit 41-1. In some embodiments, the via structure 44-1 may be closer to the active region 20-1 than the test pad 42-1. For example, the via structure 44-1 may include at least one conductive via that is closer to the active region 20-1 than the test circuit 41-1 (or the test pad 42-1). The average distance between the conductive via of the via structure 44-1 and the active region 20-1 is less than the average distance between the active region 20-1 and the test circuit 41-1 (or the test pad 42-1).

[0097] In some embodiments, the via structure 44-2 may be closer to the active region 20-2 than the test circuit 41-2. In some embodiments, the via structure 44-2 may be closer to the active region 20-2 than the test pad 42-2.

[0098] In some embodiments, the via structure 44-3 may be closer to the active region 20-1 than the test circuit 41-3. In some embodiments, the via structure 44-3 may be closer to the active region 20-1 than the test pad 42-3.

[0099] In some embodiments, the via structure 44-4 may be closer to the active region 20-2 than the test circuit 41-4. In some embodiments, the via structure 44-4 may be closer to the active region 20-2 than the test pad 42-4.

[0100] Test circuit 41-1 can be disposed between through-hole structure 44-1 and cutting area 30c. Test pad 42-1 can be disposed between through-hole structure 44-1 and cutting area 30c. Test circuit 41-2 can be disposed between through-hole structure 44-2 and cutting area 30c. Test pad 42-2 can be disposed between through-hole structure 44-2 and cutting area 30c. Test circuit 41-3 can be disposed between through-hole structure 44-3 and cutting area 30c. Test pad 42-3 can be disposed between through-hole structure 44-3 and cutting area 30c. Test circuit 41-4 can be disposed between through-hole structure 44-4 and cutting area 30c. Test pad 42-4 can be disposed between through-hole structure 44-4 and cutting area 30c.

[0101] Because the conductive vias of through-hole structures 44-1 to 44-4 have relatively large thicknesses, a large number of fragments may be generated when these structures are cut using a segmentation technique. In this embodiment, the distance between the conductive vias (e.g., through-hole structures 44-1 to 44-4) and the cutting area 30c is relatively large, thus reducing the generation of metal material fragments during the segmentation process.

[0102] Figure 7 This is a top view illustrating a semiconductor element 1d according to some embodiments of the present disclosure. Semiconductor element 1d has a similar structure to semiconductor element 1a, but with the following differences.

[0103] In some embodiments, a portion of the interconnect structure 43-1 (e.g., a conductive trace) is located within the cut area 30c, while the via structure 44-1 does not overlap with the cut area 30c along the Z direction. In some embodiments, a portion of the interconnect structure 43-2 is located within the cut area 30c, while the via structure 44-2 does not overlap with the cut area 30c along the Z direction. In some embodiments, a portion of the interconnect structure 43-3 is located within the cut area 30c, while the via structure 44-3 does not overlap with the cut area 30c along the Z direction. In some embodiments, a portion of the interconnect structure 43-4 is located within the cut area 30c, while the via structure 44-4 does not overlap with the cut area 30c along the Z direction.

[0104] Compared to conductive vias, conductive traces are less likely to break during the dicing process, so a portion of the conductive trace can be placed within the dicing area 30c. Therefore, a portion of the interconnect structures 43-1 to 43-4 can be placed within the dicing area 30c, which facilitates the miniaturization of the dicing line 30.

[0105] Figure 8 and Figure 9 This disclosure illustrates one or more stages of an example of a method for manufacturing a semiconductor element according to some embodiments of the present disclosure.

[0106] See Figure 8 Active regions 20-1 and 20-2 can be formed and separated by a cutting line 30. The cutting line 30 can define a cutting region 30c, which will be removed in a later stage. Test modules 40-1 to 40-4 can be formed within the cutting line 30 and outside the cutting region 30c. In some embodiments, via structures 44-1 to 44-4 can be formed adjacent to active regions 20-1 or 20-2. In some embodiments, each of the via structures 44-1 to 44-4 may not overlap with the cutting region 30c along the Z-direction.

[0107] See Figure 9 The process involves performing a partitioning technique P1. This creates an active region 20-2 separated from the active region 20-1. Dies 22 and 24 can then be manufactured. Die 22 may include the active region 20-1, test module 40-1, and test module 40-3. Test modules 40-1 and 40-3 may be located in the peripheral region of die 22. Die 24 may include the active region 20-2, test module 40-2, and test module 40-4. Test modules 40-2 and 40-4 may be located in the peripheral region of die 24.

[0108] In some embodiments, a laser light source can be used to isolate grain 22 and grain 24. In this embodiment, through-hole structures 44-1 to 44-4 may not be removed by the laser light source. This reduces the amount of metal material fragmentation during the segmentation process.

[0109] In this embodiment, the sidewalls of grain 22 (or grain 24) may not have a flat surface made of metallic material. For example, the sidewalls of grain 22 (or grain 24) may not have a flat surface made of conductive via (or conductive trace).

[0110] Figure 10 This is a flowchart illustrating a method for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0111] Method 2 begins at operation 202, in which a wafer is provided. A plurality of active regions, including a first active region and a second active region, are formed. The first active region and the second active region are separated by dicing lines. The first active region and the second active region are arranged along a first direction.

[0112] Method 2 continues with operation 204, where a cutting region is defined between the first active region and the second active region. The cutting line extends along the second direction.

[0113] Method 2 continues with operation 206, in which a first test module and a second test module are formed within the cutting line. The first test module and the second test module are arranged along a first direction. The first test module and the second test module are separated by the cutting area.

[0114] Method 2 continues with operation 208, wherein a segmentation technique is performed on the cutting area to form a first grain and a second grain. The first grain includes a first active region and a first test module. The second grain includes a second active region and a second test module. In some embodiments, the test module may not be cut or removed by the segmentation technique, thereby preventing damage to the device cavity from metal fragments.

[0115] One aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a first active region, a second active region, a first test module, and a second test module. The second active region is separated from the first active region by a dicing line. The dicing line extends along a first direction. The first test module is adjacent to the first active region and disposed within the dicing line. The second test module is adjacent to the second active region and disposed within the dicing line. The first test module and the second test module are arranged along a second direction substantially orthogonal to the first direction.

[0116] Another aspect of this disclosure provides a semiconductor device. This semiconductor device includes: a first active region, a second active region, and a first test module. The second active region is separated from the first active region by a dicing line. The dicing line extends along a first direction. The first test module is adjacent to the first active region and disposed within the dicing line. The first test module includes a test pad, a test circuit, and a via. The via connects to the test pad. The via is closer to the first active region than the first test circuit.

[0117] Another aspect of this disclosure provides a method for manufacturing a semiconductor device. This method includes: forming a plurality of active regions, including a first active region and a second active region, the second active region being separated from the first active region by a dicing line extending along a first direction; and forming a first test module and a second test module within the dicing line, wherein the first test module and the second test module are arranged along a second direction substantially perpendicular to the first direction.

[0118] Embodiments of this disclosure provide a semiconductor device including a plurality of test modules located within a dicing line extending along a first direction. A first test module and a second test module are arranged along a second direction substantially perpendicular to the first direction. A dicing region is located between the first test module and the second test module. This arrangement avoids cutting conductive components (e.g., traces and / or vias) of the first and second test modules, thereby preventing metal fragments from damaging the device cavity.

[0119] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0120] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: First, the primary active zone; A second active region is separated from the first active region by a cutting line, wherein the cutting line extends along a first direction; A first test module is adjacent to the first active region and is located within the cutting line; and A second test module is adjacent to the second active area and is located within the cutting line. The first test module and the second test module are arranged along a second direction that is substantially orthogonal to the first direction.

2. The semiconductor device of claim 1, wherein the first test module comprises: A first test pad and a first test circuit are arranged along the first direction.

3. The semiconductor device of claim 2, wherein the second test module comprises: A second test pad and a second test circuit are arranged along the first direction.

4. The semiconductor device of claim 3, wherein the second test pad is aligned with the first test pad along the second direction.

5. The semiconductor device of claim 3, wherein the second test pad is aligned with the first test circuit along the second direction.

6. The semiconductor element of claim 2, wherein the dicing line comprises: A cutting area is located between the first test module and the second test module.

7. The semiconductor device of claim 6, wherein the first test module comprises: A through-hole structure connects the first test pad and the first test circuit, and the through-hole structure does not overlap with the cut area along a third direction that is substantially perpendicular to the first direction and the second direction.

8. The semiconductor device of claim 6, wherein the first test pad does not overlap with the cut area along a third direction substantially perpendicular to the first direction and the second direction.

9. The semiconductor device of claim 6, wherein the first test circuit does not overlap with the cut region along a third direction substantially perpendicular to the first direction and the second direction.

10. The semiconductor device of claim 6, wherein the diced region is free of metallic material.

11. The semiconductor device of claim 2, wherein the first test module comprises: A through-hole structure connects the first test pad and the first test circuit, and the through-hole structure is closer to the first active area than the first test circuit.

12. The semiconductor device of claim 1, further comprising: A third test module, wherein the first test module and the third test module are arranged along the first direction.

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