Semiconductor device, circuit board assembly, electric control box and electrical equipment

Abstract

The invention discloses a semiconductor device, a circuit board assembly, an electric control box and electrical equipment. The semiconductor device comprises a plastic package body; a substrate; the center of the PFC driving pin frame is arranged in a manner of deviating towards one side far away from the second inversion driving pin frame in the transverse direction relative to the center of the PFC power bonding pad part, and the second inversion driving pin frame at least partially extends to one longitudinal side of the PFC power bonding pad part and corresponds to at least part of the PFC power bonding pad. Therefore, the center of the PFC driving chip corresponds to the center of the PFC power bonding pad part in the longitudinal direction; or the center of the PFC driving chip deviates towards one side which is transversely far away from the second inversion driving pin frame relative to the center of the PFC power bonding pad part, so that the second inversion driving pin frame can at least partially correspond to at least part of the PFC power bonding pad part, and therefore, on the premise of not increasing the size of the semiconductor device, the reliability of the semiconductor device can be improved. The area of the PFC power bonding pad part is increased, and good heat dissipation performance of the PFC power bonding pad part is ensured.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device, circuit board assembly, electrical control box, and electrical equipment. Background Technology

[0002] Electronic control boards for devices such as air conditioners and washing machines can incorporate semiconductor devices like intelligent power modules (IPMs). However, existing IPMs are functionally limited, only offering inverter capabilities. Furthermore, when an IPM includes a power factor correction (PFC) area, the PFC power pads have a relatively small footprint on the substrate. Since the PFC power pad area operates at high temperatures and frequencies, it may not dissipate heat effectively, leading to overheating and malfunctions in the PFC power pad area and surrounding components, ultimately causing the air conditioner's electronic control board to fail. Simply increasing the PFC power pad area on the substrate to improve heat dissipation could result in an excessively large semiconductor device. Summary of the Invention

[0003] The present invention aims to at least solve one of the technical problems existing in the prior art. Therefore, one object of the present invention is to provide a semiconductor device that can ensure good heat dissipation performance in the PFC power pad area without increasing the size of the semiconductor device.

[0004] The present invention further proposes a circuit board assembly.

[0005] The present invention further proposes an electrical control box.

[0006] The present invention further proposes an electrical device.

[0007] According to a semiconductor device of the present invention, the semiconductor device has a lateral direction, a longitudinal direction, and a vertical direction, the lateral direction, the longitudinal direction, and the vertical direction being perpendicular to each other. The semiconductor device includes: a molding compound; a substrate, the substrate being at least partially disposed within the molding compound, the substrate including a first inverter power pad portion, a second inverter power pad portion, and a PFC (power factor correction) power pad portion spaced apart in the lateral direction; and a drive-side pin frame, the drive-side pin frame being at least partially disposed within the molding compound and spaced apart on one side of the longitudinal direction of the substrate, the drive-side pin frame extending at least partially from the molding compound and including a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart in the lateral direction, the first inverter drive pin frame corresponding at least partially in the longitudinal direction to the first inverter power pad portion, the second inverter drive pin frame... The PFC drive pin frame and the second inverter power pad portion are at least partially corresponding in the longitudinal direction, and the PFC drive pin frame and the PFC (Power Factor Correction) power pad portion are at least partially corresponding in the longitudinal direction; the center of the PFC drive pin frame is offset laterally away from the center of the PFC power pad portion relative to the center of the second inverter drive pin frame, the second inverter drive pin frame extends at least partially to the longitudinal side of the PFC power pad portion and corresponds at least partially to the PFC power pad portion, a PFC drive chip is disposed on the PFC drive pin frame, and the center of the PFC drive chip corresponds longitudinally to the center of the PFC power pad portion; or the center of the PFC drive chip is offset laterally away from the center of the PFC power pad portion relative to the center of the PFC power pad portion.

[0008] The specific advantages or beneficial effects of the above scheme are as follows: By making the center of the PFC driver chip correspond to the center of the PFC power pad in the longitudinal direction; or by shifting the center of the PFC driver chip relative to the center of the PFC power pad towards the side laterally away from the second inverter driver pin frame, the second inverter driver pin frame can at least partially correspond to at least part of the PFC power pad, thereby increasing the area of ​​the PFC power pad without enlarging the semiconductor device and ensuring good heat dissipation performance of the PFC power pad.

[0009] In some examples of the present invention, the second inverter drive pin frame further includes a second inverter high-side drive floating power supply voltage first pin, a second inverter high-side drive floating power supply voltage second pin, and a second inverter high-side drive floating power supply voltage third pin arranged laterally at intervals. The second inverter high-side drive floating power supply voltage first pin, the second inverter high-side drive floating power supply voltage second pin, and the second inverter high-side drive floating power supply voltage third pin are respectively provided with a second inverter bootstrap chip first pad, a second inverter bootstrap chip second pad, and a third inverter bootstrap chip third pad at one end of the second inverter bootstrap chip first pad, the second inverter bootstrap chip second pad, and the second inverter bootstrap chip third pad. A second inverter bootstrap chip is provided on each of the second inverter bootstrap chip first pad, the second inverter bootstrap chip second pad, and the second inverter bootstrap chip third pad. The second inverter bootstrap chip third pad is located on one longitudinal side of the PFC power pad portion and corresponds to the PFC power pad portion.

[0010] The specific advantages or beneficial effects of the above scheme are as follows: it can not only optimize the layout of the second inverter drive pin frame, but also reduce the area of ​​the substrate occupied by the second inverter power pad, increase the area of ​​the substrate occupied by the PFC power pad, and improve the heat dissipation performance of the PFC power pad.

[0011] In some examples of the present invention, the second inverter drive pin frame further includes a first pin of the second inverter high-side drive floating power supply ground, a second pin of the second inverter high-side drive floating power supply ground, and a third pin of the second inverter high-side drive floating power supply ground. The first pin of the second inverter high-side drive floating power supply ground is laterally spaced between the first pin of the second inverter high-side drive floating power supply voltage and the second pin of the second inverter high-side drive floating power supply voltage. The second pin of the second inverter high-side drive floating power supply ground is laterally spaced between the second pin of the second inverter high-side drive floating power supply voltage and the third pin of the second inverter high-side drive floating power supply voltage. The third pin of the second inverter high-side drive floating power supply ground is laterally spaced on the side of the second pin of the second inverter high-side drive floating power supply voltage away from the second pin of the second inverter high-side drive floating power supply voltage. The third pin of the second inverter high-side drive floating power supply ground is located on the longitudinal side of the PFC power pad portion and corresponds to the PFC power pad portion. At least a portion of the second pin of the second inverter high-side drive floating power supply ground is located on the longitudinal side of the PFC power pad portion and corresponds to the PFC power pad portion.

[0012] The specific advantages or beneficial effects of the above scheme are as follows: it can help reduce the area of ​​the substrate occupied by the second inverter power pad, increase the area of ​​the substrate occupied by the PFC power pad, and improve the heat dissipation performance of the PFC power pad.

[0013] In some examples of the present invention, the second inverter drive pin frame includes a second inverter drive chip ground pin and a second inverter drive power supply voltage pin, wherein the second inverter drive chip ground pin and the second inverter drive power supply voltage pin extend at least partially to one longitudinal side of the PFC power pad portion and correspond to the PFC power pad portion.

[0014] The specific advantages or beneficial effects of the above scheme are as follows: it can not only provide sufficient setting area for the ground pin of the second inverter driver chip and the power supply voltage pin of the second inverter driver, but also help to reduce the area of ​​the second inverter power pad, increase the area of ​​the PFC power pad, and improve the heat dissipation performance of the PFC power pad.

[0015] In some examples of the present invention, the lateral dimension of the first inverter power pad portion is smaller than the lateral dimension of the second inverter power pad portion.

[0016] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and increase the area of ​​the substrate occupied by the second inverter power pad, which is beneficial to heat dissipation in the area of ​​the second inverter power pad.

[0017] In some examples of the present invention, the substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC (power factor correction) power pad portion. A plurality of rectifier chips are disposed on the rectifier bridge pad portion. The drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially longitudinally aligned with the rectifier bridge pad portion. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to it. The lateral dimension of the rectifier bridge pad portion is larger than the lateral dimension of the PFC (power factor correction) power pad portion.

[0018] The specific advantages or beneficial effects of the above scheme are as follows: it can not only facilitate the layout of rectifier chips and other modules on the rectifier bridge pad area, but also help optimize the layout design of the rectifier bridge pad area, and can also help improve the heat dissipation performance of the rectifier bridge pad area, thereby improving the stability and reliability of the semiconductor device.

[0019] In some examples of the present invention, the PFC driver pin frame includes a PFC driver chip ground pin and a PFC driver chip power supply voltage pin. The PFC driver chip ground pin includes a PFC driver chip pad portion and an extension portion. The extension portion extends longitudinally. The PFC driver chip pad portion is disposed at one end of the extension portion longitudinally adjacent to the substrate. The PFC driver chip pad portion protrudes relative to the extension portion toward the side longitudinally adjacent to the second inverter driver pin frame and is spaced laterally from the second inverter driver pin frame. The PFC driver chip is disposed on the PFC driver chip pad portion. The PFC driver chip power supply voltage pin extends longitudinally and is spaced laterally between the second inverter driver pin frame and the extension portion. The PFC driver chip power supply voltage pin is spaced at the side of the PFC driver chip pad portion longitudinally away from the substrate.

[0020] The specific advantages or beneficial effects of the above scheme are as follows: the electrical connection point of the ground pin of the PFC driver chip can be set on the edge of the PFC driver pin frame away from the substrate, and the PFC driver chip pad can be set adjacent to the PFC power pad on the substrate, so as to shorten the connection distance between the PFC driver pad and the PFC power chip.

[0021] In some examples of the present invention, the PFC drive pin frame extends at least partially to one longitudinal side of the rectifier bridge pad portion and corresponds to the rectifier bridge pad portion.

[0022] The specific advantages or beneficial effects of the above scheme are as follows: it can not only ensure that the PFC drive pin frame has sufficient setting area and ensure the rationality and reliability of the PFC drive pin frame setting, but also make the area of ​​the substrate occupied by the rectifier bridge pad part larger than the area of ​​the substrate occupied by the PFC power pad part. It can ensure good heat dissipation performance of the PFC power pad part and the rectifier bridge pad part while ensuring that the semiconductor device is not enlarged.

[0023] In some embodiments of the present invention, the first inverter drive pin frame is provided with a first inverter high-side drive chip and a first inverter low-side drive chip arranged laterally. The side of the first inverter low-side drive chip laterally adjacent to the first inverter high-side drive chip is defined as the boundary of the first inverter low-side drive chip, and the side of the first inverter high-side drive chip laterally adjacent to the first inverter low-side drive chip is defined as the boundary of the first inverter high-side drive chip. Both the first inverter low-side drive chip boundary and the first inverter high-side drive chip boundary extend vertically, and the lateral distance between the first inverter low-side drive chip boundary and the first inverter high-side drive chip boundary is L1. The dual-inverter drive pin frame is provided with a second inverter high-side drive chip and a second inverter low-side drive chip arranged laterally. The side of the second inverter low-side drive chip that is laterally adjacent to the second inverter high-side drive chip is defined as the boundary of the second inverter low-side drive chip, and the side of the second inverter high-side drive chip that is laterally adjacent to the second inverter low-side drive chip is defined as the boundary of the second inverter high-side drive chip. Both the boundaries of the second inverter low-side drive chip and the boundaries of the second inverter high-side drive chip extend vertically. The lateral distance between the boundaries of the second inverter low-side drive chip and the boundaries of the second inverter high-side drive chip is L2. L1 and L2 satisfy the relationship: L1 < L2.

[0024] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and increase the area of ​​the substrate occupied by the second inverter power pad, which is beneficial to heat dissipation in the area of ​​the second inverter power pad.

[0025] In some embodiments of the present invention, the first inverter drive pin frame includes a ground pin of a first inverter drive chip. The ground pin of the first inverter drive chip protrudes at least partially toward the side longitudinally away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad. The first inverter low-side drive chip is disposed on the first inverter low-side drive pad, and the first inverter high-side drive chip is disposed on the first inverter high-side drive pad. The side of the first inverter low-side drive pad laterally adjacent to the first inverter high-side drive pad is the boundary of the first inverter low-side drive pad, and the side of the first inverter high-side drive pad laterally adjacent to the first inverter low-side drive pad is the boundary of the first inverter high-side drive pad. Both the boundary of the first inverter low-side drive pad and the boundary of the first inverter high-side drive pad extend longitudinally, and the lateral distance between the boundary of the first inverter low-side drive pad and the boundary of the first inverter high-side drive pad is L3. The dual inverter drive pin frame includes a ground pin for a second inverter drive chip. The ground pin of the second inverter drive chip protrudes at least partially toward the side longitudinally away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad. The second inverter low-side drive chip is disposed on the second inverter low-side drive pad, and the second inverter high-side drive chip is disposed on the second inverter high-side drive pad. The side of the second inverter low-side drive pad that is laterally adjacent to the second inverter high-side drive pad is the boundary of the second inverter low-side drive pad. The side of the second inverter high-side drive pad that is laterally adjacent to the second inverter low-side drive pad is the boundary of the second inverter high-side drive pad. Both the boundaries of the second inverter low-side drive pad and the boundaries of the second inverter high-side drive pad extend longitudinally. The lateral distance between the boundaries of the second inverter low-side drive pad and the boundaries of the second inverter high-side drive pad is L4. L3 and L4 satisfy the relationship: L3 < L4.

[0026] The specific advantages or beneficial effects of the above scheme are as follows: it can reduce the area of ​​the substrate occupied by the first inverter power pad and increase the area of ​​the substrate occupied by the second inverter power pad, which is beneficial to heat dissipation in the area of ​​the second inverter power pad.

[0027] The circuit board assembly according to an embodiment of the present invention includes the semiconductor device described above.

[0028] The specific advantages or beneficial effects of the above solution are as follows: it can prevent local overheating of the circuit board assembly, reduce the wear and tear of the circuit board assembly, and improve the working performance of the circuit board assembly.

[0029] The electrical control box according to an embodiment of the present invention includes: the circuit board assembly described above.

[0030] The specific advantages or beneficial effects of the above solution are as follows: it can improve the working performance of the electrical control box and extend its service life.

[0031] An electrical device according to an embodiment of the present invention includes: the electrical control box described above.

[0032] The specific advantages or beneficial effects of the above solution are as follows: it can improve the working performance and quality of electrical equipment.

[0033] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0034] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 2 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 3 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 4 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 5 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 6 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 7 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention; Figure 8 This is a partial schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0035] Figure label: 100. Semiconductor devices; 1. Plastic encapsulation; 2. Substrate; 201. First inverter power pad; 2011. First inverter low-side power chip; 2012. First inverter high-side power chip; 202. Second inverter power pad; 2021. Second inverter low-side power chip; 2022. Second inverter high-side power chip; 203. PFC power pad; 2031. PFC power chip; 204. Rectifier bridge pad; 2041. Rectifier chip; 3. Driver-side pin frame; 301. First inverter drive pin frame; 3011, First inverter low-side drive pad; 30111, First inverter low-side drive chip; 3012, First inverter high-side drive pad; 30121, First inverter high-side drive chip; 3013, Ground pin of the first inverter driver chip; 30141, Boundary of the first inverter low-side driver chip; 30142, Boundary of the first inverter high-side driver chip; 30143, Boundary of the first inverter low-side driver pad; 30144, Boundary of the first inverter high-side driver pad; 302. Second inverter drive pin frame; 3021, Second inverter low-side drive pad; 30211, Second inverter low-side drive chip; 3022, Second inverter high-side drive pad; 30221, Second inverter high-side drive chip; 30231, Ground pin of the second inverter driver chip; 30232, Power supply voltage pin of the second inverter driver; 30241, Boundary of the second inverter low-side driver chip; 30242, Boundary of the second inverter high-side driver chip; 30243, Boundary of the second inverter low-side driver pad; 30244, Boundary of the second inverter high-side driver pad; 30251, First pin of the second inverter high-side drive floating power supply voltage; 30252, Second pin of the second inverter high-side drive floating power supply voltage; 30253, Third pin of the second inverter high-side drive floating power supply voltage; 30261, First pad of the second inverter bootstrap chip; 30262, Second pad of the second inverter bootstrap chip; 30263, Third pad of the second inverter bootstrap chip; 3027, Second inverter bootstrap chip; 20281, First pin of the second inverter high-side drive floating power supply ground; 30282, Second pin of the second inverter high-side drive floating power supply ground; 30283, Third pin of the second inverter high-side drive floating power supply ground; 303, PFC driver pin frame; 3031, PFC driver chip; 3032, PFC driver chip ground pin; 30321, PFC driver chip pad; 30322, extension; 3033, PFC driver chip power supply voltage pin; 304. Rectifier bridge driver pin frame. Detailed Implementation

[0036] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0037] The following is for reference. Figures 1-8A semiconductor device 100 according to an embodiment of the present invention is described. The semiconductor device 100 can be applied to a circuit board assembly, the circuit board assembly can be applied to an electrical control box, and the electrical control box can be applied to an electrical device. It should be noted that the semiconductor device 100 has a horizontal, a vertical, and a longitudinal dimension, which are perpendicular to each other.

[0038] Combination Figures 1-8 As shown, the semiconductor device 100 according to the present invention mainly includes: a molding compound 1, a substrate 2, and a drive-side pin frame 3. The substrate 2 is at least partially disposed within the molding compound 1. The substrate 2 can be completely encapsulated by the molding compound 1, or it can be partially encapsulated and partially exposed on the surface of the molding compound 1. The drive-side pin frame 3 is at least partially disposed within the molding compound 1, and partially extends out of the molding compound 1 for electrical connection with external components. The molding compound 1 protects the substrate 2 and the drive-side pin frame 3 within the semiconductor device 100, ensuring their stable placement and providing electrical insulation from the outside, thus guaranteeing the structural reliability of the semiconductor device 100. It should be noted that the pins of the drive-side pin frame 3 are spaced apart to ensure electrical isolation between them, and the longitudinal dimensions of the portions of the pins extending out of the molding compound 1 are inconsistent; this will not be elaborated further here.

[0039] Furthermore, the substrate 2 includes a first inverter power pad 201, a second inverter power pad 202, and a PFC power pad 203 arranged laterally at intervals. This ensures that the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203 are all relatively independently arranged on the substrate 2, preventing mutual interference between them. This not only ensures the normal working performance of the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203, but also facilitates their installation, testing, and maintenance.

[0040] The first inverter power pad 201 is provided with a first inverter power chip, and there are multiple first inverter power chips. These multiple first inverter power chips form a first inverter circuit; for example, six first inverter power chips can form a first three-phase inverter bridge circuit. The first three-phase inverter bridge circuit includes a first three-phase upper bridge arm inverter power chip and a first three-phase lower bridge arm inverter power chip. The first inverter power chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be a reverse-conducting IGBT that integrates the IGBT and freewheeling diode into a single chip, etc.

[0041] Furthermore, a second inverter power chip is disposed on the second inverter power pad 202, and there are multiple second inverter power chips. These multiple second inverter power chips form a second inverter circuit; for example, six second inverter power chips can form a second three-phase inverter bridge circuit. The second three-phase inverter bridge circuit includes a second three-phase upper bridge arm inverter power chip and a second three-phase lower bridge arm inverter power chip. The second inverter power chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be a reverse-conducting IGBT that integrates the IGBT and the freewheeling diode into a single chip, etc.

[0042] Furthermore, a PFC power chip 2031 is disposed on the PFC power pad section 203. The PFC power chip 2031 includes a PFC power switch chip and a PFC diode chip. The PFC power switch chip and PFC diode chip are components of the PFC circuit. The PFC circuit adjusts the power factor of the DC power and outputs the adjusted DC power. The PFC power switch chip can be composed of an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FRD), or it can be a metal-oxide-semiconductor field-effect transistor (MOS), or it can be an RC-IGBT. It should be noted that the RC-IGBT is a reverse-conducting IGBT that integrates the IGBT and the freewheeling diode into a single chip.

[0043] Furthermore, the drive-side pin frame 3 is at least partially disposed within the molding compound 1 and spaced apart on one side of the longitudinal direction of the substrate 2. This not only allows for the separate design of the drive-side pin frame 3 and the substrate 2 to reduce the mutual influence between the devices on the drive-side pin frame 3 and the devices on the substrate 2, and facilitates heat dissipation for the devices on the drive-side pin frame 3 and the devices on the substrate 2, but also allows the drive-side pin frame 3 to be disposed adjacent to the substrate 2 to facilitate the electrical connection between the devices on the drive-side pin frame 3 and the devices on the substrate 2. In addition, it can also ensure the rationality of the structural layout of the semiconductor device 100 and improve the integration of the semiconductor device 100 structure. In this invention, a driver chip is mounted on the driver-side pin frame 3. The driver-side pin frame 3 can be completely spaced apart from the substrate 2 in the vertical direction, thereby reducing the impact of heat transferred from the substrate 2 on the driver chip and ensuring the working performance of each driver chip. Alternatively, the driver-side pin frame 3 can be partially protruding in the vertical direction to form a connecting rod and connect to the substrate 2, thereby improving the stability of the substrate 2. At the same time, most of the driver-side pin frame 3 is spaced apart from the substrate 2 in the second direction, thus balancing the improvement of the stability of the substrate 2 and the reduction of the impact of heat transferred from the substrate 2 on the driver chip. In addition, in some embodiments of the present invention, the substrate 2 and the driver-side pin frame 3 can be constructed as a single frame. This not only facilitates the packaging of the semiconductor device 100 and improves the assembly efficiency of the semiconductor device 100, but also improves the overall structural strength of the semiconductor device 100 and extends the service life of the semiconductor device 100.

[0044] Furthermore, the drive-side pin frame 3 extends at least partially from the molding compound and includes a first inverter drive pin frame 301, a second inverter drive pin frame 302, and a PFC drive pin frame 303 spaced apart laterally. The first inverter drive pin frame 301 corresponds at least partially to the first inverter power pad portion 201 in the longitudinal direction. This facilitates the electrical connection between the first inverter drive pin frame 301 and the first inverter power chip on the first inverter power pad portion 201, and makes the wire connection between the first inverter drive pin frame 301 and the first inverter power pad portion 201 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. The second inverter drive pin frame 302 and the second inverter power pad portion 202 are at least partially corresponding in the longitudinal direction. This facilitates the electrical connection between the second inverter drive pin frame 302 and the second inverter power chip on the second inverter power pad portion 202, and makes the wire connection between the second inverter drive pin frame 302 and the second inverter power pad portion 202 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100. The PFC drive pin frame 303 and the PFC power pad portion 203 are at least partially corresponding in the longitudinal direction. This facilitates the electrical connection between the PFC drive pin frame 303 and the PFC power chip 2031 on the PFC power pad portion 203, and makes the wire connection between the PFC drive pin frame 303 and the PFC power pad portion 203 suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100.

[0045] Furthermore, the center of the PFC drive pin frame 303 is offset laterally from the center of the PFC power pad portion 203 toward a side away from the second inverter drive pin frame 302, and the second inverter drive pin frame 302 extends at least partially to the longitudinal side of the PFC power pad portion 203 and corresponds to at least a portion of the PFC power pad portion 203. This configuration not only ensures the reasonable layout and reliability of the second inverter drive pin frame 302 and sufficient mounting area for the second inverter drive pin frame 302, but also ensures that the second inverter drive pin frame 302 and the second inverter power pad portion 202 are largely corresponding in the vertical direction. This helps to reduce the area of ​​the second inverter power pad portion 202 on the substrate 2 without increasing the volume of the substrate 2, and increase the area of ​​the PFC power pad portion 203 on the substrate 2. This helps to improve the heat dissipation performance of the PFC power pad portion 203, prevent the devices in the PFC power pad portion 203 area from failing due to excessive temperature, improve the stability and reliability of the semiconductor device 100, and increase the integration of the semiconductor device 100.

[0046] Furthermore, a PFC driver chip 3031 is disposed on the PFC driver pin frame 303, and the center of the PFC driver chip 3031 corresponds longitudinally to the center of the PFC power pad portion 203; or the center of the PFC driver chip 3031 is offset laterally away from the center of the PFC power pad portion 203. This configuration allows the second inverter drive pin frame 302 to correspond at least partially to at least a portion of the PFC power pad portion 203 in the longitudinal direction, and allows most of the PFC drive pin frame 303 to correspond to most of the PFC power pad portion 203 in the longitudinal direction. It also allows only a small portion of the PFC drive pin frame 303 to not correspond to the PFC power pad portion 203 in the longitudinal direction. This reduces the area of ​​the substrate 2 occupied by the second inverter power pad portion 202 and increases the area of ​​the substrate 2 occupied by the PFC power pad portion 203 without increasing the size of the semiconductor device 100. This ensures good heat dissipation performance of the PFC power pad portion 203, preventing device malfunctions due to overheating in the PFC power pad portion 203 area. Furthermore, it facilitates the electrical connection between the PFC drive chip 3031 and the PFC power pad portion 203, ensuring that the wiring connection between the PFC drive chip 3031 and the PFC power pad portion 203 is suitable for the manufacturing process of the semiconductor device 100 and meets the reliability requirements of the semiconductor device 100.

[0047] Therefore, by aligning the center of the PFC driver chip 3031 with the center of the PFC power pad portion 203 longitudinally, or by offsetting the center of the PFC driver chip 3031 relative to the center of the PFC power pad portion 203 laterally away from the second inverter drive pin frame 302, the second inverter drive pin frame 302 can at least partially correspond to at least a portion of the PFC power pad portion 203. This allows for an increase in the area of ​​the PFC power pad portion 203 without enlarging the semiconductor device 100, ensuring good heat dissipation performance of the PFC power pad portion 203.

[0048] Combination Figure 3 , Figure 5 and Figure 6As shown, the second inverter drive pin frame 302 also includes a second inverter high-side drive floating power supply voltage first pin 30251, a second inverter high-side drive floating power supply voltage second pin 30252, and a second inverter high-side drive floating power supply voltage third pin 30253 arranged laterally. The second inverter high-side drive floating power supply voltage first pin 30251, second inverter high-side drive floating power supply voltage second pin 30252, and second inverter high-side drive floating power supply voltage third pin 30253 are longitudinally adjacent to one end of the substrate 2. The device is provided with a first pad 30261, a second pad 30262, and a third pad 30263 for the second inverter bootstrap chip. A second inverter bootstrap chip 3027 is provided on each of the first pad 30261, the second pad 30262, and the third pad 30263. The third pad 30263 is located on one longitudinal side of the PFC power pad section 203 and corresponds to the PFC power pad section 203.

[0049] Specifically, the first pin 30251, the second pin 30252, and the third pin 30253 of the second inverter high-side drive floating power supply voltage are spaced apart horizontally. This not only prevents mutual interference between the first pin 30251, the second pin 30252, and the third pin 30253 of the second inverter high-side drive floating power supply voltage, but also ensures a reasonable layout of the first pin 30251, the second pin 30252, and the third pin 30253 of the second inverter high-side drive floating power supply voltage. This improves the current carrying capacity of the second inverter drive pin frame 302 and enhances the reliability and stability of the second inverter drive pin frame 302.

[0050] Furthermore, the first pin 30251, the second pin 30252, and the third pin 30253 of the second inverter high-side drive floating power supply voltage are respectively provided with a first pad 30261, a second pad 30262, and a third pad 30263 of the second inverter bootstrap chip at one end of the longitudinal direction adjacent to the substrate 2. A second inverter bootstrap chip 3027 is provided on each of the first pad 30261, the second pad 30262, and the third pad 30263 of the second inverter bootstrap chip. This configuration not only ensures the rationality of the structural arrangement of the second inverter bootstrap chip 3027 on the first pad 30261, the second pad 30262, and the third pad 30263 of the second inverter bootstrap chip, but also prevents mutual interference between adjacent second inverter bootstrap chips 3027 through the spacing between the first pad 30261, the second pad 30262, and the third pad 30263 of the second inverter bootstrap chip. At the same time, it also facilitates the electrical connection between the second inverter bootstrap chip 3027 and other devices.

[0051] Furthermore, the third pad 30263 of the second inverter bootstrap chip is located on one longitudinal side of the PFC power pad portion 203 and corresponds to the PFC power pad portion 203. This allows the second inverter drive pin frame 302 to at least partially correspond to at least a portion of the PFC power pad portion 203, thereby optimizing the layout of the second inverter drive pin frame 302 and allowing the second inverter drive pin frame 302 to better accommodate the third pad 30263 of the second inverter bootstrap chip, preventing the occurrence of the third pad 30263. To address the difficulty in arranging the third pad 30263 of the dual inverter bootstrap chip, since the second inverter drive pin frame 302 and the second inverter power pad portion 202 correspond at least partially in the longitudinal direction, the second inverter power pad portion 202 can be recessed in the lateral direction away from the PFC power pad portion 203. This reduces the area of ​​the substrate 2 occupied by the second inverter power pad portion 202, increases the area of ​​the substrate 2 occupied by the PFC power pad portion 203, and improves the heat dissipation performance of the PFC power pad portion 203.

[0052] Combination Figure 3 , Figure 5 and Figure 6As shown, the second inverter drive pin frame 302 also includes a first pin 20281 for the second inverter high-side drive floating power supply ground, a second pin 30282 for the second inverter high-side drive floating power supply ground, and a third pin 30283 for the second inverter high-side drive floating power supply ground. The first pin 20281 for the second inverter high-side drive floating power supply ground is horizontally spaced between the first pin 30251 for the second inverter high-side drive floating power supply voltage and the second pin 30252 for the second inverter high-side drive floating power supply voltage. The second pin 30282 for the second inverter high-side drive floating power supply ground is horizontally spaced between the second pin 30252 for the second inverter high-side drive floating power supply voltage and the third pin 30253 for the second inverter high-side drive floating power supply voltage. The third pin 30283 for the second inverter high-side drive floating power supply ground is horizontally spaced on the side of the second pin 30253 away from the second pin 30252 for the second inverter high-side drive floating power supply voltage. This configuration allows for a horizontally spaced arrangement within the second inverter drive pin frame 302 of the following pins: first pin 30251 for the second inverter high-side drive floating power supply voltage, first pin 20281 for the second inverter high-side drive floating power supply ground, second pin 30252 for the second inverter high-side drive floating power supply voltage, second pin 30282 for the second inverter high-side drive floating power supply ground, third pin 30253 for the second inverter high-side drive floating power supply voltage, and third pin 30283 for the second inverter high-side drive floating power supply ground. This not only enhances the current carrying capacity of the second inverter drive pin frame 302 area but also improves its anti-interference capability, ensuring signal integrity and stability. Furthermore, it helps optimize the wiring design of the second inverter drive pin frame 302 area.

[0053] Furthermore, the third pin 30283 of the second inverter high-side drive floating power supply is located on one longitudinal side of the PFC power pad portion 203 and corresponds to the PFC power pad portion 203. This arrangement allows the third pin 30283 of the second inverter high-side drive floating power supply to at least partially correspond to the PFC power pad portion 203 in the longitudinal direction, and allows the second inverter drive pin frame 302 to at least partially correspond to at least a portion of the PFC power pad portion 203. The second inverter drive pin frame 302 and the second inverter power pad portion 202 correspond at least partially in the longitudinal direction, thereby helping to reduce the area of ​​the substrate 2 occupied by the second inverter power pad portion 202, increase the area of ​​the substrate 2 occupied by the PFC power pad portion 203, and improve the heat dissipation performance of the PFC power pad portion 203.

[0054] Furthermore, at least a portion of the second inverter high-side drive floating power supply ground pin 30282 is located on one longitudinal side of the PFC power pad portion 203 and corresponds to the PFC power pad portion 203. This arrangement further increases the longitudinal area of ​​the area corresponding to the second inverter drive pin frame 302 and the PFC power pad portion 203, further reduces the area of ​​the substrate 2 occupied by the second inverter power pad portion 202, and increases the area of ​​the substrate 2 occupied by the PFC power pad portion 203, thereby further improving the heat dissipation performance of the PFC power pad portion 203. Combination Figure 3 , Figure 6 and Figure 7 As shown, the second inverter drive pin frame 302 includes a second inverter drive chip ground pin 30231 and a second inverter drive power supply voltage pin 30232. The second inverter drive chip ground pin 30231 and the second inverter drive power supply voltage pin 30232 extend at least partially to one longitudinal side of the PFC power pad portion 203 and correspond to it. This configuration not only provides sufficient area for the second inverter drive chip ground pin 30231 and the second inverter drive power supply voltage pin 30232, thereby improving the structural strength and reliability of the second inverter drive pin frame 302, but also ensures that the second inverter drive pin frame 302 at least partially corresponds to at least a portion of the PFC power pad portion 203. This helps to reduce the area of ​​the second inverter power pad portion 202, increase the area of ​​the PFC power pad portion 203, and improve the heat dissipation performance of the PFC power pad portion 203.

[0055] Combination Figure 1 , Figure 3 and Figure 8 As shown, the lateral dimension of the first inverter power pad portion 201 is smaller than the lateral dimension of the second inverter power pad portion 202. Specifically, by making the lateral dimension of the first inverter power pad portion 201 smaller than the lateral dimension of the second inverter power pad portion 202, the first inverter power pad portion 201 can be recessed as a whole away from the PFC power pad portion 203 while ensuring the stable performance of the first and second inverter power pad portions 201. This reduces the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increases the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 area is usually greater than that of the first inverter power pad portion 201 area, this is beneficial for heat dissipation of the second inverter power pad portion 202 area, preventing the devices in the second inverter power pad portion 202 area from malfunctioning due to excessive temperature, and improving the stability and reliability of the semiconductor device 100.

[0056] It should be noted that, Figure 8 In this context, L7 represents the lateral dimension of the first inverter power pad portion 201, and L8 represents the lateral dimension of the second inverter power pad portion 202.

[0057] Combination Figure 1 , Figure 2 and Figure 3 As shown, the substrate 2 also includes a rectifier bridge pad portion 204, which is laterally spaced from the first inverter power pad portion 201, the second inverter power pad portion 202, and the PFC power pad portion 203. A plurality of rectifier chips 2041 are disposed on the rectifier bridge pad portion 204. The drive-side pin frame 3 also includes a rectifier bridge drive pin frame 304, which is at least partially corresponding to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge drive pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. The lateral dimension of the rectifier bridge pad portion 204 is larger than the lateral dimension of the PFC power pad portion 203.

[0058] Specifically, the rectifier bridge pad 204 is spaced laterally from the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203. This ensures that the rectifier bridge pad 204, the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203 are independently arranged on the semiconductor device 100. This prevents mutual interference between the rectifier bridge pad 204 and the first inverter power pad 201, the second inverter power pad 202, and the PFC power pad 203, ensuring good working performance of the rectifier bridge pad 204 and improving the anti-interference capability of the semiconductor device 100.

[0059] Furthermore, a rectifier chip 2041 is provided on the rectifier bridge pad section 204, so that the rectifier bridge pad section 204 can provide a setting position for the rectifier chip 2041 to ensure the reasonable layout and working stability of the rectifier chip 2041.

[0060] Furthermore, the drive-side pin frame 3 also includes a rectifier bridge drive pin frame 304, which corresponds at least partially to the rectifier bridge pad portion 204 in the longitudinal direction. The rectifier bridge drive pin frame 304 extends at least partially to the rectifier bridge pad portion 204 and is electrically connected to the rectifier bridge pad portion 204. This allows the establishment of an electrical connection point at the edge of the rectifier bridge drive pin frame 304 that is electrically connected to the rectifier bridge pad portion 204, thereby facilitating the electrical connection between the rectifier chip 2041 on the rectifier bridge pad portion 204 and external circuits or other devices. It also facilitates the input of AC signals to the rectifier chip 2041 on the rectifier bridge pad portion 204 to realize the rectification function of the semiconductor device 100.

[0061] Furthermore, the lateral dimension of the rectifier bridge pad portion 204 is larger than that of the PFC power pad portion 203. Specifically, since the rectifier chip 2041 disposed on the rectifier bridge pad portion 204 is more numerous than the PFC power chip 2031 disposed on the PFC power pad portion 203, and the rectifier bridge pad portion 204 is compatible with modules of various current specifications, by making the lateral dimension of the rectifier bridge pad portion 204 larger than that of the PFC power pad portion 203, it is not only easier to arrange the rectifier chip 2041 and other modules on the rectifier bridge pad portion 204, which helps to optimize the layout design of the rectifier bridge pad portion 204, but also helps to improve the heat dissipation performance of the rectifier bridge pad portion 204, thereby improving the stability and reliability of the semiconductor device 100.

[0062] The rectifier chip 2041 can be a rectifier diode, and a rectifier bridge can be formed by multiple rectifier diodes. For example, it can be implemented by combining four rectifier diodes arranged at intervals. The rectifier bridge composed of four rectifier diodes converts the input AC power into DC power and outputs it.

[0063] In embodiments of the present invention, the first inverter drive pin frame 301 and the first inverter power pad portion 201 together constitute a first inverter intelligent module; the second inverter drive pin frame 302 and the second inverter power pad portion 202 together constitute a second inverter intelligent module; and the PFC drive pin frame 303 and the PFC power pad portion 203 together constitute a PFC intelligent module. The rectifier bridge, PFC intelligent module, second inverter intelligent module, and first inverter intelligent module can be integrated on the semiconductor device 100. Compared to setting multiple independent components, this reduces the size of the semiconductor device 100 and eliminates the need for multiple component insertions during production, making the structure of the semiconductor device 100 simpler and more compact, and simplifying its production. In some embodiments of the present invention, one of the first inverter intelligent module and the second inverter intelligent module is a fan intelligent module, and the other is a compressor intelligent module. In other embodiments of the present invention, both the first inverter intelligent module and the second inverter intelligent module are motor intelligent modules. No specific limitations are imposed here.

[0064] Combination Figure 3 and Figure 7As shown, the PFC driver pin frame 303 includes a PFC driver chip ground pin 3032 and a PFC driver chip power supply voltage pin 3033. The PFC driver chip ground pin 3032 includes a PFC driver chip pad portion 30321 and an extension portion 30322. The extension portion 30322 extends vertically. The PFC driver chip pad portion 30321 is disposed at one end of the extension portion 30322 that is vertically adjacent to the substrate 2. The PFC driver chip pad portion 30321 protrudes from the extension portion 30322 toward the side that is vertically adjacent to the second inverter driver pin frame 302 and is spaced apart from the second inverter driver pin frame 302 in the lateral direction. The PFC driver chip 3031 is disposed on the PFC driver chip pad portion 30321. Specifically, by extending the extension 30322 longitudinally and setting the PFC driver chip pad portion 30321 at one end of the extension 30322 longitudinally adjacent to the substrate 2, not only can the longitudinal dimension of the PFC driver chip ground pin 3032 be increased, but also the electrical connection point of the PFC driver chip ground pin 3032 can be set at the edge of the PFC driver pin frame 303 away from the substrate 2. Furthermore, the PFC driver chip pad portion 30321 can be set adjacent to the PFC power pad portion 203 on the substrate 2, thereby shortening the connection distance between the PFC driver pad portion and the PFC power chip 2031. In addition, the PFC driver chip pad portion 30321 is provided to protrude from the side of the extension portion 30322 that is longitudinally adjacent to the second inverter drive pin frame 302 and is spaced apart from the second inverter drive pin frame 302 in the lateral direction. This increases the area of ​​the PFC driver chip pad portion 30321, providing sufficient space for the PFC driver chip 3031 on the PFC driver pad portion, and ensuring good working performance of the PFC driver chip 3031.

[0065] Furthermore, the PFC driver chip power supply voltage pin 3033 extends vertically and is spaced laterally between the second inverter drive pin frame 302 and the extension portion 30322. The PFC driver chip power supply voltage pin 3033 is also spaced apart on the side of the PFC driver chip pad portion 30321 that is vertically opposite to the substrate 2. Specifically, the PFC driver chip power supply voltage pin 3033 extends vertically and is spaced laterally between the second inverter drive pin frame 302 and the extension portion 30322, which allows the PFC driver chip power supply voltage pin 3033 to be positioned adjacent to the PFC drive pad portion, facilitating electrical connection between the PFC driver chip power supply voltage pin 3033 and the PFC driver chip 3031. The PFC driver chip power supply voltage pins 3033 are longitudinally spaced on the side of the PFC driver pad portion away from the substrate 2. This not only reduces the mutual interference between the PFC driver chip power supply voltage pins 3033 and the PFC driver pad portion, thus improving the anti-interference capability of the semiconductor device 100, but also facilitates the layout of the PFC driver chip power supply voltage pins 3033, making it easier to form electrical connection points for the PFC driver chip power supply voltage pins 3033 on the side of the PFC driver pin frame 303 that is longitudinally away from the substrate 2.

[0066] Combination Figure 1 , Figure 3 and Figure 7 As shown, the PFC drive pin frame 303 extends at least partially to one longitudinal side of the rectifier bridge pad portion 204 and corresponds to the rectifier bridge pad portion 204. Specifically, the required installation area of ​​the rectifier drive pin frame is relatively small. This ensures that the rectifier drive pin frame has sufficient installation area while allowing the PFC drive pin frame 303 to extend at least partially to one longitudinal side of the rectifier bridge pad portion 204 and correspond to the rectifier bridge pad portion 204. This not only ensures sufficient installation area for the PFC drive pin frame 303 and the rationality and reliability of its installation, but also allows the area of ​​the substrate 2 occupied by the rectifier bridge pad portion 204 to be larger than the area of ​​the substrate 2 occupied by the PFC power pad portion 203. This ensures that the semiconductor device 100 is not enlarged while maintaining good heat dissipation performance for both the PFC power pad portion 203 and the rectifier bridge pad portion 204.

[0067] Combination Figure 3 , Figure 4 , Figure 6 and Figure 8As shown, the first inverter drive pin frame 301 is provided with a first inverter high-side drive chip 30121 and a first inverter low-side drive chip 30111 arranged laterally. The side of the first inverter low-side drive chip 30111 that is laterally adjacent to the first inverter high-side drive chip 30121 is defined as the first inverter low-side drive chip boundary 30141, and the side of the first inverter high-side drive chip 30121 that is laterally adjacent to the first inverter low-side drive chip 30111 is defined as the first inverter high-side drive chip boundary 30142. Both the first inverter low-side drive chip boundary 30141 and the first inverter high-side drive chip boundary 30142 extend vertically, and the lateral distance between the first inverter low-side drive chip boundary 30141 and the first inverter high-side drive chip boundary 30142 is L1. Specifically, setting the boundary 30141 of the first inverter low-side driver chip and the boundary 30142 of the first inverter high-side driver chip can help to reasonably set the lateral distance between the boundary 30141 of the first inverter low-side driver chip and the boundary 30142 of the first inverter high-side driver chip. This can help to optimize the layout of the first inverter high-side driver chip 30121 and the first inverter low-side driver chip 30111 while ensuring the stable performance of the first inverter high-side driver chip 30121 and the first inverter low-side driver chip 30111.

[0068] Furthermore, the second inverter drive pin frame 302 is provided with a second inverter high-side drive chip 30221 and a second inverter low-side drive chip 30211 arranged laterally. The side of the second inverter low-side drive chip 30211 that is laterally adjacent to the second inverter high-side drive chip 30221 is defined as the second inverter low-side drive chip boundary 30241, and the side of the second inverter high-side drive chip 30221 that is laterally adjacent to the second inverter low-side drive chip 30211 is defined as the second inverter high-side drive chip boundary 30242. Both the second inverter low-side drive chip boundary 30241 and the second inverter high-side drive chip boundary 30242 extend vertically, and the lateral distance between the second inverter low-side drive chip boundary 30241 and the second inverter high-side drive chip boundary 30242 is L2. Specifically, setting the boundary 30241 of the second inverter low-side driver chip and the boundary 30242 of the second inverter high-side driver chip can help to reasonably set the lateral distance between the boundary 30241 and the boundary 30242 of the second inverter low-side driver chip. This can help to optimize the layout of the second inverter high-side driver chip 30221 and the second inverter low-side driver chip 30211 while ensuring their stable performance. Furthermore, L1 and L2 satisfy the relationship: L1 < L2. That is, the lateral distance between the first inverter low-side drive chip boundary 30141 and the first inverter high-side drive chip boundary 30142 is less than the lateral distance between the second inverter low-side drive chip boundary 30241 and the second inverter high-side drive chip boundary 30242. Specifically, the first inverter drive pin frame 301 and the first inverter power pad portion 201 are mostly vertically aligned, and the second inverter drive pin frame 302 and the second inverter power pad portion 202 are also mostly vertically aligned. By making the lateral distance between the first inverter low-side drive chip boundary 30141 and the first inverter high-side drive chip boundary 30142 smaller than the lateral distance between the second inverter low-side drive chip boundary 30241 and the second inverter high-side drive chip boundary 30242, the first inverter drive pin frame 301 can be recessed laterally away from the PFC power pad portion 203, thereby ensuring the power pad portion and the second inverter power pad portion are aligned. Under the premise of ensuring the stable performance of the power pad portion 202, the first inverter power pad portion 201 is recessed laterally away from the PFC power pad portion 203. This reduces the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increases the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 is usually greater than that of the first inverter power pad portion 201, this is beneficial for heat dissipation of the second inverter power pad portion 202, preventing the devices in the second inverter power pad portion 202 from malfunctioning due to excessive temperature, and improving the stability and reliability of the semiconductor device 100.

[0069] Combination Figure 3 , Figure 4 , Figure 6 and Figure 8As shown, the first inverter drive pin frame 301 includes a first inverter drive chip ground pin 3013. The first inverter drive chip ground pin 3013 is at least partially protruding toward the side that is longitudinally away from the substrate 2 to form a first inverter high-side drive pad 3012 and a first inverter low-side drive pad 3011. The first inverter low-side drive chip 30111 is disposed on the first inverter low-side drive pad 3011, and the first inverter high-side drive chip 30121 is disposed on the first inverter high-side drive pad 3012. Specifically, by making the ground pin 3013 of the first inverter driver chip protrude at least partially toward the side that is longitudinally away from the substrate 2 when it extends laterally, the first inverter low-side drive pad 3011 and the first inverter high-side drive pad 3012 are formed. This not only provides a setting position for the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111, but also increases the size of the ground pin 3013 of the first inverter driver chip in both the lateral and longitudinal directions, so as to shorten the distance between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100. In this way, the length of the electrical connection between the ground pin 3013 of the first inverter driver chip and other devices on the semiconductor device 100 can be shortened. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0070] Furthermore, the side of the first inverter low-side drive pad 3011 that is laterally adjacent to the first inverter high-side drive pad 3012 is the first inverter low-side drive pad boundary 30143, and the side of the first inverter high-side drive pad 3012 that is laterally adjacent to the first inverter low-side drive pad 3011 is the first inverter high-side drive pad boundary 30144. Both the first inverter low-side drive pad boundary 30143 and the first inverter high-side drive pad boundary 30144 extend longitudinally, and the lateral distance between the first inverter low-side drive pad boundary 30143 and the first inverter high-side drive pad boundary 30144 is L3. Specifically, setting the boundary 30143 of the first inverter low-side drive pad and the boundary 30144 of the first inverter high-side drive pad can help to reasonably set the lateral distance between the boundary 30143 of the first inverter low-side drive pad and the boundary 30144 of the first inverter high-side drive pad. This can help to optimize the layout of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111 while ensuring the stable performance of the first inverter high-side drive chip 30121 and the first inverter low-side drive chip 30111. Furthermore, a triangular region can extend from the side of the first inverter low-side drive pad 3011 near the first inverter high-side drive pad 3012. This not only optimizes the structural design of the first inverter low-side drive pad 3011 and the layout of the first inverter low-side drive chip 30111, facilitating the electrical connection between the first inverter low-side drive chip 30111 and the first inverter low-side power chip 2011, but also improves the structural strength of the first inverter low-side drive pad 3011 and enhances the stability and reliability of the first inverter drive pin frame 301 structure. In this case, the position of the boundary 30143 of the first inverter low-side drive pad remains unchanged, with the longitudinally extending portion of the first inverter low-side drive pad 3011 near the first inverter high-side drive pad 3012 serving as a reference.

[0071] Furthermore, the second inverter drive pin frame 302 includes a second inverter drive chip ground pin 30231, which is at least partially protruding toward the side longitudinally away from the substrate 2 to form a second inverter high-side drive pad 3022 and a second inverter low-side drive pad 3021. The second inverter low-side drive chip 30211 is disposed on the second inverter low-side drive pad 3021, and the second inverter high-side drive chip 30221 is disposed on the second inverter high-side drive pad 3022. Specifically, by making the ground pin 30231 of the second inverter driver chip protrude at least partially toward the side longitudinally away from the substrate 2 when extending laterally, a pad for the second inverter low-side driver chip 30211 and a pad for the second inverter high-side driver chip 30221 are formed. This not only provides a placement position for the second inverter high-side driver chip 30221 and the second inverter low-side driver chip 30211, but also increases the dimensions of the ground pin 30231 in both the lateral and longitudinal directions, thereby shortening the distance between the ground pin 30231 of the second inverter driver chip and other devices on the semiconductor device 100. This further shortens the length of the electrical connection between the ground pin 30231 of the second inverter driver chip and other devices on the semiconductor device 100. This not only helps to reduce the line resistance in the semiconductor device 100, but also helps to improve the structural compactness of the semiconductor device 100.

[0072] Furthermore, the side of the second inverter low-side drive pad 3021 that is laterally adjacent to the second inverter high-side drive pad 3022 is the second inverter low-side drive pad boundary 30243, and the side of the second inverter high-side drive pad 3022 that is laterally adjacent to the second inverter low-side drive pad 3021 is the second inverter high-side drive pad boundary 30244. Both the second inverter low-side drive pad boundary 30243 and the second inverter high-side drive pad boundary 30244 extend longitudinally, and the lateral distance between the second inverter low-side drive pad boundary 30243 and the second inverter high-side drive pad boundary 30244 is L4. Specifically, setting the boundary 30243 of the second inverter low-side drive pad and the boundary 30244 of the second inverter high-side drive pad can help to reasonably set the lateral distance between the boundary 30243 of the second inverter low-side drive pad and the boundary 30244 of the second inverter high-side drive pad. This can help to optimize the layout of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211 while ensuring the stable performance of the second inverter high-side drive chip 30221 and the second inverter low-side drive chip 30211.

[0073] Furthermore, L3 and L4 satisfy the relationship: L3 < L4. That is, the lateral distance between the boundary 30143 of the first inverter low-side drive pad and the boundary 30144 of the first inverter high-side drive pad is less than the lateral distance between the boundary 30243 of the second inverter low-side drive pad and the boundary 30244 of the second inverter high-side drive pad. Specifically, the first inverter drive pin frame 301 corresponds largely to the first inverter power pad portion 201 in the longitudinal direction, and the second inverter drive pin frame 302 corresponds largely to the second inverter power pad portion 202 in the longitudinal direction. By making the lateral distance between the first inverter low-side drive pad boundary 30143 and the first inverter high-side drive pad boundary 30144 smaller than the lateral distance between the second inverter low-side drive pad boundary 30243 and the second inverter high-side drive pad boundary 30244, the first inverter drive pin frame 301 can be recessed laterally away from the PFC power pad portion 203, thereby ensuring that the first inverter power pad portion 201 is within the PFC power pad portion 202. Under the premise of ensuring the stable performance of the first inverter power pad portion 202, the first inverter power pad portion 201 is recessed laterally to the side away from the power pad portion. This reduces the area of ​​the substrate 2 occupied by the first inverter power pad portion 201 and increases the area of ​​the substrate 2 occupied by the second inverter power pad portion 202. Since the current carrying capacity of the second inverter power pad portion 202 area is usually greater than that of the first inverter power pad portion 201 area, this is beneficial for heat dissipation of the second inverter power pad portion 202 area, prevents the devices in the second inverter power pad portion 202 area from malfunctioning due to excessive temperature, and improves the stability and reliability of the semiconductor device 100.

[0074] In some embodiments of the present invention, the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad, and the rectifier bridge pad 204 are all formed of a copper layer on the substrate 2. The pins on the side of the molding compound 1 away from the drive-side pin frame 3 are power-side pins. Preferably, each power-side pin is soldered to the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad, and the rectifier bridge pad 204. In addition, the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad, and the rectifier bridge pad 204 can also be electrically connected to their respective power-side pins via wires; and / or the first inverter power pad 201, the second inverter power pad 202, the PFC (Power Factor Correction) power pad, and the rectifier bridge pad 204 are integrally formed with their respective power-side pins.

[0075] In some embodiments of the present invention, the substrate 2 may include pads and an insulating heat dissipation layer disposed below the pads. The insulating heat dissipation layer is mainly formed by sequentially stacking an insulating resin sheet and a copper layer, or by sequentially stacking an insulating resin sheet and an aluminum layer. The main material of the pads is copper or aluminum. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the copper layer or the outer surface of the aluminum layer in the insulating heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads, an insulating layer, and a heat dissipation layer formed by sequentially stacking. The main material of the pads is a copper layer or an aluminum layer, the main material of the insulating layer is an ALN, or AL2O3, or Si3N4, or a combination of several materials, and the main material of the heat dissipation layer is a copper layer or an aluminum layer. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the heat dissipation layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may include pads and an insulating layer disposed below the pads. The main material of the insulating layer is an ALN ​​ceramic insulating layer or AL2O3. The substrate 2 may be constructed with a ceramic insulating layer or a Si3N4 ceramic insulating layer. In this case, most of the substrate 2 is encapsulated by the molding compound 1, and the outer surface of the insulating layer of the substrate 2 is exposed from the outer surface of the molding compound 1. Alternatively, the substrate 2 may be formed solely of solder pads. In this case, the substrate 2 is disposed within the molding compound 1, and the molding compound 1 completely encapsulates the substrate 2. The specific structural form of the substrate 2 can be adjusted according to the specific requirements and application environment of the semiconductor device 100.

[0076] The circuit board assembly according to the present invention may mainly include the semiconductor device 100 described above. Specifically, since the semiconductor device 100 has a more reliable structure and good heat dissipation and operating performance, applying the semiconductor device 100 to the circuit board assembly can prevent the circuit board assembly from generating local overheating problems and improve the operating performance of the circuit board assembly.

[0077] The electrical control box according to the present invention may mainly include the aforementioned circuit board assembly. Specifically, since the circuit board assembly has a more reliable structure and good working performance, applying the circuit board assembly to the electrical control box can improve the working performance of the electrical control box and extend its service life.

[0078] The electrical device according to the present invention may mainly include: the aforementioned electrical control box. Specifically, since the electrical control box has a more reliable structure and good working performance, applying the electrical control box to the electrical device can improve the working performance and quality of the electrical device.

[0079] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0080] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0081] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has a lateral direction, a longitudinal direction, and a vertical direction, wherein the lateral direction, the longitudinal direction, and the vertical direction are perpendicular to each other, and the semiconductor device includes: Plastic encapsulation; A substrate, which is at least partially disposed within the molding compound, the substrate including a first inverter power pad portion, a second inverter power pad portion, and a PFC (power factor correction) power pad portion disposed laterally at intervals. A drive-side pin frame is at least partially disposed within the molding compound and spaced apart on one side of the substrate along its longitudinal direction. The drive-side pin frame extends at least partially from the molding compound and includes a first inverter drive pin frame, a second inverter drive pin frame, and a PFC drive pin frame spaced apart in the lateral direction. The first inverter drive pin frame corresponds at least partially in the longitudinal direction to the first inverter power pad portion. The second inverter drive pin frame corresponds at least partially in the longitudinal direction to the second inverter power pad portion. The PFC drive pin frame corresponds at least partially in the longitudinal direction to the PFC (Power Factor Correction) power pad portion. The center of the PFC drive pin frame is offset laterally from the center of the PFC power pad portion toward a side away from the second inverter drive pin frame. The second inverter drive pin frame extends at least partially to the longitudinal side of the PFC power pad portion and corresponds to at least a portion of the PFC power pad portion. A PFC drive chip is disposed on the PFC drive pin frame, and the center of the PFC drive chip corresponds longitudinally to the center of the PFC power pad portion. Alternatively, the center of the PFC driver chip may be offset laterally away from the center of the PFC power pad portion towards the side away from the second inverter drive pin frame.

2. The semiconductor device according to claim 1, characterized in that, The second inverter drive pin frame further includes a second inverter high-side drive floating power supply voltage first pin, a second inverter high-side drive floating power supply voltage second pin, and a second inverter high-side drive floating power supply voltage third pin, which are arranged laterally at intervals. The second inverter high-side drive floating power supply voltage first pin, the second inverter high-side drive floating power supply voltage second pin, and the second inverter high-side drive floating power supply voltage third pin are respectively provided with a second inverter bootstrap chip first pad, a second inverter bootstrap chip second pad, and a third inverter bootstrap chip third pad at one end of the second inverter bootstrap chip first pad, the second inverter bootstrap chip second pad, and the second inverter bootstrap chip third pad. A second inverter bootstrap chip is provided on each of the second inverter bootstrap chip first pad, the second inverter bootstrap chip second pad, and the second inverter bootstrap chip third pad. The second inverter bootstrap chip third pad is located on one side of the PFC power pad portion and corresponds to the PFC power pad portion.

3. The semiconductor device according to claim 2, characterized in that, The second inverter drive pin frame also includes a first pin of the second inverter high-side drive floating power supply ground, a second pin of the second inverter high-side drive floating power supply ground, and a third pin of the second inverter high-side drive floating power supply ground. The first pin of the second inverter high-side drive floating power supply ground is horizontally spaced between the first pin of the second inverter high-side drive floating power supply voltage and the second pin of the second inverter high-side drive floating power supply voltage. The second pin of the second inverter high-side drive floating power supply ground is horizontally spaced between the second pin of the second inverter high-side drive floating power supply voltage and the third pin of the second inverter high-side drive floating power supply voltage. The third pin of the second inverter high-side drive floating power supply ground is horizontally spaced on the side of the third pin of the second inverter high-side drive floating power supply voltage away from the second pin of the second inverter high-side drive floating power supply voltage. The third pin of the second inverter high-side drive floating power supply ground is located on the longitudinal side of the PFC power pad and corresponds to the PFC power pad. At least a portion of the second pin of the second inverter high-side drive floating power supply ground is located on the longitudinal side of the PFC power pad portion and corresponds to the PFC power pad portion.

4. The semiconductor device according to claim 3, characterized in that, The second inverter drive pin frame includes a second inverter drive chip ground pin and a second inverter drive power supply voltage pin, which at least partially extend to one longitudinal side of the PFC power pad portion and correspond to the PFC power pad portion.

5. The semiconductor device according to claim 1, characterized in that, The lateral dimension of the first inverter power pad is smaller than the lateral dimension of the second inverter power pad.

6. The semiconductor device according to claim 1, characterized in that, The substrate further includes a rectifier bridge pad portion, which is laterally spaced from the first inverter power pad portion, the second inverter power pad portion, and the PFC (power factor correction) power pad portion. A plurality of rectifier chips are disposed on the rectifier bridge pad portion. The drive-side pin frame further includes a rectifier bridge drive pin frame, which is at least partially corresponding to the rectifier bridge pad portion in the longitudinal direction. The rectifier bridge drive pin frame extends at least partially to the rectifier bridge pad portion and is electrically connected to the rectifier bridge pad portion. The lateral dimension of the rectifier bridge pad is larger than the lateral dimension of the PFC (Power Factor Correction) power pad.

7. The semiconductor device according to claim 1, characterized in that, The PFC driver pin frame includes a PFC driver chip ground pin and a PFC driver chip power supply voltage pin. The PFC driver chip ground pin includes a PFC driver chip pad portion and an extension portion. The extension portion extends longitudinally. The PFC driver chip pad portion is disposed at one end of the extension portion that is longitudinally adjacent to the substrate. The PFC driver chip pad portion protrudes relative to the extension portion toward the side that is longitudinally adjacent to the second inverter driver pin frame and is spaced laterally from the second inverter driver pin frame. The PFC driver chip is disposed on the PFC driver chip pad portion. The PFC driver chip power supply voltage pins extend vertically and are spaced laterally between the second inverter driver pin frame and the extension portion. The PFC driver chip power supply voltage pins are spaced apart on the side of the PFC driver chip pad portion that is vertically opposite to the substrate.

8. The semiconductor device according to claim 7, characterized in that, The PFC drive pin frame extends at least partially to one longitudinal side of the rectifier bridge pad portion and corresponds to the rectifier bridge pad portion.

9. The semiconductor device according to claim 1, characterized in that, The first inverter drive pin frame is provided with a first inverter high-side drive chip and a first inverter low-side drive chip arranged horizontally. The side of the first inverter low-side drive chip that is horizontally adjacent to the first inverter high-side drive chip is defined as the boundary of the first inverter low-side drive chip. The side of the first inverter high-side drive chip that is horizontally adjacent to the first inverter low-side drive chip is defined as the boundary of the first inverter high-side drive chip. Both the boundary of the first inverter low-side drive chip and the boundary of the first inverter high-side drive chip extend vertically. The horizontal distance between the boundary of the first inverter low-side drive chip and the boundary of the first inverter high-side drive chip is L1. The second inverter drive pin frame is provided with a second inverter high-side drive chip and a second inverter low-side drive chip arranged horizontally at intervals. The side of the second inverter low-side drive chip that is horizontally adjacent to the second inverter high-side drive chip is defined as the boundary of the second inverter low-side drive chip, and the side of the second inverter high-side drive chip that is horizontally adjacent to the second inverter low-side drive chip is defined as the boundary of the second inverter high-side drive chip. Both the boundary of the second inverter low-side drive chip and the boundary of the second inverter high-side drive chip extend vertically. The horizontal distance between the boundary of the second inverter low-side drive chip and the boundary of the second inverter high-side drive chip is L2. L1 and L2 satisfy the relationship: L1 < L2.

10. The semiconductor device according to claim 1, characterized in that, The first inverter drive pin frame includes a ground pin of a first inverter drive chip. The ground pin of the first inverter drive chip protrudes at least partially toward the side that is longitudinally away from the substrate to form a first inverter high-side drive pad and a first inverter low-side drive pad. The first inverter low-side drive chip is disposed on the first inverter low-side drive pad, and the first inverter high-side drive chip is disposed on the first inverter high-side drive pad. The side of the first inverter low-side drive pad that is laterally adjacent to the first inverter high-side drive pad is the boundary of the first inverter low-side drive pad. The side of the first inverter high-side drive pad that is laterally adjacent to the first inverter low-side drive pad is the boundary of the first inverter high-side drive pad. Both the boundary of the first inverter low-side drive pad and the boundary of the first inverter high-side drive pad extend longitudinally. The lateral distance between the boundary of the first inverter low-side drive pad and the boundary of the first inverter high-side drive pad is L3. The second inverter drive pin frame includes a ground pin for a second inverter drive chip. The ground pin of the second inverter drive chip protrudes at least partially toward the side longitudinally away from the substrate to form a second inverter high-side drive pad and a second inverter low-side drive pad. The second inverter low-side drive chip is disposed on the second inverter low-side drive pad, and the second inverter high-side drive chip is disposed on the second inverter high-side drive pad. The side of the second inverter low-side drive pad that is laterally adjacent to the second inverter high-side drive pad is the boundary of the second inverter low-side drive pad. The side of the second inverter high-side drive pad that is laterally adjacent to the second inverter low-side drive pad is the boundary of the second inverter high-side drive pad. Both the boundary of the second inverter low-side drive pad and the boundary of the second inverter high-side drive pad extend longitudinally. The lateral distance between the boundary of the second inverter low-side drive pad and the boundary of the second inverter high-side drive pad is L4. L3 and L4 satisfy the relationship: L3 < L4.

11. A circuit board assembly, characterized in that... The semiconductor device included in any one of claims 1-10.

12. An electrical control box, characterized in that, Includes the circuit board assembly as described in claim 11.

13. An electrical appliance, characterized in that, Includes the electrical control box as described in claim 12.

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