Modular multilevel power conversion device based on master-slave architecture sampling communication

Abstract

The application discloses a modular multilevel power conversion device based on master-slave architecture sampling communication, which comprises a main power circuit and a control system, and the control system comprises a semi-physical simulation controller, a signal conditioning circuit and a signal sampling circuit; the signal sampling circuit samples signals of the main power circuit, acquires sampling signals and transmits the sampling signals to the semi-physical simulation controller in real time; the semi-physical simulation controller confirms on-off states of switch tubes of each SM sub-module in the MMC circuit according to the acquired sampling signals, and obtains pulse signals of the switch tubes; the signal conditioning circuit performs signal conditioning on the pulse signals of the switch tubes and outputs the pulse signals to a three-phase signal distribution board, so that the conditioned pulse signals are used for phase control of the MMC circuit. The application solves the problems of the existing MMC experimental platform, such as insufficient state monitoring reliability and main controller resource allocation, and causes serious problems of restricting the control bandwidth and dynamic response speed of the system.

Description

Technical Field

[0001] This invention relates to the field of modular multilevel power converter technology, and more particularly to a modular multilevel power converter device based on master-slave architecture sampling communication. Background Technology

[0002] With the widespread application of high-voltage direct current (HVDC) transmission and distribution technology in smart grids, modular multilevel converters (MMCs), with their modular design and excellent scalability, are gradually becoming key equipment in smart microgrid systems. While the distributed submodule structure of MMCs currently offers excellent harmonic performance and redundancy, it also significantly increases the complexity of system status monitoring. In particular, real-time detection of submodule capacitor voltages has become a core technical challenge for ensuring stable system operation. Therefore, in-depth research into MMC submodule voltage detection technology suitable for smart microgrids can effectively improve the operational reliability of converters in both rectification and inversion modes, and has significant theoretical and engineering value for building safe, efficient, and intelligent next-generation smart microgrid systems.

[0003] As research into MMC technology deepens and its engineering applications become more advanced, the problems of status monitoring and communication caused by its large number of sub-modules are becoming increasingly prominent. Traditional system architecture solutions have the following significant drawbacks.

[0004] Existing common MMC experimental platforms typically employ a centralized data acquisition scheme, where the capacitor voltages of all submodules are directly connected to the analog acquisition port of the central controller via lengthy analog sampling cables. As the number of voltage levels increases, the sheer number and complexity of these sampling cables not only pose significant challenges to platform setup and maintenance, but more importantly, long-distance analog signal transmission is highly susceptible to severe signal attenuation and electromagnetic interference, leading to decreased sampling data accuracy and increased noise. Unreliable sampling data directly restricts the performance of algorithms such as voltage equalization control, becoming a major hidden danger to system stability and failing to meet the stringent data accuracy requirements of high-performance control strategies.

[0005] In traditional architectures, the central controller directly manages data interaction with the quantum modules. This results in its limited communication interfaces and computing resources being heavily consumed by the massive underlying data acquisition and communication tasks. The controller is forced to spend a significant amount of time processing data reception, parsing, and distribution, making it unable to focus on executing more complex system-level control algorithms such as model predictive control and advanced modulation strategies. This resource contention problem severely restricts the system's control bandwidth and dynamic response speed, making the real-time implementation of many advanced algorithms extremely difficult or even impossible, thus limiting the development capabilities of the experimental platform.

[0006] In summary, existing MMC experimental platforms have significant technical deficiencies in terms of reliability of status monitoring and allocation of main controller resources. An innovative system architecture and communication scheme are needed to solve these problems, thereby providing a solid and reliable hardware platform support for in-depth research on advanced MMC control technology. Summary of the Invention

[0007] This invention provides a modular multilevel power conversion device based on master-slave architecture sampling communication to overcome the above-mentioned technical problems.

[0008] To achieve the above objectives, the technical solution of the present invention is as follows:

[0009] A modular multilevel power conversion device based on master-slave architecture sampling communication includes a main power circuit and a control system, wherein the control system includes a hardware-in-the-loop controller, a signal conditioning circuit and a signal sampling circuit for isolation protection.

[0010] The main power circuit controls the switching devices to operate in either rectification or inverter mode; the main power circuit includes at least an autotransformer, a fuse, a rectifier pre-charge device, an MMC circuit, an inverter pre-charge device, and an inductor.

[0011] The signal sampling circuit is used to sample the main power circuit, acquire the sampled signal and transmit it to the hardware-in-the-loop controller in real time. The sampled signal includes at least the DC voltage output by the rectifier mode circuit, the AC voltage output by the inverter mode circuit, the AC current output by the inverter mode circuit, the bridge arm current in the MMC circuit, the DC bus voltage, and the capacitor voltage of the SM submodule acquired and transmitted through the master-slave communication module belonging to the control system.

[0012] The hardware-in-the-loop (HIL) controller is used to obtain the on / off status of the switching transistors of each SM submodule in the MMC circuit based on the acquired sampling signal using the Simulink control algorithm, and then obtain the corresponding PWM drive pulse signal.

[0013] The signal conditioning circuit is used to process the received PWM pulse signal and output the conditioned PWM signal to the three-phase signal distribution board. The three-phase signal distribution board distributes the conditioned PWM signal to the switching transistor drive circuits of the corresponding sub-modules of each phase of the MMC according to the preset phase configuration, so as to realize the phase control of the MMC circuit. The signal conditioning process includes at least reverse expansion and signal modulation.

[0014] Furthermore, the master-slave communication module includes a slave module for acquiring the capacitor voltage of the SM sub-module corresponding to the C-phase wire, and a master module for acquiring the capacitor voltage of the SM sub-module corresponding to the A / B-phase wire. The slave module is communicatively connected to the master module to send the C-phase sub-module capacitor voltage acquired by the slave module to the master module. The master module is also used to package the C-phase sub-module capacitor voltage and the A / B-phase sub-module capacitor voltage together and upload them to the hardware-in-the-loop controller after receiving the C-phase sub-module capacitor voltage sent by the slave module.

[0015] Furthermore, one end of the autotransformer is connected to the grid output terminal of the preset input three-phase grid power.

[0016] The other end of the autotransformer is connected to one end of a fuse. The other end of the fuse is connected to one end of a rectifier pre-charging device via relay switches KM1 and KM6 connected in sequence. The other end of the rectifier pre-charging device is connected to one end of an inductor. One end of the inductor is connected to one end of the upper bridge arm module and one end of the lower bridge arm module of the MMC circuit, which are symmetrically arranged.

[0017] Furthermore, the upper arm module is provided with three sets of parallel upper arm sub-modules, including the A-phase upper arm sub-module, the B-phase upper arm sub-module, and the C-phase upper arm sub-module.

[0018] The lower bridge arm module is provided with three sets of parallel lower bridge arm sub-modules, including the A-phase lower bridge arm sub-module, the B-phase lower bridge arm module and the C-phase lower bridge arm module.

[0019] The upper bridge arm submodule and the lower bridge arm submodule are provided with several SM submodules connected in sequence;

[0020] Furthermore, the other end of each upper bridge arm submodule is connected to one end of the first resistor R3, one end of the second resistor R4, one end of the DC voltage sensor PT4, and one end of the relay switch KM4; the other end of the relay switch KM4 is connected to one end of the load capacitor C and one end of the relay switch KM11.

[0021] The other end of each lower bridge arm submodule is connected to the other end of the first resistor R3, the other end of the second resistor R4, the other end of the DC voltage sensor PT4, and the other end of the load capacitor C, and the connection point is used as a common contact.

[0022] One end of relay switch KM1 is connected to one end of relay switch KM2, and the other end of relay switch KM2 is connected to the input terminal of the three-phase uncontrolled rectifier module. The output pin 1 of the three-phase uncontrolled rectifier module is connected to one end of the inverter pre-charge device, and the other end of the inverter pre-charge device is connected to one end of relay switch KM10. The other end of relay switch KM10 is connected to one end of relay switch KM11.

[0023] An AC current sensor is provided between the rectifier pre-charging device and the inductor element, and one end of the AC current sensor is connected to one end of the relay switch KM5, while the other end of the relay switch KM5 is connected to the inverter voltage output module used to obtain the output AC power.

[0024] Furthermore, each of the SM submodules is equipped with a submodule capacitor voltage sensor; an AC voltage sensor is also provided between the rectifier pre-charging device and the inductor element.

[0025] Furthermore, the inductor includes a parallel A-phase inductor, a B-phase inductor, and a C-phase inductor; the MMC circuit also includes several bridge arm inductors L0;

[0026] Furthermore, one end of the A-phase inductor is connected to the upper and lower bridge arm submodules of the A-phase via the bridge arm inductor L0; one end of the B-phase inductor is connected to the upper and lower bridge arm submodules of the B-phase via the bridge arm inductor L0; and one end of the C-phase inductor is connected to the upper and lower bridge arm submodules of the C-phase via the bridge arm inductor L0.

[0027] Furthermore, bridge arm current sensors are provided between the bridge arm inductor L0 and the upper bridge arm submodule of phase A, between the bridge arm inductor L0 and the upper bridge arm submodule of phase B, between the bridge arm inductor L0 and the upper bridge arm submodule of phase C, between the bridge arm inductor L0 and the lower bridge arm submodule of phase A, between the bridge arm inductor L0 and the lower bridge arm submodule of phase B, and between the bridge arm inductor L0 and the lower bridge arm submodule of phase C.

[0028] Furthermore, the signal sampling circuit includes a sub-module capacitor voltage sampling circuit, a DC voltage sampling circuit, an AC voltage sampling circuit, and an AC current sampling circuit;

[0029] The submodule capacitor voltage sampling circuit is used to acquire the SM submodule capacitor voltage obtained by the submodule capacitor voltage sensor through the master-slave communication module;

[0030] The AC voltage sampling circuit is used to acquire the AC voltage output from the inverter mode circuit or the AC voltage input from the rectifier mode circuit obtained by the AC voltage sensor.

[0031] The DC voltage sampling circuit is used to acquire the DC bus voltage obtained by the DC voltage sensor;

[0032] The AC current sampling circuit is used to acquire the bridge arm current in the MMC circuit obtained by the bridge arm current sensor.

[0033] Furthermore, the signal conditioning circuit includes a signal inverting circuit and a signal buffer circuit connected in sequence;

[0034] The signal inversion circuit is used to invert and extend the corresponding PWM pulse signals of the switching transistors of each SM submodule in the MMC circuit, that is, to obtain complementary PWM pulse signals by performing a logic NOT operation.

[0035] The signal buffer circuit is used to perform signal modulation on the complementary PWM pulse signals and convert them into the same voltage level.

[0036] Furthermore, it also includes a design selection module;

[0037] The design selection module includes a sub-module switch design module, a sub-module capacitor design module, and a bridge arm inductor design module;

[0038] The submodule switch design module is used to form a switching device with a rated current greater than the peak current flowing through the submodule switch, and the peak current of the submodule switch... The formula for obtaining it is

[0039] ,

[0040] In the formula: S represents the known system capacity; Indicates the effective value of the grid-side voltage; Indicates overload rate; Indicates the ripple factor;

[0041] The submodule capacitor design module is used to quantitatively obtain the submodule capacitor. ;

[0042] And obtain the capacitor of the submodule The expression is

[0043] ,

[0044] In the formula: This indicates the power at the input of the rectifier. Indicates the total number of bridge arm submodules; This represents the modulation coefficient of the MMC output voltage; Indicates the rated operating voltage of the submodule capacitor; express The voltage fluctuation range; Indicates the system's operating angular frequency; Indicates the power factor angle;

[0045] The bridge arm inductance design module is used to quantitatively obtain the bridge arm inductance. ;

[0046] And obtain the bridge arm inductance The expression is

[0047] ,

[0048] ,

[0049] In the formula: Indicates the peak value of the bridge arm current ripple; This indicates the switching frequency of the corresponding MMC; This indicates the peak value of the capacitor voltage in the submodule; Indicates the fundamental component of the bridge arm current; This indicates the phase current on the AC side of the MMC; This indicates the DC side current of the MMC.

[0050] Beneficial Effects: This invention provides a modular multilevel power conversion device based on master-slave architecture sampling communication. By adopting a modular architecture design, including a main power circuit and a control system, the control system is designed as a signal sampling circuit, a hardware-in-the-loop controller, and a signal conditioning circuit, reserving space for upgrading to a higher level MMC. This invention establishes a master-slave communication module for the acquisition of the three-phase submodule capacitor voltages. Specifically, the master module is responsible for acquiring the A / B phase submodule capacitor voltages, while the slave module is dedicated to acquiring the C phase voltage and transmitting the C phase data to the master module in real time via communication. This phase-based distributed acquisition method can rationally distribute the concentrated and large voltage sampling bundles. The proximity to the three phases significantly shortens the transmission distance of the analog signal, physically reducing the risk of signal attenuation and electromagnetic interference, and improving the accuracy of the sampled data and the reliability of the system. After receiving the C-phase data from the slave module, the host module packages and integrates it with the locally acquired A / B-phase data to generate a complete, synchronous full-system sub-module capacitor voltage data packet, which is then uniformly uploaded to the hardware-in-the-loop controller. This allows the hardware-in-the-loop controller to obtain all three-phase capacitor voltage information by establishing a single communication link with a host module, greatly saving the communication interface resources of the hardware-in-the-loop controller, simplifying the communication protocol, and reducing the data processing load of the main controller. Furthermore, the device described in this embodiment achieves stable operation in rectification, inversion, and DC output modes. The platform adopts a modular architecture design, reserving space for upgrading to higher-level MMCs, while integrating a high-precision measurement system and comprehensive protection functions. In specific implementation, by rationally selecting submodule switching transistors, designing DC support capacitor parameters, and bridge arm reactors, and in conjunction with a master-slave architecture control system, the reliability and real-time performance of the platform operation are ensured. This experimental platform provides important support for MMC system topology optimization, advanced modulation strategy verification, and innovative control algorithm development. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic diagram of the modular multilevel power conversion device based on master-slave architecture sampling communication in this invention;

[0053] Figure 2 This is a schematic diagram of the main power circuit in this embodiment;

[0054] Figure 3 This is a block diagram of the submodule capacitor voltage sampling in this embodiment;

[0055] Figure 4 This is a diagram of the DC 24V power supply control circuit in this embodiment;

[0056] Figure 5 This is the AC 24V power supply control circuit diagram in this embodiment;

[0057] Figure 6 This is a schematic diagram of the power supply circuit for the capacitor voltage sampling circuit of the submodule in this embodiment;

[0058] Figure 7 This is a schematic diagram of the master-slave communication circuit of the submodule capacitor voltage sampling circuit in this embodiment;

[0059] Figure 8 This is a schematic diagram of the Ethernet and serial interface circuit of the submodule sampling circuit in this embodiment;

[0060] Figure 9 This is a schematic diagram of the DC voltage sampling circuit in this embodiment;

[0061] Figure 10 This is a schematic diagram of the AC voltage sampling circuit in this embodiment.

[0062] Figure 11 This is a schematic diagram of the AC current sampling circuit in this embodiment;

[0063] Figure 12 This is a block diagram of the PWM signal conditioning circuit design in this embodiment;

[0064] Figure 13 This is a schematic diagram of the PWM signal inverting circuit in this embodiment;

[0065] Figure 14 This is a schematic diagram of the PWM buffer circuit in this embodiment;

[0066] Figure 15 This is a schematic diagram of the signal distribution circuit in this embodiment;

[0067] Figure 16 This is a schematic diagram of the sub-module circuit in this embodiment;

[0068] Figure 17 This is a schematic diagram illustrating the principle of submodule deployment / removal in this embodiment;

[0069] Figure 18 This is a diagram showing the PWM signal flow in this embodiment;

[0070] Figure 19 This is a flowchart of the submodule fault detection process in this embodiment;

[0071] Figure 20 This is the design diagram of the main experimental program in this embodiment;

[0072] Figure 21 This is a flowchart of the software protection design in this embodiment;

[0073] Figure 22 This is a flowchart of the main communication program in this embodiment;

[0074] Figure 23 This is the control flowchart of the slave interrupt subroutine in this embodiment;

[0075] Figure 24 This is the host interrupt subroutine control flowchart in this embodiment;

[0076] Figure 25 This is an experimental effect diagram of the present invention under a three-phase balanced power grid in this embodiment. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] This embodiment provides a modular multilevel power conversion device based on master-slave architecture sampling communication, such as... Figure 1 As shown, it includes a main power circuit and a control system, and the control system includes a signal sampling circuit, a hardware-in-the-loop controller and a signal conditioning circuit.

[0079] The main power circuit controls the switching devices to operate in either rectification or inverter mode; the main power circuit includes at least an autotransformer, a fuse, a rectifier pre-charge device, an MMC circuit, an inverter pre-charge device, and an inductor.

[0080] Specifically, such as Figure 2 As shown, one end of the autotransformer is connected to the grid output terminal of the preset input three-phase grid power.

[0081] The other end of the autotransformer is connected to one end of a fuse. The other end of the fuse is connected to one end of a rectifier pre-charging device via relay switches KM1 and KM6 connected in sequence. The other end of the rectifier pre-charging device is connected to one end of an inductor. One end of the inductor is connected to one end of the upper bridge arm module and one end of the lower bridge arm module of the MMC circuit, which are symmetrically arranged.

[0082] Furthermore, the upper bridge arm module is provided with three sets of parallel upper bridge arm sub-modules, including the A-phase upper bridge arm sub-module, the B-phase upper bridge arm sub-module, and the C-phase upper bridge arm sub-module; the lower bridge arm module is provided with three sets of parallel lower bridge arm sub-modules, including the A-phase lower bridge arm sub-module, the B-phase lower bridge arm sub-module, and the C-phase lower bridge arm sub-module.

[0083] The upper bridge arm submodule and the lower bridge arm submodule are provided with several SM submodules connected in sequence;

[0084] Furthermore, the other end of each upper bridge arm submodule is connected to one end of the first resistor R3, one end of the second resistor R4, one end of the DC voltage sensor PT4, and one end of the relay switch KM4; the other end of the relay switch KM4 is connected to one end of the load capacitor C and one end of the relay switch KM11.

[0085] The other end of each lower bridge arm submodule is connected to the other end of the first resistor R3, the other end of the second resistor R4, the other end of the DC voltage sensor PT4, and the other end of the load capacitor C, and the connection point is used as a common contact.

[0086] One end of relay switch KM1 is connected to one end of relay switch KM2, and the other end of relay switch KM2 is connected to the input terminal of the three-phase uncontrolled rectifier module. The output pin 1 of the three-phase uncontrolled rectifier module is connected to one end of the inverter pre-charge device, and the other end of the inverter pre-charge device is connected to one end of relay switch KM10. The other end of relay switch KM10 is connected to one end of relay switch KM11. The voltage between the output pin 2 of the three-phase uncontrolled rectifier module and the other end of relay switch KM11 is used as the output voltage for obtaining the output DC power.

[0087] An AC current sensor is provided between the rectifier pre-charging device and the inductor element, and one end of the AC current sensor is connected to one end of the relay switch KM5, while the other end of the relay switch KM5 is connected to the inverter voltage output module for obtaining the output AC power.

[0088] The rectification mode is the circuit that outputs DC power to external loads when the grid power passes through an autotransformer, fuse, rectifier pre-charge device, inductor and MMC circuit in sequence.

[0089] Specifically, the grid power is transmitted to the autotransformer for voltage regulation. The autotransformer can regulate the voltage by changing the turns ratio of the windings. When used as a step-down transformer, a portion of the windings is removed as secondary windings, thus reducing the voltage. When used as a step-up transformer, the applied voltage is only applied to a portion of the windings, thus increasing the voltage. Relay switches KM1 and KM6 are closed to transmit the regulated voltage through a fuse, a rectifier pre-charge device, and an inductor to the MMC circuit. The MMC circuit can be used for reactive power compensation in the power grid, providing reactive power support and regulation. By controlling the phase difference between current and voltage, the MMC circuit can achieve rapid reactive power regulation, improving the stability and power quality of the power grid. Relay switches KM4, KM8, KM9, and KM11 are closed to output DC power.

[0090] Inverter mode is the circuit that outputs AC power to external loads when grid power passes through an autotransformer, fuse, inverter pre-charge device, MMC circuit and inductor in sequence.

[0091] Specifically, grid power is transmitted to an autotransformer for voltage regulation; relay switches KM1 and KM2 are closed while relay switches KM6 and KM11 are simultaneously opened, so that the regulated voltage is transmitted to the three-phase uncontrolled rectifier module through a fuse to convert the three-phase AC power to DC power; relay switches KM4, KM8, and KM9 are closed to transmit the DC power to the MMC circuit, where the DC power is inverted to obtain AC voltage, and the AC power is output through the inverter voltage output module; this embodiment also includes a DC 24V power supply control circuit and an AC 24V power supply control circuit, such as... Figure 4 and Figure 5 As shown, this is the switching circuit between the rectification mode circuit and the inverter mode circuit set according to the preset target requirements in this embodiment.

[0092] The signal sampling circuit is used to sample signals from the main power circuit in different operating modes, acquire the sampled signals, and transmit them to the hardware-in-the-loop controller in real time. The sampled signals include at least the DC voltage output from the rectifier mode circuit or the AC voltage output from the inverter mode circuit acquired by the AC voltage sensor, the bridge arm current in the MMC circuit acquired by the bridge arm current sensor, the DC bus voltage acquired by the DC voltage sensor, and the SM submodule capacitor voltage acquired by the submodule capacitor voltage sensor and transmitted through the master-slave communication module belonging to the control system. The master-slave communication module includes a slave module for acquiring the capacitor voltage of the SM submodule corresponding to the C-phase wire and a master module for acquiring the capacitor voltage of the SM submodule corresponding to the A / B phase wire. The slave module is communicatively connected to the master module to send the C-phase submodule capacitor voltage acquired by the slave module to the master module. The master module is also used to package the C-phase submodule capacitor voltage sent by the slave module with the A / B phase submodule capacitor voltage and upload it to the hardware-in-the-loop controller.

[0093] Specifically, in the design of the MMC control system, high-precision signal acquisition and real-time transmission form the foundation of closed-loop control. The system needs to acquire multiple key electrical parameters, including grid-side AC voltage, output AC voltage and current, phase arm current, submodule capacitor voltage, and DC bus voltage. Accurate measurement of arm current and submodule capacitor voltage directly affects the stability and reliability of the system operation, while accurate acquisition of grid-side electrical parameters is a prerequisite for achieving grid synchronization and power control. All signals are synchronously acquired at a fixed sampling frequency to ensure the real-time response performance of the control system. Since the sensors acquire specific values, the signal sampling circuit in this embodiment serves as an isolation and protection mechanism. It uses internal chips and operational amplifiers to scale the voltage and current to a range that the hardware-in-the-loop controller dSPACE1202 can handle. The signal sampling circuit specifically includes...

[0094] A. Submodule capacitor voltage sampling circuit: such as Figure 3 As shown, in this embodiment, the submodule capacitor voltage sampling circuit consists of a communication control board and two DC voltage sampling circuits; as Figures 6 to 8The diagram shows the schematic of the capacitor voltage sampling circuit for the submodule. It consists of three parts: a power supply circuit, two DSP TMS320F28335 core boards (DSP-1 and DSP-2) and their peripheral circuits, and an RS485 communication circuit. It also includes an Ethernet interface circuit, a serial communication circuit, and a voltage signal input circuit. The power input is DC 24V, and the outputs are DC ±5V 30W and DC 3.3V 10W. The DC voltage sampling circuit samples the voltage and outputs a signal, which is transmitted to the DSP's AD sampling interface via an FPC cable. The two DSPs communicate through a cross-connection of the GPIO62-SCIRXDC and GPIO63-SCITXDC interfaces. The slave DSP-1 reads 16-bit ADC sampling data and transmits it to the master DSP-2. After receiving the data, the master DSP merges it with its own 16-bit ADC sampling data and sends it to the hardware-in-the-loop controller dSPACE1202 via the RS485 communication interface.

[0095] B. DC voltage sampling circuit: such as Figure 9 The diagram shows the schematic of a DC voltage sampling circuit. The circuit uses the ACPL-C87B-500E as the isolation sampling chip, which is an optically isolated proportional amplifier specifically designed for DC voltage sampling. The primary side is powered by a B2405S-1WR3 power supply, and the secondary side is powered by a ±5V power supply. The primary and secondary power supplies are isolated from each other. The input voltage range of 0~2V and the input impedance of 1GΩ make it very suitable for the isolation voltage sensing requirements in electronic power converter applications. A resistor divider circuit is used on the primary side of the isolation sampling chip to narrow the DC link voltage to accommodate the input range of the voltage sensor. In practice, this circuit uses two 100kΩ and two 3kΩ resistors in series for voltage division, resulting in an actual voltage sampling ratio of approximately 30:1. An operational amplifier is used at the end of the circuit to enhance the signal driving capability.

[0096] C. AC voltage sampling circuit: such as Figure 10As shown, this circuit system implements the isolated sampling function of AC voltage. The NSI1300D25 DSWVR serves as the core isolated sampling component, employing NOVOSENSE capacitor isolation technology to ensure complete electrical isolation between the input and output terminals. In terms of power supply configuration, the B2405S-1WR3 provides power to the primary side, while the secondary side is independently powered by a 5V power supply, maintaining electrical isolation between the two. This isolated amplifier has a linear differential input range of ±250mV (full scale up to ±320mV), and its differential input characteristics are particularly suitable for shunt resistor current detection under high-voltage environments. The device has a built-in fixed gain of 8.2 and outputs a differential analog signal. The power supply system shares the same architecture as the DC voltage sampling circuit. In this embodiment, the voltage divider network design uses two 200kΩ and two 100Ω resistors in series to form a voltage divider structure, achieving a voltage sampling ratio of approximately 2000:1. To meet AC sampling requirements, a 2.5V DC bias voltage is connected to the non-inverting input of the operational amplifier through a 10kΩ resistor. The output stage uses an operational amplifier to enhance signal driving capability, and the final sampled signal is transmitted to the analog input port of the hardware-in-the-loop controller dSPACE1202 via a coaxial cable.

[0097] D. Alternating current sampling circuit: Figure 11 This is the schematic diagram of an AC current sampling circuit. The AC current sampling circuit uses the CC6920BSO-20A chip, with a measurement range of ±20A. This chip consists of a precise, low-bias linear Hall effect circuit, with its copper conduction path located near the chip surface. When current flows through the copper conduction path, a magnetic field is generated. Simultaneously, the Hall effect circuit converts the magnetic signal into an output voltage signal. The internal copper conductor resistance is typically 0.9mΩ, providing lower power loss than general resistor sampling methods. The inherent internal insulation provides a basic operating isolation voltage of 424VRMS and an insulation withstand voltage of 3500VRMS between the input current path and the secondary circuit. The chip is powered by a 5V power supply. The zero-current output voltage is 50%VCC, and the linear output voltage range is 0.2~4.8V with a linearity of up to 0.1%. The non-inverting input of the operational amplifier at the end of the circuit is also connected to a 2.5V DC bias via a 10k resistor. The operational amplifier at the end of the circuit enhances the signal driving capability. The AC current sampling signal is directly output to the analog input interface of the dSPACE1202 hardware-in-the-loop controller via a coaxial cable.

[0098] The hardware-in-the-loop (HIL) controller is used to obtain the on / off status of the switching transistors of each SM submodule in the MMC circuit, i.e., the on / off status of the SM submodule, based on the acquired sampling signal, and then obtain the corresponding PWM drive pulse signal.

[0099] In this embodiment, a simulation experimental platform is first pre-built in MATLAB, and the Simulink control algorithm is loaded into the simulation experimental platform through the hardware-in-the-loop simulation controller dSPACE1202. Thus, based on the sampled signal input, the pulse signals for the switching of each SM sub-module in the MMC circuit can be obtained from the simulation experimental platform. The method of simulating the Simulink control algorithm in this embodiment is a well-known existing technology, and will not be described in detail here.

[0100] The signal conditioning circuit is used to process the received PWM pulse signal and output the conditioned PWM signal to the three-phase signal distribution board. The three-phase signal distribution board then distributes the conditioned PWM signal to the switching transistor drive circuits of the corresponding sub-modules of each phase of the MMC according to a preset phase configuration, thereby achieving phase control of the MMC circuit. The signal conditioning process includes at least inverse expansion and signal modulation. The signal inversion circuit is used to obtain complementary PWM pulse signals by inverse expansion of the PWM pulse signals corresponding to the on / off states of the switching transistors of each SM sub-module in the MMC circuit, i.e., by performing a logic NOT operation. The signal buffer circuit is used to perform signal modulation on the complementary PWM pulse signals and convert them to the same voltage level.

[0101] Specifically, the signal conditioning circuit includes a signal inversion circuit and a signal buffer circuit. The signal inversion circuit is used to inversely expand the 24 PWM pulse signals representing the on / off states of the switching transistors of each SM submodule in the MMC circuit into 48 complementary PWM pulse signals. These signals are then passed through the signal buffer circuit to enhance the driving capability (the main function of the signal buffer circuit is to receive the input signal and output a signal that is the same as or processed from the input signal. When processing PWM signals, the buffer circuit can be used for isolation, amplification, or level conversion. In this embodiment, it is used to convert the complementary PWM pulse signals into the same voltage level to enhance the driving capability). Finally, the 48 complementary PWM pulse signals are output to the three-phase signal distribution board, and then transmitted to the 24 half-bridge submodules, i.e., SM submodules, in the MMC circuit to realize the control of the on / off state of the half-bridge submodules (e.g., as shown in the image). Figure 17The diagram shows the schematic of a submodule. Each submodule has two switching transistors, and only one can be turned on at a time. These 48 complementary PWM pulse signals are randomly distributed to phases A, B, and C via a three-phase signal distribution board. Each submodule occupies two complementary pulse signals, thus enabling on / off switching. Because the MMC circuit needs to acquire 24 submodule capacitor voltage signals, the analog input ports of the dSPACE1202 hardware-in-the-loop controller are insufficient, and the analog inputs consume a large amount of memory. In this embodiment, a DSP28335 is used as the submodule capacitor voltage acquisition and communication processor. The collected submodule capacitor voltage is input to the hardware-in-the-loop controller dSPACE1202 via RS485 communication; the remaining AC side current and bridge arm current are input to the hardware-in-the-loop controller dSPACE1202 as analog signals after passing through sensors and conditioning circuits; the AC side voltage, the three-phase upper and lower bridge arm voltages and the DC bus voltage are input to the hardware-in-the-loop controller dSPACE1202 as analog signals after passing through voltage sensors and conditioning circuits; finally, the processed information in the hardware-in-the-loop controller dSPACE1202 is transmitted to the PWM signal conditioning circuit, thereby controlling the operation of the entire MMC system.

[0102] In a specific embodiment, each of the SM submodules is equipped with a submodule capacitor voltage sensor; an AC voltage sensor is also provided between the rectifier pre-charging device and the inductor element.

[0103] In a specific embodiment, the

[0104] The inductor components include a parallel A-phase inductor, a B-phase inductor, and a C-phase inductor; the MMC circuit also includes several bridge arm inductors L0;

[0105] Furthermore, one end of the A-phase inductor is connected to the upper and lower bridge arm submodules of the A-phase via the bridge arm inductor L0; one end of the B-phase inductor is connected to the upper and lower bridge arm submodules of the B-phase via the bridge arm inductor L0; and one end of the C-phase inductor is connected to the upper and lower bridge arm submodules of the C-phase via the bridge arm inductor L0.

[0106] In a specific embodiment, bridge arm current sensors are provided between the bridge arm inductor L0 and the upper bridge arm submodule of phase A, between the bridge arm inductor L0 and the upper bridge arm submodule of phase B, between the bridge arm inductor L0 and the upper bridge arm submodule of phase C, between the bridge arm inductor L0 and the lower bridge arm submodule of phase A, between the bridge arm inductor L0 and the lower bridge arm submodule of phase B, and between the bridge arm inductor L0 and the lower bridge arm submodule of phase C.

[0107] In a specific embodiment, the design of the main power circuit affects the operating performance and reliability of the MMC system. Therefore, the selection of the three core components—power switching devices, energy storage capacitors, and bridge arm reactors—is particularly critical. The selection of power switching devices requires careful consideration of their voltage and current stress margins and switching characteristics. The capacitance value of the energy storage capacitor must balance voltage ripple suppression with the system's dynamic response performance. The parameter design of the bridge arm inductor must simultaneously meet the dual requirements of circulating current suppression and harmonic attenuation. The parameter optimization and matching design of these three types of components together constitute an important foundation for ensuring the safe and stable operation of the system. Specifically, this embodiment also includes a design selection module.

[0108] The design selection module includes a sub-module switch design module, a sub-module capacitor design module, and a bridge arm inductor design module;

[0109] The submodule switching transistor design module is used to select switching devices whose rated current is greater than the peak current flowing through the submodule switching transistor. In this embodiment, to ensure the stable operation of the MMC rectifier, the nominal voltage of a single submodule is set to 50V. Since transient voltage peaks and other transient phenomena may occur during switching operations, and a single submodule needs to bear the voltage load of the entire bridge arm under fault conditions, a high safety factor is adopted in the design of the switching devices. Based on the comprehensive consideration of the above factors, the breakdown voltage threshold of the device is determined to be 400V, thereby effectively improving the overall reliability of the system. The rated current of the selected switching device should be greater than the peak current flowing through the switching transistor, and the peak current flowing through the power switching transistor in the MMC should be greater than the peak current flowing through the switching transistor. The calculation formula is:

[0110] ,

[0111] In the formula: S represents the known system capacity; Indicates the effective value of the grid-side voltage; Indicates overload rate; Ripple factor; based on peak current The calculation results show that the maximum system current reaches 28.81A. To ensure safe circuit operation, the selected switching elements must have a voltage withstand capability of no less than 400V, and their current carrying capacity must not be less than 28.81A. In practical engineering applications of medium and high voltage MMCs, the switching elements of the modules generally use IGBT devices with excellent voltage and current withstand performance, and their rated voltage is usually set at 1.6kV or 2.4kV. Under rated current conditions, the on-state voltage drop of the IGBT is about 3V, which is less than 0.2% of the rated voltage. This is relevant to the design of small-power prototypes. Due to the requirement that the rated voltage of the submodule be reduced to 50V, the on-state voltage drop of the IGBT under rated current reaches 1.5~2V, accounting for more than 3%, which causes a significant deviation between the working waveform of the MMC and the actual engineering situation. Based on this, the IPW60R037P7 MOSFET was selected as the switching element of the submodule of the MMC experimental platform. This device has a rated voltage of 650V and a rated current of 76A, and its on-state resistance is 37mΩ. When the bridge arm current is 5A, the voltage drop generated is only 0.185V, and the on-state voltage drop ratio is as low as 0.19%, which is more consistent with the actual engineering situation.

[0112] The submodule capacitor design module is used to quantitatively obtain the submodule capacitors. In the modular multilevel converter structure, each submodule is equipped with a parallel DC support capacitor, and the optimized configuration of its capacity parameters plays a decisive role in the system's operating characteristics. If the capacitor capacity is insufficient, it will cause significant voltage fluctuations, leading to output waveform distortion, which in turn affects the system's balanced control performance and may even cause device instability in severe cases. Conversely, while an excessively large capacitor capacity can effectively suppress voltage fluctuations, it will reduce the charging and discharging rate and affect the system's dynamic response capability during sudden load changes. At the same time, the capacitor capacity is positively correlated with its physical size; increasing the capacity not only leads to volume expansion but also significantly increases manufacturing costs. When determining the submodule capacitor parameters, multiple key indicators need to be comprehensively evaluated, including the dynamic response characteristics of power regulation, transient voltage fluctuation range, steady-state voltage fluctuation amplitude, and the limitation of DC bipolar short-circuit current. These technical indicators together constitute the basic basis for capacitor selection, and their specific values ​​can be quantitatively determined through corresponding calculation formulas.

[0113] And obtain the capacitor of the submodule The expression is

[0114] ,

[0115] In the formula: This indicates the power at the input of the rectifier. Indicates the total number of bridge arm submodules; This represents the modulation coefficient of the MMC output voltage; Indicates the rated operating voltage of the submodule capacitor; express The voltage fluctuation range; Indicates the system's operating angular frequency; Indicates the power factor angle;

[0116] The bridge arm inductor design module is used to quantitatively obtain the bridge arm inductance.

[0117] In this embodiment of the MMC structure, in addition to the energy storage capacitor, each phase's upper and lower bridge arms are connected in series with a bridge arm inductor. This inductor plays a crucial buffering role between the submodule and the AC / DC system, primarily in three aspects: First, it effectively alleviates circulating current caused by uneven energy distribution between the upper and lower bridge arms and between phases; second, it significantly limits the bridge arm short-circuit current during a short-circuit fault; and finally, it filters out high-frequency harmonic components from the bridge arm current. The selection of the bridge arm inductor must adhere to several key criteria, including ensuring output power adaptability, maintaining the stability of current tracking performance, and controlling the amplitude of current ripple. Based on these criteria, by analyzing the extreme cases of voltage surges across the bridge arm under transient operating conditions, the fluctuation characteristics of the bridge arm current can be derived, leading to an approximate calculation expression for the bridge arm inductor.

[0118] ,

[0119] ,

[0120] In the formula: Indicates the peak value of the bridge arm current ripple; This indicates the switching frequency of the corresponding MMC; This indicates the peak value of the capacitor voltage in the submodule; Indicates the fundamental component of the bridge arm current; This indicates that the phase current is measured by MMC AC. This represents the DC side current of the MMC; the maximum value of the arm current ripple is generally taken as 20% of the fundamental component of the arm current.

[0121] In a specific embodiment, the signal conditioning circuit of this embodiment is a PWM signal conditioning circuit: as shown in the figure. Figure 12As shown, the signal conditioning circuit includes a power supply, two DB50 signal input interfaces, three DB37 signal output interfaces, and three synchronization signal interfaces. The power supply input is DC 24V, and the outputs are DC 5V 15W and DC 3.3V 6W. The DB50 signal input interfaces connect to the dSPACE1202 hardware-in-the-loop controller and receive PWM pulse signals. After conditioning, the signals are output to the three-phase signal distribution board via the DB37 interface. Additionally, the DB37 interface provides DC 24V power to the sub-modules. The synchronization signal interfaces output a synchronization clock signal to the DSP for communication synchronization. The PWM signal conditioning circuit includes a PWM signal inverting circuit and a PWM signal buffering circuit.

[0122] like Figure 13 The diagram shows the schematic of the PWM signal inverting circuit. The PWM signal inverting circuit uses a 74HC04D chip to invert the PWM signal required by the submodule. The 74HC04D is a commonly used six-channel inverter integrated circuit. In digital circuits, the 74HC04 can be used to perform logical NOT operations on signals to achieve signal inversion. The two switches on the MMC half-bridge submodule, i.e., the SM submodule, can only work normally when they receive two opposite signals simultaneously. The 5-level MMC topology includes three phases, a total of 6 bridge arms, and 24 submodules. Using 6 chips, it can complete the inversion of 36 PWM signals, reserving space for upgrading to a 7-level MMC. The 74HC04D chip is powered by a 3.3V power supply.

[0123] like Figure 14 The diagram shows the schematic of the PWM signal buffer circuit. The circuit uses the CD74HC244M chip to buffer and isolate the PWM signal from the half-bridge submodule's drive circuit. The CD74HC244M is a high-speed CMOS eight-channel positive phase buffer / line driver with tri-state output functionality, widely used in various electronic devices. Similarly, each phase circuit is designed with 12 channels, reserving space for upgrades to 7-level MMC. The CD74HC244M chip uses a 3.3V power supply.

[0124] Signal distribution circuit: such as Figure 15 The diagram shows the signal distribution circuit schematic of a three-phase signal distribution board. The board includes twelve 10-pin JTAG interfaces and one DB37 interface. PWM pulse signals and DC 24V and DC 5V power supplies enter the distribution board through the DB37 interface and are distributed to the corresponding JTAG interface of each sub-module. These sub-modules are then connected to the SM sub-modules via FC cables. Specifically, the sub-module circuit principle in this embodiment is as follows: Figure 16 As shown Figure 18As shown, the PWM signal generated by the hardware-in-the-loop controller dSPACE1202, after inverting and isolating, has a high-level output of 3.3V and a low-level output of 0V. This voltage level cannot directly drive the switching devices, so the PWM signal needs to be amplified to achieve effective control of the switching devices. This submodule uses the UCC21520DW isolated dual-channel gate driver, which has a peak pull-up current of 4A and a peak sink current of 6A, and can effectively drive power MOSFETs, IGBTs, and SiC. The chip utilizes semiconductor devices such as MOSFETs. Regarding isolation characteristics, it separates the input side from the output driver using a 5.7kVRMS enhanced isolation gate, achieving a common-mode transient immunity (CMTI) as low as 125V / ns. Simultaneously, internal functional isolation is employed between the two secondary-side drivers, allowing them to withstand a maximum operating voltage of 1500VDC. Notably, pin 5 of the driver serves as a disable control terminal; when set high, it simultaneously shuts down both output channels, while maintaining an open circuit or grounded state ensures normal device operation. Furthermore, the chip features primary-side logic fault protection, forcing both outputs to a low level in case of an anomaly. This embodiment also employs a dual-power supply scheme, significantly improving the reliability and stability of the switching device's driving process.

[0125] In this embodiment, the design of the hardware-in-the-loop (HIL) controller dSPACE1202 software includes the use of the dSPACE1202 HIL to acquire analog inputs of MMC AC voltage and current, bridge arm current, and DC bus voltage, as well as existing core algorithms such as control algorithms, modulation algorithms, and sub-module voltage equalization sorting (e.g., the control modulation algorithm is dual-pi control and...). The program design includes modulation algorithms and software protection; and the DSP software design includes using two TMS320F28335 ADC modules to collect the capacitor voltage of the three-phase sub-modules, and transmitting the sampled data in parallel to the hardware-in-the-loop controller dSPACE1202 via RS485 communication.

[0126] In this embodiment, the main experimental program design, i.e., the core program flow of the experimental system, is as follows: Figure 20As shown, during system startup, the sub-modules in the main circuit are pre-charged first, and the load is connected only after the charging process is complete. Using a hardware-in-the-loop (HIL) controller dSPACE1202, key parameters such as AC voltage and current, bridge arm current, DC output voltage, and three-phase sub-module capacitor voltage are acquired in real time. Based on the collected data, system status is assessed: when a system anomaly is detected, PWM signal transmission is immediately blocked, and fault information is transmitted to the host computer; if the system is operating normally, a reference voltage signal is generated through a control algorithm. This signal undergoes sector determination and vector optimization processing to calculate the duty cycle of the upper and lower bridge arm sub-modules. Subsequently, the sub-modules to be activated are determined through voltage equalization sorting, and a software interrupt mechanism is used to ensure the synchronization of the three-phase PWM signals, effectively preventing phase deviation. Finally, the PWM signal output module is enabled, signal blocking is lifted, and signal transmission is completed.

[0127] The software protection program design flow in this embodiment is as follows: Figure 21 As shown, the execution flow of the software protection program first detects the grid-side voltage and current, as well as the DC output voltage signal. Figure 19 As shown, when the system does not detect overvoltage or overcurrent, flag 1 is set to 1. Then, the communication data of the submodule capacitor voltage is verified. If the verification value in the communication data matches the preset value, communication is considered normal, and flag 2 is set to 1. The system performs a logical AND operation on Flag 1 and Flag 2. If the result is 1, it indicates that the system is operating normally and PWM signal output is allowed; if the result is 0, it indicates that there is an anomaly in the system. In this case, the PWM signal is blocked, and fault information is sent to the host computer. The flowchart of the DSP communication main program design in this embodiment is as follows: Figure 22 As shown, the master and slave use the same main program; first, the system is initialized, and then the GPIO, ADC and interrupt initialization are completed using known techniques; after initialization, the external interrupt function of GPIO65 is enabled, and the interrupt program is executed waiting for an external signal.

[0128] The DSP communication interrupt subroutine design in this embodiment includes a slave interrupt subroutine and a master interrupt subroutine: the control flowchart of the slave interrupt subroutine is as follows. Figure 23 As shown, upon entering an external interrupt, the system first waits for the rising edge of the external interrupt trigger signal. Upon the rising edge, ADC sampling is performed, and the sampled data is stored in an array. Then, it waits for the falling edge of the external interrupt trigger signal. Upon the falling edge, the data in the array is sent to the host FIFO, triggering the host FIFO interrupt subroutine and returning to the main program. The host interrupt subroutine control flowchart is shown below. Figure 24As shown. Upon entering an external interrupt, first, it waits for the rising edge of the external interrupt trigger signal. After the rising edge arrives, it performs ADC sampling and stores the sampled data in an array. Then, it waits for the falling edge of the external interrupt trigger signal. After the falling edge arrives, it waits for the FOFI interrupt subroutine to be triggered, merges the received data with the host ADC sampling data, and sends it to the host computer. After completion, it returns to the main program. In this embodiment... Figure 25 The experimental results of this invention under a balanced three-phase power grid are shown in Table 1. The parameters of the physical experimental platform built in this embodiment are as follows:

[0129] Table 1. Parameters of the hardware physical experimental platform built in this invention

[0130]

[0131] experiment Figure 25 (a) Demonstrates the experimental results of three-phase current. Figure 25 (b) Display the output voltage of the upper and lower bridge arm submodules of phase A and the output voltage of phase A. Figure 25 (c) and Figure 25 (d) Demonstrates the experimental results from uncontrolled rectification to a stable DC bus voltage, showing that the experimental platform and control method can effectively control the DC voltage, with no voltage overshoot and good voltage steady state during the voltage build-up process.

[0132] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A modular multilevel power conversion device based on master-slave architecture sampling communication, characterized in that, It includes the main power circuit, the control system, and the design selection module. The control system includes a hardware-in-the-loop controller, a signal conditioning circuit, and a signal sampling circuit for isolation protection. The main power circuit controls the switching devices to operate in either rectification or inverter mode; the main power circuit includes at least an autotransformer, a fuse, a rectifier pre-charge device, an MMC circuit, an inverter pre-charge device, and an inductor. The signal sampling circuit is used to sample the main power circuit, acquire the sampled signal and transmit it to the hardware-in-the-loop controller in real time. The sampled signal includes at least the DC voltage output by the rectifier mode circuit, the AC voltage output by the inverter mode circuit, the AC current output by the inverter mode circuit, the bridge arm current in the MMC circuit, the DC bus voltage, and the capacitor voltage of the SM submodule acquired and transmitted through the master-slave communication module belonging to the control system. The hardware-in-the-loop (HIL) controller is used to obtain the on / off status of the switching transistors of each SM submodule in the MMC circuit based on the acquired sampling signal using the Simulink control algorithm, and then obtain the corresponding PWM drive pulse signal. The signal conditioning circuit is used to process the received PWM pulse signal and output the conditioned PWM signal to the three-phase signal distribution board; and enables the three-phase signal distribution board to distribute the conditioned PWM signal to the switching transistor drive circuit of the corresponding sub-module of each phase of the MMC according to the preset phase configuration, so as to realize the phase control of the MMC circuit; the signal conditioning process includes at least reverse spread and signal modulation. The signal conditioning circuit includes a signal inverting circuit and a signal buffering circuit connected in sequence. The signal inversion circuit is used to invert and extend the corresponding PWM pulse signals of the switching transistors of each SM submodule in the MMC circuit, that is, to obtain complementary PWM pulse signals by performing a logic NOT operation. The signal buffer circuit is used to perform signal modulation on the complementary PWM pulse signals and convert them into the same voltage level; The design selection module includes a sub-module switch design module, a sub-module capacitor design module, and a bridge arm inductor design module; The submodule switch design module is used to form a switching device with a rated current greater than the peak current flowing through the submodule switch, and the peak current of the submodule switch... The formula for obtaining it is In the formula: S represents the known system capacity; Indicates the effective value of the grid-side voltage; Indicates overload rate; Indicates the ripple factor; The submodule capacitor design module is used to quantitatively obtain the submodule capacitor. ; And obtain the capacitor of the submodule The expression is In the formula: This indicates the power at the input of the rectifier. Indicates the total number of bridge arm submodules; This represents the modulation coefficient of the MMC output voltage; Indicates the rated operating voltage of the submodule capacitor; express The voltage fluctuation range; Indicates the system's operating angular frequency; Indicates the power factor angle; The bridge arm inductance design module is used to quantitatively obtain the bridge arm inductance. ; And obtain the bridge arm inductance The expression is In the formula: Indicates the peak value of the bridge arm current ripple; This indicates the switching frequency of the corresponding MMC; This indicates the peak value of the capacitor voltage in the submodule; Indicates the fundamental component of the bridge arm current; This indicates the phase current on the AC side of the MMC; This indicates the DC side current of the MMC.

2. The modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 1, characterized in that, The master-slave communication module includes a slave module for acquiring the capacitor voltage of the SM sub-module corresponding to the C-phase wire, and a master module for acquiring the capacitor voltage of the SM sub-module corresponding to the A / B phase wire. The slave module is communicatively connected to the master module to send the C-phase sub-module capacitor voltage acquired by the slave module to the master module. The master module is also used to package the C-phase sub-module capacitor voltage and the A / B phase sub-module capacitor voltage together after receiving the C-phase sub-module capacitor voltage sent by the slave module and upload them to the hardware-in-the-loop controller.

3. The modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 1, characterized in that, One end of the autotransformer is connected to the grid output terminal of the preset input three-phase power grid; The other end of the autotransformer is connected to one end of a fuse. The other end of the fuse is connected to one end of a rectifier pre-charging device via relay switches KM1 and KM6 connected in sequence. The other end of the rectifier pre-charging device is connected to one end of an inductor. One end of the inductor is connected to one end of the upper bridge arm module and one end of the lower bridge arm module of the MMC circuit, which are symmetrically arranged. Furthermore, the upper arm module is provided with three sets of parallel upper arm sub-modules, including the A-phase upper arm sub-module, the B-phase upper arm sub-module, and the C-phase upper arm sub-module. The lower bridge arm module is provided with three sets of parallel lower bridge arm sub-modules, including the A-phase lower bridge arm sub-module, the B-phase lower bridge arm module and the C-phase lower bridge arm module. The upper bridge arm submodule and the lower bridge arm submodule are provided with several SM submodules connected in sequence; Furthermore, the other end of each upper bridge arm submodule is connected to one end of the first resistor R3, one end of the second resistor R4, one end of the DC voltage sensor PT4, and one end of the relay switch KM4; the other end of the relay switch KM4 is connected to one end of the load capacitor C and one end of the relay switch KM11. The other end of each lower bridge arm submodule is connected to the other end of the first resistor R3, the other end of the second resistor R4, the other end of the DC voltage sensor PT4, and the other end of the load capacitor C, and the connection point is used as a common contact. One end of relay switch KM1 is connected to one end of relay switch KM2, and the other end of relay switch KM2 is connected to the input terminal of the three-phase uncontrolled rectifier module. The output pin 1 of the three-phase uncontrolled rectifier module is connected to one end of the inverter pre-charge device, and the other end of the inverter pre-charge device is connected to one end of relay switch KM10. The other end of relay switch KM10 is connected to one end of relay switch KM11. An AC current sensor is provided between the rectifier pre-charging device and the inductor element, and one end of the AC current sensor is connected to one end of the relay switch KM5, while the other end of the relay switch KM5 is connected to the inverter voltage output module used to obtain the output AC power.

4. A modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 3, characterized in that, Each of the SM submodules is equipped with a submodule capacitor voltage sensor.

5. A modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 4, characterized in that, The inductor includes a parallel A-phase inductor, a B-phase inductor, and a C-phase inductor; the MMC circuit also includes several bridge arm inductors L0; Furthermore, one end of the A-phase inductor is connected to the upper and lower bridge arm submodules of the A-phase via the bridge arm inductor L0; one end of the B-phase inductor is connected to the upper and lower bridge arm submodules of the B-phase via the bridge arm inductor L0; and one end of the C-phase inductor is connected to the upper and lower bridge arm submodules of the C-phase via the bridge arm inductor L0.

6. A modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 5, characterized in that, Bridge arm current sensors are provided between the bridge arm inductor L0 and the upper bridge arm submodule of phase A, between the bridge arm inductor L0 and the upper bridge arm submodule of phase B, between the bridge arm inductor L0 and the upper bridge arm submodule of phase C, between the bridge arm inductor L0 and the lower bridge arm submodule of phase A, between the bridge arm inductor L0 and the lower bridge arm submodule of phase B, and between the bridge arm inductor L0 and the lower bridge arm submodule of phase C.

7. A modular multilevel power conversion device based on master-slave architecture sampling communication according to claim 6, characterized in that, The signal sampling circuit includes a sub-module capacitor voltage sampling circuit, a DC voltage sampling circuit, an AC voltage sampling circuit, and an AC current sampling circuit. The submodule capacitor voltage sampling circuit is used to collect the SM submodule capacitor voltage obtained by the submodule capacitor voltage sensor through the master-slave communication module; The AC voltage sampling circuit is used to acquire the AC voltage output from the inverter mode circuit or the AC voltage input from the rectifier mode circuit obtained by the AC voltage sensor. The DC voltage sampling circuit is used to acquire the DC bus voltage obtained by the DC voltage sensor; The AC current sampling circuit is used to acquire the bridge arm current in the MMC circuit obtained by the bridge arm current sensor.

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