Amplifier, integrated circuit, chip, and electronic device
By splitting the input differential pair transistors and adjusting the current mirror ratio, the stability and bandwidth performance issues of the folded cascode amplifier were resolved, resulting in a reduction in chip area and an increase in conversion rate.
Patent Information
- Application Number
- CN202510732790.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-03
- Publication Date
- 2025-10-31
AI Technical Summary
The stability and bandwidth performance of existing folded cascode amplifiers need to be improved, and Miller compensation technology slows down the slew rate of operational amplifiers while increasing chip area.
The input differential pair of the traditional folded cascode amplifier is split into symmetrical first and second input differential units, and the load current transistors are combined into a current mirror. The current of the compensation capacitor is adjusted by adjusting the mirror ratio of the current mirror, thereby reducing the size of the compensation capacitor.
While maintaining the Miller capacitance compensation function, the size of the compensation capacitor was reduced, the chip area was reduced, and the conversion rate of the operational amplifier was accelerated.
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Figure CN120880346A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of amplifier technology, specifically to an amplifier, integrated circuit, chip, and electronic device. Background Technology
[0002] Advances in CMOS technology have greatly propelled the continuous development of mobile and portable electronic devices. This is thanks to the high integration of analog and digital circuits. In analog circuits, transconductance amplifiers are a crucial component, often occupying the largest area and consuming the most power in many applications. To a certain extent, the performance of the transconductance amplifier determines the performance of the entire analog circuit. Folded cascode amplifiers are widely used in analog circuits due to their low power consumption. A folded cascode amplifier typically consists of a tail current source, an input differential pair of transistors, two sets of cascode amplifier transistors, and a current mirror. However, the stability and bandwidth performance of folded cascode amplifiers need improvement. Miller compensation is a commonly used circuit design technique to enhance the stability and bandwidth of amplifiers. By cleverly introducing an additional capacitor, the dominant pole of the amplifier is shifted to a lower frequency, while the non-dominant poles are shifted to a higher frequency, thus achieving pole separation. This reduces or even eliminates the impact of zeros on system stability and improves phase margin, making the amplifier more stable. Miller compensation technology, widely used in the electronics field, is crucial for improving amplifier performance.
[0003] In a two-stage operational amplifier, the Miller capacitor is usually located between the first-stage output and the second-stage output. If the load capacitance is large, the value of the Miller capacitor often needs to be large in order to achieve better compensation and improve the phase margin. With the increase in capacitance, the chip area also has to be increased, and the slew rate of the operational amplifier will also be slowed down because the Miller capacitor needs to be charged and discharged. Summary of the Invention
[0004] To address the aforementioned technical problems, this application provides an amplifier, integrated circuit, chip, and electronic device.
[0005] According to one aspect of the present invention, an amplifier is provided, comprising: a first input differential unit, the control terminal of which receives a positive input voltage; a second input differential unit, the control terminal of which receives a negative input voltage; a folded cascode unit, including a first current mirror and a second current mirror connected to the first input differential unit, a third current mirror and a fourth current mirror connected to the second input differential unit, a first output transistor connected to the first current mirror, and a second output transistor connected to the fourth current mirror; an output current mirror, the first node of which has its current replication branch connected to the second output transistor being a first output terminal; an output unit connected to the first output terminal, including an upper driving transistor and a lower driving transistor, the second node of which is connected to the upper driving transistor and the lower driving transistor being a second output terminal; and a compensation unit, including a first compensation capacitor connected between the fourth current mirror and the second output terminal and a second compensation capacitor connected between the second current mirror and the second output terminal.
[0006] Optionally, the amplifier further includes a bias circuit that receives a bias voltage to output a bias current. The bias circuit includes a tail current source, the input terminal of which receives the supply voltage, the control terminal of which receives the bias voltage, and the output terminal of which is connected to the input terminal of the first input differential unit and the input terminal of the second input differential unit.
[0007] Optionally, the first input differential unit includes a first positive input transistor, a second positive input transistor, and a third positive input transistor connected in parallel. The sources of the first positive input transistor to the third positive input transistor are all connected to a bias circuit. The gates of the first positive input transistor to the third positive input transistor are connected and serve as the non-inverting input terminal of the amplifier, receiving the positive input voltage. The second input differential unit includes a first negative input transistor, a second negative input transistor, and a third negative input transistor connected in parallel. The sources of the first negative input transistor to the third negative input transistor are all connected to a bias circuit. The gates of the first negative input transistor to the third negative input transistor are connected and serve as the inverting input terminal of the amplifier, receiving the negative input voltage.
[0008] Optionally, the size ratio of the first positive input transistor to the third positive input transistor is the same as the size ratio of the first negative input transistor to the third negative input transistor.
[0009] Optionally, the first current mirror includes a first load current transistor, the first output transistor and the first load current transistor form a first group of common source and common gate transistors, and the common node of the first output transistor and the first load current transistor is connected to the drain of the first positive input transistor; the fourth current mirror includes a second load current transistor, the second output transistor and the second load current transistor form a second group of common source and common gate transistors, and the common node of the second output transistor and the second load current transistor is connected to the drain of the first negative input transistor.
[0010] Optionally, the first current mirror further includes a first transistor and a first enhancement transistor. The gate of the first load current transistor is connected to the gate of the first transistor. The source of the first load current transistor and the source of the first transistor are grounded together. The drain of the first transistor is connected to the source of the first enhancement transistor. The drain of the first enhancement transistor is connected to the gate of the first transistor and the drain of the third negative input transistor. The gate of the first enhancement transistor receives a control voltage. The second current mirror includes a second transistor, a second enhancement transistor, a third transistor, and a third enhancement transistor. The gate of the second transistor is connected to the gate of the third transistor. The source of the second transistor and the source of the third transistor are grounded together. The drain of the second transistor is connected to the source of the second enhancement transistor. The drain of the second enhancement transistor is connected to the gate of the second transistor and the drain of the second positive input transistor. The drain of the third transistor is connected to the source of the third enhancement transistor. The drain of the third enhancement transistor is connected to the drain of the third negative input transistor. The gate of the second enhancement transistor and the gate of the third enhancement transistor are connected and receive the control voltage. The fourth current mirror further includes a fourth transistor and a fourth enhancement transistor. The gate of the second load current transistor is connected to the gate of the fourth transistor. The source of the second load current transistor and the source of the fourth transistor are grounded together. The drain of the fourth transistor is connected to the source of the fourth enhancement transistor. The drain of the fourth enhancement transistor is connected to the gate of the fourth transistor and the drain of the third positive input transistor. The gate of the fourth enhancement transistor receives the control voltage. The third current mirror includes a fifth transistor, a fifth enhancement transistor, a sixth transistor, and a sixth enhancement transistor. The gate of the fifth transistor is connected to the gate of the sixth transistor. The source of the fifth transistor and the source of the sixth transistor are grounded together. The drain of the fifth transistor is connected to the source of the fifth enhancement transistor. The drain of the fifth enhancement transistor is connected to the gate of the fifth transistor and the drain of the second negative input transistor. The drain of the sixth transistor is connected to the source of the sixth enhancement transistor. The drain of the sixth enhancement transistor is connected to the drain of the third positive input transistor. The gate of the fifth enhancement transistor and the gate of the sixth enhancement transistor are connected and receive the control voltage.
[0011] Optionally, the mirror ratio of the first current mirror is 1:N, where N is greater than 1; the mirror ratio of the second current mirror is 1:K, where K is greater than 1; and the mirror ratio of the fourth current mirror is 1:M, where M is greater than 1.
[0012] Optionally, the output current mirror includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is connected to the gate of the eighth transistor. The source of the seventh transistor and the source of the eighth transistor share the same supply voltage. The drain of the seventh transistor is connected to the drain of the first output transistor. The drain of the eighth transistor is connected to the drain of the second output transistor. The gate of the seventh transistor is also connected to the drain of the seventh transistor. The gates of the first output transistor and the second output transistor are connected and receive a control voltage. The connection node between the second output transistor and the eighth transistor is the first node.
[0013] Optionally, the gate of the upper driving transistor and the gate of the lower driving transistor are both connected to the first node, the source of the upper driving transistor receives the supply voltage, the source of the lower driving transistor is grounded, and the common node of the drain of the upper driving transistor and the drain of the lower driving transistor is the second node, from which the output voltage is provided.
[0014] Optionally, the first positive input transistor to the third positive input transistor are all PMOS transistors, and the first negative input transistor to the third negative input transistor are all PMOS transistors, the transistors included in the first current mirror to the fourth current mirror are all NMOS transistors, the seventh transistor and the eighth transistor included in the output current mirror are both PMOS transistors, the first output transistor and the second output transistor are both NMOS transistors, the upper driving transistor is a PMOS transistor, and the lower driving transistor is an NMOS transistor.
[0015] According to another aspect of the present invention, an integrated circuit is provided, comprising the amplifier described above, which amplifies an input differential signal and outputs an output voltage.
[0016] According to another aspect of the present invention, a chip is provided, comprising the amplifier described above, which amplifies an input differential signal and outputs an output voltage.
[0017] According to another aspect of the present invention, an electronic device is provided, comprising the amplifier described above, which amplifies an input differential signal and outputs an output voltage.
[0018] The beneficial effects of this application include at least the following:
[0019] This application provides an amplifier, integrated circuit, chip, and electronic device. The traditional folded cascode amplifier's input differential pair is split into a symmetrical first input differential unit and a second input differential unit. Each input differential unit includes multiple parallel transistors. Two load current transistors connected to the input differential pair form current mirrors, and the two input differential units are connected to a total of four current mirrors. The first node between the output current mirror and the second output transistor is the first output terminal, while the output unit connected to the first node provides the second output terminal, forming a negative feedback loop. A first compensation capacitor is connected between the fourth current mirror and the second output terminal, while a second compensation capacitor is connected between the second current mirror and the second output terminal. In this circuit structure, the first compensation capacitor is connected to the first output terminal through the fourth current mirror, and the second compensation capacitor is connected to the first output terminal through the second and first current mirrors. By adjusting the mirror ratio of the four current mirrors, the current flowing through the compensation capacitors can be adjusted. Thus, while maintaining the Miller capacitance compensation function, a reasonable mirror ratio can be designed to increase the current of the compensation capacitor, reduce its size, and consequently reduce the chip area, thereby accelerating the operational amplifier's conversion rate.
[0020] Furthermore, the mirror ratios of the fourth current mirror, the second current mirror, and the first current mirror are set to 1:M, 1:K, and 1:N, respectively, with M, K, and N all greater than 1. This results in the current flowing through the first compensation capacitor being approximately increased by a factor of M, and the current flowing through the second compensation capacitor being approximately increased by a factor of K×N. Depending on the values of M, K, and N, the compensation capacitors can be reduced by different factors, thereby reducing the chip area and accelerating the operational amplifier's conversion rate.
[0021] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit this application. Attached Figure Description
[0022] Figure 1 A circuit diagram of a folded common-source cascode amplifier in the prior art is shown;
[0023] Figure 2 A circuit diagram of an amplifier according to an embodiment of the present invention is shown. Detailed Implementation
[0024] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in different forms and is not limited to the embodiments described herein.
[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means two or more.
[0026] In addition, the same reference numerals in the figures indicate the same or similar structures, so repeated descriptions of them will be omitted. That is, the various parts in this specification are described in a combination of parallel and progressive manner. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referred to each other.
[0027] Figure 1 A circuit diagram of a folded cascode amplifier in the prior art is shown.
[0028] like Figure 1 As shown, the folded cascode amplifier 100 mainly includes a bias circuit 110, an input differential pair transistor 120, a folded cascode circuit 130, an output current mirror 140, an output unit 150, and a Miller compensation unit 160. The bias circuit 110 receives the bias voltage Vbp1 and converts it into a bias current Iss. The bias circuit 110 includes, for example, a tail current source, which typically includes a transistor. In this embodiment, the tail current source includes transistor M0, which is a PMOS transistor. The source of transistor M0 receives the supply voltage VDD, the gate receives the bias voltage Vbp1, and the drain serves as the output terminal, outputting the bias current Iss. The input differential pair transistor 120 is connected to the output terminal of the bias circuit 110 and includes transistors M1 and M2. Transistors M1 and M2 are used to shunt the bias current Iss. Furthermore, the gate of transistor M1 is used to receive the positive input voltage Vin+, and the gate of transistor M2 is used to receive the negative input voltage Vin-. Transistor M1 serves as the positive input terminal of the amplifier, and transistor M2 serves as the negative input terminal of the amplifier. Transistors M1 and M2 are, for example, PMOS transistors, and the sources of transistors M1 and M2 are both connected to the output terminal of the bias circuit 110.
[0029] The folded cascode circuit 130 includes two sets of cascode transistors. One set consists of a first output transistor M5 connected in series with a first-side load current transistor M3. The common node of the first output transistor M5 and the first-side load current transistor M3 is connected to the drain of transistor M1. The other set consists of a second output transistor M6 and a second-side load current transistor M4. The common node of the second output transistor M6 and the second-side load current transistor M4 is connected to the drain of transistor M2. Specifically, the drain of the first-side load current transistor M3 is connected to the drain of transistor M1 and the source of the first output transistor M5. The drain of the second-side load current transistor M4 is connected to the drain of transistor M2 and the source of the second output transistor M6. The sources of both the first-side load current transistor M3 and the second-side load current transistor M4 are grounded to GND. The gates of the first-side load current transistor M3 and the second-side load current transistor M4 are connected and receive a control voltage Vbn1. The gates of the first output transistor M5 and the second output transistor M6 are connected and receive a control voltage Vbn2. The load current transistor M3 on the first side, the load current transistor M4 on the second side, the first output transistor M5, and the second output transistor M6 are all, for example, NMOS transistors.
[0030] The output current mirror 140 includes a seventh transistor M7 and an eighth transistor M8. The gate of the seventh transistor M7 is connected to the gate of the eighth transistor M8, and the source of the seventh transistor M7 and the source of the eighth transistor M8 share the supply voltage VDD. The drain of the seventh transistor M7 is connected to the drain of the first output transistor M5, and the drain of the eighth transistor M8 is connected to the drain of the second output transistor M6. The gate of the seventh transistor M7 is also connected to its drain. Both the seventh transistor M7 and the eighth transistor M8 are, for example, PMOS transistors. The connection node between the second output transistor M6 and the eighth transistor M8 is the first node A, providing the first-stage output Vom. The output unit 150 is generally a push-pull circuit, including an upper driving transistor M9 and a lower driving transistor M10. The gate of the upper driving transistor M9 and the gate of the lower driving transistor M10 are connected to node C, and the first node A is connected through node C. The source of the upper driving transistor M9 receives the supply voltage VDD, and the source of the lower driving transistor M10 is grounded (the ground voltage is GND). The common node of the drains of the upper driving transistor M9 and the drains of the lower driving transistor M10 is the second node B. The output voltage Vout is provided from the second node B, which serves as the output terminal of the amplifier.
[0031] The Miller compensation unit 160 includes Miller compensation capacitors Cm1 and Cm2, both of which are connected between the first node A and the second node B to improve the phase margin and stabilize the amplifier performance. However, in Figure 1In the amplifier circuit architecture shown, if the load capacitance connected to the output terminal is large, a further increase in phase margin is needed to achieve better compensation. Therefore, the capacitance values of the two Miller compensation capacitors often need to be very large. With the increase in capacitance, the chip area inevitably increases, and the amplifier's slew rate also slows down due to the need to charge and discharge the Miller compensation capacitors. Therefore, to reduce the chip area while maintaining Miller compensation functionality, this invention proposes another folded cascode amplifier, detailed in [link to details]. Figure 2 .
[0032] Figure 2 A circuit diagram of an amplifier according to an embodiment of the present invention is shown.
[0033] like Figure 2 As shown, the amplifier 200 in this embodiment is a folded cascode amplifier, including a bias circuit 110, a first input differential unit 221, a second input differential unit 222, a folded cascode unit 230, an output current mirror 140, an output unit 150, and a compensation unit 260. The bias circuit 110, the output current mirror 140, and the output unit 150 are all connected to... Figure 1 The descriptions in the embodiments are consistent and will not be repeated here. In this embodiment, Figure 1 Transistor M1 is replaced with the first input differential unit 221, and transistor M2 is replaced with the second input differential unit 222. Correspondingly, the load current transistor M3 on the first side is replaced with the first load current transistor M3b, and the load current transistor M4 on the second side is replaced with the second load current transistor M4b. The first output transistor M5 and the second output transistor M6 are also... Figure 1 The implementation methods are the same, so they will not be repeated here.
[0034] Furthermore, the first input differential unit 221 serves as the non-inverting input terminal of the amplifier, receiving the positive input voltage Vin+. The first input differential unit 221 includes a first positive input transistor M1a, a second positive input transistor M1b, and a third positive input transistor M1c connected in parallel. The sources of the first positive input transistor M1a to the third positive input transistor M1c are all connected to the output terminal of the bias circuit 110, and their gates are connected together to serve as the non-inverting input terminal, receiving the common positive input voltage Vin+. The first positive input transistor M1a to the third positive input transistor M1c are, for example, PMOS transistors. The second input differential unit 222 serves as the inverting input terminal of the amplifier, receiving the negative input voltage Vin-. The second input differential unit 222 includes a first negative input transistor M2a, a second negative input transistor M2b, and a third negative input transistor M2c connected in parallel. The sources of all three transistors (M2a to M2c) are connected to the output terminal of the bias circuit 110, and their gates, when connected, serve as the inverting input terminal, receiving the negative input voltage Vin-. For example, all three transistors (M2a to M2c) are PMOS transistors.
[0035] In this embodiment, the size ratio of the first positive input transistor M1a to the third positive input transistor M1c is the same as the size ratio of the first negative input transistor M2a to the third negative input transistor M2c, and different size ratios can be set according to actual circuit requirements.
[0036] The folded cascode unit 230 of this embodiment includes a first group of cascode transistors and a second group of cascode transistors, as well as a first current mirror 231, a second current mirror 232, a third current mirror 233, and a fourth current mirror 234. The first group of cascode transistors includes a first output transistor M5 and a first load current transistor M3b connected in series, with the common node of the first output transistor M5 and the first load current transistor M3b connected to the drain of the first positive input transistor M1a. The second group of cascode transistors includes a second output transistor M6 and a second load current transistor M4b connected in series, with the common node of the second output transistor M6 and the second load current transistor M4b connected to the drain of the first negative input transistor M2a. The first current mirror 231 multiplexes the first load current transistor M3b, and the fourth current mirror 234 multiplexes the second load current transistor M4b.
[0037] Specifically, the first current mirror 231 includes a first load current transistor M3b, a first transistor M3a, and a first enhancement transistor M3e. The gate of the first load current transistor M3b is connected to the gate of the first transistor M3a. The source of the first load current transistor M3b and the source of the first transistor M3a are grounded to GND. The drain of the first transistor M3a is connected to the source of the first enhancement transistor M3e. The drain of the first enhancement transistor M3e is connected to the gate of the first transistor M3a and the drain of the third negative input transistor M2c. The gate of the first enhancement transistor M3e receives the control voltage Vbn. The second current mirror 232 includes a second transistor M3c, a second enhancement transistor M3f, a third transistor M3d, and a third enhancement transistor M3g. The gate of the second transistor M3c is connected to the gate of the third transistor M3d. The source of the second transistor M3c and the source of the third transistor M3d are grounded together. The drain of the second transistor M3c is connected to the source of the second enhancement transistor M3f. The drain of the second enhancement transistor M3f is connected to the gate of the second transistor M3c and the drain of the second positive input transistor M1b. The drain of the third transistor M3d is connected to the source of the third enhancement transistor M3g. The drain of the third enhancement transistor M3g is connected to the drain of the third negative input transistor M2c. The gates of the second enhancement transistor M3f and the third enhancement transistor M3g are connected and receive a control voltage Vbn. The fourth current mirror 234 includes a second load current transistor M4b, a fourth transistor M4a, and a fourth enhancement transistor M4e. The gate of the second load current transistor M4b is connected to the gate of the fourth transistor M4a. The source of the second load current transistor M4b and the source of the fourth transistor M4a are grounded together. The drain of the fourth transistor M4a is connected to the source of the fourth enhancement transistor M4e. The drain of the fourth enhancement transistor M4e is connected to the gate of the fourth transistor M4a and the drain of the third positive input transistor M1c. The gate of the fourth enhancement transistor M4e receives the control voltage Vbn. The third current mirror 233 includes a fifth transistor M4c, a fifth enhancement transistor M4f, a sixth transistor M4d, and a sixth enhancement transistor M4g. The gate of the fifth transistor M4c is connected to the gate of the sixth transistor M4d. The sources of the fifth transistor M4c and the sixth transistor M4d are grounded together. The drain of the fifth transistor M4c is connected to the source of the fifth enhancement transistor M4f. The drain of the fifth enhancement transistor M4f is connected to the gate of the fifth transistor M4c and the drain of the second negative input transistor M2b. The drain of the sixth transistor M4d is connected to the source of the sixth enhancement transistor M4g. The drain of the sixth enhancement transistor M4g is connected to the drain of the third positive input transistor M1c. The gates of the fifth enhancement transistor M4f and the sixth enhancement transistor M4g are connected and receive a control voltage Vbn. All transistors included in the first current mirror 231 to the fourth current mirror 234 are, for example, NMOS transistors.
[0038] The compensation unit 260 includes a first compensation capacitor Cm3 connected between the fourth current mirror 234 and the second output terminal, and a second compensation capacitor Cm4 connected between the second current mirror 232 and the second output terminal. Specifically, the first end of the first compensation capacitor Cm3 is connected to the gate of the second load current transistor M4b, and the second end is connected to the second node B. The first end of the second compensation capacitor Cm4 is connected to the gate of the third transistor M3d, and the second end is connected to the second node B. Both the first compensation capacitor Cm3 and the second compensation capacitor Cm4 are Miller compensation capacitors. Therefore, the first end of the first compensation capacitor Cm3 can be approximately connected to the first node A through the fourth current mirror 234 and the second output transistor M6, that is, the first compensation capacitor Cm3 is approximately connected between the first node A and the second node B. Similarly, the first end of the second compensation capacitor Cm4 can be approximately connected to the first node A through the second current mirror 232, the first current mirror 231, the first output transistor M5, the output current mirror 140, and the second output transistor M6. That is, the second compensation capacitor Cm4 is approximately connected between the first node A and the second node B, and the Miller compensation function is not affected.
[0039] In this embodiment, the mirror ratio of the first current mirror 231 is 1:N, the mirror ratio of the second current mirror 232 is 1:K, and the mirror ratio of the fourth current mirror 234 is 1:M, where M, N, and K are all greater than 1. Therefore, all three current mirrors can increase the current in the current replication branch. For the first compensation capacitor Cm3, the current flowing through it is amplified by a factor of M after passing through the fourth current mirror 234, effectively increasing the capacitance of the first compensation capacitor Cm3 by a factor of M. Therefore, while maintaining the same compensation effect, the first compensation capacitor Cm3 can be reduced to... Figure 1 The circuit structure is 1 / M. Similarly, the current flowing through the second compensation capacitor Cm4 is first amplified by a factor of K through the second current mirror 232, and then amplified by a factor of N after passing through the first current mirror 231. This is equivalent to the capacitance value of the second compensation capacitor Cm4 being reduced to 1 / K*N of its original value. Depending on the values of M, K, and N, the Miller compensation capacitor can be reduced by different factors, thereby reducing the chip area and accelerating the operational amplifier's conversion rate.
[0040] In summary, for Figure 2 The folded cascode amplifier shown can flexibly adjust the values of K, M, and N according to the actual circuit requirements, thereby changing the current flowing through the two Miller compensation capacitors. Moreover, with a reasonable proportional design, while maintaining the Miller compensation function, the capacitance value of the Miller compensation capacitors can be reduced by a factor of two, and the chip area can be reduced by a factor of two, thereby improving the amplifier's slew rate.
[0041] In addition, the present invention also provides an integrated circuit, which can be an analog circuit and may include the folded cascode amplifier mentioned in the above embodiments. The folded cascode amplifier amplifies the input differential signal and outputs an output voltage.
[0042] Furthermore, the present invention also provides a chip, the electronic device may include analog circuitry, the analog circuitry including the above-described folded common-source common-gate amplifier.
[0043] Furthermore, the present invention also provides an electronic device that may include the aforementioned integrated circuit, wherein the integrated circuit includes the aforementioned folded cascode amplifier.
[0044] The amplifier and integrated circuits, chips, and electronic devices using it in this invention split the input differential pair of a traditional folded cascode amplifier into symmetrical first and second input differential units. Each input differential unit includes multiple parallel transistors. Two load current transistors connected to the input differential pair form current mirrors, and the two input differential units are connected to a total of four current mirrors. The first node between the output current mirror and the second output transistor is the first output terminal, while the output unit connected to the first node provides the second output terminal, forming negative feedback in the overall circuit. A first compensation capacitor is then connected between the fourth current mirror and the second output terminal, while a second compensation capacitor is connected between the second current mirror and the second output terminal. In this circuit structure, the first compensation capacitor is connected to the first output terminal through the fourth current mirror, and the second compensation capacitor is connected to the first output terminal through the second and first current mirrors. By adjusting the mirror ratio of the four current mirrors, the current flowing through the compensation capacitors can be adjusted. Thus, while maintaining the Miller capacitance compensation function, a reasonable mirror ratio can be designed to increase the current of the compensation capacitor, reduce the size of the compensation capacitor, thereby reducing the chip area and accelerating the operational amplifier's conversion rate.
[0045] Finally, it should be noted that the above embodiments are merely examples for clearly illustrating this application and are not intended to limit the implementation. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. An amplifier, comprising: The first input differential unit receives the positive input voltage at its control terminal; The second input differential unit receives the negative input voltage at its control terminal; The folded cascode cell includes a first current mirror and a second current mirror connected to the first input differential cell, a third current mirror and a fourth current mirror connected to the second input differential cell, a first output transistor connected to the first current mirror, and a second output transistor connected to the fourth current mirror. The output current mirror has a first output terminal where its current replication branch is connected to the first node of the second output transistor. The output unit, connected to the first output terminal, includes an upper driving transistor and a lower driving transistor, and the second node connecting the upper driving transistor and the lower driving transistor is the second output terminal; as well as The compensation unit includes a first compensation capacitor connected between the fourth current mirror and the second output terminal, and a second compensation capacitor connected between the second current mirror and the second output terminal.
2. The amplifier according to claim 1, further comprising: A bias circuit receives a bias voltage and outputs a bias current. The bias circuit includes a tail current source. The input terminal of the tail current source receives the supply voltage, the control terminal receives the bias voltage, and the output terminal is connected to the input terminal of the first input differential unit and the input terminal of the second input differential unit.
3. The amplifier according to claim 1, wherein, The first input differential unit includes a first positive input transistor, a second positive input transistor, and a third positive input transistor connected in parallel. The sources of the first positive input transistor and the third positive input transistor are all connected to a bias circuit. The gates of the first positive input transistor and the third positive input transistor are connected and serve as the non-inverting input terminal of the amplifier to receive the positive input voltage. The second input differential unit includes a first negative input transistor, a second negative input transistor, and a third negative input transistor connected in parallel. The sources of the first negative input transistor to the third negative input transistor are all connected to a bias circuit. The gates of the first negative input transistor to the third negative input transistor are connected and serve as the inverting input terminal of the amplifier to receive the negative input voltage.
4. The amplifier according to claim 3, wherein, The size ratio of the first positive input transistor to the third positive input transistor is the same as the size ratio of the first negative input transistor to the third negative input transistor.
5. The amplifier according to claim 3, wherein, The first current mirror includes a first load current transistor, the first output transistor and the first load current transistor form a first group of common source and common gate transistors, and the common node of the first output transistor and the first load current transistor is connected to the drain of the first positive input transistor. The fourth current mirror includes a second load current transistor, the second output transistor and the second load current transistor form a second set of common source and common gate transistors, and the common node of the second output transistor and the second load current transistor is connected to the drain of the first negative input transistor.
6. The amplifier according to claim 5, wherein, The first current mirror further includes a first transistor and a first enhancement transistor. The gate of the first load current transistor is connected to the gate of the first transistor. The source of the first load current transistor and the source of the first transistor are grounded together. The drain of the first transistor is connected to the source of the first enhancement transistor. The drain of the first enhancement transistor is connected to the gate of the first transistor and the drain of the third negative input transistor. The gate of the first enhancement transistor receives a control voltage. The second current mirror includes a second transistor, a second enhancement transistor, a third transistor, and a third enhancement transistor. The gate of the second transistor is connected to the gate of the third transistor. The source of the second transistor and the source of the third transistor are grounded together. The drain of the second transistor is connected to the source of the second enhancement transistor. The drain of the second enhancement transistor is connected to the gate of the second transistor and the drain of the second positive input transistor. The drain of the third transistor is connected to the source of the third enhancement transistor. The drain of the third enhancement transistor is connected to the drain of the third negative input transistor. The gate of the second enhancement transistor and the gate of the third enhancement transistor are connected and receive the control voltage. The fourth current mirror further includes a fourth transistor and a fourth enhancement transistor. The gate of the second load current transistor is connected to the gate of the fourth transistor. The source of the second load current transistor and the source of the fourth transistor are grounded together. The drain of the fourth transistor is connected to the source of the fourth enhancement transistor. The drain of the fourth enhancement transistor is connected to the gate of the fourth transistor and the drain of the third positive input transistor. The gate of the fourth enhancement transistor receives the control voltage. The third current mirror includes a fifth transistor, a fifth enhancement transistor, a sixth transistor, and a sixth enhancement transistor. The gate of the fifth transistor is connected to the gate of the sixth transistor. The source of the fifth transistor and the source of the sixth transistor are grounded together. The drain of the fifth transistor is connected to the source of the fifth enhancement transistor. The drain of the fifth enhancement transistor is connected to the gate of the fifth transistor and the drain of the second negative input transistor. The drain of the sixth transistor is connected to the source of the sixth enhancement transistor. The drain of the sixth enhancement transistor is connected to the drain of the third positive input transistor. The gate of the fifth enhancement transistor and the gate of the sixth enhancement transistor are connected and receive the control voltage.
7. The amplifier according to claim 1, wherein, The mirror ratio of the first current mirror is 1:N, where N is greater than 1; the mirror ratio of the second current mirror is 1:K, where K is greater than 1; and the mirror ratio of the fourth current mirror is 1:M, where M is greater than 1.
8. The amplifier according to claim 1, wherein, The output current mirror includes a seventh transistor and an eighth transistor. The gates of the seventh transistor and the eighth transistor are connected. The sources of the seventh transistor and the eighth transistor share the same supply voltage. The drain of the seventh transistor is connected to the drain of the first output transistor, and the drain of the eighth transistor is connected to the drain of the second output transistor. The gate of the seventh transistor is also connected to its drain. The gate of the first output transistor is connected to the gate of the second output transistor and receives a control voltage. The connection node between the second output transistor and the eighth transistor is the first node.
9. The amplifier according to claim 1, wherein, The gate of the upper driving transistor and the gate of the lower driving transistor are both connected to the first node. The source of the upper driving transistor receives the supply voltage, and the source of the lower driving transistor is grounded. The common node of the drain of the upper driving transistor and the drain of the lower driving transistor is the second node, and the output voltage is provided from the second node.
10. The amplifier according to claim 6, wherein, All three positive input transistors are PMOS transistors, and all three negative input transistors are PMOS transistors. All transistors in the first current mirror to the fourth current mirror are NMOS transistors. The seventh and eighth transistors in the output current mirror are PMOS transistors. The first output transistor and the second output transistor are NMOS transistors. The upper driving transistor is a PMOS transistor, and the lower driving transistor is an NMOS transistor.
11. An integrated circuit, wherein, include: The amplifier according to any one of claims 1-10 amplifies the input differential signal and outputs an output voltage.
12. A chip, wherein, include: The amplifier according to any one of claims 1-10 amplifies the input differential signal and outputs an output voltage.
13. An electronic device, wherein, include: The amplifier according to any one of claims 1-10 amplifies the input differential signal and outputs an output voltage.