High-speed master-slave double-sampling D flip-flop for inputting approximation clock

Abstract

The invention discloses a high-speed master-slave type double-sampling D flip-flop for inputting an approximation clock. The high-speed master-slave type double-sampling D flip-flop comprises a control signal generating circuit, a master trigger circuit and a slave trigger circuit, the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the CK is in a low level, the master trigger circuit receives data input, and the slave trigger circuit is in a maintenance state; and when the CK is at a high level, the main trigger circuit is not influenced by the input signal and is in a maintenance state, and the slave trigger circuit receives the storage state of the main trigger circuit, so that the trigger state is updated. Compared with a traditional D trigger with a scanning structure, the control of a data input signal D of the trigger is finer, the trigger is not only controlled by a clock signal, but also controlled by an enable signal and an internal signal of the main trigger circuit, and meanwhile, the slave trigger circuit receives an output signal of the main trigger circuit by using a double-sampling structure; the delay characteristic of the trigger is improved, the average delay is reduced by 8.74%, and the maximum delay is reduced by 24.9%.

Description

Technical Field

[0001] This invention relates to the field of digital circuit technology, specifically to a high-speed master-slave type dual-sampling D flip-flop with an input approximation clock. Background Technology

[0002] With the rapid development of digital circuit technology, flip-flops, as one of the core components in digital integrated circuits, face increasingly higher performance requirements. Especially in high-speed digital circuits, the stability and speed of flip-flops directly affect the performance of the entire digital circuit and chip. Among them, D flip-flops have the widest range of applications and the strongest adaptability. However, traditional D flip-flop designs face many challenges in high-speed applications, such as large signal delay, high power consumption, and poor anti-interference capabilities. The long signal path of traditional D flip-flops leads to significant signal transmission delay, limiting the improvement of operating frequency. Therefore, to overcome the problem of large delay in traditional flip-flops and improve the operating frequency, developing a high-performance, high-speed master-slave dual-sampling D flip-flop with input approximation clock speed is of significant practical importance.

[0003] Figure 1 The diagram shown is of a D flip-flop unit with a scan structure. Figure 2 The circuit shown is a traditional master-slave flip-flop structure with scan-enabled conventional transmission-gate flip-flop (STGFF). Figure 3 The circuit shown is a master-slave D flip-flop (Conventional transmission-gate flip-flop (TGFF)) structure, widely used in the design of standard cell libraries for commercial digital circuits at various process nodes. The advantage of this structure is its simplicity, but its performance is fixed and difficult to improve under a fixed process. Therefore, a high-speed master-slave dual-sampling D flip-flop with an input approaching the clock can be designed to improve the flip-flop's delay characteristics for application in higher-performance digital integrated circuit design. Summary of the Invention

[0004] To address the technical problems existing in the prior art, this invention provides a high-speed master-slave type dual-sampling D flip-flop with input approximation clock that greatly improves the delay characteristics of the flip-flop.

[0005] To solve the above-mentioned technical problems, the technical solution proposed by this invention is as follows: A high-speed master-slave dual-sample D flip-flop with input approximation clock, comprising a master trigger circuit, a control signal generation circuit, and a slave trigger circuit; The main trigger circuit includes: PMOS transistor MP1 has its substrate connected to power supply VDD, its source connected to power supply VDD, its gate connected to control signal cks2n, and its drain connected to drive signal v1. PMOS transistor MP2 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to clock complementary signal ckn, and its drain connected to drive signal ml_ax. PMOS transistor MP3, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal ml_b, drain driven signal v1; PMOS transistor MP4 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to data input signal D, and its drain driven by signal ml_ax. NMOS transistor MN1, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to control signal cks3n, drain driven signal v2; NMOS transistor MN2, substrate connected to power supply VSS, source connected to signal v2, gate connected to clock signal cknn, drain driven by signal ml_ax; NMOS transistor MN3, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to signal ml_b, drain driven signal v2; NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driven by signal ml_ax; Inverter X5 is driven by signal ml_ax at its input and by signal ml_b at its output. The scanning structure has input signals sen, SI, cknn, SE, and ckn, and outputs a drive signal ml_ax. The control signal generation circuit is driven by clock signal CK and enable signal SE at its input terminal, and drives clock complementary signal ckn, signal cknn and enable signal SE complementary signal sen at its output terminal; and signal ckn and signal sen further generate control signal cks2n and control signal cks3n. The input terminals of the trigger circuit are connected to signals ml_ax and sl_ax, and the output terminal drives the output signal Q.

[0006] Preferably, the trigger circuit includes: Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn; Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn; Transmission gate TG3 has the data input terminal connected to the sl_ax signal, the data output terminal connected to the sl_bn signal, the clock signal PMOS input terminal connected to the cknn signal, and the clock signal NMOS input terminal connected to the ckn signal. Inverter X6 is driven by signal sl_ax at its input and by signal sl_b at its output. Inverter X7 is driven by signal sl_b at its input and by signal sl_bn at its output. The inverter X8 is driven by the signal sl_b at its input and by the output signal Q at its output.

[0007] Preferably, the trigger circuit further includes: The inverter X9 is driven by the signal sl_ax at its input and by the signal QN at its output.

[0008] Preferably, the scanning structure includes: PMOS transistor MP5, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal sen, drain driven signal v3; PMOS transistor MP6, substrate connected to power supply VDD, source connected to signal v3, gate scan signal SI, drain drive signal v4; PMOS transistor MP7 has its substrate connected to power supply VDD, its source connected to signal v4, its gate connected to clock signal cknn, and its drain connected to drive signal ml_ax. NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain drive signal v6; NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scan signal SI, drain drive signal v5; NMOS transistor MN7 has the substrate connected to power supply VSS, the source connected to signal v5, the gate connected to clock signal ckn, and the drain connected to drive signal ml_ax.

[0009] Preferably, the control signal generation circuit includes: Inverter X1 is driven by clock signal CK at its input and by clock complementary signal ckn at its output. Inverter X2 is driven at its input by a clock complementary signal ckn and at its output by a drive signal cknn. Inverter X3 has an input driven by the enable signal SE and an output driven by the complementary signal sen of the enable signal SE. Inverter X4 is driven by signal cks2n at its input and by signal cks3n at its output. The two-input NAND gate is driven by the complementary enable signal sen and the complementary clock signal ckn at its inputs, and outputs the drive signal cks2n.

[0010] Compared with the prior art, the advantages of the present invention are as follows: Compared to traditional STGFF D flip-flops with scanning structures, the data input signal D of the flip-flop in this invention is controlled more precisely. It is controlled not only by the clock signal but also by the enable signal and the signals inside the main trigger circuit. At the same time, it receives the output signal of the main trigger circuit from the trigger circuit using a dual sampling structure, which greatly improves the delay characteristics of the flip-flop (average delay reduced by 8.74%, maximum delay reduced by 24.9%). This reduces the setup time of the flip-flop and optimizes the CK2Q delay, making it very suitable for the design of high-performance chips such as high-frequency CPUs and GPUs.

[0011] Compared with traditional D flip-flops with scanning structure, the high-speed master-slave dual-sampling D flip-flop (SDTGFF) with input approximation clock proposed in this invention has one less transmission gate circuit during data input, resulting in a shorter setup time. The slave trigger circuit uses a dual-sampling structure, and the state of the master trigger circuit is transmitted to the output circuit only needs one inversion when the clock signal rises, resulting in a shorter CK2Q delay.

[0012] Compared with traditional D flip-flops, the high-speed master-slave dual-sampling D flip-flop with input approximation clock proposed in this invention has a dual-sampling structure. At the same time, the state of the master trigger circuit is transmitted to the output circuit only once when the clock signal rises, and the delay of CK2Q is shorter. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a traditional D flip-flop circuit with a scanning structure; where D is the data input signal, CK is the clock input signal, SE is the enable signal, SI is the scan input signal, and Q is the output signal.

[0014] Figure 2 This is a circuit diagram of a traditional STGFF D flip-flop with a scanning structure.

[0015] Figure 3 This is the circuit structure diagram of a traditional D flip-flop TGFF.

[0016] Figure 4 This is a circuit diagram of the high-speed master-slave type dual-sampling D flip-flop SDTGFF according to Embodiment 1 of the present invention.

[0017] Figure 5 This is a circuit diagram of the high-speed master-slave type dual-sampling D flip-flop NSDTGFF according to Embodiment 2 of the present invention. Detailed Implementation

[0018] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0019] Example 1: like Figure 4 As shown, the high-speed master-slave dual-sampling D flip-flop with input approximation clock provided in this embodiment of the invention includes a slave trigger circuit, a master trigger circuit, and a control signal generation circuit; the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK; when the clock signal CK is low, the master trigger circuit receives data input at the D terminal, while the slave trigger circuit is in a holding state; when the clock signal CK is high, the master trigger circuit is not affected by the input signal and is in a holding state, while the slave trigger circuit receives the stored state of the master trigger circuit, thereby updating the flip-flop state; The trigger circuit includes: Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn; Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn; Transmission gate TG3, data input terminal connected to sl_ax signal, data output terminal connected to sl_bn signal, clock signal PMOS input terminal (G) connected to signal cknn, clock signal NMOS input terminal (G) connected to signal ckn; Inverter X6 is driven by signal sl_ax at its input and by signal sl_b at its output. Inverter X7 is driven by signal sl_b at its input and by output signal sl_bn at its output. The inverter X8 is driven by the signal sl_b at its input and by the output signal Q at its output.

[0020] The main trigger circuit includes: PMOS transistor MP1 has its substrate connected to power supply VDD, its source connected to power supply VDD, its gate connected to signal cks2n, and its drain driven by signal v1. PMOS transistor MP2 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to clock complementary signal ckn, and its drain connected to drive signal ml_ax. PMOS transistor MP3, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal ml_b, drain driven signal v1; PMOS transistor MP4 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to data input signal D, and its drain driven by signal ml_ax. PMOS transistor MP5, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal sen, drain driven signal v3; PMOS transistor MP6, substrate connected to power supply VDD, source connected to signal v3, gate scan signal SI, drain drive signal v4; PMOS transistor MP7 has its substrate connected to power supply VDD, its source connected to signal v4, its gate connected to clock signal cknn, and its drain connected to drive signal ml_ax. NMOS transistor MN1, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to control signal cks3n, drain driven signal v2; NMOS transistor MN2 is connected to power supply VSS on the substrate, signal v2 at the source, clock signal cknn at the gate, and drive signal ml_ax at the drain. NMOS transistor MN3, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to signal ml_b, drain driven signal v2; NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driven by signal ml_ax; NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain drive signal v6; NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scan signal SI, drain drive signal v5; NMOS transistor MN7, substrate connected to power supply VSS, source connected to signal v5, gate connected to clock signal ckn, drain driven by signal ml_ax; Inverter X5 is driven by signal ml_ax at its input and by signal ml_b at its output.

[0021] The control signal generation circuit includes: Inverter X1 is driven by clock signal CK at its input and by clock complementary signal ckn at its output. Inverter X2 is driven at its input by a clock complementary signal ckn and at its output by a drive signal cknn. Inverter X3 has an input driven by the enable signal SE and an output driven by the complementary signal sen of the enable signal SE. Inverter X4 is driven by signal cks2n at its input and by control signal cks3n at its output. The two-input NAND gate is driven by the complementary enable signal sen and the complementary clock signal ckn at its inputs, and outputs the drive control signal cks2n.

[0022] The aforementioned high-speed master-slave dual-sampling D flip-flop (Scan-Enabled Doubletransmission-gate flip-flop, abbreviated as SDTGFF) with input approximation clock uses a dual-sampling circuit structure in its slave triggering circuit, such as... Figure 4 As shown, under the control of the clock signal, the output signals ml_ax and ml_b of the master trigger circuit are transmitted to the slave trigger circuit through two transmission gates TG1 and TG2 with the same internal transistor size. Figure 2 In the traditional D flip-flop structure STGFF shown, under clock control, the output signal of inverter X4 passes through transmission gate TG3, and then through inverters X6 and X8 to reach output Q. The signal undergoes two inversions. However, as shown... Figure 4 The high-speed master-slave dual-sampling D flip-flop SDTGFF of the present invention has a master trigger circuit output signal ml_ax that, after passing through transmission gate TG2, only needs to pass through inverter X8 once to reach output Q. This reduces the number of signal inversions, improves the high delay characteristics of the flip-flop, and reduces the clock-to-output delay (CK2Q).

[0023] Figure 4 The working principle of the SDTGFF flip-flop circuit shown is as follows: Signal ckn is the inverse of signal CK and is complementary to signal CK; similarly, signal cknn is complementary to signal ckn. That is, when the clock signal CK is high, ckn is low and cknn is high; conversely, when CK is low, ckn is high and cknn is low. Similarly, SE and sen are complementary signals. When SE is 1, sen is 0; when SE is 0, sen is 1.

[0024] When the enable signal SE is set to 0, sen is 1, MP5 and MN5 are cut off. Regardless of changes in signals SI and cknn, signal ml_ax remains unchanged. At this time, the signal input is controlled by the data input terminal D, independent of the scan signal terminal SI. Simultaneously, CK is set to 0, ckn is 1, and the NAND gate output cks2n is 0, driving MP1 to conduct. After cks2n is inverted by inverter X4, signal cks3n becomes high (1), driving MN1 to conduct. At this time, when the data input signal D is 0, MP4 conducts, and signal ml_ax is pulled up to 1. After passing through inverter X2, signal ml_b is pulled down to 0. Conversely, when D is 1, MN4 conducts, signal ml_ax is pulled down to 0, and signal ml_b is pulled up to 1. Therefore, when the enable signal SE and signal CK are both set to 0, the control signal generation circuit inputs signal D, and the main trigger circuit samples the data input signal D and updates the state.

[0025] When the enable signal SE is set to 1, sen is 0, MP5 and MN5 are turned on, and the NAND gate output cks2n is always 0. After driving inverter X4, signal cks3n is always 1, so MP1 and MN1 are turned off. At this time, no matter how the data input signal D changes, signal ml_ax is related to SI. When SE is 1, sen is 0 and CK is 1 (ckn is 0, cknn is 1, ck3n is 0), MP5, MN5, MP7 and MN7 are all turned on. When SI is 0, MP13 is also turned on, MN13 is turned off, signal ml_ax is pulled up to 1, and after passing through inverter X5, it drives signal ml_b to be pulled down to 0, consistent with signal SI. Conversely, when SI is 1, signal ml_ax is pulled down to 0 and signal ml_b is pulled up to 1. Therefore, when the enable signal SE is set to 1 and signal CK is set to 0, the control signal generation circuit inputs the scan signal SI, and the main trigger circuit samples the scan signal SI and updates the state.

[0026] When the clock input signal CK is set to 0, ckn is 1, cknn is 0, ck3n is 1, transmission gates TG1 and TG2 are cut off, and TG3 is turned on; inverters X7 and X6 form two inverters connected in series, which maintains the state of the slave trigger circuit and drives inverter X8 to maintain the output signal Q.

[0027] When the clock input signal CK is set to 1, ckn is 0, cknn is 1, and ck3n is 1. The NAND gate output cks2n is always 0. After driving inverter X4, the signal cks3n is always 1, so MP1 and MN1 are cut off. At this time, MP3, MN3 and inverter X5 form two inverters connected in series, so that the main trigger circuit maintains its state. The transmission gate TG2 is turned on, and the state of the transmission signal ml_ax is transmitted to the sl_b node. At this time, the state of node ml_ax is the OR scan signal of the previous data input signal. After passing through inverter X8, it is transmitted to Q to complete the data update. The transmission gate TG1 transmits the state of the signal ml_b to the sl_ax node. After passing through inverter X6, it is transmitted to node sl_b. At this time, node sl_b is the state of node ml_ax (i.e., the inverted signal sl_ax). After another inversion, the signal is consistent with the original sl_ax node signal. Because the main trigger circuit is always in a sustain state, the signals ml_ax and ml_b remain stable without being affected by the data input signal D and the scan signal SI. Therefore, the state update of the trigger circuit occurs when the signal CK changes from low level to high level. That is, the trigger of the present invention is a rising edge triggered D flip-flop with a scan structure.

[0028] The high-speed master-slave dual-sampling D flip-flop SDTGFF with input approximation clock proposed in this embodiment, such as Figure 4As shown, the SDTGFF exhibits excellent delay characteristics, including short setup time and low CK2Q delay. Compared to traditional D flip-flop STGFF circuits with scanning structures, this circuit can be widely used in high-performance, high-frequency digital circuit designs.

[0029] Example 2: Based on the SDTGFF in Example 1, the output is inverted to obtain a high-speed D flip-flop with an inverted signal and a scan structure (Inverted Signal Scan-Enabled Double Transmission-Gate Flip-Flop (NSDTGFF)). Figure 5 As shown, this is applicable to common scenarios where the output signal needs to be inverted.

[0030] like Figure 5 As shown, compared with the trigger in Embodiment 1, the data output of this embodiment is the inverted signal of the data stored in the master trigger. The trigger also includes a slave trigger circuit, a master trigger circuit, and a control signal generation circuit. From the trigger circuit, including: Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn; Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal (G) connected to signal ckn, clock signal NMOS input terminal (G) connected to signal cknn; Transmission gate TG3, data input terminal connected to sl_ax signal, data output terminal connected to sl_bn signal, clock signal PMOS input terminal (G) connected to signal cknn, clock signal NMOS input terminal (G) connected to signal ckn; Inverter X6 is driven by signal sl_ax at its input and by signal sl_b at its output. Inverter X7 is driven by signal sl_b at its input and by output signal sl_bn at its output. The inverter X8 is driven by the signal sl_b at its input and by the output signal Q at its output.

[0031] Inverter X9 is driven by signal sl_ax at its input and by signal QN at its output. The main trigger circuit includes: PMOS transistor MP1 has its substrate connected to power supply VDD, its source connected to power supply VDD, its gate connected to signal cks2n, and its drain driven by signal v1. PMOS transistor MP2 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to clock complementary signal ckn, and its drain connected to drive signal ml_ax. PMOS transistor MP3, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal ml_b, drain driven signal v1; PMOS transistor MP4 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to data input signal D, and its drain driven by signal ml_ax. PMOS transistor MP5, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal sen, drain driven signal v3; PMOS transistor MP6, substrate connected to power supply VDD, source connected to signal v3, gate scan signal SI, drain drive signal v4; PMOS transistor MP7 has its substrate connected to power supply VDD, its source connected to signal v4, its gate connected to clock signal cknn, and its drain connected to drive signal ml_ax. NMOS transistor MN1, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to control signal cks3n, drain driven signal v2; NMOS transistor MN2 is connected to power supply VSS on the substrate, signal v2 at the source, clock signal cknn at the gate, and drive signal ml_ax at the drain. NMOS transistor MN3, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to signal ml_b, drain driven signal v2; NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driven by signal ml_ax; NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain drive signal v6; NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scan signal SI, drain drive signal v5; NMOS transistor MN7, substrate connected to power supply VSS, source connected to signal v5, gate connected to clock signal ckn, drain driven by signal ml_ax; Inverter X5 is driven by signal ml_ax at its input and by signal ml_b at its output.

[0032] MP5, MP6, MP7, MN5, MN6, and MN7 are scanning structures; The control signal generation circuit includes: Inverter X1 is driven by clock signal CK at its input and by clock complementary signal ckn at its output. Inverter X2 is driven at its input by a clock complementary signal ckn and at its output by a drive signal cknn. Inverter X3 has an input driven by the enable signal SE and an output driven by the complementary signal sen of the enable signal. Inverter X4 is driven by signal cks2n at its input and by signal cks3n at its output. The two-input NAND gate is driven by the complementary enable signal sen and the complementary clock signal ckn at its inputs, and outputs the drive signal cks2n.

[0033] Figure 5 The NSDTGFF flip-flop circuit shown works on the same principle as the SDTGFF, except that an inverter X9 is added to the sl_ax node. The input of X9 is connected to the sl_ax signal, and the output drives QN.

[0034] Compared to the traditional STGFF D flip-flop with a scanning structure, the data input signal D of the SDTGFF flip-flop of this invention is controlled more precisely. It is controlled not only by the clock signal, but also by the enable signal and the signals inside the main trigger circuit. At the same time, the trigger circuit uses a dual sampling circuit structure, which greatly improves the delay characteristics of the flip-flop (average delay reduced by 8.74%, maximum delay reduced by 24.9%). This reduces the setup time of the flip-flop and optimizes the CK2Q delay, making it very suitable for the design of high-performance chips such as high-frequency CPUs and GPUs.

[0035] Compared to traditional STGFF D flip-flops with scanning structure, the high-speed master-slave dual-sampling D flip-flop (SDTGFF) with input approximation clock proposed in this invention has one less transmission gate circuit during data input, resulting in a shorter setup time. Under clock signal control, such as Figure 2 In the traditional D flip-flop STGFF with scanning structure shown, the output signal of inverter X4, after passing through transmission gate TG3, needs to pass through inverters X6 and X8 again to reach output Q, requiring two inversions. However, the slave trigger circuit of SDTGFF uses a dual sampling structure. After passing through transmission gate TG2, the output signal ml_ax of the master trigger circuit only needs to pass through inverter X8, and only one inversion is required to reach output Q. The delay of CK2Q is shorter.

[0036] Compared with the traditional D flip-flop TGFF, the high-speed master-slave dual-sampling D flip-flop with input approximation clock proposed in this invention uses a dual-sampling structure in its slave trigger circuit. After the master flip-flop output signal ml_ax passes through the transmission gate TG2, it only needs to pass through the inverter X8 once to reach the output Q, and the delay of CK2Q is shorter.

[0037] To compare the performance characteristics of the high-speed master-slave dual-sample D flip-flop with input approximation clock (SDTGFF) proposed in this invention, under the same conditions, the traditional scan-structure D flip-flop (STGFF) and the high-speed master-slave dual-sample D flip-flop with input approximation clock (SDTGFF) proposed in this invention were characterized using the LIBERATE17 tool and then compared and analyzed using the qualib tool.

[0038] Table 1 shows the comparison data of relevant parameters of the flip-flop described in this invention. Compared with the traditional STGFF D flip-flop with scan structure, the D flip-flop circuit (SDTGFF) proposed in this invention, under the condition of maximum timing arc, has a 2.2% reduction in rise-edge CK2Q delay (rise_CK2Q), a 4.5% reduction in fall-edge CK2Q delay (fall_CK2Q), a 66.8% reduction in rise-edge setup time (rise_setup), a 57.8% reduction in fall-edge setup time (fall_setup), and a 24.9% reduction in total maximum delay (max_total_delay). Therefore, the high-speed master-slave dual-sampling D flip-flop (SDTGFF) standard cell with input approximation clock implemented in this invention has broad application prospects in high-performance, high-frequency digital integrated circuit design compared with the traditional STGFF D flip-flop standard cell.

[0039] Table 1 shows the comparison results of qualib under the maximum time arc.

[0040] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A high-speed master-slave type double-sampling D flip-flop with input approximation clock, characterized in that, It includes a master trigger circuit, a control signal generation circuit, and a slave trigger circuit; The main trigger circuit includes: PMOS transistor MP1 has its substrate connected to power supply VDD, its source connected to power supply VDD, its gate connected to control signal cks2n, and its drain connected to drive signal v1. PMOS transistor MP2 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to clock complementary signal ckn, and its drain connected to drive signal ml_ax. PMOS transistor MP3, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal ml_b, drain driven signal v1; PMOS transistor MP4 has its substrate connected to power supply VDD, its source connected to signal v1, its gate connected to data input signal D, and its drain driven by signal ml_ax. NMOS transistor MN1, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to control signal cks3n, drain driven signal v2; NMOS transistor MN2, substrate connected to power supply VSS, source connected to signal v2, gate connected to clock signal cknn, drain driven by signal ml_ax; NMOS transistor MN3, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to signal ml_b, drain driven signal v2; NMOS transistor MN4, substrate connected to power supply VSS, source connected to signal v2, gate connected to data signal D, drain driven by signal ml_ax; Inverter X5 is driven by signal ml_ax at its input and by signal ml_b at its output. The scanning structure has input signals sen, SI, cknn, SE, and ckn, and outputs a drive signal ml_ax. The control signal generation circuit is driven by clock signal CK and enable signal SE at its input terminal, and drives clock complementary signal ckn, signal cknn and enable signal SE complementary signal sen at its output terminal; and signal ckn and signal sen further generate control signal cks2n and control signal cks3n. The input terminals of the trigger circuit are connected to signals ml_ax and sl_ax, and the output terminal drives the output signal Q.

2. The high-speed master-slave dual-sampling D flip-flop with input approximation clock as described in claim 1, characterized in that, The trigger circuit includes: Transmission gate TG1, data input terminal connected to signal ml_b, data output terminal connected to signal sl_ax, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn; Transmission gate TG2, data input terminal connected to signal ml_ax, data output terminal connected to signal sl_b, clock signal PMOS input terminal connected to signal ckn, clock signal NMOS input terminal connected to signal cknn; Transmission gate TG3 has the data input terminal connected to the sl_ax signal, the data output terminal connected to the sl_bn signal, the clock signal PMOS input terminal connected to the cknn signal, and the clock signal NMOS input terminal connected to the ckn signal. Inverter X6 is driven by signal sl_ax at its input and by signal sl_b at its output. Inverter X7 is driven by signal sl_b at its input and by signal sl_bn at its output. The inverter X8 is driven by the signal sl_b at its input and by the output signal Q at its output.

3. The high-speed master-slave type dual-sampling D flip-flop with input approximation clock as described in claim 2, characterized in that, The trigger circuit further includes: The inverter X9 is driven by the signal sl_ax at its input and by the signal QN at its output.

4. The high-speed master-slave type double-sampling D flip-flop with input approximation clock according to claim 1, 2, or 3, characterized in that, The scanning structure includes: PMOS transistor MP5, substrate connected to power supply VDD, source connected to power supply VDD, gate connected to signal sen, drain driven signal v3; PMOS transistor MP6, substrate connected to power supply VDD, source connected to signal v3, gate scan signal SI, drain drive signal v4; PMOS transistor MP7 has its substrate connected to power supply VDD, its source connected to signal v4, its gate connected to clock signal cknn, and its drain connected to drive signal ml_ax. NMOS transistor MN5, substrate connected to power supply VSS, source connected to power supply VSS, gate connected to enable signal SE, drain drive signal v6; NMOS transistor MN6, substrate connected to power supply VSS, source connected to signal v6, gate scan signal SI, drain drive signal v5; NMOS transistor MN7 has the substrate connected to power supply VSS, the source connected to signal v5, the gate connected to clock signal ckn, and the drain connected to drive signal ml_ax.

5. The high-speed master-slave type double-sampling D flip-flop with input approximation clock according to claim 1, 2, or 3, characterized in that, The control signal generation circuit includes: Inverter X1 is driven by clock signal CK at its input and by clock complementary signal ckn at its output. Inverter X2 is driven at its input by a clock complementary signal ckn and at its output by a drive signal cknn. Inverter X3 has an input driven by the enable signal SE and an output driven by the complementary signal sen of the enable signal SE. Inverter X4 is driven by signal cks2n at its input and by signal cks3n at its output. The two-input NAND gate is driven by the complementary enable signal sen and the complementary clock signal ckn at its inputs, and outputs the drive signal cks2n.

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