Delay adjustment circuit, delay adjustment device, delay adjustment method, and electronic device

Abstract

The application discloses a delay adjustment circuit, a delay adjustment device, a delay adjustment method and electronic equipment, and belongs to the technical field of electronic design. The delay adjustment circuit comprises an input buffer unit, an RC filter unit and a high-frequency compensation unit. The first end of the RC filter unit is connected with the output end of the input buffer unit, and the third end is grounded GND. The input end of the input buffer unit is connected with a signal input terminal. The high-frequency compensation unit and the second end of the RC filter unit are respectively connected with a signal output terminal. The input buffer unit is used for driving the signal input through the signal input terminal. The RC filter unit is used for performing delay adjustment on the signal processed by the input buffer unit. The high-frequency compensation unit is used for performing high-frequency compensation on the signal adjusted by the RC filter unit.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronic design, and particularly relates to a delay adjustment circuit, a delay adjustment device, a delay adjustment method and an electronic device. BACKGROUND

[0002] In related technologies, when multi-lane parallel transmission is performed, the skew between lanes can reach 9ps or more, and further deteriorate as the number of lanes increases. In this case, if skew calibration is not performed, the effective transmission eye width of the system will be significantly deteriorated, seriously affecting the system bit error rate.

[0003] To this end, a load adjustment method is introduced in related technologies to alleviate the skew problem between lanes. However, for high-speed transmission scenarios such as 32 Gbps, the load adjustment method provided in related technologies still has problems such as eye diagram quality deterioration, affecting transmission reliability. SUMMARY

[0004] The purpose of the embodiments of the application is to provide a delay adjustment device, a delay adjustment method and an electronic device, which can solve the problem of eye diagram quality deterioration in high-speed transmission scenarios such as 32 Gbps.

[0005] In a first aspect, a delay adjustment circuit is provided, comprising: an input buffer unit, an RC filter unit and a high-frequency compensation unit, a first end of the RC filter unit is connected with an output end of the input buffer unit, a third end is grounded GND, an input end of the input buffer unit is connected with a signal input terminal, the high-frequency compensation unit and a second end of the RC filter unit are respectively connected with a signal output terminal; wherein the input buffer unit is configured to drive a signal input through the signal input terminal, the RC filter unit is configured to adjust the delay of the signal processed by the input buffer unit, and the high-frequency compensation unit is configured to compensate the high frequency of the signal adjusted by the RC filter unit.

[0006] In a second aspect, a delay adjustment device is provided, comprising a delay adjustment module, the delay adjustment module comprises a first delay adjustment circuit, a second delay adjustment circuit and a cross-coupled inverter; an input end of the first delay adjustment circuit is connected with a first signal input terminal, and an output end is connected with a first input end of the cross-coupled inverter; an input end of the second delay adjustment circuit is connected with a second signal input terminal, and an output is connected with a second input end of the cross-coupled inverter; a first output end of the cross-coupled inverter is connected with a first signal output terminal, and a second output end is connected with a second signal output terminal; the first signal and the second signal are differential signals obtained based on the same signal, and the first delay adjustment circuit and the second delay adjustment circuit are respectively the delay adjustment circuit of the first aspect.

[0007] In a third aspect, a chip is provided, comprising the delay adjustment circuit according to the first aspect, or comprising the delay adjustment apparatus according to the second aspect.

[0008] In a fourth aspect, an electronic device is provided, comprising at least one delay adjustment circuit according to the first aspect, or comprising at least one delay adjustment apparatus according to the second aspect, or comprising at least one chip according to the third aspect; wherein the delay adjustment circuit corresponds to a receiving channel included in the electronic device one-to-one, and the delay adjustment apparatus corresponds to a receiving channel included in the electronic device one-to-one.

[0009] In a fifth aspect, a delay adjustment method is provided, comprising: receiving at least two parallel signals from a signal sending end; determining a to-be-adjusted signal in the at least two parallel signals and a delay difference of the to-be-adjusted signal; and adjusting a capacitance size of an adjustable capacitor in the delay adjustment circuit or the delay adjustment module according to the delay difference of the to-be-adjusted signal, so that a delay deviation between signal sampling starting positions corresponding to the at least two parallel signals after adjustment is less than a first threshold; wherein the delay adjustment circuit is the delay adjustment circuit according to the first aspect, and the delay adjustment apparatus is the delay adjustment apparatus according to any one of the second aspect.

[0010] In a sixth aspect, an electronic device is provided, comprising: a memory, a processor, and computer executable instructions stored in the memory and executable in the processor, and when the computer executable instructions are executed by the processor, steps of the method according to the fourth aspect are implemented.

[0011] In a seventh aspect, a readable storage medium is provided, for storing executable instructions, and when the executable instructions are executed by a processor, steps of the method according to the fourth aspect are implemented.

[0012] In the embodiments of the present application, through the ingenious design of the delay adjustment circuit, the high-frequency compensation unit can be used to compensate the signal after delay adjustment while the RC filter unit is used to delay the signal, so that the complete output of the signal is realized, and the problem of serious deterioration of eye diagram quality in related art when adjusting the delay for the high-speed data transmission scene is solved. BRIEF DESCRIPTION OF DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the accompanying drawings in the following description only represent some embodiments of the present application, and for those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0014] Figure 1 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0015] Figure 2 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0016] Figure 3 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0017] Figure 4 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0018] Figure 5 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0019] Figure 6 is a structural schematic diagram of a delay adjustment circuit provided by an exemplary embodiment of the present application.

[0020] Figure 7 is a structural schematic diagram of a delay adjustment device provided by an exemplary embodiment of the present application.

[0021] Figure 8 is a structural schematic diagram of a delay adjustment device provided by an exemplary embodiment of the present application.

[0022] Figure 9 is a flow schematic diagram of a delay adjustment method provided by an exemplary embodiment of the present application.

[0023] Figure 10a is a schematic diagram of skew between multiple channels before adjustment provided by an exemplary embodiment of the present application.

[0024] Figure 10b is a schematic diagram of skew between multiple channels before adjustment provided by an exemplary embodiment of the present application.

[0025] Figure 10c is a schematic diagram of skew between multiple channels after adjustment provided by an exemplary embodiment of the present application.

[0026] Figure 11FIG. 1 is a structural schematic diagram of an electronic device provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0027] In order for those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor should fall within the scope of protection of the present application.

[0028] In the rapidly developing field of artificial intelligence (AI) and data-intensive applications, higher requirements are put forward for high bandwidth density and high energy efficiency. However, due to the limitations of chip manufacturing equipment such as photolithography machines and processes, the maximum size of the current single chip (die) is difficult to further increase, so in order to achieve higher integration, chiplet has become the main direction of current chip development. With the development of chiplet, the Die to Die (D2D) high-speed interconnection technology is becoming more and more important. Since the inter-chip distance of D2D is extremely short, the layout and wiring area are greatly limited, therefore, in order to achieve higher bandwidth in limited space, single lane (lane) higher rate transmission has become an inevitable trend.

[0029] In addition, due to the deviation of physical manufacturing and wiring layout, there will be a certain inter-lane skew when D2D multi-lane parallel transmission occurs, which will cause the multi-lane common eye diagram (Eye Diagram) to shrink sharply. For example, in a single lane 32 Gbps application scenario, the duration of a unit interval (UI) is 31.25ps, and the inter-lane skew when multi-lane transmission occurs can reach about 9ps (this value will further increase with the increase of the number of lanes), therefore, if the inter-lane skew is not adjusted (or calibrated or adjusted), the effective transmission eye width of the whole system will be significantly deteriorated (such as possibly less than 22.25ps), resulting in an increase in system error rate.

[0030] To this end, the related art can generally achieve skew adjustment through load adjustment, but this method is not suitable for high-speed data transmission scenarios, such as when using the above load adjustment method for delay adjustment, there is still a serious problem of eye diagram quality deterioration, affecting transmission reliability.

[0031] To this end, the present application provides a delay adjustment scheme, which can achieve delay adjustment in a high-speed data transmission scenario, improve eye diagram quality, and improve transmission reliability.

[0032] The technical solutions provided by the embodiments of this application will be described in detail below with reference to the accompanying drawings and through some examples and application scenarios. It should be noted that the "delay" mentioned in this application can also be understood as time delay.

[0033] like Figure 1 The diagram shown is a schematic diagram of the structure of a delay adjustment circuit 10 provided in an exemplary embodiment of this application. The delay adjustment circuit 10 may include an input buffer unit 11, an RC filter unit 12, and a high-frequency compensation unit 13.

[0034] The first terminal 1 of the RC filter unit 12 is connected to the output terminal of the input buffer unit 11, and the third terminal 3 is grounded to GND. The input terminal of the input buffer unit 11 is connected to the signal input terminal. The high-frequency compensation unit 13 and the second terminal 2 of the RC filter unit 12 are respectively connected to the signal output terminal.

[0035] The input buffer unit 11 can have the characteristics of high input impedance and low output impedance, thereby reducing the load driving requirements of the front-end circuit when the input buffer unit 11 is used to drive the full-swing signal input to the front-end circuit in this embodiment.

[0036] In addition, the input buffer unit 11 used in this embodiment can also be used to isolate the influence of the signal input environment on subsequent circuits (such as RC filter unit 12 and high frequency compensation unit 13) to ensure signal transmission quality.

[0037] Optionally, the input signal of the input buffer unit 11 can be a full swing signal.

[0038] Optionally, the input buffer unit 11 provided in this embodiment can be implemented in various ways while achieving the aforementioned functions. For example, in this embodiment, the input buffer unit 11 can be an inverter or other input buffer circuits implemented based on an inverter, etc., and there is no limitation here.

[0039] For example, assuming the input buffer unit 11 is an inverter, then as Figure 2 As shown, the input buffer unit 11 may include, but is not limited to, a second P-type MOSFET MP2 and a second N-type MOSFET MN2. The gates of the second P-type MOSFET MP2 and the second N-type MOSFET MN2 are respectively connected to the signal input terminal. The drains of the second P-type MOSFET MP2 and the second N-type MOSFET MN2 are respectively connected to the first terminal 1 of the RC filter unit 12. The source of the second P-type MOSFET MP2 is connected to the power supply VDD, and the source of the second N-type MOSFET MN2 is grounded to GND.

[0040] Optionally, the input buffer unit 11 provided in this embodiment can also be Figure 2 Variations of the circuit shown are not limited here.

[0041] The RC filter unit 12 is used to adjust the delay of the signal processed by the input buffer unit 11. For example, the size of the capacitor in the RC filter unit 12 can be designed to adjust the delay of the input signal.

[0042] In this embodiment, considering that the RC filter unit 12 has a low-pass characteristic, when the RC filter unit 12 is used to adjust the delay of the signal in a high-speed transmission scenario such as 32 Gbps, high-frequency loss may be caused, such as a certain deviation in the amplitude and phase of high-frequency signals and low-frequency signals. To this end, the high-frequency compensation unit 13 is further introduced after the RC filter unit 12 in this embodiment, to compensate the high frequency of the signal adjusted by the RC filter unit 12 through the high-frequency compensation unit 13, so that the complete output of the high-speed signal and the like can be realized after the delay adjustment of the signal, and the eye diagram quality during the delay adjustment in the high-speed data transmission scenario is improved.

[0043] That is, through the ingenious design of the delay adjustment circuit 10 in this embodiment, the high-frequency compensation unit 13 can be used to compensate the high frequency of the signal adjusted by the RC filter unit 12, so that the complete output of the signal can be realized, and the problem of serious deterioration of the eye diagram quality during the delay adjustment in the high-speed data transmission scenario in the related art is solved.

[0044] In some embodiments, the filter capacitor C in the RC filter unit 12 can be a fixed capacitor, or the filter capacitor C in the RC filter unit 12 can also be a tunable capacitor. When the filter capacitor C is a fixed capacitor, the size of the fixed capacitor can be set according to the historical delay value or the experience value of the signal.

[0045] When the filter capacitor C in the RC filter unit 12 is a tunable capacitor, the capacitance size of the tunable capacitor C can be adjusted according to the real-time delay of the signal, so that the applicability and use flexibility of the delay adjustment circuit 10 can be improved while realizing the multi-grade delay adjustment of the signal, to achieve the purpose of maximizing the multi-channel common eye diagram under different process corners.

[0046] In addition, the RC filter unit 12 is used for delay adjustment in this application, which can also achieve the purpose of low power consumption while adjusting the delay.

[0047] Optionally, in the embodiment, when adjusting the capacitance C in the RC filter unit 12 to achieve signal delay adjustment, the adjustment can be performed according to the time delay difference between the to-be-adjusted signal and the reference signal or the reference channel, or the adjustment can be performed according to the difference between the boundary of the common eye diagram of the signals among the multiple channels and the clock position corresponding to each signal. The embodiment is not limited in this regard.

[0048] For the latter adjustment mode, since an additional reference channel or reference signal does not need to be introduced in the delay adjustment process, the complexity of the analog circuit design is reduced, and the flexibility of signal delay adjustment is improved. In the embodiment, the implementation process of the latter adjustment mode can be referred to the related description of the delay adjustment method 900 below, and will not be described herein.

[0049] In some embodiments, the high-frequency compensation unit 13 can be a passive inductive unit, or the high-frequency compensation unit 13 can also be an active inductive unit. In the embodiment, the active inductive unit is used as the high-frequency compensation unit 13 in the delay adjustment circuit 10, which can reduce the occupied area of the delay adjustment circuit 10.

[0050] Optionally, taking the active inductive unit as the high-frequency compensation unit 13 as an example, the type of the high-frequency compensation unit 13 can be various. For example Figure 3 As shown in the figure, the high-frequency compensation unit 13 can include a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, and a first resistor R1.

[0051] The source of the first P-type MOS transistor MP1 is connected to a power supply VDD, the gate of the first P-type MOS transistor MP1 is connected to the first end of the first resistor R1 and the gate of the first N-type MOS transistor MN1, the drain of the first P-type MOS transistor MP1, the second end of the first resistor, and the drain of the first N-type MOS transistor MN1 are respectively connected to a signal output terminal, and the source of the first N-type MOS transistor MN1 is connected to a ground GND.

[0052] Optionally, the high-frequency compensation unit 13 provided in the embodiment can also be Figure 3 The circuit variants are not limited herein.

[0053] In some embodiments, as Figure 4 As shown in the figure, the delay adjustment circuit 10 can further include a negative feedback amplification unit 14. The negative feedback amplification unit 14 can be used to compensate for the signal amplitude attenuation caused by the RC filter unit 12 and the high-frequency compensation unit 13, and improve the signal transmission quality.

[0054] In the embodiment, the type of the negative feedback amplification unit 14 can be various, for example Figure 4As shown, the negative feedback amplification unit 14 can include a third P-type MOS transistor MP3 and a third N-type MOS transistor MN3. The gate of the third P-type MOS transistor MP3 is connected to the output of the high-frequency compensation unit 13 and the RC filter unit 12, respectively, the gate of the third N-type MOS transistor MN3 is connected to the output of the high-frequency compensation unit 13 and the RC filter unit 12, respectively, the source of the third P-type MOS transistor MP3 is connected to the power supply VDD, the drain of the third P-type MOS transistor MP3 and the drain of the third N-type MOS transistor MN3 are connected to the signal output terminal, respectively, and the source of the third N-type MOS transistor MN3 is connected to the ground GND.

[0055] In some embodiments, as shown in FIG. 1, the negative feedback amplification unit 14 can further include a second resistor R2, a first end of the second resistor R2 being connected to the output of the high-frequency compensation unit 13 and the RC filter unit 12, respectively, and a second end of the second resistor R2 being connected to the signal output terminal. Figure 5

[0056] In this embodiment, by arranging the second resistor R2 in the negative feedback amplification unit 14, the common mode level can be determined by resistance feedback, and the amplitude compensation of the input signal can be performed based on the common mode level, such as amplifying the signal processed by the high-frequency compensation unit 13 to full swing and outputting, thereby improving the adjustment reliability of the delay adjustment circuit 10.

[0057] Based on the foregoing description of the delay adjustment circuit 10, as shown in FIG. 1, an exemplary schematic diagram of a delay adjustment circuit 10 provided by the present application can include the foregoing input buffer unit 11, RC filter unit 12, high-frequency compensation unit 13, and negative feedback amplification unit 14, wherein the input buffer unit 11, high-frequency compensation unit 13, and negative feedback amplification unit 14 share the same power supply VDD and share the same ground GND. Figure 6 It can be understood that,

[0058] As shown in FIG. 1, the delay adjustment circuit 10 is only an example, i.e., the delay adjustment circuit provided by the present application can be a variant of the structure as shown in FIG. 1, which is not limited herein. Figure 6 Figure 6 As shown in FIG. 1, an exemplary embodiment of the present application further provides a delay adjustment device, which can include a delay adjustment module 20, and the delay adjustment module 20 includes a first delay adjustment circuit 21, a second delay adjustment circuit 22, and a cross-coupled inverter 23.

[0059] As shown in FIG. 1, an exemplary embodiment of the present application further provides a delay adjustment device, which can include a delay adjustment module 20, and the delay adjustment module 20 includes a first delay adjustment circuit 21, a second delay adjustment circuit 22, and a cross-coupled inverter 23. Figure 7

[0060] ​​​The input end of the first delay adjustment circuit 21 is connected with the first signal input terminal, and the output end is connected with the first input end of the cross-coupled inverter 23. The input end of the second delay adjustment circuit 22 is connected with the second signal input terminal, and the output is connected with the second input end of the cross-coupled inverter 23. The first output end of the cross-coupled inverter 23 is connected with the first signal output terminal, and the second output end is connected with the second signal output terminal. Figure 7 As shown, “INV” represents each inverter included in the cross-coupled inverter 23.

[0061] In the embodiment, the first delay adjustment circuit 21 and the second delay adjustment circuit 22 can be understood as the delay adjustment circuit 10 mentioned in the foregoing embodiments, and can have the same or corresponding technical features and achieve the same or corresponding technical effects as the foregoing delay adjustment circuit 10. To avoid repetition, the embodiment will not be described here.

[0062] The first signal and the second signal are differential signals based on the same signal. For example, the first signal can be a P (Positive) signal in the differential signal, and the second signal can be an N (Negative) signal in the differential signal.

[0063] In the embodiment, the first signal and the second signal in the differential signal can be introduced into the delay adjustment circuit 10 for delay adjustment, and a cross-coupled inverter 23 is further added. Therefore, the relative skew adjustment between the first signal and the second signal by the cross-coupled inverter 23 can be performed, and the signals output by the first delay adjustment circuit 21 and the second delay adjustment circuit 22 can be further driven to full swing, thereby ensuring the quality of the differential signal.

[0064] That is, in the delay adjustment device provided in the embodiment, the cooperation of the delay adjustment circuit 10 and the cross-coupled inverter 23 can achieve the adjustment of the differential signal, and can also reduce the eye diagram loss caused by the relative skew between the first signal and the second signal in the differential signal, thereby greatly optimizing the signal quality of the high-speed data signal and the like.

[0065] In some embodiments, the delay adjustment device can include at least two delay adjustment modules 20, and the at least two delay adjustment modules 20 can be connected in a cascade manner. In the embodiment, the at least two delay adjustment modules 20 can be provided to achieve multi-stage adjustment of the differential signal, thereby improving the adjustment effect of the relative skew in the differential signal.

[0066] It is worth noting that in the case of cascading connection between at least two delay adjustment modules 20, for the two cascaded delay adjustment modules 20, the cross-coupled inverters 23 in the front-stage delay adjustment module 20 can also be used to isolate the delay adjustment circuits in the two-stage delay adjustment modules 20, so as to avoid mutual influence between the two.

[0067] For example, it is assumed that the delay adjustment device can include Figure 8 As shown in the two delay adjustment modules 20, i.e. the first-stage delay adjustment module 20 and the second-stage delay adjustment module 20, the cross-coupled inverters 23 in the first-stage delay adjustment module 20 can not only be used to adjust the differential signal so as to reduce the eye diagram loss caused by the relative skew between the first signal and the second signal in the differential signal, but also be used to isolate the delay adjustment circuits in the first-stage delay adjustment module 20 and the delay adjustment circuits in the second-stage delay adjustment module 20, so as to avoid mutual influence between the two, and improve the transmission quality of the differential signal.

[0068] An example embodiment of the present application also provides a chip, which can include at least one delay adjustment circuit 10 mentioned in the foregoing embodiments, or the chip can also include at least one delay adjustment device mentioned in the foregoing embodiments.

[0069] Optionally, when a plurality of delay adjustment circuits 10 mentioned in the foregoing embodiments are included in the chip, each delay adjustment circuit 10 can be used for delay adjustment of a received signal.

[0070] Optionally, the chip can include one or more delay adjustment devices mentioned in the foregoing embodiments, and each delay adjustment device can be used for relative skew adjustment of a differential signal corresponding to a received signal.

[0071] The delay adjustment circuits 10 and the delay adjustment devices included in the chip in the embodiment can refer to the related descriptions in the foregoing embodiments and achieve the same or corresponding technical effects, and thus will not be described here again to avoid repetition.

[0072] An example embodiment of the present application also provides an electronic device, which can include at least one delay adjustment circuit 10 mentioned in the foregoing embodiments, or the electronic device can include at least one delay adjustment device mentioned in the foregoing embodiments, or the electronic device can include at least one chip mentioned in the foregoing embodiments.

[0073] The delay adjustment circuit corresponds to each receiving channel included in the electronic device. The delay adjustment device corresponds to each receiving channel included in the electronic device. The delay adjustment circuit 10 or the delay adjustment device can refer to the related description of the foregoing embodiments, and achieve the same or corresponding technical effects. To avoid repetition, it will not be described here.

[0074] Optionally, in the case that the electronic device includes at least one delay adjustment circuit 10 mentioned in the foregoing embodiments, assuming that the electronic device can include at least two delay adjustment circuits 10 arranged side by side, the delay adjustment circuit 10 corresponds to the signal receiving channel arranged in the electronic device, that is, in this embodiment, one delay adjustment circuit 10 can be arranged for each channel (or each parallel signal) to adjust the delay of the signal in each channel, so that the delay deviation between the adjusted signal sampling start positions of each channel is less than the first threshold, thereby improving the eye diagram quality in the signal transmission scene such as high-speed data transmission scene, and ensuring the reliability of transmission.

[0075] Similarly, in the case that the electronic device includes at least one delay adjustment device mentioned in the foregoing embodiments, assuming that the electronic device can include at least two delay adjustment devices arranged side by side, the delay adjustment circuit device corresponds to the signal receiving channel arranged in the electronic device, that is, in this embodiment, one delay adjustment device can be arranged for each channel (or each parallel signal) to adjust the delay of the signal in each channel, so that the delay deviation between the adjusted signal sampling start positions of each channel is less than the first threshold, thereby improving the eye diagram quality in the signal transmission scene such as high-speed data transmission scene, and ensuring the reliability of transmission.

[0076] Optionally, the first threshold can be set according to the delay adjustment accuracy requirement, can be a pre-defined historical experience value, or can be set according to the accuracy of the minimum adjustment gear in the plurality of pre-configured adjustment gears (corresponding to the adjustment gears of the capacitor C in the foregoing RC filter unit 12), without limitation here.

[0077] It can be understood that for the case that the electronic device can include at least one delay adjustment device, when the delay adjustment device is used for delay adjustment, for each receiving channel, the received signal can be processed into a differential signal first, and then the differential signal is input into the delay adjustment device for relative skew adjustment of the differential signal.

[0078] As Figure 9As shown, the exemplary embodiment of the present application also provides a delay adjustment method 900, which can be applied to an electronic device in which at least one delay adjustment circuit 10 mentioned in the foregoing embodiments is provided, or in which at least one delay adjustment device mentioned in the foregoing embodiments is provided. As to the delay adjustment circuit 10 and the delay adjustment device, the present embodiment will not be described again.

[0079] Based on this, the method 900 provided by the present embodiment can include but is not limited to the following steps.

[0080] Step S910: receiving at least two parallel signals from a signal sending end.

[0081] Step S920: determining a to-be-adjusted signal in the at least two parallel signals and a delay difference value of the to-be-adjusted signal.

[0082] Optionally, the manner of determining the delay difference value between the at least two parallel signals in S920 can be various. For example, the delay difference value between the at least two parallel signals in S920 can be determined according to an empirical value or a historical measurement value, etc.

[0083] For another example, the delay difference value between the at least two parallel signals in S920 can be determined by determining a common eye diagram boundary position (such as a left boundary of a common eye diagram, etc.) of the at least two parallel signals through an eye diagram scanning function possessed by the electronic device; and then determining the to-be-adjusted signal and the delay difference value of the delay of the to-be-adjusted signal relative to the common eye diagram boundary position according to the common eye diagram boundary position.

[0084] It can be understood that, by determining the common eye diagram boundary position of the at least two parallel signals and then determining the to-be-adjusted signal and the delay difference value of the delay of the to-be-adjusted signal relative to the common eye diagram boundary position based on the common eye diagram boundary position, the present embodiment can avoid introducing an additional reference channel or a reference signal in the delay adjustment process, reduce the complexity of the analog circuit design, and improve the flexibility of the signal delay adjustment.

[0085] Step S930: adjusting the capacitance size of the adjustable capacitor in the delay adjustment circuit 10 or the delay adjustment module according to the delay difference value of the to-be-adjusted signal, so that the delay deviation between the signal sampling starting positions corresponding to the at least two parallel signals after adjustment is less than a first threshold value. As to the first threshold value, reference can be made to the foregoing related description, which will not be described again herein.

[0086] Exemplarily, it is assumed that the electronic device (which can also be referred to as a top-level system) to which the delay adjustment method 900 is applied has the functions shown in (1)-(2) below.

[0087] (1) Pseudo-Random Binary Sequence (Prbs) transmission and verification function, which is used to send Prbs code at the signal transmitting end TX and complete the detection at the signal receiving end RX, and feed back the detection result through a readable register, such as detection pass or detection failure.

[0088] It is understandable that, in this example, the electronic device can be equipped with both a signal transmitter TX and a signal transmitter RX for the purpose of simulating the delay adjustment process.

[0089] (2) Clock phase adjustment function, which is used to realize the sampling clock phase adjustment and eye diagram scanning function of the signal receiving end RX, and the clock phase adjustment function can realize an adjustment amount of at least 1.5 UI.

[0090] Based on this, assuming that the signal transmitter TX has three channels, such as channel 1, channel 2, and channel 3, after the signal transmitter TX sends out three parallel signals based on the three channels, the three signals received by the signal receiver RX may be skewed (or channel skewed) due to path length deviations and channel loss deviations. Therefore, the delay adjustment process provided in this embodiment is as follows.

[0091] Step 1: Assume that before delay adjustment, the signal receiver RX receives 3 parallel signals, and the channel skew between the 3 parallel signals is as follows: Figure 10a As shown.

[0092] Step 2: Determine the common eye diagram boundary position of at least two parallel signals using the eye diagram scanning function, and set the sampling clock of the signal receiver RX to such a value. Figure 10b The indicated position is the left boundary of the common eye diagram. Based on the boundary position of the common eye diagram, it can be seen that the signals to be tuned are signal 1 and signal 3. Figure 10b The sampling clock of the signal receiver RX in the middle is relative to Figure 10a The sampling clock of the signal receiver RX shown in the diagram has been shifted to facilitate subsequent signal sampling.

[0093] Step 3: The difference between the clock position corresponding to signal 1 and the left boundary of the common eye diagram is taken as a delay deviation, and the adjustable capacitance in the delay adjustment circuit 10 corresponding to channel 1 is adjusted according to the delay deviation and at a predetermined step value (such as 0.1 UI or 0.02 UI, etc.), so that the delay position (i.e. the clock position) of signal 1 in channel 1 is moved backward, and after each adjustment, Prbs verification is performed, if the verification result of Prbs is pass, the adjustable capacitance in the delay adjustment circuit 10 corresponding to channel 1 is continuously adjusted, until Prbs verification fails, and the adjustment position is set at the position before the failure, i.e. the last adjustment position is the optimal adjustment position.

[0094] Step 4: The adjustment position of the adjustable capacitance in the delay adjustment circuit 10 corresponding to channel 3 is adjusted in the same way as the adjustment of channel 1, until the delay adjustment of the signals of all channels is completed, and the final (i.e. after the delay adjustment is completed) effect can be as shown in Figure 10c

[0095] In the foregoing delay adjustment scheme proposed in the embodiment, the signal delay adjustment is performed by determining the boundaries of the common eye diagram, without introducing an additional reference channel or reference signal in the delay adjustment process, which reduces the complexity of the analog circuit design and improves the flexibility of the signal delay adjustment.

[0096] In addition, the sampling time mismatch calibration based on correlation in the embodiment does not require the pre-input of a specific signal, has no requirement for the input signal, and can realize background calibration.

[0097] In the foregoing delay adjustment scheme provided by the application, multi-channel skew optimization can be realized under the conditions of low delay, low area, low power consumption and high data rate, the purpose of widening the common eye diagram is achieved, the low power consumption, low delay, low area and high rate requirements of the D2D interconnection technology are met, and the data transmission quality in the D2D scene is ensured.

[0098] The foregoing delay adjustment scheme provided by the application can be applied to, but is not limited to, a 32Gbps UCIe D2D system, other data transmission scenes requiring multi-channel delay adjustment and having a rate not higher than 32Gbps, etc.

[0099] Figure 11 ​A hardware structure schematic diagram of an electronic device is shown, and reference is made to the diagram. At the hardware level, the electronic device includes a processor, and optionally, an internal bus, a network interface, and a memory. The memory can include a memory, such as a high-speed random access memory (RAM), and can also include a non-volatile memory, such as at least one disk memory. Of course, the electronic device can also include other hardware required by a business.

[0100] The processor, the network interface, and the memory can be connected to each other through the internal bus, which can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one bidirectional arrow is used in the diagram, but it does not mean that there is only one bus or only one type of bus.

[0101] The memory is used to store a program. Specifically, the program can include program code, and the program code includes computer operation instructions. The memory can include a memory and a non-volatile memory, and provides instructions and data to the processor.

[0102] The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs, and forms a device for positioning a specified user at the logical level. The processor executes the program stored in the memory, and is specifically used to execute: Figure 9 The method disclosed in the illustrated embodiment achieves the functions and beneficial effects of the methods described in the foregoing method embodiments, and thus will not be described again.

[0103] The above as described in the present application Figure 9The method disclosed by the embodiment shown can be applied to a processor or implemented by the processor. The processor can be an integrated circuit chip with processing capability of signals. In the implementation process, each step of the above method can be completed by integrated logic circuits in hardware of the processor or instructions in the form of software. The above processor can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; or a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. Each method, step and logic block diagram disclosed in the embodiment of the present application can be implemented or executed. The general processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the art. The storage medium is located in the memory, and the processor reads the information in the memory, and combines the hardware to complete the steps of the above method.

[0104] The electronic device can also perform the methods described in the foregoing method embodiments, and achieve the functions and beneficial effects of the methods described in the foregoing method embodiments, which will not be repeated here.

[0105] Of course, in addition to the software implementation, the electronic device of the present application does not exclude other implementation manners, such as logic devices or a combination of software and hardware, etc. That is, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or a logic device.

[0106] The embodiment of the present application also proposes a readable storage medium, which stores one or more programs, and when the electronic device including a plurality of application programs executes the one or more programs, the electronic device executes Figure 9 The method disclosed by the embodiment shown and the functions and beneficial effects of the methods disclosed in the foregoing method embodiments will not be repeated here.

[0107] The readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0108] The embodiment of the present application further provides a program product, the computer program product includes a program stored on a non-transitory readable storage medium, the program includes program instructions, when the program instructions are executed by a computer, the following processes are realized: Figure 9 The method disclosed by the embodiment and the functions and advantages of the methods described in the foregoing method embodiments are not described here again.

[0109] The readable storage medium includes a permanent and non-permanent, removable and non-removable medium, which can store information by any method or technology. The information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage devices or any other non-transmission medium that can be used to store information that can be accessed by a computing device. According to the definition herein, the readable storage medium does not include the transitory computer readable medium, such as modulated data signals and carriers.

[0110] In summary, the above only describes the preferred embodiments of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0111] The system, device, module or unit illustrated in the above embodiments can be specifically implemented by a computer chip or entity, or by a product with certain functions. A typical implementation device is a computer. Specifically, the computer may, for example, be a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device or a combination of any of these devices.

[0112] It is also to be noted that the terms "comprising", "including", and any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0113] The various embodiments described in this specification are presented as examples. Each example is provided by way of explanation of the overall subject matter and is not a limitation on the overall subject matter. Changes in, or replacements to, parts of certain examples are covered by this specification. The various embodiments described in this specification are presented as examples. Each example is provided by way of explanation of the overall subject matter and is not a limitation on the overall subject matter. Changes in, or replacements to, parts of certain examples are covered by this specification.

Claims

1. A delay adjustment circuit, comprising: Input buffer unit, RC filter unit and high frequency compensation unit; The first end of the RC filter unit is connected to the output end of the input buffer unit, and the third end is grounded (GND). The input end of the input buffer unit is connected to the signal input terminal. The second ends of the high-frequency compensation unit and the RC filter unit are respectively connected to the signal output terminal. The input buffer unit is used to drive the signal input through the signal input terminal, the RC filter unit is used to adjust the delay of the signal processed by the input buffer unit, and the high-frequency compensation unit is used to perform high-frequency compensation on the signal adjusted by the RC filter unit. The high-frequency compensation unit is an active inductor unit, which includes a first P-type MOS transistor MP1, a first N-type MOS transistor MN1, and a first resistor R1. The source of the first P-type MOS transistor MP1 is connected to the power supply VDD, and its gate is connected to the first terminal of the first resistor R1 and the gate of the first N-type MOS transistor NN1, respectively. The drain of the first P-type MOS transistor MP1, the second terminal of the first resistor, and the drain of the first N-type MOS transistor NN1 are connected to the signal output terminal, respectively. The source of the first N-type MOS transistor NN1 is grounded to GND.

2. The delay adjustment circuit according to claim 1, characterized in that, The filter capacitor C in the RC filter unit is an adjustable capacitor.

3. The delay adjustment circuit according to claim 1, characterized in that, The input buffer unit includes a second P-type MOS transistor MP2 and a second N-type MOS transistor MN2; The gates of the second P-type MOS transistor MP2 and the second N-type MOS transistor MN2 are respectively connected to the signal input terminal. The drains of the second P-type MOS transistor MP2 and the second N-type MOS transistor MN2 are respectively connected to the first end of the RC filter unit. The source of the second P-type MOS transistor MP2 is connected to the power supply VDD, and the source of the second N-type MOS transistor MN2 is grounded to GND.

4. The delay adjustment circuit according to any one of claims 1-3, characterized in that, The delay adjustment circuit also includes a negative feedback amplification unit, which includes a third P-type MOS transistor MP3 and a third N-type MOS transistor MN3. The gate of the third P-type MOS transistor MP3 is connected to the outputs of the high-frequency compensation unit and the RC filter unit, respectively. The gate of the third N-type MOS transistor MN3 is connected to the outputs of the high-frequency compensation unit and the RC filter unit, respectively. The source of the third P-type MOS transistor MP3 is connected to the power supply VDD. The drains of the third P-type MOS transistor MP3 and the third N-type MOS transistor MN3 are connected to the signal output terminal, respectively. The source of the third N-type MOS transistor MN3 is grounded to GND.

5. The delay adjustment circuit according to claim 4, characterized in that, The negative feedback amplification unit also includes a second resistor R2. The first end of the second resistor R2 is connected to the outputs of the high-frequency compensation unit and the RC filter unit, respectively, and the second end of the second resistor R2 is connected to the signal output terminal.

6. A delay adjustment device, comprising a delay adjustment module, wherein the delay adjustment module includes a first delay adjustment circuit, a second delay adjustment circuit, and a cross-coupled inverter; The input terminal of the first delay adjustment circuit is connected to the first signal input terminal, and the output terminal is connected to the first input terminal of the cross-coupled inverter. The input terminal of the second delay adjustment circuit is connected to the second signal input terminal, and the output terminal is connected to the second input terminal of the cross-coupled inverter. The first output terminal of the cross-coupled inverter is connected to the first signal output terminal, and the second output terminal is connected to the second signal output terminal. The first signal and the second signal are differential signals obtained based on the same signal, and the first delay adjustment circuit and the second delay adjustment circuit are delay adjustment circuits as described in any one of claims 1-5.

7. The delay adjustment device according to claim 6, characterized in that, The delay adjustment device includes at least two delay adjustment modules, which are connected in a cascaded manner.

8. A chip comprising a delay adjustment circuit according to any one of claims 1-5, or comprising a delay adjustment device according to any one of claims 6-7.

9. An electronic device comprising at least one delay adjustment circuit according to any one of claims 1-5, or comprising at least one delay adjustment device according to any one of claims 6-7, or comprising at least one chip according to claim 8; in, The delay adjustment circuit corresponds one-to-one with the receiving channel included in the electronic device. The delay adjustment device corresponds one-to-one with the receiving channel included in the electronic device.

10. A delay adjustment method, the method comprising: Receive at least two parallel signals from the signal transmitter; Determine the signal to be tuned in one of the at least two parallel signals and the delay difference between the signals to be tuned; Adjust the capacitance of the adjustable capacitor in the delay adjustment circuit or the delay adjustment module according to the delay difference of the signal to be adjusted, so that the delay deviation between the signal sampling start positions corresponding to the at least two parallel signals after adjustment is less than the first threshold. Wherein, the delay adjustment circuit is the delay adjustment circuit according to any one of claims 1-5, and the delay adjustment device is the delay adjustment device according to any one of claims 6-7.

11. The delay adjustment method as described in claim 10, characterized in that, Determining the delay difference between the at least two parallel signals includes: The common eye diagram boundary position of the at least two parallel signals is determined by the eye diagram scanning function; The signal to be tuned and the delay difference between the delay of the signal to be tuned and the delay of the signal to be tuned relative to the boundary position of the common eye diagram are determined based on the boundary position of the common eye diagram.

12. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the steps of the method as described in any one of claims 10 or 11.

13. A readable storage medium, characterized in that, The readable storage medium stores a program that, when executed by a processor, implements the steps of the method as described in any one of claims 10 or 11.

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