Power FET device and device including the same

Abstract

A power FET device and a device including the same are disclosed. Techniques for temperature sensing in power FET switches are described. An example power field effect transistor (FET) device includes back-to-back power FETs coupled in series between a first power terminal and a second power terminal and connected to a common drain node. The power FET device also includes a temperature sensing diode including a cathode coupled to the common drain node. A temperature sensing circuit coupled to the power FET device is configured to determine a temperature of the first power FET and the second power FET based on a voltage drop across the temperature sensing diode. The temperature sensing circuit may include a voltage averaging circuit configured to sense a first voltage at the first power terminal, sense a second voltage at the second power terminal, and average the first voltage and the second voltage to generate a drain voltage representative of a voltage of the common drain node.

Description

[0001] priority

[0002] This application claims priority to Indian Patent Application No. 202411034338, filed April 30, 2024, and U.S. Patent Application No. 18 / 909,759, filed October 8, 2024, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure generally relates to the field of power transmission devices and systems and methods for controlling power transmission devices. Background Technology

[0004] Various electronic devices (e.g., smartphones, tablets, laptops, hubs, chargers, adapters, etc.) can be configured for wired charging via a USB Type-C (USB-C) connector, according to the USB power delivery protocol defined in various revisions of the Universal Serial Bus (USB) Power Delivery (USB-PD) specification. For example, in some applications, the electronic device can be configured as a power consumer (e.g., a laptop computer charging its own battery) to receive power via the USB-C connector, while in other applications, the electronic device can be configured as a power provider (e.g., a laptop computer) to provide power to another device (e.g., a smartphone) connected to it via the USB-C connector. The USB-PD specification allows power providers and power consumers to dynamically negotiate various power levels, such as 5V (volts) 3A (amperes), 15V 3A, 20V 3A, 12V 5A, 20V 5A, 48V 5A, etc. However, power delivery and its control are challenging in USB and other technologies that require accurate power levels (e.g., voltage and / or current) and stringent overvoltage, overcurrent, and overheat protection. Summary of the Invention

[0005] One aspect of this disclosure relates to an apparatus comprising: a power field-effect transistor (FET) device instantiated on a first die, the power FET device including: a first power FET coupled to a first power terminal of the first die; a second power FET disposed back-to-back with the first power FET and coupled to a second power terminal of the first die, wherein the first power FET and the second power FET are connected to a common drain node within the first die; a temperature sensing diode including a cathode coupled to the common drain node; and a temperature sensing circuit coupled to the power FET device and configured to determine the temperature of the first power FET and the second power FET based on a voltage drop across the temperature sensing diode, the temperature sensing circuit including a voltage averaging circuit coupled to a first voltage at the first power terminal and a second voltage at the second power terminal, wherein the temperature sensing circuit is configured to average the first voltage and the second voltage to generate a drain voltage representing the voltage of the common drain node.

[0006] Another aspect of this disclosure relates to a power field-effect transistor (FET) device, comprising: a first power FET and a second power FET arranged in series and electrically coupled through a common drain node, wherein the first power FET and the second power FET are configured to deliver an output current to a load in response to a first gate drive signal coupled to the first power FET through a first gate terminal of the power FET device and a second gate drive signal coupled to the second power FET through a second gate terminal of the power FET device; a temperature sensing diode for indicating the temperature of the first power FET and the second power FET, the temperature sensing diode including a cathode coupled to the common drain node and an anode coupled to a temperature sensing terminal; and a replica FET for providing a sensing voltage corresponding to the voltage of the common drain node, wherein the first power FET, the second power FET, and the replica FET are vertical FETs. Attached Figure Description

[0007] The disclosure is illustrated by way of example and not limitation in the accompanying drawings.

[0008] Figure 1 A circuit block diagram of a device for temperature sensing in a common-drain power field-effect transistor (FET) device is shown, according to some example embodiments of the present disclosure.

[0009] Figure 2 A circuit block diagram of another device for temperature sensing in a common-drain power FET device according to some embodiments of the present disclosure is shown.

[0010] Figure 3A more detailed circuit block diagram of another device for temperature sensing in a common-drain power FET device according to some embodiments of the present disclosure is shown.

[0011] Figure 4 An example structure of a vertical field-effect transistor (FET) according to some embodiments of this disclosure is shown.

[0012] Figure 5 This is a block diagram illustrating an integrated circuit (IC) controller according to some embodiments of the present disclosure, which may be configured together with a power FET semiconductor device on a provider and / or consumer power path.

[0013] Figure 6 This is a block diagram illustrating a system-in-package (SiP) comprising an IC controller and a power FET semiconductor device within a single package, according to some embodiments of the present disclosure. Detailed Implementation

[0014] The following description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a good understanding of the various implementations of the techniques described herein for temperature sensing in a common-drain power FET switch implemented with vertical FET technology. However, it will be apparent to those skilled in the art that at least some implementations can be practiced without these specific details. In other instances, well-known components, elements, or methods have not been described in detail or have been presented in a simple block diagram format to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and may still be considered within the spirit and scope of this disclosure.

[0015] In this specification, references to "implementation," "an embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" indicate that a specific feature, structure, step, operation, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Furthermore, the appearance of the phrases "implementation," "an embodiment," "an exemplary embodiment," "some embodiments," and "various embodiments" in various positions in this specification does not necessarily refer to the same (one or more) embodiments.

[0016] The specification includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate illustrations according to exemplary embodiments. These embodiments (which may also be referred to herein as “examples”) are described in sufficient detail to enable those skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments may be combined, other embodiments may be utilized, or structural, logical, and electrical changes may be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable those skilled in the art to practice, make, and / or use the subject matter.

[0017] This document describes various implementations of temperature sensing techniques for power FET devices used in a variety of USB-enabled electronic devices. Examples of such USB-enabled electronic devices include, but are not limited to, personal computers (e.g., laptops, notebook computers, etc.), mobile computing devices (e.g., tablets, tablet computers, etc.), mobile communication devices (e.g., smartphones, cellular phones, personal digital assistants, messaging devices, handheld PCs, etc.), audio / video / data recording and / or playback devices (e.g., camera devices, recorders, handheld scanners, etc.), and other similar electronic devices that can use a USB-C connector for battery charging and / or power delivery.

[0018] Some USB-enabled electronic devices may comply with specific revisions and / or versions of the USB-PD specification. The USB-PD specification defines a standard protocol designed to enable the maximum functionality of USB-enabled devices by providing more flexible power delivery and data communication over a single USB-C cable via a USB-C port. The USB-PD specification also describes the architecture, protocols, power delivery behavior, parameters, and wiring necessary to manage power delivery up to 100W (or up to 240W in the case of extended power range or EPR) over a USB-C cable. According to the USB-PD specification, devices with USB-C ports (e.g., USB-enabled devices) can negotiate greater current and / or higher or lower voltages over a USB-C cable compared to those allowed in older USB specifications (e.g., USB 2.0, USB Battery Charging Specification versions 1.1 / 1.2, etc.). For example, the USB-PD specification defines a protocol for negotiating a power delivery contract (PD contract) between a pair of USB-enabled devices. A PD contract can specify both the power levels and the direction of power transfer that two devices can accommodate, and can dynamically renegotiate the power levels and direction of power transfer (e.g., without unplugging the devices) based on requests from either device and / or in response to various events and conditions (e.g., power role swapping, data role swapping, hard reset, power failure, etc.). According to the USB-PD specification, electronic devices are typically configured to deliver power to another device via a power path configured on a USB VBUS line. The device providing power is typically referred to as (or includes) a "provider" (or power source), and the device consuming power is typically referred to as (or includes) a "consumer" (or power consumer). In some implementations, a USB-PD power source can be configured to draw power from a direct current (DC) power source and may include a DC-DC converter. In other implementations, a USB-PD power source can be configured to draw power from an AC power adapter or another AC source.

[0019] In USB-enabled and other technologies that require accurate power levels (e.g., voltage and / or current) and stringent overvoltage, overcurrent, and overtemperature protection, power delivery and its control are often challenging. Electronic devices are typically configured to deliver power via field-effect transistors (FETs) or other similar switching devices. In some cases, FETs can become susceptible to electrical damage (e.g., overcurrent damage, overvoltage damage, overtemperature damage, reverse current damage, etc.) due to one or more electrical faults, for example, that may occur in a USB-C connector system. Power delivery IC controllers in such technologies often struggle to meet the conflicting requirements of accurate power levels, protection, and efficiency in high-current (e.g., 3A or above) implementations and applications.

[0020] Electronic devices typically use power transfer circuits (power paths) to transfer power to / from the device. Among other electronic components, a power path can include one or more power FETs coupled in series on the circuit path to operate as switches (e.g., as "ON" / "OFF" switches). Power FETs differ from FETs and other types of transistor switching devices used in other non-power transfer applications in several important characteristics. As discrete semiconductor switching devices, power FETs can carry a large current between their source and drain during "on" operation, can have low resistance from their source to their drain during "on" operation, and can withstand high voltages from their source to their drain during "off" operation. For example, a power FET can be characterized as being able to carry currents ranging from hundreds of milliamps (e.g., 500mA to 900mA) to several amperes (e.g., 3A to 5A or higher) across their source and drain, and withstand voltages ranging from 12V to 40V (or higher). For example, the resistance between the source and drain of a power FET device can be very small to prevent, for example, power losses on the device. The examples, implementations, and embodiments disclosed herein may use different types of FETs, such as metal-oxide FETs (MOSFETs), nFETs (e.g., N-type MOSFETs), pFETs (e.g., P-type MOSFETs), etc.

[0021] The use of vertical FETs is a relatively new trend in integrated circuit design. Compared to traditional lateral FET designs, vertical FETs offer several advantages, such as higher current density, improved thermal performance, smaller device size, and higher die area efficiency. Due to these advantages, vertical FETs are beneficial for high-density integrated circuits. However, vertical FETs face additional challenges in temperature sensing.

[0022] In some implementations, temperature is sensed using a PN junction diode fabricated very close to the power FET within the power FET die. Due to the linear temperature behavior of the PN junction diode, its forward voltage (VF) under given operating conditions is directly related to its temperature. Therefore, the temperature of the PN junction diode can be determined by measuring the voltage drop across it.

[0023] Typically, for power FETs, the source and body terminals are indistinguishable. The PN junction then becomes the drain terminal and the source / body terminal. However, to achieve this temperature sensing, the method involves measuring the voltage across the drain and body terminals. Accessing these nodes of a power FET is relatively straightforward using lateral FETs, but difficult using vertical FETs. If a back-to-back power FET with a common drain is implemented using vertical FET technology, conventional temperature sensing methods would require various processing technology changes or new custom packaging modifications to enable access to the common drain (e.g., back-side metallization of each die). However, such technology changes would increase costs and could even require new development cycles, which could be very expensive and time-consuming.

[0024] To address these and other shortcomings of conventional temperature sensing in power FET devices, the techniques described herein provide temperature sensing techniques for common-drain dual power FET devices with vertical FETs. The power FET device according to embodiments includes dual power FETs arranged in series and sharing a common drain node (i.e., back-to-back). A temperature-sensing diode (e.g., in the form of a scaled PN junction) is coupled to the common drain node. The anode of the diode is coupled to a temperature-sensing terminal, thereby enabling direct measurement of the voltage at the anode. The cathode of the temperature-sensing diode is coupled to the common drain between the power FETs. Various techniques are described herein that enable determination of the voltage at the common drain node, although without direct access to the drain node.

[0025] In some implementations, the voltage at the drain node is determined by measuring the voltage drop across a power path that includes an input terminal coupled to the source of a first power FET and an output terminal coupled to the source of a second power FET. As long as both FETs operate as switches in the linear region, where their gate-to-source voltages are significantly higher than their threshold voltages, the voltage drop across each FET will be equal, and the voltages across the input and output terminals can be measured and averaged to determine the voltage at the drain node.

[0026] In some implementations, the voltage at the drain node is accessed via a replicated FET. A power FET device may include one or more replicated FETs fabricated within the same die, wherein the drain of each replicated FET is coupled to the common drain node of the two power FETs. Various replicated FETs can be implemented to achieve a variety of current sensing and voltage sensing features. One of the replicated FETs (referred to herein as a temperature sensing FET) is used to provide a sense voltage representing the voltage at the common drain node.

[0027] Each of these techniques for measuring the voltage at the drain has its own advantages and disadvantages. For example, sensing voltage by replicating the voltage drop across the power FET presents accuracy challenges due to the voltage drop across the FET. In contrast, voltage averaging techniques will be highly accurate as long as both power FETs operate in the linear region. However, in some cases, a current-limiting scheme can be used to reduce the gate drive signal supplied to one of the power FETs. This increases the resistance of the affected power FET and limits the load current to a specified maximum current level. However, the affected power FET will no longer operate in the linear region. Therefore, the voltage drops across the power FETs will no longer be equal, and voltage averaging will no longer provide an accurate reading of the drain voltage.

[0028] To address these drawbacks, two temperature sensing technologies can be implemented within the same package. When current limiting is not in effect, voltage averaging can be used to determine the drain voltage. When current limiting is in effect, the drain voltage can be measured by replicating the FET.

[0029] Implementations of this technology also provide improvements in the fabrication of temperature-sensing diodes. In some embodiments, the PN junction diode is fabricated as an additional replicated FET with gate and source terminals coupled together. In this configuration, the drain-to-body junction of the replicated FET operates as a PN junction diode. Fabricating a PN junction diode as a replicated FET reduces manufacturing costs compared to an explicit PN junction diode because it utilizes existing processes and masks.

[0030] The sensed voltage across the temperature sensing diode can be digitized and processed (e.g., by an IC controller) to determine the temperature of the power FET. The sensed temperature can be used (e.g., by firmware) to manage or interrupt the load current to prevent overheating.

[0031] In some embodiments, the techniques described herein provide for implementing such power FET devices using vertical FET technology, thereby improving power efficiency while enabling the delivery and control of higher currents than lateral FETs. However, it should be understood that while the disclosed techniques may be particularly well-suited for power FET devices comprising back-to-back vertical FETs with a common drain, the disclosed techniques are not limited to such embodiments. For example, the disclosed techniques can also be used with FET devices using a single power FET instead of dual power FETs and with lateral FETs.

[0032] In some implementations, the techniques described herein also enable the implementation of such power FET devices and IC controller dies in SiP packages or dual-chip modules. In some USB-enabled implementations, the techniques described herein conform to common footprint definitions, thereby making such implementations easy for vendors to design into various electronic devices such as laptops and notebooks.

[0033] Figure 1 A circuit block diagram of a device 100 for temperature sensing in a common-drain power FET device 102, according to some example embodiments of the present disclosure, is shown. The device 100 may include a power FET device 102 and a temperature sensing circuit 104. In some embodiments, the power FET device 102 and the temperature sensing circuit 104 may be instantiated on a separate die and packaged in a single chip carrier package as a system-in-package (SiP) device.

[0034] The power FET device 102 is a power switch instantiated on a single die, comprising two power FETs 106A and 106B connected in series between power terminals 108A and 108B. According to the technique described herein, the power FETs 106A and 106B are arranged back-to-back within the power FET device 102, therefore, in operation, as depicted, the load current I... L The bus voltage VBUS flows to load 112. Additionally, the drain of power FET 106 is connected to share a common drain node 120. The voltage at the common drain 120 may be referred to herein as V112. DRAIN .

[0035] During operation, the gates 110A and 110B of power FET 106 are controlled by gate drivers (not shown) to turn on power FETs 106A and 106B, thereby connecting the bus voltage VBUS to load 112 to supply current to load 112. In some embodiments, the magnitude of the bus voltage may be determined according to a power delivery (PD) contract as described above. Power FET device 102 is depicted to operate in power delivery mode, in which case terminal 108A may be referred to as input terminal 108A and terminal 108B may be referred to as output terminal 108B. However, power FET device 102 may also be configured to operate in power receiving mode, in which case the current through power FETs 106A and 106B will be relative to... Figure 1 In the opposite direction shown in the diagram.

[0036] The power FET device 102 also includes a temperature sensing diode 114. Figure 1In the embodiment shown, the temperature sensing diode 114 is a replicated FET with its source and gate coupled together by a conductor. The replicated FET 108 is an area-scaled version of the power FETs 106A and 106B. Due to the body diode 116 (also referred to as the body diode) formed as an intrinsic diode in the FET, as... Figure 1 The source and gate are coupled together, enabling the replicated FET to operate as a PN junction diode. It should be understood that any suitable type of PN junction diode can be used to implement the temperature sensing diode 114, including other types of diode-connected transistors (e.g., bipolar junction transistors with collector and base coupled together), standard PN junction diodes, and other configurations.

[0037] The cathode of the temperature sensing diode 114 (i.e., the drain of the replicated FET) is coupled to a common drain node 120, which can be accessed by fabricating the replicated FET in linear mode or using a simple contact mask. The anode of the temperature sensing diode 114 is coupled to the temperature sensing terminal 118 of the power FET device 102.

[0038] Temperature sensing circuit 104 includes current source 122 configured to provide a constant current of known value to temperature sensing diode 114 through temperature sensing terminal 118. Temperature sensing terminal 118 is also coupled to input of comparator 124 configured to determine the voltage difference between temperature sensing terminal 118 and common drain node 120. The voltage at temperature sensing terminal 118 may be referred to herein as V. DIODE The difference between the voltage at the temperature sensing terminal 118 and the voltage at the common drain 120 is equal to the voltage drop across the temperature sensing diode 114.

[0039] To determine the voltage at the common drain node 120, power terminals 108A and 108B are coupled to a voltage averaging circuit 126, which generates the input voltage (V) at input terminal 108A. IN ) and the output voltage (V) at output terminal 108B OUT The average value of the voltage is then used as the drain voltage to determine the voltage drop across the temperature sensing diode.

[0040] The voltage averaging circuit 126 may include any suitable type of circuit for generating the average of two voltages. For example, the voltage averaging circuit 126 may be a resistor ladder circuit (e.g., a voltage divider) consisting of two resistors with equal resistance R, wherein power terminals 108A and 108B are coupled to opposite ends of the resistor ladder circuit. Figure 3An embodiment of a voltage averaging circuit 126, including a resistor ladder circuit, is shown. If the voltage drops across the two power FETs 106A and 106B are the same, the average voltage output by the voltage averaging circuit 126 will be equal to the drain voltage V. DRAIN The drain voltage can be coupled to the input of comparator 124. It should be understood that other techniques can be used to generate the average voltage. For example, in some implementations, the input and output voltages can be converted into digital values, and averaging can be performed in the digital domain. Therefore, the voltage averaging circuit 126 can be implemented with one or more analog-to-digital converters, digital signal processors, microcontrollers, and combinations thereof.

[0041] Comparator 124 receives two input voltages V DIODE and V DRAIN The voltage drop across the temperature sensing diode 114 is then determined. This voltage drop can then be correlated with an equivalent temperature value. Comparator 124 can include any suitable combination of circuitry for performing the operations described herein. Figure 3 A more detailed example of the comparator is shown below. In some implementations, an analog-to-digital converter (not shown) can be used to digitize and process the voltage drop across the measured temperature sensing diode 114 to obtain a digital value of the temperature. The detected temperature value can be used, for example, in a feedback loop to control the bus voltage (VBUS) and / or the gate driver (not shown) to limit or terminate the load current to avoid overheating.

[0042] It should be understood that Figure 1 The circuit depicted is an example of temperature sensing technology according to an embodiment, and various modifications can be made without departing from the scope of the claims. Figure 2 and Figure 3 Other embodiments of this technology are further described.

[0043] Figure 2 A circuit block diagram of another device 200 for temperature sensing in a common-drain power FET device 102, according to some example embodiments of the present disclosure, is shown. Device 200 may include power FET device 202 and temperature sensing circuitry 204. Figure 2 The power FET device 202 shown is similar to Figure 1 The power FET device 202 includes a replicated FET 206. The replicated FET 206 is an area-scaled version of the power FETs 106A and 106B and is used to provide access to the voltage at drain 120. The drain of the replicated FET 206 is coupled to a common drain node 120, and the source of the replicated FET 206 is coupled to the voltage sensing terminal 212 of the power FET device 202.

[0044] exist Figure 2 In the example shown, the gates of the power FET 106A and the replica FET 206 may each have separate gate terminals 110A and 210, respectively. However, in some embodiments, the gate of the power FET 106A is internally connected to the gate of the replica FET 206, such that they share a common gate terminal. It should also be understood that the power FET device 202 may include... Figure 2 Additional replica FETs not shown.

[0045] Temperature sensing based on the above... Figure 1 The same principle applies as described. Current source 122 drives a specified current of known value through temperature sensing diode 114, and measures the voltage drop across temperature sensing diode 114 and converts it into temperature. Figure 1 As shown, the voltage (V) at the temperature sensing terminal 118 DIODE The drain voltage 120 is directly measured by comparator 124. However, the drain voltage 120 is accessed via a replicated FET 206. Activation of the replicated FET 206 couples the drain node 120 to the voltage sensing terminal 212, which is coupled to the input of comparator 124. Comparator 124 receives two input voltages V. DIODE and V DRAIN The voltage drop across the temperature sensing diode 114 is determined and converted into the corresponding temperature.

[0046] It should be understood that Figure 2 The circuit depicted is an example of temperature sensing technology according to an embodiment, and various modifications may be made without departing from the scope of the claims.

[0047] Figure 3 A more detailed circuit block diagram of a temperature sensing device 300 for a common-drain power FET device 302, according to some example embodiments of the present disclosure, is shown. The device 300 may include components configured to perform the above-described... Figure 1 and Figure 2 The power FET device 302 and temperature sensing circuit 304 describe two temperature sensing technologies.

[0048] Figure 3 The power FET device 302 shown is similar to Figure 2The power FET device 202, in addition to power FET device 302 including additional replicated FETs. Specifically, power FET device 302 includes replicated FETs 308A and 308B, which can be used to sense the voltage at drain node 120. Power FET device 302 includes replicated FETs 306A and 306B that can be used for additional applications (e.g., current sensing, etc.) beyond the scope of this disclosure. Any number of additional replicated FETs may also be included.

[0049] Although not shown, the replicated FET may also include a corresponding body diode. The drain of each of the replicated FETs (including the replicated FET for the temperature sensing diode 114, and replicated FETs 306A, 306B, 308A, and 308B) is coupled to the same common drain node 120 as the two power FETs 106A and 106B. Therefore, all seven FETs in the power FET device 302 share a common drain. The common drain node 120 can be accessed by fabricating the replicated FETs in a linear pattern or using a simple contact mask.

[0050] In addition, Figure 3 In the example shown, the gate of power FET 106A is internally connected to the gates of replica FETs 306A and 308A, such that they share a common gate terminal 310A. Similarly, the gate of power FET 106B is internally connected to the gates of replica FETs 306B and 308B, such that they share a common gate terminal 310B. For simplicity, conductive connections between the respective gates are not shown. For the purposes of this description, power FET 106A may be referred to as input power FET 106A, and power FET 106B may be referred to as output power FET 106B.

[0051] Device 300 combines the above-mentioned... Figure 1 and Figure 2 The temperature sensing technology described is used to measure the voltage (V) at drain node 120. DRAIN The technology used varies depending on whether a current limit is being implemented. Although not shown, device 300 may also be coupled to or include a circuit system for limiting the current through power FET device 302. For example, in USB-enabled applications, the current limit is dynamically determined by a PD contract established between the provider and the consumer. In such applications, the current limit can be determined using appropriate firmware-controlled and / or programmable circuitry (e.g., circuitry with a controllable current source).

[0052] In some implementations, current limiting can be achieved by limiting the magnitude of the gate signal supplied to one of the gate terminals (e.g., gate terminal 310B). This, in turn, increases the resistance of the output power FET 106B and reduces the load current I. L The current is limited to a specified maximum current level. In this way, the current through the output power FET 106B is limited, which also effectively limits the current through the power FET device 302. Simultaneously, the gate signal supplied to the gate terminal 310A is unaffected by the current-limiting circuitry. Therefore, the input power FET 106A and the output power FET 106B will not operate in the same way and will not have equal drain-to-source voltage drops. The drain-to-source voltage drop on the output power FET 106B will be higher because it no longer operates in the linear region.

[0053] Such as about Figure 2 As described, when current limiting is in effect, the drain voltage can be sensed by replicating FET 308A. To receive the drain voltage from replicating FET 308A, switch 312B is closed and switch 312A is open.

[0054] If current limiting is not applied, the voltage across the power path (i.e., input terminal 108A (V)) can be adjusted. IN ) and output terminal 108B (V OUT The drain voltage (V) is sensed by averaging the voltages between them. DRAIN Voltage average can be derived from... Figure 1 The voltage averaging circuit 126 shown is executed. Figure 3 In the illustrated embodiment, the voltage averaging circuit is a resistor ladder circuit (e.g., a voltage divider) consisting of two resistors 326 with equal resistance R, wherein power terminals 108A and 108B are coupled to opposite ends of the resistor ladder circuit. The resistance R of the resistors 326 can be several times larger than the resistance of the power FETs 106A to 106B (e.g., 500 ohms or greater). The voltage at the center of the resistor ladder circuit (i.e., between resistors 326) will be the voltage at the input terminal 108A (V). IN ) and the voltage (V) at output terminal 108B OUT The average value of ). If the voltage drop across the two power FETs 106A and 106B is the same, the voltage at the center of the resistor ladder circuit will be the same as the drain voltage V. DRAIN Same. The drain voltage can be coupled to the input of comparator 124.

[0055] For simplicity, the conductive connection between the voltage ladder circuit and output terminal 108B is not shown. However, it should be understood that output terminal 108B, as... Figure 1The circuit is coupled to a resistor ladder circuit. To receive the drain voltage from the voltage ladder circuit, switch 312B is open and switch 312A is closed. Additionally, in some embodiments, such as... Figure 3 As shown, the resistor ladder circuit may include a pair of switches 324 coupled between resistors 326. When the resistor ladder circuit is not in use, resistors 324 can be used to prevent current from flowing between input terminal 108A and output terminal 108B. Switches 324 can be open when switch 312A is open and closed when switch 312A is closed.

[0056] Figure 3 It also shows about Figure 1 and Figure 2 Additional details of the example implementation of comparator 124 shown in the figure. The voltage (V) sensed at the temperature sensing terminal. DIODE The voltage V is transferred from FET 314 to unity-gain voltage buffer 316. The output of voltage buffer 316 is coupled to the inverting input of operational amplifier 322 via resistor R1. DRAIN The voltage is transferred from FET 318 to another unity-gain voltage buffer 320, the output of which is coupled to the non-inverting input of operational amplifier 322. Unity-gain voltage buffers 316 and 320 transfer the corresponding voltage to the input of operational amplifier 322 while presenting a high input impedance, so that the temperature sensing circuit 304 does not load the circuit system of power FET device 302.

[0057] Operational amplifier 322 is configured as a closed-loop amplifier such that the current I through resistor R2 will be equal to (V DIODE -V DRAIN The voltage across the sensing resistor (R2) can be measured and used as an indication of the voltage drop across the temperature sensing diode 114. In some embodiments, an analog-to-digital converter (not shown) can be used to digitize and process the voltage across the sensing resistor (R2) to obtain a numerical value of the detected temperature.

[0058] The power FET device 302 can also be configured to operate in a power receiving mode, in which case the current through the power FETs 106A and 106B will be relative to... Figure 3In the opposite direction shown. If the power FET device 302 is operating in power receiving mode, some functions can be swapped on the power FET device 302. For example, current limiting can be performed on the power FET 106A, which will become the output power FET. Alternatively, if current limiting is in effect, the drain voltage can be sensed by replicating the FET 308B. Therefore, it should be understood that the source terminal of the replica FET 308B can be coupled to the temperature sensing circuit 304 using additional conductors and switches.

[0059] It should be understood that Figure 3 The circuit depicted is an example of temperature sensing technology according to an embodiment, and various modifications may be made without departing from the scope of the claims.

[0060] Figure 4 An example structure of a vertical FET 400 according to some implementations is shown. Figure 4 The vertical FET 400 shown can be referred to as a trench MOSFET. However, the current technology can be applied to any type of vertical FET, including vertical MOSFETs (VMOS), vertical diffused MOSFETs (VDMOS), etc. Furthermore, the implementation of the disclosed technology is not limited to this. Figure 4 The specific layout shown is as follows: Figure 4 Only one example of a vertical FET technology that can benefit from the disclosed technology is provided.

[0061] like Figure 4 As shown, source 402 and gate 404 are disposed on the top surface of vertical FET 400, and drain 406 is disposed on the bottom surface of the opposite side of the bulk semiconductor substrate of vertical FET 400, compared to source 402 and gate 404. Current flows vertically from source 402 to drain 406, as indicated by arrow 419. Typically, any additional vertical FETs fabricated in the same die will have their drain 406 oriented in a similar manner on the bottom surface. Because drain 406 is located on the same semiconductor layer as the drain of any adjacent vertical FET, fabricating two or more vertical FETs with shared connections / common drains is relatively simple and cost-effective. Compared to lateral FETs, vertical FETs, for example... Figure 4 The vertical FET depicted uses far less lateral area. Therefore, such a vertical FET is well-suited for integrated circuit applications that benefit from higher circuit density.

[0062] However, because the drains of vertical FETs are coupled to each other on the back side of the die, the drains may not be accessible without additional processing (e.g., backside metallization and / or developing additional masks and structures to bring the drain connections to the top of the die). Such a process can add significant additional costs to IC chip manufacturing. Implementations of the techniques disclosed herein achieve temperature sensing technology that does not require access to the drains, or achieves drain access in a relatively cost-effective manner using scaled-down versions of other components on the die.

[0063] Figure 5 This is a block diagram illustrating an IC controller 500 according to some embodiments. The IC controller 500 can be configured as a USB-PD controller, working alongside power FET semiconductor devices in the provider and / or consumer power path. The IC controller 500 may include a peripheral subsystem 510, which includes components for USB-PD power delivery. The peripheral subsystem 510 may include a peripheral interconnect 511, which includes a clock module—a peripheral clock (PCLK) 512—for providing clock signals to the various components of the peripheral subsystem 510. The peripheral interconnect 511 may be a peripheral bus, such as a single-level or multi-level Advanced High-Performance Bus (AHB), and may provide a data and control interface between the peripheral subsystem 510, the CPU subsystem 530, and system resources 540. The peripheral interconnect 511 may include controller circuitry, such as a Direct Memory Access (DMA) controller, which can be programmed to transfer data between peripheral blocks without input, control, or burden on the CPU subsystem 530.

[0064] Peripheral interconnects 511 can be used to couple components of the peripheral subsystem 510 to other components of the IC controller 500. Coupled to the peripheral interconnects 511 can be multiple general purpose input / output (GPIO) 515s for transmitting and receiving signals. GPIO 515s may include circuitry configured to implement various functions (e.g., pull-up, pull-down, input threshold selection, input and output buffer enable / disable, single-multiplexing, etc.). Other functions may also be implemented by GPIO 515s. One or more timer / counter / pulse width modulator (TCPWM) 517s may also be coupled to the peripheral interconnects and include circuitry for implementing timing circuitry (timers), counters, pulse width modulator (PWM) decoders, and other digital functions that can operate on I / O signals and provide digital signals to system components of the IC controller 500. The peripheral subsystem 510 may also include one or more serial communication blocks (SCBs) 519 for implementing a serial communication interface, such as an internal integrated circuit (I2C), a serial peripheral interface (SPI), a universal asynchronous receiver / transmitter (UART), a controller area network (CAN), a clock extended peripheral interface (CXPI), etc.

[0065] The peripheral subsystem 510 may include a USB power delivery subsystem 520, which is coupled to a peripheral interconnect and includes a set of USB-PD modules 521 for USB power delivery. The USB-PD modules 521 may be coupled to the peripheral interconnect 511 via a USB-PD interconnect 523. USB-PD module 521 may include: an analog-to-digital converter (ADC) module for converting various analog signals into digital signals; an error amplifier (AMP) for regulating the output voltage on the VBUS line according to the PD contract; a high-voltage (HV) regulator for converting the power supply voltage into an accurate voltage (e.g., 3.5V to 5V) for the power IC controller 500; a high-side or low-side current sensing amplifier (LSCSA) for accurately measuring the load current; an overvoltage protection (OVP) module and an overcurrent protection (OCP) module for providing overcurrent and overvoltage protection on the VBUS line with configurable thresholds and response times; one or more gate drivers for external power field-effect transistors (FETs) used in USB power delivery in provider and / or consumer configurations; and a communication channel PHY (CC BB PHY) module for supporting communication on the USB-C communication channel (CC) line. USB-PD module 521 may also include: a charger detection module for determining the presence of a charging circuit and coupling the charging circuit to the IC controller 500; and a VBUS discharge module for controlling the discharge of the voltage on the VBUS line. The discharge control module can be configured to couple to a power node or an output (power consumer) node on the VBUS line and discharge the voltage on the VBUS line to a desired voltage level (i.e., the voltage level negotiated in the PD contract). The USB power delivery subsystem 520 may also include pads 527 for external connections and electrostatic discharge (ESD) protection circuitry 529, which may be required on the Type-C port. The USB-PD module 521 may also include a bidirectional communication module for supporting bidirectional communication with another controller.

[0066] GPIO 515, TCPWM 517, and SCB 519 can be coupled to input / output (I / O) subsystem 550, which may include a high-speed (HS) I / O matrix 551 coupled to multiple GPIO 553. GPIO 515, TCPWM 517, and SCB 519 can be coupled to GPIO 553 via HSI / O matrix 551.

[0067] The IC controller 500 may also include a central processing unit (CPU) subsystem 530 for processing commands, stored program information, and data. The CPU subsystem 530 may include one or more processing units 531 for executing instructions and reading from and writing to memory locations from multiple memories. The processing units 531 may be processors suitable for operation in an integrated circuit (IC) or system-on-a-chip (SOC) device. In some embodiments, extended clock gating may be used to optimize the processing unit 531 for low-power operation. In this embodiment, various internal control circuitry may be implemented for operation of the processing unit in various power states. For example, the processing unit 531 may include a wake-up interrupt controller (WIC) configured to wake the processing unit from a sleep state, thereby enabling power cut-off when the IC or SOC is in a sleep state. The CPU subsystem 530 may include one or more memories, including flash memory 533, static random access memory (SRAM) 535, and read-only memory (ROM) 537. Flash memory 533 may be a non-volatile memory (NAND flash, NOR flash, etc.) configured to store data, programs, and / or other firmware instructions. Flash memory 533 may include a read accelerator and may improve access time by integration within CPU subsystem 530. SRAM 535 may be a volatile memory configured to store data and firmware instructions accessible by processing unit 531. ROM 537 may be configured to store boot routines, configuration parameters, and other firmware parameters and settings that do not change during operation of IC controller 500. SRAM 535 and ROM 537 may have associated control circuitry. Processing unit 531 and memory may be coupled to system interconnect 539 to route signals to and from various components of CPU subsystem 530 to other blocks or modules of IC controller 500. System interconnect 539 may be implemented as, for example, a single-level or multi-level AHB system bus. System interconnect 539 may be configured as an interface that couples various components of CPU subsystem 530 to each other. System interconnect 539 can be coupled to peripheral interconnect 511 to provide a signal path between components of CPU subsystem 530 and peripheral subsystem 510.

[0068] IC controller 500 may also include multiple system resources 540, including a power module 541, a clock module 543, a reset module 545, and a test module 547. Power module 541 may include a sleep control module, a wake-up interrupt control (WIC) module, a power-on reset (POR) module, multiple voltage references (REF), and a power system (PWRSYS) module. In some embodiments, power module 541 may include circuitry that enables IC controller 500 to draw power from and / or supply power to external sources at different voltage and / or current levels and supports operation of the controller in different power states, such as active, low-power, or sleep. In various embodiments, more power states can be implemented as IC controller 500 slows down operation to achieve desired power consumption or output. Clock module 543 may include a clock control module, a watchdog timer (WDT), and an internal low-speed oscillator (I0). L The reset module 545 may include a reset control module and an external reset (XRES) module. The test module 547 may include modules for controlling and entering test modes, as well as test control modules for analog and digital functions (digital test and analog DFT).

[0069] In some implementations, the IC controller 500 can be implemented in a single (e.g., a single) semiconductor die. According to the techniques described herein, in some implementations, the IC controller 500 die is disposed together with a power FET semiconductor die in a single package as a SiP or a single multi-chip module. The power FET die includes two back-to-back power FETs having a connected / common drain. The power FET die may also include a temperature sensing diode coupled to the common drain and used to determine the temperature of the power FET. The power FET die may also include a corresponding replica FET for sensing the voltage at the common drain. In such an implementation, the peripheral subsystem 510 of the IC controller 500 includes one or more gate drivers (via corresponding terminals) coupled to the FETs of the power FET die to control the power FETs therein in a provider or consumer configuration according to the techniques described herein, and to activate the temperature sensing diode for voltage / temperature sensing operation. Additionally, the peripheral subsystem 510 of the IC controller 500 may include... Figures 1 to 3 Any of the temperature sensing circuits 104, 204, and 304 described. For example, temperature sensing circuits 104, 204, and 304 may be components of the USB-PD module 521.

[0070] Figure 6This is a block diagram illustrating a system-in-package (SiP) 600 that includes an IC controller 500 and a power FET device 602 within a single package, according to some embodiments. The power FET device 602 may be as described above. Figures 1 to 3 Any of the power FET devices 102, 202, and 302 described herein. According to the techniques described herein, within the SiP 600, various terminals of the IC controller 500 are coupled to terminals of the power FET device 602 via multiple metal lines (or buses). As shown, multiple pins of the SiP 600 may be coupled to other components of the power path 604. In various implementations, the power path 604 may be a provider power path (e.g., for providing power to a consumer) or a consumer power path (e.g., for receiving power from a provider).

[0071] In the above description, some technical details are presented based on the algorithms and symbolic representations of operations performed within firmware and / or computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Here, an algorithm is generally conceived as a self-consistent sequence of steps that produce a desired result. These steps require physical operations on physical quantities. Although not mandatory, these quantities are often in the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. It has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc., primarily for general reasons.

[0072] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise explicitly stated, it is evident from the above discussion that, throughout the description, the use of terms such as “determine,” “allocate,” “dynamically allocate,” “redistribute,” “ignore,” “reassign,” “detect,” “execute,” “polling,” “register,” “monitor,” etc., refers to the actions and processes of a device or similar electronic system that manipulate and convert data representing physical (e.g., electronic) quantities in the system’s registers or memory into other data similarly represented in the system’s memory or registers.

[0073] The terms “example” or “exemplary” are used herein to mean as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or becomes clear from the context, “X comprises A or B” is intended to mean any natural substitution of inclusion. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied in any of the foregoing cases. Additionally, unless otherwise specified or clearly indicated by the context to be a singular form, the articles “a” and “an” as used in this application and claims should generally be interpreted as “one or more.” Furthermore, the use of the terms “implementation” or “an implementation” or “implementation” or “one embodiment” throughout the text is not intended to mean the same implementation or implementation unless so described.

[0074] The embodiments described herein may also relate to means for performing the operations described herein. Such means may be specifically constructed for the intended purpose (e.g., application-specific integrated circuit, ASIC), or may be an integrated circuit (IC) including a CPU subsystem capable of executing instructions stored as firmware in a non-transitory computer-readable storage medium. Such non-transitory computer-readable storage media may include, but is not limited to, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered to include a single medium storing one or more sets of instructions. The term "computer-readable medium" should also be considered to include any medium capable of storing, encoding, or carrying a set of instructions that is executed by the means and causes the means to perform any or more of the methods of this embodiment.

[0075] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of several embodiments of this disclosure. It should be understood that the foregoing description is intended to be illustrative and not restrictive. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the foregoing description. Therefore, the scope of this disclosure should be determined by reference to the claims and the full scope of their equivalents.

Claims

1. An apparatus comprising: A power field-effect transistor (FET) device instantiated on a first die, the power FET device comprising: A first power FET is coupled to a first power terminal of the first die; A second power FET, disposed back-to-back with the first power FET and coupled to a second power terminal of the first die, wherein the first power FET and the second power FET are connected to a common drain node within the first die; and A temperature sensing diode includes a cathode coupled to the common drain node; and a temperature sensing circuit coupled to the power FET device and configured to determine the temperatures of the first power FET and the second power FET based on a voltage drop across the temperature sensing diode, the temperature sensing circuit including a voltage averaging circuit coupled to a first voltage at the first power terminal and a second voltage at the second power terminal, wherein the temperature sensing circuit is configured to average the first voltage and the second voltage to generate a drain voltage representing the voltage of the common drain node.

2. The apparatus according to claim 1, wherein, The voltage averaging circuit includes a resistor trapezoidal circuit, which includes a pair of resistors with equal resistance, wherein the first power terminal is coupled to a first end of the resistor trapezoidal circuit, and the second power terminal is coupled to a second end of the resistor trapezoidal circuit.

3. The apparatus according to claim 1, wherein, When both the first power FET and the second power FET are operating in the linear region, the drain voltage provided by the voltage averaging circuit is used to determine the voltage drop across the temperature sensing diode.

4. The apparatus according to claim 1, wherein, The power FET device further includes a replica FET, wherein the source of the replica FET is coupled to a voltage sensing terminal of the first die, and the drain of the replica FET is coupled to the common drain node, wherein the replica FET is configured to provide the drain voltage to the temperature sensing circuit through the voltage sensing terminal.

5. The apparatus according to claim 4, wherein, If the first power FET or the second power FET is not operating in the linear region, the drain voltage provided by the replica FET is used to determine the voltage drop across the temperature sensing diode.

6. The apparatus of claim 4, wherein the temperature sensing circuit further comprises a set of switches, the set of switches being configured to: When the current limit is not activated, the drain voltage provided by the voltage averaging circuit is coupled to the comparator; and When current limiting is activated, the drain voltage provided by the replicated FET is coupled to the comparator.

7. The apparatus according to claim 1, wherein, The temperature sensing diode includes a replicated FET, wherein the source and gate of the replicated FET are coupled together, and the drain of the replicated FET is coupled to the common drain node.

8. The apparatus according to claim 2, wherein, The temperature sensing circuit is included in an integrated circuit (IC) controller instantiated on the second die.

9. The apparatus according to claim 8, wherein, The IC controller is configured as a Universal Serial Bus Power Delivery (USB-PD) controller.

10. The apparatus according to claim 8, wherein, The power FET device and the IC controller are housed within a single semiconductor package as a system-in-package (SiP).

11. The apparatus according to claim 1, wherein, The first power FET and the second power FET are vertical FETs.

12. A power field-effect transistor (FET) device, comprising: A first power FET and a second power FET are arranged in series and electrically coupled through a common drain node, wherein the first power FET and the second power FET are configured to deliver an output current to a load in response to a first gate drive signal coupled to the first power FET through a first gate terminal of the power FET device and a second gate drive signal coupled to the second power FET through a second gate terminal of the power FET device; A temperature sensing diode for indicating the temperature of the first power FET and the second power FET, the temperature sensing diode including a cathode coupled to the common drain node and an anode coupled to a temperature sensing terminal; and A replica FET is used to provide a sensing voltage corresponding to the voltage of the common drain node, wherein the first power FET, the second power FET, and the replica FET are vertical FETs.

13. The power FET device according to claim 12, wherein, The gate of the replicated FET is conductively coupled to the first gate terminal of the first power FET.

14. The power FET device of claim 12, wherein, The replicating FET is A first replica FET, configured to provide a sense voltage corresponding to the voltage of the common drain node when the power FET device is operating in power provider mode, the power FET device further comprising: The second replica FET is used to provide a sensing voltage corresponding to the voltage of the common drain node when the power FET device is operating in power receiving mode.

15. The power FET device according to claim 12, wherein, The temperature sensing diode includes an additional replicated FET, wherein the source and gate of the additional replicated FET are coupled together, and the drain of the additional replicated FET is coupled to the common drain node.

16. The power FET device of claim 12, wherein, The power FET device is instantiated on a first die disposed within a semiconductor package, which is a system-in-package (SiP), wherein the semiconductor package further includes an integrated circuit (IC) controller instantiated on a second die.

17. The power FET device of claim 16, wherein, The integrated circuit (IC) controller also includes: A temperature sensing circuit is used to determine the temperature of the power FET device based on the voltage drop across the temperature sensing diode.

18. The power FET device of claim 17, wherein, When the current limiting is activated, the temperature sensing circuit is configured to: The voltage drop across the temperature sensing diode is determined by using the sensing voltage provided by the replicated FET as the voltage of the common drain node.

19. The power FET device of claim 17, wherein, When the current limit is not activated, the temperature sensing circuit is configured to: An average voltage is generated, the average voltage comprising the average of the input voltage at a first power terminal and the output voltage at a second power terminal, wherein the first power terminal is coupled to the source of the first power FET, and the second power terminal is coupled to the source of the second power FET; and The average voltage is used as the voltage across the common drain node to determine the voltage drop across the temperature sensing diode.

20. The power FET device of claim 16, wherein, The IC controller is configured as a Universal Serial Bus Power Delivery (USB-PD) controller.

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