Delay circuit, oscillator and soft start circuit
By using branch current mirror technology, the reference current is converted into multiple branch currents to charge the energy storage element. The delayed output is triggered by voltage comparison, which solves the problem of insufficient accuracy and stability of current mirrors in existing delay circuits and achieves higher accuracy and stability of delay circuits.
Patent Information
- Application Number
- CN202510959319.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-11
- Publication Date
- 2025-10-31
AI Technical Summary
The accuracy and stability of the current mirror in existing delay circuits have large deviations, making it difficult for the precision of the delay circuits to meet actual needs.
The reference current is converted into the main current using branch current mirror technology. The main current is then converted into multiple branch currents through a second current mirror module to charge the energy storage element. The action module compares the charging voltage with the reference voltage to trigger a delayed output signal.
This improves the charging current accuracy of the delay circuit, reduces the impact of temperature and process on current accuracy, and enhances the stability and precision of the delay circuit.
Smart Images
Figure CN120880417A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic circuit technology, and in particular to a delay circuit, an oscillator, and a soft-start circuit. Background Technology
[0002] In the design of analog chips such as switching power supplies, the huge surge current of a high-power amplifier at the moment of power-on can have a significant impact on the internal electronic components. Therefore, a soft-start delay circuit is usually designed in the chip to protect the internal electronic components.
[0003] In related technologies, existing delay circuits generally use traditional current mirrors. Specifically, the delay time is adjusted by generating an nA-level current through the current mirror to charge and discharge the energy storage element. However, due to the influence of manufacturing process, temperature, and other factors, the accuracy and stability of the nA-level current mirror have significant deviations, which makes it difficult for the precision of the delay circuit to meet actual needs. Summary of the Invention
[0004] This invention provides a delay circuit, an oscillator, and a soft-start circuit to solve the problem that the accuracy and stability of the current mirror in existing delay circuits are relatively large, resulting in low precision of the delay circuit.
[0005] On one hand, the present invention provides a delay circuit, including: a first current mirror module, a second current mirror module, an energy storage element, and an action module;
[0006] The first current mirror module, the second current mirror module, and the action module are all connected to the energy storage element, and the first current mirror module is also connected to the second current mirror module.
[0007] The first current mirror module is used to convert the reference current into the main current; the second current mirror module is used to convert the main current into multiple branch currents, and charge the energy storage element through the branch currents connected in series with the energy storage element; the action module is used to compare the charging voltage of the energy storage element with a preset reference voltage, and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
[0008] According to the delay circuit provided by the present invention, the first current mirror module includes: a current source, a first transistor, and a second transistor;
[0009] The positive terminal of the current source and the drain of the second transistor are both connected to the power supply VDD. The negative terminal of the current source is connected to the drain and the gate of the first transistor, respectively. The gate of the first transistor is connected to the gate of the second transistor. The source of the first transistor is grounded. The source of the second transistor is connected to the positive terminal of the energy storage element and the second current mirror module, respectively.
[0010] According to the delay circuit provided by the present invention, the second current mirror module includes: a current mirror core unit and an auxiliary capacitor;
[0011] The current mirror core unit is connected to the energy storage element and the first current mirror module respectively. The positive terminal of the auxiliary capacitor is connected to the current mirror core unit, and the negative terminal of the auxiliary capacitor is grounded.
[0012] The current mirror core unit is used to convert the main current into multiple branch currents.
[0013] The auxiliary capacitor is used to assist the energy storage element in being charged by the multiple branch currents.
[0014] According to the delay circuit provided by the present invention, the current mirror core unit includes: a current branch subunit and a bias control subunit;
[0015] The current branch subunit is connected to the energy storage element, the first current mirror module and the bias control subunit respectively;
[0016] The current branching subunit is used to split the main current into multiple branch currents, and the bias control subunit is used to regulate the multiple branch currents according to the charging conditions of the energy storage element.
[0017] According to the delay circuit provided by the present invention, the current branch subunit includes: a third transistor, a fourth transistor, and a fifth transistor;
[0018] The gate of the fourth transistor is connected to the gate of the third transistor and the gate of the fifth transistor, respectively. The source of the third transistor is grounded. The drains of the fourth transistor and the fifth transistor are both connected to the positive terminal of the energy storage element and the first current mirror module. The sources of the fourth transistor and the fifth transistor are both connected to the bias control subunit.
[0019] According to the delay circuit provided by the present invention, the bias control subunit includes: a sixth transistor and a seventh transistor;
[0020] The drain of the sixth transistor and the drain of the seventh transistor are connected to the current branch subunit, and the source of the sixth transistor and the source of the seventh transistor are both grounded.
[0021] According to the delay circuit provided by the present invention, the action module includes: a discharge unit and a comparator;
[0022] Both the discharge unit and the comparator are connected to the energy storage element;
[0023] The discharge unit is used to provide a discharge path for the energy storage element, and the comparator is used to compare the charging voltage of the energy storage element with a preset reference voltage, and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
[0024] According to the delay circuit provided by the present invention, the discharge unit includes: an eighth transistor and a ninth transistor;
[0025] The drain of the eighth transistor is connected to the first current mirror module, the source of the eighth transistor and the source of the ninth transistor are both grounded, and the drain of the ninth transistor is connected to the negative terminal of the energy storage element.
[0026] On the other hand, the present invention also provides an oscillator including any of the delay circuits described above.
[0027] On the other hand, the present invention also provides a soft-start circuit, including any of the delay circuits described above.
[0028] The delay circuit, oscillator, and soft-start circuit provided by this invention convert a reference current into a main current through a first current mirror module, and then converts the main current into multiple branch currents through a second current mirror module. The branch currents, connected in series with the energy storage element, charge the energy storage element. Finally, an action module compares the charging voltage of the energy storage element with a preset reference voltage, and triggers a delay output signal when the charging voltage is higher than the reference voltage. This invention uses a branch current mirror method to divide a complete main current into multiple branch currents. Since the main current is obtained from a zero-temperature-drift reference current, when the reference current is stable, the generated branch currents and other shunt currents will change proportionally with temperature and process variations, thus avoiding large current fluctuations. This improves the accuracy of the charging current in the delay circuit, thereby improving timing accuracy and mitigating the impact of temperature on current accuracy. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0030] Figure 1 This is the circuit schematic corresponding to the existing delay circuit;
[0031] Figure 2 This is a structural block diagram of the delay circuit provided in the embodiments of the present invention;
[0032] Figure 3 This is a schematic diagram of the circuit principle corresponding to the delay circuit provided in the embodiment of the present invention;
[0033] Figure 4 This is a schematic diagram of the simulation results obtained by simulating the improved delay circuit and the traditional delay circuit provided in this embodiment under the same simulation scenario;
[0034] Figure 5 This is a schematic diagram of the circuit principle of the oscillator provided in an embodiment of the present invention;
[0035] Figure 6 This is a schematic diagram of the circuit principle of the soft-start circuit provided in an embodiment of the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.
[0037] This embodiment relates to the field of electronic circuits, and can be specifically applied to the structural design of soft-start delay circuits. Existing delay circuits generally use traditional current mirrors for implementation; for a detailed circuit schematic, please refer to [reference needed]. Figure 1 ,like Figure 1 As shown, this delay circuit uses a current mirror composed of transistors Ma and Mo. A reference current I1 with zero temperature drift is provided by a current source, and a charging current I2 is obtained through the current mirror. The charging current I2 charges capacitor C. The formula for calculating the delay time is as follows:
[0038]
[0039] Among them, T D It is the delay duration, VDD I is the power supply voltage, I2 is the charging current, and C is the charging capacitor.
[0040] According to the above formula, the delay duration is determined by the charging capacitance of capacitor C and the charging current I2. Transistor Mc provides a discharge path for capacitor C. When transistor Mc is off, the charging current I2 charges capacitor C. When transistor Mc is on, capacitor C discharges through the path from transistor Mc to ground. During the charging process, since the voltage across capacitor C cannot change abruptly, the potential of capacitor C gradually increases. Using the potential of capacitor C and the reference potential Vref as the positive and negative inputs of comparator Uo, respectively, the soft-start delay function is achieved.
[0041] The delay duration satisfies T D =1ms or T D For example, with a capacitance of 500ns, the capacitance C = 4pF, and the voltage V... DD =5V. T D = 1ms, the required charging current I2 is 20nA; T D At 500ns, a current I2 of 40nA is required. However, generating a stable 20nA current, especially 40nA, using a traditional current mirror is significantly affected by process and temperature. This makes it difficult to meet practical requirements because temperature and process have a large impact on the accuracy of the delay circuit.
[0042] To improve the accuracy of delay circuits and reduce the impact of temperature and process on their accuracy, this embodiment provides corresponding solutions, which are described below. Figures 2 to 6 This invention describes the detailed solutions for the delay circuit, oscillator, and soft-start circuit provided in the embodiments of the present invention.
[0043] like Figure 2 As shown, the delay circuit provided in this embodiment of the invention specifically includes: a first current mirror module 110, a second current mirror module 120, an energy storage element 130, and an action module 140.
[0044] The first current mirror module 110, the second current mirror module 120, and the action module 140 are all connected to the energy storage element 130. The first current mirror module 110 is also connected to the second current mirror module 120.
[0045] The first current mirror module 110 is used to convert the reference current into the main current. The reference current is generated by the internal bandgap reference module of the chip. The bandgap reference module can not only provide a stable voltage reference that is not affected by the power supply voltage and temperature, but also generate a reference current for bias and other applications. The second current mirror module 120 is used to convert the main current into multiple branch currents and charge the energy storage element 130 through the branch currents connected in series with the energy storage element 130. The action module 140 is used to compare the charging voltage of the energy storage element 130 with the preset reference voltage and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
[0046] In one embodiment, such as Figure 3 As shown, the first current mirror module 110 specifically includes: a current source A, a first transistor M1, and a second transistor M2.
[0047] The positive terminal of current source A and the drain of the second transistor M2 are both connected to the power supply VDD. The negative terminal of current source A is connected to the drain and gate of the first transistor M1, respectively. The gate of the first transistor M1 is connected to the gate of the second transistor M2. The source of the first transistor M1 is grounded. The source of the second transistor M2 is connected to the positive terminal of the energy storage element 130 and the second current mirror module 120, respectively. Figure 3 As shown, the energy storage element 130 is specifically an energy storage capacitor C1.
[0048] In one embodiment, such as Figure 3 As shown, the second current mirror module 120 specifically includes: a current mirror core unit and an auxiliary capacitor C2.
[0049] The current mirror core unit is connected to the auxiliary capacitor C2 and the first current mirror module 110 respectively. The positive terminal of the auxiliary capacitor C2 is connected to the current mirror core unit, and the negative terminal of the auxiliary capacitor C2 is grounded.
[0050] The current mirror core unit is used to convert the main current into multiple branch currents.
[0051] The auxiliary capacitor C2 is used to assist the energy storage element in charging through the branch current.
[0052] Furthermore, the core unit of the current mirror specifically includes: a current branch subunit and a bias control subunit.
[0053] The current branch subunit is connected to the energy storage element, the first current mirror module, and the bias control subunit, respectively.
[0054] The current branching subunit is used to split the main current into multiple branch currents, and the bias control subunit is used to regulate the multiple branch currents according to the charging conditions of the energy storage element itself.
[0055] In a specific implementation, such as Figure 3 As shown, the current branch subunit specifically includes: the third transistor M3, the fourth transistor M4, and the fifth transistor M5.
[0056] The gate of the fourth transistor M4 is connected to the gate of the third transistor M3 and the gate of the fifth transistor M5, respectively. The source of the third transistor M3 is grounded. The drains of the fourth transistor M4 and the fifth transistor M5 are both connected to the positive terminal of the energy storage element 130 and the first current mirror module 110. The sources of the fourth transistor M4 and the fifth transistor M5 are both connected to the bias control subunit.
[0057] In a specific implementation, such as Figure 3 As shown, the bias control subunit specifically includes: the sixth transistor M6 and the seventh transistor M7;
[0058] The drain of the sixth transistor M6 and the drain of the seventh transistor M7 are connected to the current branch subunit, and the source of the sixth transistor M6 and the source of the seventh transistor M7 are both grounded.
[0059] In one embodiment, such as Figure 2 and Figure 3 As shown, the action module 140 specifically includes a discharge unit and a comparator U1.
[0060] Both the discharge unit and the comparator U1 are connected to the energy storage element 130.
[0061] The discharge unit is used to provide a discharge path for the energy storage element 130. The comparator U1 is used to compare the charging voltage of the energy storage element 130 with a preset reference voltage, and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
[0062] In this embodiment, the positive terminal of the energy storage element 130 is connected to the positive input terminal of the comparator U1, and the inverting input terminal is connected to the reference voltage Vref. This is used to compare the charging voltage of the energy storage element with the preset reference voltage to achieve a delay. The output terminal of the comparator U1 can be connected to an actuator to form a soft-start circuit, or the output terminal of the comparator U1 can be connected to a Schmitt trigger to form a feedback loop to form a low-frequency oscillator.
[0063] In a specific implementation, such as Figure 3 As shown, the discharge unit specifically includes: the eighth transistor M8 and the ninth transistor M9.
[0064] The drain of the eighth transistor M8 is connected to the first current mirror module 110. The source of the eighth transistor M8 and the source of the ninth transistor M9 are both grounded. The drain of the ninth transistor M9 is connected to the negative terminal of the energy storage element 130.
[0065] Understandable, Figure 3The current I1 is a reference current with zero temperature drift, which generates the main current through the current mirror formed by the first transistor M1 and the second transistor M2. Initially, both the eighth transistor M8 and the ninth transistor M9 are turned off. At this time, the energy storage capacitor C1 and the auxiliary capacitor C2 are connected in series. Since the voltage across the capacitor cannot change abruptly, the gates of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all at a low level. At this time, the third transistor M3, the fourth transistor M4, and the fifth transistor M5 are all in the off state, and the auxiliary capacitor C2 is charged through the main current I2.
[0066] When the potential of the auxiliary capacitor C2 reaches VGS3, the gate potentials of the third transistor M3, the fourth transistor M4, and the fifth transistor M5 all increase. At this time, all three transistors M3, M4, and M5 are turned on. Since the aspect ratio of these three transistors is 1:N:M, the current mirror formed by these three transistors will generate a branch current I in the branch of the third transistor M3. C Branch current I C Specifically, it can be expressed as follows:
[0067]
[0068] Then, using the branch current I C The energy storage capacitor C1 is charged, and the charging voltage of C1 and the reference voltage Vref are used as the positive and negative inputs of comparator U1 to achieve the delay purpose. The third transistor M3 branch charges the energy storage capacitor C1, the fourth transistor M4 and the fifth transistor M5 are used for shunt, and the eighth transistor M8 and the ninth transistor M9 are used as the discharge circuit for the energy storage capacitor C1 and the auxiliary capacitor C2. The ninth transistor M9 is mainly used to discharge the auxiliary capacitor C2. At the same time, the ninth transistor M9 can be used to accelerate the discharge of the energy storage capacitor C1.
[0069] After both the eighth transistor M8 and the ninth transistor M9 are turned on, the energy storage capacitor C1 and the auxiliary capacitor C2 discharge. Different charging currents can be adjusted by controlling the on / off states of the sixth transistor M6 and the seventh transistor M7, thereby adjusting different delay durations.
[0070] To verify the advantages of the improved delay circuit provided in this embodiment, a reference current of 420nA and a charging current of 20nA were set. MOSFETs with the same aspect ratio were used to construct [the circuit]. Figure 3 The improved delay circuit provided in this embodiment is shown. Figure 1 The traditional delay circuit is shown, and simulations were performed at temperatures ranging from -50℃ to 150℃. The final results are as follows. Figure 4 As shown.
[0071] Specifically, in traditional delay circuits, the current mirror uses a ratio of 1:1 / 21, that is... Figure 1 The Mo transistor in the circuit uses 21 transistors of the same size as the Ma transistor connected in series to generate a charging current of 20nA.
[0072] In the improved delay circuit provided in this embodiment, the current mirror in the second current mirror module adopts a ratio of 1:10:10, that is... Figure 3 The fourth transistor M4 and the fifth transistor M5 are 10 transistors of the same size as the third transistor M3 connected in parallel to generate a charging current of 20nA.
[0073] Figure 4 The horizontal axis represents time, and the vertical axis represents the magnitude of the current. Figure 4 The simulation results show that, due to circuit structure and mismatch issues, the charging current generated by the current mirror using the traditional multi-MOS transistor series configuration can be seen from [the following text is incomplete and requires further context]. Figure 4 Curve 310 in the figure shows a significant error compared to the expected 20nA current. However, the charging current generated by the branch current mirror method used in this invention can be found in [reference needed]. Figure 4 The curve 320 in the figure shows that the charging current is almost identical to the expected 20nA charging current.
[0074] Because transistors are sensitive to temperature, the charging current generated by the current mirror in traditional delay circuits is significantly affected by temperature, resulting in a large current swing and thus impacting the accuracy and stability of the entire delay circuit. However, the branch current mirror technology used in this invention generates a charging current that is not sensitive to temperature, significantly improving the stability and accuracy of the entire delay circuit.
[0075] Based on the same general inventive concept, this invention also protects an oscillator and a soft-start circuit. The oscillator and soft-start circuit provided by this invention are described below. The oscillator and soft-start circuit described below can be referred to in correspondence with the delay circuit described above.
[0076] like Figure 5 As shown, the oscillator provided in this embodiment of the invention specifically includes the delay circuit 100 and the Schmitt trigger 400 provided in the above embodiments.
[0077] Considering that the current accuracy of the delay circuit provided in this embodiment is higher, it can also be used to construct oscillator structures such as low-frequency oscillators. Specifically, a Schmitt trigger 400 can be connected to the output of comparator U1, so that the delayed output signal can be converted into a square wave signal. This square wave signal can be used as a clock signal to control the conduction of the eighth transistor M8 and the ninth transistor M9, thereby realizing a continuous square wave clock signal.
[0078] like Figure 6 As shown, the soft-start circuit provided in this embodiment of the invention specifically includes the delay circuit 100 and the execution device 500 provided in the above embodiments.
[0079] In this embodiment, the positive terminal of the energy storage capacitor C1 is connected to the first positive input terminal of the comparator U1, the second input terminal is connected to the power supply Vcc, and the third input terminal is connected to the reference voltage Vref. Initially, the power supply at the second input terminal is disabled. At this time, the charging voltage of the energy storage capacitor C1 is compared with the preset reference voltage Vref. When the charging voltage of the energy storage capacitor C1 reaches the reference voltage Vref, the power supply at the second input terminal becomes effective, and the actuator 500 can be powered by the power supply.
[0080] In practical applications, the actuator 500 can be any power-consuming unit inside a chip, thereby enabling the chip to be powered through the use of a delay circuit.
[0081] Regarding the oscillator and soft-start circuit in the above embodiments, the specific structure and implementation principle of the delay circuit have been described in detail in the embodiments related to the delay circuit, and will not be elaborated here.
[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A delay circuit, characterized in that, include: The system comprises a first current mirror module, a second current mirror module, an energy storage element, and an action module. The first current mirror module, the second current mirror module, and the action module are all connected to the energy storage element, and the first current mirror module is also connected to the second current mirror module. The first current mirror module is used to convert the reference current into the main current; the second current mirror module is used to convert the main current into multiple branch currents, and charge the energy storage element through the branch currents connected in series with the energy storage element; the action module is used to compare the charging voltage of the energy storage element with a preset reference voltage, and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
2. The delay circuit according to claim 1, characterized in that, The first current mirror module includes: a current source, a first transistor, and a second transistor; The positive terminal of the current source and the drain of the second transistor are both connected to the power supply VDD. The negative terminal of the current source is connected to the drain and the gate of the first transistor, respectively. The gate of the first transistor is connected to the gate of the second transistor. The source of the first transistor is grounded. The source of the second transistor is connected to the positive terminal of the energy storage element and the second current mirror module, respectively.
3. The delay circuit according to claim 1, characterized in that, The second current mirror module includes: a current mirror core unit and an auxiliary capacitor; The current mirror core unit is connected to the energy storage element and the first current mirror module respectively. The positive terminal of the auxiliary capacitor is connected to the current mirror core unit, and the negative terminal of the auxiliary capacitor is grounded. The current mirror core unit is used to convert the main current into multiple branch currents. The auxiliary capacitor is used to assist the energy storage element in being charged by the multiple branch currents.
4. The delay circuit according to claim 3, characterized in that, The core unit of the current mirror includes: a current branching subunit and a bias control subunit; The current branch subunit is connected to the energy storage element, the first current mirror module and the bias control subunit respectively; The current branching subunit is used to split the main current into multiple branch currents, and the bias control subunit is used to regulate the multiple branch currents according to the charging conditions of the energy storage element.
5. The delay circuit according to claim 4, characterized in that, The current branch subunit includes: a third transistor, a fourth transistor, and a fifth transistor; The gate of the fourth transistor is connected to the gate of the third transistor and the gate of the fifth transistor, respectively. The source of the third transistor is grounded. The drains of the fourth transistor and the fifth transistor are both connected to the positive terminal of the energy storage element and the first current mirror module. The sources of the fourth transistor and the fifth transistor are both connected to the bias control subunit.
6. The delay circuit according to claim 4, characterized in that, The bias control subunit includes: a sixth transistor and a seventh transistor; The drain of the sixth transistor and the drain of the seventh transistor are connected to the current branch subunit, and the source of the sixth transistor and the source of the seventh transistor are both grounded.
7. The delay circuit according to claim 1, characterized in that, The action module includes: a discharge unit and a comparator; Both the discharge unit and the comparator are connected to the energy storage element; The discharge unit is used to provide a discharge path for the energy storage element, and the comparator is used to compare the charging voltage of the energy storage element with a preset reference voltage, and trigger a delayed output signal when the charging voltage is higher than the reference voltage.
8. The delay circuit according to claim 7, characterized in that, The discharge unit includes: an eighth transistor and a ninth transistor; The drain of the eighth transistor is connected to the first current mirror module, the source of the eighth transistor and the source of the ninth transistor are both grounded, and the drain of the ninth transistor is connected to the negative terminal of the energy storage element.
9. An oscillator, characterized in that, Includes the delay circuit as described in any one of claims 1 to 8.
10. A soft-start circuit, characterized in that, Includes the delay circuit as described in any one of claims 1 to 8.